CN110164352A

CN110164352A - Shift-register circuit and its driving method, gate driving circuit and display panel

Info

Publication number: CN110164352A
Application number: CN201910350434.7A
Authority: CN
Inventors: 程鸿飞
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2019-04-28
Filing date: 2019-04-28
Publication date: 2019-08-23
Anticipated expiration: 2039-04-28
Also published as: CN110164352B; WO2020220812A1

Abstract

Disclose a kind of shift-register circuit and its driving method, gate driving circuit and display panel.The shift-register circuit includes: input terminal, the first reference voltage end, the second reference voltage end, the first clock end, second clock end, output end, input circuit, first control circuit, second control circuit, third control circuit and output circuit, wherein first control circuit is configured in response to control the on-off of first node and third node from the received input signal of input terminal and from the received second clock signal in second clock end.

Description

Shift-register circuit and its driving method, gate driving circuit and display panel

Technical field

The present invention relates to field of display technology more particularly to shift-register circuit and its driving methods, gate driving electricity Road, display panel and display device.

Background technique

Array substrate row driving (GOA, i.e. Gate Driver on Array) circuit or shift-register circuit are answered extensively For showing in product.GOA circuit integration is prepared in array substrate with other display electric elements in array substrate simultaneously, The cost of display product can be reduced.

In the GOA circuit of the relevant technologies, in order to increase the drive of transistor in shift register (by taking P-type transistor as an example) Kinetic force or fan-out capability are allowed to repeat to be turned or switched on, it usually needs the voltage of pulldown transistors grid.At this moment, due to neighbour The fluctuation of nearly electric elements current potential is likely to cause the spread of voltage of transistor gate, to influence the drive waveforms of transistor Stability, and then the stability of entire GOA circuit output waveform may be influenced.

Summary of the invention

The purpose of the present invention is at least one of defects for overcoming the relevant technologies.

According to the first aspect of the invention, a kind of shift-register circuit is provided, comprising: input terminal is configured to receive Input signal；First reference voltage end is configured to be applied the first reference voltage；Second reference voltage end is configured to be applied Second reference voltage；First clock end is configured to receive the first clock signal；Second clock end is configured to receive second clock Signal；Output end is configured to output signal output；Input circuit, is configured to the first clock signal, control signal with The on-off of the on-off of first node and the first reference voltage end and second node, and in response to the current potential of first node, control Make the on-off of the first clock end and second node；First control circuit is configured to the input signal and described second Clock signal controls the on-off of first node and third node；Second control circuit is configured to the current potential of second node With the second clock signal, the on-off of the second reference voltage end and first node is controlled；Third control circuit, is configured to respond to In the current potential of the first node, the on-off of the second reference voltage end and fourth node is controlled, and in response to second section The current potential and second clock signal of point control the on-off at second clock end and fourth node；Output circuit is configured to institute The current potential of third node is stated, controls the on-off of first reference voltage end and the output end, and in response to the described 4th The current potential of node controls the on-off of second reference voltage end and the output end.

In some embodiments of shift-register circuit according to the present invention, the first control circuit is further matched It is set to and is in effective current potential, input signal effectively in response to third node and second clock signal is effective, make first node and the Three nodes disconnect.

In some embodiments of shift-register circuit according to the present invention, input circuit includes: the first transistor, Grid is connected to first clock end, and first electrode is connected to input terminal, and its second electrode is connected to first node； Second transistor, grid are connected to the first node, and first electrode is connected to the first clock end, and its second electrode It is connected to second node；Third transistor, grid are connected to first clock end, and first electrode is connected to the first reference Voltage end, and its second electrode is connected to second node.

In some embodiments of shift-register circuit according to the present invention, first control circuit includes: the 4th crystal Pipe, grid are connected to the first reference voltage end, and first electrode is connected to first node, and its second electrode is connected to the Three nodes；5th transistor, grid are connected to input terminal, and first electrode is connected to the 5th node, and its second electrode It is connected to first node；First capacitor device is connected between second clock end and the 5th node；And second capacitor, It is connected between third node and second clock end.

In some embodiments of shift-register circuit according to the present invention, second control circuit includes the 6th transistor With the 7th transistor, wherein the 6th transistor gate is connected to second node, first electrode is connected to the second reference voltage end, And its second electrode connects the first electrode of the 7th transistor；The grid of 7th transistor is connected to second clock end, the One electrode is connected to the second electrode of the 6th transistor, and its second electrode is connected to first node.

In some embodiments of shift-register circuit according to the present invention, third control circuit includes: the 8th crystal Pipe, grid are connected to second node, and first electrode is connected to second clock end, and second electrode connects the 6th node；The Nine transistors, grid are connected to second clock end, and first electrode is connected to the 6th node, and its second electrode is connected to Fourth node；Tenth transistor, grid are connected to first node, and first electrode is connected to the second reference voltage end, and Its second electrode is connected to fourth node.

In some embodiments of shift-register circuit according to the present invention, output circuit includes: the 11st transistor, Its grid is connected to fourth node, and first electrode is connected to the second reference voltage end, and its second electrode is connected to output End；Tenth two-transistor, grid are connected to third node, and first electrode is connected to the first reference voltage end, and its Two electrodes are connected to output end.

In some embodiments of shift-register circuit according to the present invention, output circuit further comprises third capacitor Device is connected between fourth node and the second reference voltage end.

In some embodiments of shift-register circuit according to the present invention, third control circuit further comprises: the 13 transistors, grid are connected to the first reference voltage end, and first electrode is connected to second node, and its second electrode It is connected to the 7th node；And the 4th capacitor, it is connected between the 6th node and the 7th node.

In some embodiments of shift-register circuit according to the present invention, input circuit, output circuit, the first control The transistor that circuit, second control circuit and third control circuit respectively include is single gridistor.Optionally, the crystal Pipe can be N-type transistor or be P-type transistor.

According to the second aspect of the invention, a kind of gate driving circuit is provided, including N number of cascade such as according to the present invention one The shift-register circuit of a little embodiments, N are the integer more than or equal to 2, wherein in N number of shift-register circuit, m The output end of a shift-register circuit is connected to the input terminal of the m+1 shift-register circuit, and m is integer and 1≤m < N.

According to the third aspect of the invention we, a kind of display panel is provided, comprising: the first reference voltage line is configured to transmit First reference voltage；Second reference voltage line is configured to the second reference voltage of transmission；First clock line and second clock line, match It is set to the first clock signal of transmission and second clock signal, the first clock signal and second clock signal have opposite phase； And gate driving circuit according to some embodiments of the invention, wherein each first reference of N number of shift-register circuit Voltage end is connected to the first reference voltage line, wherein each second reference voltage end of N number of shift-register circuit is connected to Second reference voltage line, wherein the first clock of the 2k-1 shift-register circuit in N number of shift-register circuit End and the second clock end of the 2k shift-register circuit are connected to the first clock line, and wherein N number of shift LD The second clock end of the 2k-1 shift-register circuit in device circuit and the first clock of the 2k shift-register circuit End is connected to second clock line, and k is positive integer and 2k≤N.

According to the fourth aspect of the invention, a kind of display device is provided, comprising: such as showing according to some embodiments of the invention Show panel；Sequence controller is configured to control the operation of the display panel, and wherein sequence controller is configured to One clock line and second clock line supply the first clock signal and second clock signal, the first clock signal and second clock respectively Signal has opposite phase；And voltage generator, it is configured under the control of sequence controller to first with reference to electricity Crimping and the second reference voltage line supply the first reference voltage and the second reference voltage respectively.

According to the fifth aspect of the invention, a kind of shift register that driving is described according to some embodiments of the invention is provided The method of circuit, comprising: provide input signal to input terminal；The first clock is provided respectively to the first clock end and second clock end Signal and second clock signal；First ginseng is supplied respectively to first reference voltage end and second reference voltage end Voltage and second reference voltage are examined, wherein first reference voltage and second reference voltage are in different electricity Position；And in response to the input signal, first clock signal, the second clock signal, first reference voltage With second reference voltage, operations described below is executed by the shift-register circuit: the output is exported by the output end Signal.

In some embodiments of the driving method of shift-register circuit according to the present invention, first reference voltage In effective voltage, it is horizontal be in dead voltage for horizontal and the second reference voltage, and described is held by the shift-register circuit Capable operation further comprises executing operations described below by first control circuit: in response to the third node be in effective current potential, The input signal is effective and the second clock signal is effective, disconnects the first node and the third node.

Detailed description of the invention

According to features as discussed above, it will readily appreciate that each different aspects, features and advantages of the invention, In attached drawing:

Fig. 1 schematically shows the structural block diagram of shift-register circuit according to some embodiments of the invention；

Fig. 2 schematically shows the exemplary circuit for shift-register circuit shown in FIG. 1 according to some embodiments of the invention Circuit diagram；

Fig. 3 schematically shows the example timing diagram for example shift-register circuit shown in Fig. 2；

Fig. 4 schematically shows the example electricity for shift-register circuit shown in FIG. 1 of other embodiments according to the present invention The circuit diagram on road；

Fig. 5 schematically shows the block diagram of the gate driving circuit of the shift-register circuit based on Fig. 2；And

Fig. 6 schematically shows the block diagram of display device according to some embodiments of the invention.

It should be pointed out that above-mentioned attached drawing is only schematical and illustrative, and it is not necessarily drawn to scale.

Specific embodiment

Several embodiments that the present invention will be described in more detail below with reference to accompanying drawings are to make those skilled in the art It can be realized the present invention.However, the present invention can be presented as many different forms and should not be construed as being limited to herein The embodiment illustrated.On the contrary, thesing embodiments are provided so that the present invention is comprehensively and complete, and will be fully to this field skill Art personnel convey the scope of the present invention.The embodiment does not limit the present invention.

It will be appreciated that although term first, second, third, etc. can be used to describe various component, assembly units herein And/or part, but these component, assembly units and/or part should not be limited by these terms.These terms are only used to one Component, assembly unit or part are mutually distinguished with another component, assembly unit or part.Therefore, first element discussed below, component or portion Second element, part or part can be referred to as without departing from the teachings of the present invention by dividing.

Term used herein is merely for for the purpose of describing particular embodiments and being not intended to limit the present invention.As herein Used in, singular "one", " one " and "the" be intended to also include plural form, unless context clearly separately has finger Show.It will be further appreciated that term " includes " and/or "comprising" when used in this manual specify addressed feature, The presence of entirety, step, operations, elements, and/or components, but be not excluded for other one or more features, entirety, step, operation, One or more other features, entirety, step, operation, component, assembly unit are added in the presence of component, assembly unit and/or its group And/or its group.As used in this article, term "and/or" includes associated times for listing one or more of project Meaning and all combination.

It will be appreciated that when element is referred to as " being connected to another element " or " being coupled to another element ", it can To be directly connected to another element or be directly coupled to another element, or may exist intermediary element.On the contrary, working as element When referred to as " being directly connected to another element " or " being directly coupled to another element ", exist without intermediary element.

Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have and the present invention The normally understood identical meanings of those of ordinary skill in the art institute.It will be further appreciated that such as those usually make Term defined in dictionary etc should be interpreted as having and it is in related fields and/or this specification context The consistent meaning of meaning, and will not idealization or it is too formal in the sense that explain, unless clear herein Ground is so defined.

Fig. 1 schematically shows the block diagram of shift-register circuit 100 according to some embodiments of the invention.With reference to Fig. 1, move Bit register circuit 100 includes being configured to receive the input terminal IN of input signal, being configured to be applied the first reference voltage The first reference voltage end VGL, be configured to be applied the second reference voltage end VGH of the second reference voltage, be configured to connect It receives the first clock end CK of the first clock signal, be configured to receive the second clock end CB of second clock signal and configuration Output end OUT for output signal output.As shown in Figure 1, shift-register circuit 100 further includes be illustrated as square defeated Enter circuit 110, first control circuit 120, second control circuit 130, third control circuit 140 and output circuit 150.

Input circuit 110 can be configured in response in received first clock signal of the first clock end CK, control input IN and the on-off of first node N1 and the on-off of the first reference voltage end VGL and second node N2 are held, and in response to first The current potential of node N1 controls the on-off of the first clock end CK and second node N2.Specifically, such as input circuit 110 can be with It is configured in response to effective in received first clock signal of the first clock end CK, input signal is input to first node N1 And the first reference voltage is input to second node N2, and be in effective current potential in response to first node N1, by the first clock Signal is input to second node N2.

First control circuit 120 can be configured in response to from the received input signal of input terminal IN and from second clock end The received second clock signal of CB controls the on-off of first node N1 and third node N3.Specifically, the such as first control electricity Road 120 can be configured to when third node N3 is in effective current potential in response to from the received input signal of input terminal IN effectively and At second clock end, the received second clock signal of CB is effective, disconnects first node N1 and third node N3.

Second control circuit 130 can be configured in response to the current potential of second node N2 and received in second clock end CB Second clock signal controls the on-off of the second reference voltage end VGH and first node N1.Specifically, the such as second control electricity Road 130 may be configured to be in effective current potential in response to second node N2 and in the received second clock letter of second clock end CB Number effectively, the second reference voltage end VGH is connected with first node N1.

Third control circuit 140 can be configured to the current potential in response to first node N1, control the second reference voltage end VGH With the on-off of fourth node N4, and believe in response to the current potential of second node N2 and in the received second clock of second clock end CB Number, control the on-off of second clock end CB and fourth node N4.Specifically, for example third control circuit 140 can be configured to In response to second node N2 be in effective current potential and in the received second clock signal of second clock end CB it is effective, by second clock End CB is connected with fourth node N4, and is in effective current potential in response to first node N1, by the second reference voltage end VGH and the Four node N4 conducting.

Output circuit 150 can be configured to the current potential in response to third node N3, control the first reference voltage end VGL and defeated The on-off of outlet OUT, and in response to the current potential of fourth node N4, control the logical of the second reference voltage end VGH and output end OUT It is disconnected.Specifically, such as output circuit 150 can be configured to be in effective current potential in response to third node N3, by the first reference Voltage end VGL is connected with output end OUT, and is in effective current potential in response to fourth node N4, by the second reference voltage end VGH It is connected with output end OUT.

It is locating that term " effective current potential " as used herein refers to that related circuit element (for example, transistor) is activated Current potential, even if such as be applied to transistor gate and current potential that make transistor turns, source electrode and drain electrode conducting.As made herein Term " invalid current potential " refers to the disabled locating current potential of related circuit element, such as is applied to transistor gate Even and if make transistor cutoff, source electrode and drain electrode disconnect current potential.For n-type transistor, effective current potential is high electricity Position, and invalid current potential is low potential.For p-type transistor, effective current potential is low potential, and invalid current potential is high electricity Position.It it will be appreciated that effectively current potential or invalid current potential are not intended to refer to some specific current potential, but may include one The range of current potential.In addition, the intention such as term " level voltage ", " voltage level ", " voltage level " interchangeably makes with " current potential " With.

Herein, clock signal effectively refers to that corresponding clock end is in " effective current potential ", i.e., so that being related to circuit elements Part (for example, transistor) is activated locating current potential, and disabling clock signals refer to that corresponding clock end is in " invalid electricity Position ", i.e., the related disabled locating current potential of circuit element.For some embodiments of the present invention, clock signal has Effect refers to that corresponding clock end is in low potential, and disabling clock signals refer to that corresponding clock end is in high potential.

It is easily understood that in shift-register circuit 100 according to some embodiments of the invention shown in Fig. 1, In first control circuit 120, effective current potential is in third node N3, is had in the received second clock signal of second clock end CB Effect and input terminal IN is when being in effective current potential, can be such that first node N1 is fully disconnected with third node N3, and in other times, First node N1 is kept to be connected with third node N3.In this way, guaranteeing the same of the entire normal work of shift-register circuit 100 When, when needing that third node N3 is kept steadily to be in effective current potential, first node N1 can break completely with third node N3 It opens, so that the two current potential is completely independent, is independent of each other, first node N1 is avoided to destroy adjacent to the potential fluctuation of electric elements The stability of the current potential of third node N3.In addition, since third node N3 is connected with output circuit 150, keep third section The current potential of point N3 is stablized, it is ensured that the operation is stable of transistor relevant to third node in output circuit 150 improves entire The stability of the output waveform of shift-register circuit 100, to ensure that the quality of the output pulse of output end OUT.

More specifically, first control circuit 120, effective current potential is in third node N3, is in effective in input terminal IN Current potential and when CB received second clock signal in second clock end is effective, make first node N1 and third node N3 disconnect (or It is completely switched off), it can be to avoid the leakage current formed in the related technology because transistor non-fully ends to electric at third node N3 The adverse effect of position guarantees the steady of output waveform so that it is guaranteed that the transistor in output circuit 150 is fully and stably opened Qualitative and output pulse quality.

Fig. 2 schematically shows the circuit structure of the first exemplary circuit 200 of shift-register circuit 100 as shown in Figure 1. First example arrangement of shift-register circuit 200 is described below with reference to Fig. 2.

Input circuit 110 includes the first transistor T1, second transistor T2 and third transistor T3.The first transistor T1 tool There is the grid for being connected to the first clock end CK, be connected to the first electrode of input terminal IN and be connected to the of first node N1 Two electrodes.Second transistor T2 have be connected to the grid of first node N1, the first electrode for being connected to the first clock end CK, with And it is connected to the second electrode of second node N2.Third transistor T3 has the grid for being connected to the first clock end CK, is connected to The first electrode of first reference voltage end VGL and the second electrode for being connected to second node N2.

First control circuit 120 includes the 4th transistor T4, the 5th transistor T5, first capacitor device C1 and the second capacitor C2.4th transistor T4 have be connected to the grid of the first reference voltage end VGL, the first electrode for being connected to first node N1, And it is connected to the second electrode of third node N3.5th transistor T5 has the grid for being connected to input terminal IN, is connected to the The first electrode of five node N5 and the second electrode for being connected to first node N1.First capacitor device C1 is connected to second clock It holds between CB and the 5th node N5.Second capacitor C2 is connected between second clock end CB and third node N3.

Second control circuit 130 includes the 6th transistor T6 and the 7th transistor T7, is connected wherein the 6th transistor T6 has The first electrode for being connected to the grid of second node N2, being connected to the second reference voltage end VGH, the 7th transistor T7, which has, to be connected to The grid of second clock end CB, the second electrode for being connected to first node N1, and the second electrode and the 7th of the 6th transistor T6 Transistor T7 first electrode is connected with each other.

Third control circuit 140 includes the 8th transistor T8, the 9th transistor T9 and the tenth transistor T10.8th crystal Pipe T8 has the grid for being connected to second node N2, is connected to the first electrode of second clock end CB and is connected to Section six The second electrode of point N6.9th transistor T9 has the grid, the 6th node N6 being connected to for being connected to second clock end CB First electrode and the second electrode for being connected to fourth node N4.Tenth transistor T10 has the grid for being connected to first node N1 Pole, the first electrode for being connected to the second reference voltage end VGH and the second electrode for being connected to fourth node N4.

Output circuit 120 includes the 11st transistor T11 and the tenth two-transistor T12.11st transistor T11, which has, to be connected It is connected to the grid of fourth node N4, the first electrode of the second reference voltage end VGH is connected to and is connected to output end OUT's Second electrode.Tenth two-transistor T12 has the grid for being connected to third node N3, is connected to the first reference voltage end VGL's First electrode and the second electrode for being connected to output end OUT.

Optionally, as shown in Fig. 2, input circuit can also include third capacitor C3, it is connected to the second reference voltage It holds between VGH and fourth node N4.The presence of third capacitor C3 is advantageous, because the current potential at fourth node N4 can be borrowed The energy storage for helping capacitor C3 acts on to remain stable, so that the 11st transistor T11's is in stable condition, to guarantee to export The stabilization of waveform.

It should be noted that the transistor that the present invention is previously mentioned is not limited in single transistor, it can be multiple crystalline substances The series connection of body pipe.In an embodiment of the present invention, term " the n-th transistor " include a transistor for illustrated, and on Stating transistor can be P-type transistor or be N-type transistor.In some embodiments in accordance with the present invention, when above-mentioned When transistor is P-type transistor, term " first electrode of transistor " is specially source electrode, and " second electrode of transistor " is specific For drain electrode.And when above-mentioned transistor is N-type transistor, term " first electrode " is drains, and term " second electrode " For source electrode.The embodiment of the present invention is illustrated so that each transistor is P-type transistor as an example, and gate turn-on voltage is low level electricity Pressure, shutdown voltage are high level voltage.Although each transistor is depicted and described as P-type transistor, N-type transistor is can Can.In the case where N-type transistor, gate turn-on voltage has high level, and gate off voltage has low level.? In each embodiment, each transistor can for example take the form of thin film transistor (TFT), be typically produced so that they first, Second electrode is interchangeably used.

Fig. 3 schematically shows the example timing diagram for example shift-register circuit 200 shown in Fig. 2.In the example In it can be assumed that the first reference voltage end VGL and the second reference voltage end VGH be applied respectively low level voltage and high level electricity Pressure.

The operating process of exemplary circuit 200 shown in Fig. 2 is described below with reference to Fig. 3.Hereinafter, high level is indicated with 1, And low level is indicated with 0.As shown in figure 3, the operating process of circuit 200 includes 5 stage P1-P5, but when due to first The clock signal of clock end CK and the clock signal of second clock end CB are not fully synchronized variation, therefore between above-mentioned each stage also There are four small time interval t1-t4.As shown, the first clock letter of the first clock end CK and second clock end CB output Number and second clock signal waveform in, high level time be slightly larger than low level time.

Firstly, in conjunction with the working condition of Fig. 3 analysis circuit 200 (before input pulse arrives) before P1.Such as Fig. 3 institute Show, at each moment before P1, IN remains 0.As CK=0, CB=1, the 7th transistor T7 and the 4th transistor T4 Cut-off；The first transistor T1 is connected and the low-voltage of input terminal IN is transmitted to first node N1, and therefore, N1 is in effective low electricity Position.It is in low potential, second transistor T2 and the tenth transistor T10 conducting in response to N1, and respectively by the first clock end CK Low-voltage and the high voltage of the second reference voltage end (VGH) be transmitted to second node N2 and fourth node N4, then the second section Point N2 is in low potential and fourth node N4 is in high potential.When CK, which becomes 1, CB from 0, maintains 1, first node N1 remains low Current potential, the tenth transistor T10 keep cut-off, and then fourth node N4 maintains high potential.Therefore, each moment between P1, Fourth node N4 maintains high potential always and first node N1 and third node N3(is since the first reference voltage end VGL is applied Add low level voltage, the 4th transistor T4 conducting) it is in low potential always, such 11st transistor T11 keeps cut-off and the Ten two-transistor T12 are kept it turning on, so that it is guaranteed that output end OUT exports low-voltage.

As shown in figure 3, in the P1 stage, IN=1, CK=0, CB=1.Due to CK=0 and IN=1, so the first transistor T1 is opened It opens and the high level voltage from input terminal IN is transmitted to first node N1, so that first node N1 is set in invalid electricity Position (high potential)；Third transistor is turned on and the low level of the first reference voltage end VGL is transmitted to second node N2, so that Second node N2 is set in effective current potential；And the 5th transistor T5 ends.Due to CB=1, the 7th transistor T7 and the 9th Transistor T9 cut-off.Invalid current potential, second transistor T2 and the tenth transistor T10 cut-off are in accordingly, due to N1.Due to N2 In effective current potential, the 6th transistor T6 and the 8th transistor T8 are opened.

In turn, since the first reference voltage end VGL is applied low level voltage, so the 4th transistor T4 is turned on, make The high level voltage for obtaining N1 point is transmitted to third node N3.Third node N3 is identical as first node N1 current potential in this way, is in nothing It imitates current potential (high potential), so that the tenth two-transistor T12 ends.Since the 9th transistor T9 and the tenth transistor T10 is cut Only, so that fourth node N4 suspends, the current potential of last moment is kept, i.e., (based on analysis above, fourth node N4's high potential exists High potential is kept before the P1 stage), so that the 11st transistor T11 ends.Therefore, because T11 and T12 end, output end The output voltage of OUT should be the output voltage of previous moment (at the time of before P1), i.e. low level voltage.

During time interval at t1, IN=1, CK becomes 1, CB=1 from 0.At this moment, in response to CK=1, the first clock signal In vain, the first transistor T1 and third transistor T3 cut-off；In response to CB=1, second clock signal keeps invalid, then the 7th is brilliant Body pipe T7, the 9th transistor T9 keep off state；Off state is kept in response to IN=1, the 5th transistor T5.Correspondingly, One node N1 keeps the high potential (invalid current potential) in (P1 stage) on last stage, thus second transistor T2 and the tenth transistor T10 keeps off state；Then, second node N2 keeps effective current potential (low potential), and fourth node N4 is still within suspension State, keeps the high potential of (P1) on last stage, and such 11st transistor T11 still maintains off state.When due to second Clock end CB keeps high level, and third node N3 also keeps high potential state, and then the tenth two-transistor T12 still maintains cut-off shape State.Therefore, output end OUT still exports the low level voltage of previous stage.

In the P2 stage, IN=1, CK=1, CB become 0 from 1.In response to CK=1, the first disabling clock signals, the first transistor T1 and third transistor T3 keeps off state；Off state is kept in response to IN=1, the 5th transistor T5；In response to CB=0, Second clock signal effectively (is in low level), and the 7th transistor T7, the 9th transistor T9 are turned on.Correspondingly, first node N1 keeps the high potential (invalid current potential) in (P1 stage) on last stage, so that second transistor T2 and the tenth transistor T10 is kept Off state；Second node N2 keeps effective current potential (low potential), and then the 6th transistor T6 and the 8th transistor T8 holding is opened Open state.

Since CB becomes 0 from 1, i.e. second clock end CB becomes low level state from high level state, then due to being connected to The drop-down of capacitor C2 between second clock end CB and third node N3 acts on (the principle class with the boot strap of capacitor Like), the voltage of third node N3 is possible to be dragged down by the second capacitor C2.But simultaneously, in response to the 6th transistor T6 and Seven transistor T7 are opened simultaneously, then the second reference voltage end VGH will be connected with N1 point, and then pass through the 4th transistor T4 and third Node N3 conducting, then the second reference voltage end VGH will charge to first node N1 and third node N3, make the two nodes Always it is in high potential (because the second reference voltage end VGH is applied high level voltage), the current potential of third node N3 is not It can be dragged down by the second capacitor C2.

It is readily appreciated that, the effect of the 6th transistor T6 and the 7th transistor T7 are exactly to be in invalid current potential in N1 point and N3 point Since second clock end CB voltage is lower so that the current potential of N3 is possible to the feelings dragged down by the second capacitor C2 when (i.e. high potential) It under condition, is charged using the high voltage of the second reference voltage end VGH to it, is allowed to current potential and keeps stablizing, that is, be in high potential, in order to avoid Influence the normal output of output end OUT.

It is in invalid current potential, i.e. high potential in response to third node N3, the 12nd crystal T12 keeps off state.Meanwhile It is opened simultaneously in response to the 8th transistor T8 and the 9th transistor T9, so that the low level voltage of second clock end CB is transferred into Fourth node N4, then fourth node N4 is set in effective current potential (i.e. low potential), so that the 11st transistor T11 is opened It opens and the high voltage of the second reference voltage end VGH is transmitted to output end OUT.End accordingly, in response to the tenth two-transistor T12 And the 11st transistor T11 open, output end OUT output high level voltage.

At time interval t2, IN=1, CK=1, CB=from 0 become 1.At this moment, in response to CK=1, i.e. the first clock signal without Effect, the first transistor T1 and third transistor T3 still maintain cut-off；Cut-off shape is kept in response to IN=1, the 5th transistor T5 State.In response to CB=1, second clock signal becomes invalid (i.e. high level), and the 7th transistor T7, the 9th transistor T9 are ended. Cut-off is still maintained accordingly, due to the first transistor T1, third transistor T3 and the 5th transistor T5, first node N1 is kept The invalid current potential (high potential) in (P2 stage) on last stage is cut so that second transistor T2 and the tenth transistor T10 are still maintained Only state, then second node N2 keeps effective current potential in (P2 stage) on last stage, i.e. low potential.

Ended in response to the 9th transistor T9 and the tenth transistor T10, fourth node N4 is in suspended state, in holding Effective current potential (low potential) in one stage (P2), such 11st transistor T11 still maintain open state；And third node N3 It is identical as the current potential of the first current potential N1 all in invalid current potential (high potential) (due to CB keep high level, the second capacitor C2 will not drag down the current potential of N3), then the tenth two-transistor T12 still maintains off state.Accordingly, in response to the 11st crystal Pipe T11 is kept it turning on and the tenth two-transistor T12 ends, output end OUT still output high level voltage.

In the P3 stage, identical with the P1 stage is that IN=1, CK becomes 0, CB=1 from 1.Due to CK=0 and IN=1, so One transistor T1 is turned on and the high level voltage from input terminal IN is transmitted to first node N1, so that first node N1 quilt It is set at invalid current potential (high potential)；Third transistor T3 is turned on and transmits the low level of the first reference voltage end VGL To second node N2, so that second node N2 is set in effective current potential (low potential)；And the 5th transistor T5 is still protected Hold cut-off.Since CB=1, the 7th transistor T7 and the 9th transistor T9 end.Invalid current potential is in accordingly, due to N1, second Transistor T2 and the tenth transistor T10 cut-off.Since N2 is in effective current potential, the 6th transistor T6 and the 8th transistor T8 are opened It opens.

In turn, since the first reference voltage end VGL is applied low level voltage, so the 4th transistor T4 is turned on, make The high level voltage for obtaining N1 point is transmitted to third node N3.Third node N3 is identical as first node N1 current potential in this way, is in nothing It imitates current potential (high potential), so that the tenth two-transistor T12 ends.Since the 9th transistor T9 and the tenth transistor T10 is cut Only, so that fourth node N4 suspends, the current potential of (t2 period) on last stage, i.e., effective current potential (low potential), thus the tenth are kept One transistor T11 is kept it turning on.It is opened accordingly, in response to the 11st transistor T11 and the tenth two-transistor T12 ends, output End OUT still exports the high level voltage of the second reference voltage end VGH transmission.

At time interval t3, IN=1, CK becomes 1, CB=1 from 0.At this moment, in response to CK=1, i.e. the first clock signal without Effect, the first transistor T1, third transistor T3 are ended；In response to CB=1, i.e. second clock signal keeps invalid, the 7th crystal Pipe T7, the 9th transistor T9 keep off state；Cut-off is kept in response to IN=1, the 5th transistor T5.

Ended accordingly, in response to the first transistor T1, first node N1 keeps the height electricity in (P3 stage) on last stage Position (invalid current potential), so that second transistor T2 and the tenth transistor T10 keeps off state；In response to third transistor T3 and Second transistor T2 is ended, and second node N2 keeps effective current potential (low potential) of (P3) on last stage, thus the 8th crystal Pipe T8 is opened；And end in response to the 9th transistor T9, fourth node N4 is still within suspended state, keeps on last stage (P3) low potential (effective current potential), such 11st transistor T11 are kept it turned on.Since second clock end CB keeps high Level 1, N1 and N3 also keep high potential state.Although the 5th transistor T5 is opened, first capacitor device C1 can't drag down N1 The voltage of node, and the second capacitor C2 will not drag down the voltage of third node N3.Then, the tenth two-transistor T12 is still Keep off state.Therefore, output end OUT still exports the high level voltage of the second reference voltage end VGH transmission.

In the P4 stage, IN becomes 0, CK=1 from 1, and CB becomes 0 from 1.In response to CK=1, i.e. the first disabling clock signals, One transistor T1 and third transistor T3 keeps off state；In response to IN=0, the 5th transistor T5 is kept it turned on；Response In CB=0, second clock signal effectively (is in low level), and the 7th transistor T7, the 9th transistor T9 are turned on.

Ended accordingly, in response to the first transistor T1, first node N1 keeps the high potential (nothing of (t3) on last stage Imitate current potential), so that second transistor T2 and the tenth transistor T10 keeps off state；In response to third transistor T3 and second Transistor T2 cut-off, second node N2 keep effective current potential (low potential) on last stage, then the 6th transistor T6 and the 8th Transistor T8 is kept it turned on.

Similar with described in the P2 stage, in the P4 stage, since CB becomes 0 from 1, i.e., second clock end CB is by high level state Become low level state, then due to the drop-down effect for the capacitor C2 being connected between second clock end CB and third node N3 (similar with the principle of the boot strap of capacitor), the voltage of third node N3 are possible to be dragged down by the second capacitor C2；And Since the 5th transistor T5 is turned on, first node N1 is connected with the 5th node N5, thus, similarly due to first capacitor device C1 Drop-down effect, first node N1(and the 5th node N5) voltage be possible to be dragged down by first capacitor device C1.But it meanwhile responding It is opened simultaneously in the 6th transistor T6 and the 7th transistor T7, the second reference voltage end VGH will be connected with N1 point, and then pass through the Four transistor T4(are because the first reference voltage end VGL of its grid connection is low level voltage) it is connected with N3 point, then second Reference voltage end VGH will charge to N1 and N3 point, i.e., high level is sent to N1 and N3, the two nodes is made to be in high always Current potential (because VGH is applied high level voltage), the current potential of first node N1 and third node N3 will not be respectively by first Capacitor C1 and the second capacitor C2 are dragged down.

As described above, the effect of the 6th transistor T6 and the 7th transistor T7 is exactly in first node N1 and third node N3 Since the second clock signal of second clock end CB is lower so that its current potential is possible to point when in invalid current potential (i.e. high potential) It in the case where not dragged down by first capacitor device C1 and the second capacitor C2, charges to it, makes the two current potential keep stablizing, i.e., always In high potential, in order to avoid the off state of second transistor T2, the tenth transistor T10 and the tenth two-transistor T12 are influenced, in turn It avoids impacting the normal output of output end OUT.

Then, it is in invalid current potential, i.e. high potential in response to third node N3, the tenth two-transistor T12 keeps cut-off shape State；It is opened simultaneously in response to the 8th transistor T8 and the 9th transistor T9 simultaneously, so that the low level voltage of second clock end CB It is transferred into fourth node N4, then fourth node N4 is set in effective current potential (i.e. low potential), thus the 11st crystal Pipe T11 is turned on.It is opened accordingly, in response to the 11st transistor T11 and the tenth two-transistor T12 ends, second with reference to electricity Pressure side VGH's is sent to high level voltage output end OUT, thus output end OUT output high level voltage.

At time interval t4, IN=0, CK=1, CB=from 0 become 1.At this moment, in response to CK=1, i.e. the first clock signal without Effect, the first transistor T1 and third transistor T3 still maintain cut-off；In response to IN=0, the 5th transistor T5 is turned on；Response In CB=1, second clock signal becomes invalid (i.e. high level), and the 7th transistor T7, the 9th transistor T9 are ended.Correspondingly, Since the first transistor T1, third transistor T3 still maintain cut-off, first node N1 keeps the nothing in (P4 stage) on last stage It imitates current potential (high potential), so that second transistor T2 and the tenth transistor T10 still maintain off state, then second node N2 Keep effective current potential in (P4 stage) on last stage, i.e. low potential.

Ended in response to the 9th transistor T9 and the tenth transistor T10, fourth node N4 is in suspended state, in holding Effective current potential (low potential) in one stage (P5), such 11st transistor T11 still maintain open state；And third node N3 It is identical as the current potential of the first current potential N1 all in invalid current potential (high potential) (due to CB keep high level, the second capacitor C2 will not drag down the current potential of N3, and first capacitor device C1 will not drag down the current potential of N1 point), then the tenth two-transistor T12 is still Keep off state.It is kept it turning on accordingly, in response to the 11st transistor T11 and the tenth two-transistor T12 keeps cut-off, output End OUT still exports the high level voltage of the second reference voltage end VGH transmission.

In the P5 stage, IN=0, CB=1, CK=from 1 become 0.In response to CK=0 and IN=0, the first transistor T1 is turned on simultaneously Low level voltage from input terminal IN is transmitted to first node N1, so that first node N1 is set in effective current potential (low potential)；Third transistor T3 is turned on and the low level of the first reference voltage end VGL is transmitted to second node N2, so that Second node N2 is set in effective current potential (low potential)；And the 5th transistor T5 is turned on, by first node N1 and Five node N5 conducting.It keeps ending in response to CB=1, the 7th transistor T7 and the 9th transistor T9.

Be in effective current potential in response to first node N1, second transistor T2 conducting and the tenth transistor T10 be connected and incite somebody to action The high level voltage of second reference voltage end VGH is transmitted to fourth node N4, so that fourth node N4 is set in invalid electricity Position (high potential), so that the 11st transistor T11 ends.It is brilliant in response to effective low-voltage of the first reference voltage end VGL, the 4th Body pipe T4 is turned on and the low-voltage of N1 point is transmitted to third node N3, so that N3 is in low potential, then the 12nd is brilliant Body pipe T12 is turned on.Accordingly, in response to the 11st transistor T11 cut-off and the tenth two-transistor T12 is opened, and output end OUT is defeated The low level voltage of first reference voltage end VGL transmission out.

In stage after P5, as shown in figure 3, input terminal IN persistently keeps low level voltage, first node N1 keeps low Current potential, second transistor T2 are connected always, therefore the voltage of second node N2 depends on the output level of the first clock end CK, i.e., When the first clock end CK exports high level signal, second node N2 point current potential is height.As shown in figure 3, the first clock end CK connects The first clock signal and the received second clock signal waveform of second clock end CB received are substantially on the contrary, i.e. the first clock end CK When low level signal, second clock end CB exports high level signal；And when second clock end CB output low level signal, when first Clock end CK exports high level signal.In this way, the first clock end CK exports high level when second clock end CB exports low level, That is second node N2 is in high potential, and then the 6th transistor T6 and the 7th transistor T7 can not be simultaneously turned on.In this way, guaranteeing N1 point and N3 point will not be charged the high voltage of the second reference voltage end VGH.

According to being described above, the effect of second transistor T2 is to control the on and off of transistor T6, to guarantee in P5 Stage first node N1 and third node N3 later keeps low potential, from the high voltage of the second reference voltage end VGH transmission Influence.

In addition, the stage after P5, according to analysis above, the input pulse of input terminal IN is kept effectively, i.e. low level, So that the 5th transistor T5 is held on；First node N1 and third node N3 is in effective current potential, i.e. low potential, to guarantee The conducting of ten two-transistor T12, output end OUT export low level voltage.Then, when the second clock of second clock end CB output When signal becomes low level signal from high level (when i.e. effective), due to the antihypertensive effect (similar with boot strap) of capacitor, Second capacitor C2 will further drag down the current potential of third node N3, so that the tenth two-transistor T12 opens more abundant, output Ability enhancing.At this moment, if removing first capacitor device C1 and the 5th transistor T5 in the circuit structure of Fig. 2, due to third The voltage of node N3 is pulled low, and the current potential of first node N1 is higher than third node N3, then the voltage meeting on first node N1 It is (this although T12 may end since third node N3 current potential reduces to the charging of first node N1 node by T12 Cut-off is not fully disconnected, because N4 point voltage is higher than N1, still may have a small amount of leakage current to flow through T12), cause the 12nd The fluctuation of transistor T12 grid voltage, influences the stability of circuit output waveform.

Just because of in first control circuit 120, there are first capacitor device C1, when the second of second clock end CB output When clock signal becomes low level signal from high level (when i.e. effective), first capacitor device C1 (will be dragged down with the second capacitor C2 The current potential of N3 point) synchronize the current potential for dragging down first node N1.At this moment, since N1 and N3 are synchronized to drag down, current potential is identical, keeps away completely Leakage current is exempted from and has flowed through T4, is i.e. T4 completely switched off (be equal to and be fully disconnected), i.e. first node N1 will not be filled to third node N3 Electricity guarantees the stabilization of third node N3 current potential, so that it is guaranteed that the stabilization of shift-register circuit output waveform, improves the drive of circuit Dynamic quality.

Fig. 4 schematically shows the circuit structure of the second exemplary circuit 400 of shift-register circuit 100 as shown in Figure 1. As shown in figure 4, the structure of the second exemplary circuit 400 of shift-register circuit 100 and the first exemplary circuit 200 shown in Fig. 2 Structure it is essentially identical, difference is, in the second exemplary circuit 400 shown in Fig. 4, third control circuit 140 further includes 13 transistor T13 and the 4th capacitor C4, wherein the 4th capacitor C4 is connected between the 6th node N6 and the 7th node N7, and The grid of 13rd transistor T13 is connected to the first reference voltage end VGL, and first electrode is connected to second node N2, and Its second electrode is connected to the 7th node N7.

In some embodiments in accordance with the present invention, similar with the effect of first capacitor device C1 and the second capacitor C2, the The presence of four capacitor C4 can be advantageous, because when the current potential at the place the 7th node N7 is low and second clock end CB second When clock signal becomes effective (becoming low level from high level) (such as P2 stage shown in Fig. 3), the 8th transistor T8 and 9th transistor T9 conducting, at this moment can draw more by means of the effect of the 4th capacitor C4 by the current potential of the 7th node N7 It is low, to enhance the driving capability of the 8th transistor T8, it is allowed to be turned or switched on more sufficiently.In addition, increasing between N2 and N7 brilliant The effect of body pipe T13 is that (such as the current potential of above-mentioned 7th node N7 drags down the (electricity lower than N2 by the 4th capacitor C4 if necessary Position) when) the 7th node N7 point is isolated or is disconnected with second node N2 point, it reduces to avoid the current potential of the 7th node N7 to second Node N2 is impacted, and maintains the current potential of N2 point, reduces jump, to guarantee the stability of second transistor T2.

Specifically, the P2 stage shown in Fig. 3, the second clock signal of second clock end CB output is lower by height, the Two node N2 are in low potential, and the 13rd transistor T13 is connected in response to the low-voltage of the first reference voltage end VGL, thus the Seven node N7 are also low potential, the 8th transistor T8 and the 9th transistor T9 conducting, and then the 4th capacitor C4 is by means of capacitor The current potential of 7th node N7 is drawn lower by the effect of device, to enhance the driving capability of the 8th transistor T8；At this moment, due to the 7th The current potential of node N7 reduces and (is lower than N2 point current potential), and the 13rd transistor T13 is ended to a certain extent to reduce from the second section The leakage current that point N2 is flowed through to the 7th node N7 reduces jump so that second node N2 is able to maintain that metastable current potential, with Guarantee the stability of second transistor T2.

Fig. 5 schematically shows the block diagram of the gate driving circuit 500 of the shift-register circuit based on Fig. 2.Such as Fig. 5 institute Showing, gate drivers 500 include N number of cascade shift-register circuit SR (1), SR (2) ..., SR (N-1) and SR (N), Wherein each shift-register circuit can be taken such as the form above for the shift-register circuit 200 described in Fig. 2.N It may be greater than or the integer equal to 2.In gate drivers 500, other than n-th shift-register circuit SR (N), respectively The output end OUT of each of shift-register circuit is connected to the input terminal IN of adjacent next shift-register circuit.

N number of shift-register circuit SR (1) in gate drivers 500, SR (2) ..., SR (N-1) and SR (N) can To be connected respectively to N grid line G [1], G [2] ..., G [N-1] and G [N].Each of each shift-register circuit is also It may be coupled to and be configured to the first reference voltage line vgl of the first reference voltage of transmission, can be configured to transmit the second reference voltage The second reference voltage line vgh, be configured to the first clock line clka and the of the first clock signal of transmission and second clock signal Two clock line clkb.Particularly, (1) shift-register circuit SR, SR (2) ..., the 2k-1 in SR (N-1) and SR (N) First clock end CK of a shift-register circuit and the second clock end CB of the 2k shift-register circuit are connected to first Clock line clka, and shift-register circuit SR (1), SR (2) ..., the 2k-1 displacement in SR (N-1) and SR (N) The second clock end CB of register circuit and the first clock end CK of the 2k shift-register circuit are connected to second clock line Clkb, wherein k is positive integer and 2k≤N.It will be appreciated that the first, second clock signal CK and CB is supplied in this way Shift-register circuit SR (1), SR (2) ..., SR (N-1) and SR (N) should be given, so that each in shift-register circuit It is a all using the sequential operation of identical (but by " time shift ") to sequentially generate output signal as grid unbalanced pulse.

Fig. 6 schematically shows the block diagram of display device 600 according to some embodiments of the invention.With reference to Fig. 6, display device 600 include display panel 610, sequence controller 620, gate drivers 630, data driver 640 and voltage generator 650. Gate drivers 630 can take the form above for gate driving circuit 500 shown in fig. 5, and be shown in FIG. 5 First clock line clka, second clock line clkb, the first reference voltage line vgl and the second reference voltage line vgh in Fig. 6 in order to Diagram is conveniently omitted.

Display panel 610 is connected to the multiple gate lines G L extended in the first direction dl and intersects with first direction D1 The multiple data line DL extended on the second direction D2 of (for example, substantially vertical).Display panel 610 includes being arranged in matrix Multiple pixel (not shown).Each of described pixel may be electrically connected to one grid line sum number of the correspondence in gate lines G L According to the one data line of correspondence in line DL.It is aobvious that display panel 610 can be liquid crystal display panel, Organic Light Emitting Diode (OLED) Show panel or the display panel of any other suitable type.

Sequence controller 620 controls the display panel 610, gate drivers 630, data driver 640 and voltage generator 650 operation.Sequence controller 620 receives input image data RGBD and input control letter from external equipment (for example, host) Number CONT.Input image data RGBD may include multiple input pixel datas for multiple pixels.Each input pixel data It may include for correspondence one red gradation data R, the green gradation data G and blue gradation data B in multiple pixels.It is defeated Entering to control signal CONT may include master clock signal, data enable signal, vertical synchronizing signal, horizontal synchronizing signal etc..Timing Controller 620 is based on input image data RGBD and input control signal CONT and generates output image data RGBD ', the first control Signal CONT1 and second control signal CONT2.Being achieved in that for sequence controller 620 is known in the art.Sequence controller 620 (such as such as utilizing specialized hardware) can realize in many ways to execute a variety of different functions being discussed herein. " processor " is using an example of the sequence controller 620 of one or more microprocessors, and the microprocessor can make It is programmed with software (such as microcode) to execute a variety of different functions being discussed herein.Sequence controller 620 can be with Using or realize in the case where not using processor, and also can be implemented as executing some functions specialized hardware and Execute the combination of the processor of other function.The example of sequence controller 620 includes but is not limited to conventional microprocessor, dedicated Integrated circuit (ASIC) and field programmable gate array (FPGA).

Gate drivers 630 receive first control signal CONT1 from sequence controller 620.First control signal CONT1 can To include via the first, second clock line clka and clkb transmission being shown in FIG. 5 and first, second with opposite phase Clock signal.Gate drivers 630 generate multiple grids for being output to gate lines G L based on first control signal CONT1 and drive Dynamic signal.Multiple gate drive signals sequentially can be applied to gate lines G L by gate drivers 630.

Data driver 640 receives second control signal CONT2 and output image data RGBD ' from sequence controller 620. Data driver 640 is based on second control signal CONT2 and output image data RGBD ' generates multiple data voltages.Data are driven Multiple data voltages of generation can be applied to data line DL by dynamic device 640.

Voltage generator 650 is to display panel 610, sequence controller 620, gate drivers 630, data driver 640 And potentially other component supplies electric power.Specifically, voltage generator 650 is configured to the control in sequence controller 620 The first ginseng that the lower supply of system is transmitted via the first reference voltage line vgl being shown in FIG. 5 and the second reference voltage line vgh respectively Examine voltage and the second reference voltage.The configuration of voltage generator 650 can be known in the art.

In some embodiments in accordance with the present invention, gate drivers 630 and/or data driver 640 may be disposed at On display panel 610, or (Tape Carrier Package, TCP) can be encapsulated by such as tape carrier and be connected to Display panel 610.For example, gate drivers 630 can be incorporated in display panel 610 as array substrate row driving (GOA) Circuit.

The example of display device 600 include but is not limited to mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator.

In some embodiments of the invention, it is as shown in Figure 1 according to some embodiments of the invention also to provide a kind of driving Shift-register circuit 100 method, comprising: to input terminal IN provide input signal；When to the first clock end CK and second Clock end CB provide the first clock signal and second clock signal respectively；The first reference voltage is supplied to the first reference voltage end VGL And the second reference voltage is supplied to the second reference voltage end VGH, wherein the first reference voltage and the second reference voltage are in difference Current potential；And in response to input signal, the first clock signal, second clock signal, the first reference voltage and second with reference to electricity Pressure, executes operations described below by shift-register circuit 100: exporting the output signal by output end OUT.

In some embodiments of above-mentioned driving method according to the present invention, the first reference voltage may be at effective voltage Horizontal and the second reference voltage may be at dead voltage level, and the operation executed by shift-register circuit 100 can be with It specifically includes and is performed the following operations by first control circuit 120: being in effective current potential in response to third node N3, input signal has It imitates and second clock signal is effective, disconnect first node N1 and third node N3.

Using the driving method of above-mentioned shift-register circuit 100 according to some embodiments of the invention, phase can be avoided Adverse effect of the leakage current formed in the technology of pass because transistor non-fully ends to current potential at third node N3, so that it is guaranteed that Transistor in output circuit 150 is fully and stably opened, and guarantees the stability and quality of output signals of output waveform.

While particular embodiments of the present invention have been shown and described, but it is obvious for those skilled in the art It is that can make several changes and modification, therefore, appended claims at its broader aspect in the case where not departing from invention Book should be within its scope comprising all such changes and modification, as fallen within the true spirit and scope of the invention.

Claims

1. a kind of shift-register circuit, comprising:

Input terminal is configured to receive input signal；

First reference voltage end is configured to be applied the first reference voltage；

Second reference voltage end is configured to be applied the second reference voltage；

First clock end is configured to receive the first clock signal；

Second clock end is configured to receive second clock signal；

Output end is configured to output signal output；

Input circuit is configured to the first clock signal, the on-off and the first reference of control signal and first node The on-off of voltage end and second node, and in response to the current potential of first node controls the logical of the first clock end and second node It is disconnected；

First control circuit, is configured to the input signal and the second clock signal, controls first node and the The on-off of three nodes；

Second control circuit is configured to the current potential and the second clock signal of second node, and control second is with reference to electricity The on-off of pressure side and first node；

Third control circuit is configured to the current potential of the first node, controls the second reference voltage end and fourth node On-off control second clock end and fourth node and in response to the current potential and second clock signal of the second node On-off；

Output circuit is configured to the current potential of the third node, controls first reference voltage end and the output The on-off at end, and in response to the current potential of the fourth node controls the logical of second reference voltage end and the output end It is disconnected.

2. shift-register circuit according to claim 1, wherein the first control circuit is further configured to ring Effective current potential, input signal should be in effectively in third node and second clock signal is effective, make first node and third node It disconnects.

3. shift-register circuit according to claim 2, wherein the input circuit includes:

The first transistor, grid are connected to first clock end, and first electrode is connected to the input terminal, and its Two electrodes are connected to the first node；

Second transistor, grid are connected to the first node, and first electrode is connected to first clock end, and its Second electrode is connected to the second node；And

Third transistor, grid are connected to first clock end, and first electrode is connected to first reference voltage end, And its second electrode is connected to the second node.

4. shift-register circuit according to claim 2, wherein the first control circuit includes:

4th transistor, grid are connected to first reference voltage end, and first electrode is connected to the first node, and And its second electrode is connected to the third node；

5th transistor, grid are connected to the input terminal, and first electrode is connected to the 5th node, and its second electrode It is connected to the first node；

First capacitor device is connected between the second clock end and the 5th node；And

Second capacitor is connected between the third node and the second clock end.

5. shift-register circuit according to claim 2, wherein the second control circuit include the 6th transistor and 7th transistor, wherein the grid of the 6th transistor is connected to the second node, first electrode is connected to second ginseng Voltage end is examined, and its second electrode connects the first electrode of the 7th transistor；And the 7th transistor grid be connected to it is described Second clock end, first electrode is connected to the second electrode of the 6th transistor, and its second electrode is connected to described first Node.

6. shift-register circuit according to claim 2, wherein the third control circuit includes:

8th transistor, grid are connected to the second node, and first electrode is connected to the second clock end, and second Electrode connects the 6th node；

9th transistor, grid are connected to the second clock end, and first electrode is connected to the 6th node, and its Second electrode is connected to the fourth node；

Tenth transistor, grid are connected to the first node, and first electrode is connected to second reference voltage end, and And its second electrode is connected to the fourth node.

7. shift-register circuit according to claim 2, wherein the output circuit includes:

11st transistor, grid are connected to the fourth node, and first electrode is connected to second reference voltage end, And its second electrode is connected to the output end；

Tenth two-transistor, grid are connected to the third node, and first electrode is connected to first reference voltage end, And its second electrode is connected to the output end.

8. shift-register circuit according to claim 7, wherein the output circuit further comprises third capacitor, It is connected between the fourth node and second reference voltage end.

9. shift-register circuit according to claim 6, wherein the third control circuit further comprises:

13rd transistor, grid are connected to first reference voltage end, and first electrode is connected to the second node, And its second electrode is connected to the 7th node；

4th capacitor is connected between the 6th node and the 7th node.

10. shift-register circuit according to claim 1, wherein the input circuit, the output circuit, described The transistor that one control circuit, the second control circuit and the third control circuit respectively include is single gridistor.

11. shift-register circuit according to claim 10, wherein the transistor is N-type transistor or is P-type transistor.

12. a kind of gate driving circuit, including N number of cascade shift register described in any one of -11 according to claim 1 Circuit, N are integer more than or equal to 2, wherein in N number of shift-register circuit, m-th shift-register circuit it is defeated Outlet is connected to the input terminal of the m+1 shift-register circuit, and m is integer and 1≤m < N.

13. a kind of display panel, comprising:

First reference voltage line is configured to the first reference voltage of transmission；

Second reference voltage line is configured to the second reference voltage of transmission；

First clock line and second clock line are configured to the first clock signal of transmission and second clock signal, first clock Signal and the second clock signal have opposite phase；And

Gate driving circuit according to claim 12,

Wherein each first reference voltage end of N number of shift-register circuit is connected to first reference voltage line,

Wherein each second reference voltage end of N number of shift-register circuit is connected to second reference voltage line,

Wherein the first clock end of the 2k-1 shift-register circuit in N number of shift-register circuit and the 2k shifting The second clock end of bit register circuit is connected to first clock line, and

Wherein the second clock end of the 2k-1 shift-register circuit in N number of shift-register circuit and the 2k shifting First clock end of bit register circuit is connected to the second clock line, and k is positive integer and 2k≤N.

14. a kind of display device, comprising:

Display panel according to claim 13；

Sequence controller is configured to control the operation of the display panel, wherein the sequence controller is configured to institute It states the first clock line and the second clock line supplies first clock signal and the second clock signal respectively, described One clock signal and the second clock signal have opposite phase；And

Voltage generator is configured under the control of the sequence controller to first reference voltage line and described second Reference voltage line supplies first reference voltage and second reference voltage respectively.

15. a kind of method for driving shift-register circuit according to any one of claim 1 to 11, comprising:

The input signal is provided to the input terminal；

First clock signal and second clock letter are provided respectively to first clock end and the second clock end Number；

First reference voltage and described are supplied respectively to first reference voltage end and second reference voltage end Two reference voltages, wherein first reference voltage and second reference voltage are in different current potentials；And

In response to the input signal, first clock signal, the second clock signal, first reference voltage and institute The second reference voltage is stated, operations described below is executed by the shift-register circuit:

The output signal is exported by the output end.

16. according to the method for claim 15, wherein first reference voltage is in, effective voltage is horizontal and second joins It examines voltage and is in dead voltage level, and the operation executed by the shift-register circuit further comprises by first Control circuit executes operations described below:

It is in that effective current potential, the input signal are effective and the second clock signal is effective in response to the third node, makes The first node and the third node disconnect.