CN212675894U - Grid driving circuit and display device thereof - Google Patents
Grid driving circuit and display device thereof Download PDFInfo
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- CN212675894U CN212675894U CN202021117643.1U CN202021117643U CN212675894U CN 212675894 U CN212675894 U CN 212675894U CN 202021117643 U CN202021117643 U CN 202021117643U CN 212675894 U CN212675894 U CN 212675894U
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Abstract
Disclosed is a gate driving circuit including a plurality of cascaded gate driving units, each gate driving unit including: the pre-charging module charges the first node according to the preceding-stage transmission signal; the pull-down module discharges the first node according to the post-stage transmission signal; the output module generates a current-stage transmission signal according to any one of the clock signals in the first clock signal group and the voltage of the first node, and generates a plurality of current-stage gate driving signals according to a plurality of clock signals in the second clock signal group and the voltage of the first node; the stabilizing module is used for stabilizing the voltage of the first node and maintaining the transmission signal and the plurality of gate driving signals at a low level signal. The grid driving circuit keeps the voltage of a Q point unchanged through the stabilizing module, guarantees the consistency of waveform output of a plurality of grid driving signals, and reduces the generation of bright lines.
Description
Technical Field
The utility model relates to a show technical field, in particular to gate drive circuit and display device thereof.
Background
In recent years, liquid crystal displays have been widely used as display devices because of their characteristics of high-quality image display capability and low power consumption.
In the case of a liquid crystal display, the display panel is mainly driven by a driving circuit, and the driving circuit includes a gate driving circuit and a source driving circuit. The grid driving circuit sequentially generates grid signals to be transmitted on the grid lines for driving the display panel. Fig. 1 shows a schematic structural diagram of a display panel according to the prior art. The display panel 100 includes a display region 110, a source driving circuit 120, and a gate driving circuit 130. The display region 110 includes an array formed by a plurality of data lines (N data lines DL 1-DLN) and a plurality of gate lines (M gate lines GL 1-GLM) alternately arranged, and a plurality of pixel units 115, and the pixel units 115 are arranged in the array. The source driving circuit 120 is coupled to the data lines DL 1-DLN and transmits data signals to the display area 110 through the data lines, and the gate driving circuit is coupled to the gate lines GL 1-GLM and transmits gate driving signals to the display area 110 through the gate lines. Each pixel unit 115 comprises a first thin film transistor T and a liquid crystal capacitor CLCAnd a storage capacitor CSTAnd the grid electrode of the first thin film transistor T is connected with the grid line. In the gate driving circuit, the channel layer of the thin film transistor may be made of amorphous silicon or Indium Gallium Zinc Oxide (IGZO) or the like. However, in the gate driving circuits made of two materials, the gate driving circuit of the amorphous silicon element is designed based on the Enhance mode, and the gate driving circuit of the IGZO element needs to be designed based on the Depletion mode. Therefore, when the gate driving circuit is made of Indium Gallium Zinc Oxide (IGZO), the gate driving circuit design of the amorphous silicon device cannot be used, otherwise, the leakage current phenomenon is likely to occur, so that the ripple phenomenon of the output signal is generated.
SUMMERY OF THE UTILITY MODEL
In view of the above problem, an object of the present invention is to provide a gate driving circuit, which maintains the voltage of the Q point through a stabilizing module, thereby ensuring the output consistency of a plurality of gate driving signal waveforms and reducing the generation of bright lines.
According to an aspect of the present invention, there is provided a gate driving circuit, the gate driving circuit includes a plurality of cascaded gate driving units, and each gate driving unit includes:
the pre-charging module is connected with the output end of the grid driving unit of the previous stage and charges the first node according to the preceding stage transmission signal;
the pull-down module is connected with the output end of the next-stage grid drive unit and discharges the first node according to the post-stage transmission signal;
the output module is connected with the pre-charging module and the pull-down module and is used for generating a current-stage transmission signal according to any one clock signal in the first clock signal group and the voltage of the first node and generating a plurality of current-stage gate driving signals according to a plurality of clock signals in the second clock signal group and the voltage of the first node;
and the stabilizing module is connected with the output module and the first node so as to stabilize the voltage of the first node and maintain the transmission signal and the plurality of gate driving signals at a low level signal.
Preferably, the pre-charge module includes:
the control end of the first transistor receives a previous stage transmission signal, the first end of the first transistor receives one previous stage grid driving signal in a plurality of previous stage grid driving signals, and the second end of the first transistor is connected with the first node.
Preferably, when the gate driving unit is a first-stage gate driving unit, the control end of the first transistor receives a first start signal, and the first end of the first transistor receives a second start signal.
Preferably, the output module includes:
a control end of the second transistor is connected with the first node, a first end of the second transistor receives any clock signal in the first clock signal group, a second end of the second transistor is connected with a first output end of the grid driving circuit, and the first output end is a current-stage transmission signal end;
a control end of the third transistor is connected with the first node, a first end of the third transistor receives any clock signal in the second clock signal group, a second end of the third transistor is connected with a second output end of the grid driving circuit, and the second output end is a first grid driving signal end of the current stage;
a control end of the fourth transistor is connected with the first node, a first end of the fourth transistor receives any unselected clock signal in the second clock signal group, a second end of the fourth transistor is connected with a third output end of the gate driving circuit, and the third output end is a second gate driving signal end of the current stage;
a fifth transistor, a control terminal of which is connected to the first node, a first terminal of which is connected to receive any unselected clock signal in the second clock signal group, a second terminal of which is connected to a fourth output terminal of the gate driving circuit, and the fourth output terminal is a third gate driving signal terminal of the current stage;
and the capacitor is connected between the control end and the second end of the second transistor.
Preferably, the stabilizing module comprises:
a sixth transistor having a control terminal and a first terminal connected to a power supply voltage;
a control end of the seventh transistor is connected with the first node, a first end of the seventh transistor is connected with a second end of the sixth transistor, and the second end of the seventh transistor receives a second low-voltage signal;
a control end of the eighth transistor is connected with a second end of the sixth transistor, and the second end of the eighth transistor is connected with the first node;
a ninth transistor, a control terminal of which is connected to the second terminal of the sixth transistor, a first terminal of which receives the second low voltage signal, and a second terminal of which is connected to the first terminal of the eighth transistor;
a control end of the tenth transistor is connected with a second end of the sixth transistor, a first end of the tenth transistor receives the second low-voltage signal, and a second end of the tenth transistor is connected with the current-stage transmission signal end;
the control end of the eleventh transistor is connected with the second end of the sixth transistor, the first end of the eleventh transistor receives the first low-voltage signal, and the second end of the eleventh transistor is connected with the current-stage first gate drive signal end;
a control end of the twelfth transistor is connected with a second end of the sixth transistor, a first end of the twelfth transistor receives the first low-voltage signal, and a second end of the twelfth transistor is connected with a current-stage second gate drive signal end;
and the control end of the thirteenth transistor is connected with the second end of the sixth transistor, the first end of the thirteenth transistor receives the first low-voltage signal, and the second end of the thirteenth transistor is connected with the third grid driving signal end of the current stage.
Preferably, the pull-down module includes:
and the control end of the fourteenth transistor is connected with the rear-stage signal transmission end, the first end of the fourteenth transistor is connected with any one rear-stage grid driving signal end, and the second end of the fourteenth transistor is connected with the first node.
Preferably, after the first node is precharged, the power supply voltage reaches the first node via the sixth transistor, the seventh transistor, the ninth transistor, and the eighth transistor, and the potential level of the first node is maintained.
Preferably, the first clock signal group includes a plurality of clock signals with a duty ratio of 1/3 and a voltage range of-11V to 18V, and the second clock signal group includes a plurality of clock signals with a duty ratio of 1/9 and a voltage range of-7V to 18V.
Preferably, the plurality of clock signals of the first clock signal group are different in phase, and the plurality of clock signals of the second clock signal group are different in phase.
According to another aspect of the present invention, there is provided a display device including the gate driving circuit as described above.
The utility model provides a gate drive circuit has adopted the design of new stable first node Q voltage, has guaranteed the stability of the voltage of Q point, has reduced the condition and the bright line problem of electric leakage, has simplified circuit design, has increased the design space, is favorable to realizing narrow frame and reduction circuit consumption.
The utility model provides a gate drive circuit because four second ends have used the clock signal of four different phases, when charging to the pixel unit, has reduced the overlapping cycle of wave form in the adjacent gate line, has reduced the striae condition when showing, has improved display device's quality.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic structural diagram of a display panel according to the prior art;
fig. 2 shows a block diagram of a gate driving unit according to an embodiment of the present invention;
fig. 3 shows a circuit schematic of a gate drive unit according to an embodiment of the invention;
fig. 4 shows a schematic structural diagram of a 3-stage gate driving unit in a gate driving circuit according to an embodiment of the present invention;
FIG. 5 shows a timing diagram of control signals of the gate driving circuit of FIG. 4;
fig. 6 shows an operation waveform diagram of the gate driving unit according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.
Fig. 2 shows a structure diagram of a gate driving unit according to an embodiment of the present invention, and fig. 3 shows a circuit schematic diagram of a gate driving unit according to an embodiment of the present invention. The gate driving unit 200 is, for example, an i (i ≧ 1) th-stage gate driving unit in the gate driving circuit, and can be used for the gate driving circuit 130 shown in fig. 1, wherein the gate driving circuit 130 includes a plurality of cascaded gate driving units 200, and each gate driving unit 200 can output three gate driving signals to three gate lines, respectively.
Referring to fig. 2 and 3, each stage of the gate driving unit 200 includes preceding stage signal input terminals Zn-1, Gn-1, following stage signal input terminals Zn +1, Gn +3, a first clock signal terminal CLK1, a second clock signal terminal CLK4, a third clock signal terminal CLK5, a fourth clock signal terminal CLK6, first and second low-level signal terminals VGL and VGL1, and a present stage first output terminal Zn, a present stage second output terminal Gn, a present stage third output terminal Gn +1, and a present stage fourth output terminal Gn + 2. Specifically, the gate driving unit 200 includes a pre-charging module 210, a pull-down module 220, an output module 230, and a stabilizing module 240.
Specifically, the pre-charge module 210 is coupled to a previous stage signal input terminal for receiving a previous stage gate driving signal Gn-1 and a previous stage transfer signal Zn-1 of a previous stage gate driving unit, and has an output terminal coupled to the first node Q for pre-charging the first node Q according to the previous stage gate driving signal Gn-1 and the previous stage transfer signal Zn-1. For example, when the previous stage transfer signal Zn-1 is high, the previous stage gate driving signal Gn-1 is supplied to the first node Q. Referring to fig. 3, the precharge module 210 includes a first transistor T1, a control terminal of the first transistor T1 is connected to the previous stage transfer signal Zn-1, a first terminal is connected to the previous stage gate driving signal Gn-1, and a second terminal is connected to the first node Q.
In other embodiments, when the gate driving unit 200 is the first stage of a plurality of gate driving units in which gate driving circuits are cascaded, the precharge module 210 precharges the first node Q according to the first start signal STV1 and the second start signal STV2, that is, the control terminal of the first transistor T1 is connected to the first start signal STV1, and the first terminal is connected to the second start signal terminal STV 2.
The pull-down module 220 is connected to the first node Q, and connected to the post-stage gate driving signal Gn +3 and the post-stage transfer signal Zn +1, and configured to pull down the potential of the Q point according to the post-stage gate driving signal Gn +3 and the post-stage transfer signal Zn +1, and further pull down the first gate driving signal Gn, the second gate driving signal Gn +1, and the third gate driving signal Gn +2 of the present stage. Specifically, the pull-down module 220 includes a fourteenth transistor T14, a control terminal of the fourteenth transistor T14 is connected to the post-stage transmission signal Zn +1, and a first terminal is connected to the post-stage gate driving signal Gn + 3.
The output module 230, connected to the precharge module 210 and the pull-down module 220, is connected to the Q point, and includes four clock signal input terminals and four output terminals. When the potential of the point Q is at a high level, the first output terminal Zn outputs the first clock signal CLK1 as the present-stage transfer signal Zn, the second output terminal Gn outputs the second clock signal CLK4 as the present-stage first gate drive signal Gn, the third output terminal Gn +1 outputs the third clock signal CLK5 as the present-stage second gate drive signal Gn +1, and the fourth output terminal Gn +2 outputs the fourth clock signal CLK6 as the present-stage third gate drive signal Gn + 2.
In this embodiment, the output module 230 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a capacitor C1. The control terminal of the second transistor T2 is connected to the point Q, the first terminal is connected to the first clock signal CLK1, the second terminal is connected to the first output terminal Zn, and is configured to output the first clock signal CLK1 as the present-stage transfer signal Zn, and the capacitor C1 is connected between the control terminal and the second terminal of the second transistor T2. The third transistor T3 has a control terminal connected to the point Q, a first terminal connected to the second clock signal CLK4, and a second terminal connected to the second output terminal Gn, for outputting the second clock signal CLK4 as the current-stage first gate driving signal Gn. The fourth transistor T4 has a control terminal connected to the point Q, a first terminal connected to the third clock signal CLK5, and a second terminal connected to the third output terminal Gn +1, for outputting the third clock signal CLK5 as the present-stage second gate driving signal Gn + 1. The fifth transistor T5 has a control terminal connected to the point Q, a first terminal connected to the fourth clock signal CLK6, and a second terminal connected to the fourth output terminal Gn +2, for outputting the fourth clock signal CLK6 as the present-stage third gate driving signal Gn + 2.
In this embodiment, as will be understood by those skilled in the art, there are a total of 12 clock signals CLK 1-CLK 12, which are divided into two groups, wherein the first clock signal group includes CLK 1-CLK 3 as signal transmission groups with voltages of-11V-18V, and in the gate driving circuit, the clock signals CLK 1-CLK 3 of the signal transmission groups are connected to the first clock signal terminal, which is only one of the cascaded gate driving units in fig. 2 and 3, for example, the first clock signal terminal may also be connected to CLK2 or CLK 3. The second clock signal group includes CLK4 to CLK12 as driving signal groups having voltages of-7V to 18V, and the gate driving circuit is not limited to CLK4 to CLK6, but the second to fourth clock signal terminals are connected to any three of the clock signals CLK4 to CLK12 of the driving signal groups, respectively.
The stabilizing module 240 is connected to the precharge module 210, the pull-down module 220 and the output module 230, and receives the power voltage signal VDD and the first and second low level signals VGL and VGL1 for maintaining the voltage level of the Q point and providing the first and second low level signals VGL and VGL1 to the first to fourth output terminals Zn to Gn +2, respectively.
In this embodiment, the stabilizing module 240 includes sixth to thirteenth transistors T6 to T13, a control terminal of the sixth transistor T6 receives the power voltage signal VDD, a first terminal is connected to the control terminal, and a second terminal is connected to the control terminals of the eighth to thirteenth transistors T8 to T13 and a second terminal of the seventh transistor T7. The ninth transistor T9 has a first terminal connected to the second low level signal VGL1, a second terminal connected to a first terminal of the eighth transistor T8, and a second terminal connected to a point Q of the eighth transistor T8. The tenth transistor T10 has a first terminal connected to the second low level signal VGL1 and a second terminal connected to the first output terminal Zn. The eleventh transistor T11 has a first terminal connected to the first low level signal VGL and a second terminal connected to the second output terminal Gn. The twelfth transistor T12 has a first terminal connected to the first low level signal VGL and a second terminal connected to the third output terminal Gn + 1. The thirteenth transistor T13 has a first terminal connected to the first low level signal VGL and a second terminal connected to the fourth output terminal Gn + 2.
In this embodiment, the second terminal of the sixth transistor T6 is always at a high level, and thus the eighth to thirteenth transistors T8 to T13 are always in an on state. At this time, when the Q point is a high voltage, the seventh transistor T7 is turned on, and the high voltage of the second terminal of the sixth transistor T6 reaches the Q point from the second terminal of the seventh transistor T7 to the first terminal and via the ninth transistor T9 and the eighth transistor T8, the stability of the Q point voltage can be maintained according to this loop when the Q point voltage fluctuates.
In the gate driving unit of the present application, the pre-charge module 210, the pull-down module 220, the output module 230 and the stabilization module 240 share the Q point, and the voltage of the Q point is stabilized by the stabilization module 240, so that not only the bootstrap capability of the Q point is ensured, but also the voltage of the Q point can be maintained at the same voltage when the gate outputs by the coupling effect of the waveform.
Fig. 4 shows a schematic structural diagram of a 3-stage gate driving unit in a gate driving circuit according to an embodiment of the present invention.
The display device 300 includes a gate driving circuit 330, a source driving circuit (not shown in fig. 4), and the display panel 110. In the display panel 110, a plurality of pixel units are arranged in an array, and the pixel units in the same row are connected and a Gate line is drawn out to an edge area of the display panel 110, thereby forming Gate lines Gate1 to Gate9, as shown in fig. 4.
The Gate driving circuit 330 is, for example, an integrated Gate driving circuit (GIA), and includes a plurality of Gate driving units 200 cascaded in sequence. The gate driving units 200 are respectively connected to the gate lines of the display panel 110, and select the pixel units of the display panel 110 by rows through the gate lines, and provide corresponding gray scale signals by columns through the data lines to realize image display. In this embodiment, each Gate driving unit 200 includes three Gate driving signal output terminals, so that only three Gate driving units 200 are required to drive 9 Gate lines Gate 1-Gate 9 led out from the display panel 110.
In a preferred embodiment, the gate driving circuit 330 is a double-sided structure and includes two sets of gate driving units, which are respectively disposed at the left and right sides of the display panel 110 in a cascade manner and include a first portion 330a and a second portion 330 b. The first portion 330a includes a first set of cascaded gate drive units Stage1 through Stage3, and the second portion 330b includes a second set of cascaded gate drive units Stage1 through Stage 3.
In a preferred embodiment, each gate line is driven by two sets of gate driving units, respectively, as shown in fig. 4. The Gate line Gate1 is commonly driven by the Gate driving unit Stage1 in the first portion 330a and the Gate driving unit Stage1 in the second portion 330b, so that bidirectional driving is realized, and the driving capability of the Gate driving circuit can be further improved.
In the gate driving unit 200 of each stage, the first clock signal terminal is connected to any one of the plurality of first clock signal groups CLK 1-CLK 3 to receive the clock signal, and the second clock signal terminal to the fourth clock signal terminal are connected to any three of the plurality of second clock signal groups CLK 4-CLK 12 to receive the clock signal. For example, the gate driving unit Stage1 is connected to CLK1, CLK4, CLK5, and CLK6, respectively, and the gate driving unit Stage2 is connected to CLK2, CLK7, CLK8, and CLK9, respectively.
When the gate driving unit 200 is a first stage gate driving unit, its connection ports to the previous stage signal input terminals Zn-1 and Gn-1 are connected to the first start signal line STV1 and the second start signal line STV 2.
The utility model discloses gate drive unit 200, pre-charge module 210, pull-down module 220, output module 230 and stabilizing module 240 share the Q point, and stabilizing module 240 has improved the stability of Q point voltage to electric leakage phenomenon has been reduced.
Fig. 5 shows a timing diagram of control signals of the gate driving circuit in fig. 4.
As shown in the figure, the clock signals CLK 1-CLK 12 are square wave signals with a clock period of 9T, wherein the first clock signal group comprises CLK 1-CLK 3 with a duty ratio of 1/3 and a voltage range of-11V-18V, the second clock signal group comprises CLK 4-CLK 12 with a duty ratio of 1/9 and a voltage range of-7V-18V, and T is a predetermined clock period, for example, the minimum clock period of the system clock signal or an integer multiple thereof.
The first start signal STV1 and the second start signal line STV2 are single pulse signals, the high level duration of the first start signal STV1 is 3T and the voltage range is-11V to 18V, and the high level duration of the second start signal STV2 is 1T and the voltage range is-7V to 18V.
In this embodiment, the second start signal STV2 and the first start signal STV1 have falling edges at the same time. Meanwhile, the clock signals CLK1 and CLK4 start at the falling edges of the second start signal STV2 and the first start signal STV1, the clock signals CLK2 and CLK3 are delayed by 3T in phase sequence compared to the clock signal CLK1, and the clock signals CLK5 to CLK12 are delayed by T in phase sequence compared to the clock signal CLK 4.
Fig. 6 shows an operation waveform diagram of the gate driving unit according to the embodiment of the present invention, in which the abscissa represents time T and the ordinate represents signal level V, and the first Stage gate driving unit Stage1 is taken as an example and described in detail below with reference to fig. 3 and 6.
As described above, the Stage gate driving unit Stage1 has the front Stage signal input terminal for receiving the first start signal STV1 and the second start signal STV2, the rear Stage signal input terminal for receiving the rear Stage transfer signal Z2 and the rear Stage driving signal G4, the first to fourth clock signal terminals for receiving the clock signals CLK1, CLK4, CLK5 and CLK6, and the two low level signal terminals for receiving the first low level signal VGL and the second low level signal VGL 1.
In the first stage, i.e., the stages T1 to T2, when the first start signal STV1 changes from low level to high level, the first transistor T1 is turned on, the first transistor T1 supplies the second start signal STV2 to the first node Q, the Q-point is precharged when the second start signal STV2 changes from high level to low level, the potential of the Q-point changes from low level to high level, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned on. Since the control terminal and the first terminal of the sixth transistor T6 are both connected to the power supply voltage VDD, and the second terminal is at a high level, the eighth transistor T8 to the thirteenth transistor T13, whose control terminals are connected to the second terminal of the sixth transistor T6, are turned on, the first low-level signal VGL passes through the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 to reach the second output terminal Gn, the third output terminal Gn +1, and the fourth output terminal Gn +2, respectively, and the power supply voltage VDD reaches the Q point through the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the eighth transistor T8, thereby maintaining the high voltage at the Q point.
In the second phase, i.e., the phases T2 to T3, the clock signal CLK1 and the clock signal CLK4 are turned on at the falling edge of the first start signal STV1, and since the second transistor T2 and the third transistor T3 are in the turned-on state, the clock signal CLK1 and the clock signal CLK4 reach the first output terminal Zn and the second output terminal Gn via the second transistor T2 and the third transistor T3, respectively. The start timings of the clock signals CLK5 and CLK6 are sequentially delayed by one clock cycle compared to CLK, and thus, the arrival of the clock signals CLK5 and CLK6 at the third output terminal Gn +1 and the fourth output terminal Gn +2 via the second transistor T5 and the third transistor T6, respectively, is also delayed by one clock cycle.
In this embodiment, the capacitor C1 between the control terminal and the second terminal of the second transistor T2 keeps the voltage of the first node Q in a relatively stable state.
In the third stage, i.e., the stages T3 to T4, the clock signal becomes low, the outputs of the first to fourth output terminals Zn to Gn +2 become low, and at the same time, the potential of the first node Q is pulled low by the coupling action of the capacitor C1, and the seventh transistor T7 is turned off.
After the fourth stage T4, the pull-down module 220 is connected to the signal output terminal of the next stage, and since the signal output terminal of the next stage is at a low level, the voltage at the point Q is pulled down, and since the seventh transistor T7 is turned off, and the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned on, the second low-level signal VGL1 reaches the point Q through the eighth transistor T8 and the ninth transistor T9, and stabilizes the potential at the point Q to a low level through the tenth transistor T10 to the first output terminal Zn, and since the second transistor T2 to the fifth transistor T5 are continuously turned off, the potentials at the first output terminal Zn to the fourth output terminal Gn +2 stabilize to a low level.
The grid driving circuit adopts the new design of stabilizing the Q voltage of the first node, ensures the stability of the voltage of the Q point, reduces the electric leakage condition and the bright line problem, simplifies the circuit design, increases the design space, and is favorable for realizing a narrow frame and reducing the power consumption of the circuit.
The gate driving circuit provided by the application has the advantages that the four output ends use the clock signals with different phases, so that when the pixel units are charged, the overlapping period of waveforms in adjacent gate lines is reduced, the cross striation condition during display is reduced, and the quality of the display device is improved.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A gate drive circuit comprising a plurality of cascaded gate drive units, each gate drive unit comprising:
the pre-charging module is connected with the output end of the grid driving unit of the previous stage and charges the first node according to the preceding stage transmission signal;
the pull-down module is connected with the output end of the next-stage grid drive unit and discharges the first node according to the post-stage transmission signal;
the output module is connected with the pre-charging module and the pull-down module and is used for generating a current-stage transmission signal according to any one clock signal in the first clock signal group and the voltage of the first node and generating a plurality of current-stage gate driving signals according to a plurality of clock signals in the second clock signal group and the voltage of the first node;
and the stabilizing module is connected with the output module and the first node so as to stabilize the voltage of the first node and maintain the transmission signal and the plurality of gate driving signals at a low level signal.
2. The gate driving circuit of claim 1, wherein the pre-charge module comprises:
the control end of the first transistor receives a previous stage transmission signal, the first end of the first transistor receives one previous stage grid driving signal in a plurality of previous stage grid driving signals, and the second end of the first transistor is connected with the first node.
3. A gate driving circuit as claimed in claim 2, wherein when the gate driving unit is a first stage gate driving unit, the control terminal of the first transistor receives a first enable signal, and the first terminal receives a second enable signal.
4. A gate drive circuit as claimed in claim 1, wherein the output module comprises:
a control end of the second transistor is connected with the first node, a first end of the second transistor receives any clock signal in the first clock signal group, a second end of the second transistor is connected with a first output end of the grid driving circuit, and the first output end is a current-stage transmission signal end;
a control end of the third transistor is connected with the first node, a first end of the third transistor receives any clock signal in the second clock signal group, a second end of the third transistor is connected with a second output end of the grid driving circuit, and the second output end is a first grid driving signal end of the current stage;
a control end of the fourth transistor is connected with the first node, a first end of the fourth transistor receives any unselected clock signal in the second clock signal group, a second end of the fourth transistor is connected with a third output end of the gate driving circuit, and the third output end is a second gate driving signal end of the current stage;
a fifth transistor, a control terminal of which is connected to the first node, a first terminal of which is connected to receive any unselected clock signal in the second clock signal group, a second terminal of which is connected to a fourth output terminal of the gate driving circuit, and the fourth output terminal is a third gate driving signal terminal of the current stage;
and the capacitor is connected between the control end and the second end of the second transistor.
5. A gate drive circuit as claimed in claim 4, wherein the stabilization module comprises:
a sixth transistor having a control terminal and a first terminal connected to a power supply voltage;
a control end of the seventh transistor is connected with the first node, a first end of the seventh transistor is connected with a second end of the sixth transistor, and the second end of the seventh transistor receives a second low-voltage signal;
a control end of the eighth transistor is connected with a second end of the sixth transistor, and the second end of the eighth transistor is connected with the first node;
a ninth transistor, a control terminal of which is connected to the second terminal of the sixth transistor, a first terminal of which receives the second low voltage signal, and a second terminal of which is connected to the first terminal of the eighth transistor;
a control end of the tenth transistor is connected with a second end of the sixth transistor, a first end of the tenth transistor receives the second low-voltage signal, and a second end of the tenth transistor is connected with the current-stage transmission signal end;
the control end of the eleventh transistor is connected with the second end of the sixth transistor, the first end of the eleventh transistor receives the first low-voltage signal, and the second end of the eleventh transistor is connected with the current-stage first gate drive signal end;
a control end of the twelfth transistor is connected with a second end of the sixth transistor, a first end of the twelfth transistor receives the first low-voltage signal, and a second end of the twelfth transistor is connected with a current-stage second gate drive signal end;
and the control end of the thirteenth transistor is connected with the second end of the sixth transistor, the first end of the thirteenth transistor receives the first low-voltage signal, and the second end of the thirteenth transistor is connected with the third grid driving signal end of the current stage.
6. The gate drive circuit of claim 1, wherein the pull-down module comprises:
and the control end of the fourteenth transistor is connected with the rear-stage signal transmission end, the first end of the fourteenth transistor is connected with any one rear-stage grid driving signal end, and the second end of the fourteenth transistor is connected with the first node.
7. A gate driver circuit according to claim 5, wherein after the first node is precharged, the power supply voltage reaches the first node via the sixth transistor, the seventh transistor, the ninth transistor and the eighth transistor, and the potential level of the first node is maintained.
8. The gate driving circuit of claim 1, wherein the first clock signal group comprises a plurality of clock signals with a duty ratio of 1/3 and a voltage range of-11V-18V, and the second clock signal group comprises a plurality of clock signals with a duty ratio of 1/9 and a voltage range of-7V-18V.
9. The gate driving circuit of claim 1, wherein the plurality of clock signals of the first clock signal group are different in phase, and the plurality of clock signals of the second clock signal group are different in phase.
10. A display device comprising the gate driver circuit according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021117643.1U CN212675894U (en) | 2020-06-17 | 2020-06-17 | Grid driving circuit and display device thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021117643.1U CN212675894U (en) | 2020-06-17 | 2020-06-17 | Grid driving circuit and display device thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113658535A (en) * | 2021-08-17 | 2021-11-16 | 深圳市华星光电半导体显示技术有限公司 | Scan control driver and display device |
| CN114944139A (en) * | 2022-06-29 | 2022-08-26 | 昆山龙腾光电股份有限公司 | Multistage output grid transfer circuit and display device |
| CN117456924A (en) * | 2023-12-25 | 2024-01-26 | 惠科股份有限公司 | Driving circuit and display device |
-
2020
- 2020-06-17 CN CN202021117643.1U patent/CN212675894U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113658535A (en) * | 2021-08-17 | 2021-11-16 | 深圳市华星光电半导体显示技术有限公司 | Scan control driver and display device |
| CN113658535B (en) * | 2021-08-17 | 2023-12-22 | 深圳市华星光电半导体显示技术有限公司 | Scan control driver and display device |
| CN114944139A (en) * | 2022-06-29 | 2022-08-26 | 昆山龙腾光电股份有限公司 | Multistage output grid transfer circuit and display device |
| CN114944139B (en) * | 2022-06-29 | 2023-07-25 | 昆山龙腾光电股份有限公司 | Multi-level output grid transfer circuit and display device |
| CN117456924A (en) * | 2023-12-25 | 2024-01-26 | 惠科股份有限公司 | Driving circuit and display device |
| CN117456924B (en) * | 2023-12-25 | 2024-04-19 | 惠科股份有限公司 | Driving circuit and display device |
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