CN114944139A

CN114944139A - Multistage output grid transfer circuit and display device

Info

Publication number: CN114944139A
Application number: CN202210753686.6A
Authority: CN
Inventors: 黄丽玉; 许雅琴; 顾小祥
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2022-08-26
Anticipated expiration: 2042-06-29
Also published as: CN114944139B

Abstract

The invention provides a multi-stage output grid transmission circuit and a display device, wherein the multi-stage output grid transmission circuit comprises multi-stage grid transmission units, each stage of grid transmission unit comprises a pre-charging module, a first output module, a second output module, a third output module, a pull-down module and a stabilizing module, the pre-charging module charges a first node according to a transmission signal output by an n-1 stage grid transmission unit and a second grid signal output by the n-1 stage grid transmission unit, the first output module outputs a first grid signal according to a first clock signal, the second output module outputs a second grid signal according to the second clock signal, the third output module outputs a transmission signal according to the transmission clock signal, the pull-down module pulls down the first node according to the transmission signal output by an n +1 stage grid transmission unit and the first grid signal output by an n +1 stage grid transmission unit, the stabilizing module is used for maintaining low level. The invention reduces the number of devices used for driving the grid electrode and improves the stability of the circuit.

Description

Multistage output grid transfer circuit and display device

Technical Field

The invention relates to the technical field of display driving, in particular to a multi-stage output grid transfer circuit and a display device.

Background

Display devices, such as Liquid Crystal Displays (LCDs), have been widely used in electronic devices, such as high-definition digital televisions, desktop computers, personal digital assistants, notebook computers, mobile phones, and digital cameras, because they have many advantages, such as being light, thin, energy-saving, and radiation-free.

Today, narrow bezel display technology is fast and starts to gradually become the mainstream flat panel display technology. In the conventional TFT-LCD panel adopting the a-Si: H, due to the low a-Si mobility and the large variation and floating of the TFT characteristic along with the manufacturing process, and due to the threshold voltage drift characteristic of amorphous silicon, the pull-down stabilizing transistor can be degraded after being biased for a long time, the stability of the circuit is deteriorated due to the reduction of on-state current, and finally the failure of the circuit can be caused. Therefore, with the increase of resolution and panel load and the requirement of ultra-narrow frame, how to reduce the layout occupation of the gate driving circuit and improve the stability becomes a problem to be solved. Therefore, it is necessary to design a novel high-stability gate driving circuit to improve the output capability and stability of the circuit, so that the circuit can exert stable output capability in a limited layout space.

Disclosure of Invention

In view of the above, the present invention provides a multi-level output gate transfer circuit and a display device, which can reduce the number of devices used for driving gates and improve the stability of the circuit.

The embodiment of the invention provides a multi-stage output grid electrode transfer circuit which comprises multi-stage grid electrode transfer units, wherein each stage of grid electrode transfer unit comprises a pre-charging module, a first output module, a second output module, a third output module, a pull-down module and a stabilizing module. The precharge module is connected with a first node and charges the first node according to a transmission signal output by the (n-1) th-level gate transmission unit and a second gate signal output by the (n-1) th-level gate transmission unit. The first output module and the pre-charging module are connected to the first node, and output a first gate signal at a first output end according to a first clock signal. The second output module and the pre-charging module are connected to the first node, and output a second gate signal at a second output end according to a second clock signal, wherein the periods and duty ratios of the first clock signal and the second clock signal are the same, and the first gate signal and the second gate signal are sent to two adjacent gate lines of the display panel. The third output module and the pre-charging module are connected to the first node, and output a transfer signal at a third output end according to a transfer clock signal, where a high level time period of the transfer clock signal includes a high level time period of the first clock signal and a high level time period of the second clock signal. The pull-down module and the pre-charging module are connected to the first node, and the first node is pulled down to a low level according to the transmission signal output by the (n +1) th-level gate transmission unit and the first gate signal output by the (n +1) th-level gate transmission unit. The stabilizing module is connected to the first node, the first output terminal, the second output terminal, and the third output terminal, and configured to maintain the first node, the first output terminal, the second output terminal, and the third output terminal at a low level when the first node is pulled down to a low level.

Specifically, the pre-charging module includes a first switching element, the first switching element includes a first control terminal, a first pass terminal and a second pass terminal, the first control terminal of the first switching element receives the transmission signal output by the n-1 th stage gate transmission unit, the first pass terminal of the first switching element receives the second gate signal output by the n-1 th stage gate transmission unit, and the second pass terminal of the first switching element is connected to the first node.

Specifically, the first output module includes a second switch element, the second switch element includes a second control terminal, a third pass terminal and a fourth pass terminal, the second control terminal of the second switch element is connected to the first node, the third pass terminal of the second switch element receives the first clock signal, and the fourth pass terminal of the second switch element is connected to the first output terminal.

Specifically, the second output module includes a third switching element including a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switching element being connected to the first node, the fifth path terminal of the third switching element receiving the second clock signal, the sixth path terminal of the third switching element being connected to the second output terminal.

Specifically, the third output module includes a fourth switching element, the fourth switching element includes a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switching element is connected to the first node, the seventh path terminal of the fourth switching element receives the transmission clock signal, and the eighth path terminal of the fourth switching element is connected to the third output terminal.

Specifically, the pull-down module includes a fifth switching element including a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switching element receives the transfer signal output by the (n +1) th stage gate transfer unit, the ninth path terminal of the fifth switching element is connected to the first node, and the tenth path terminal of the fifth switching element receives the first gate signal output by the (n +1) th stage gate transfer unit.

Specifically, the stabilization module includes sixth to nineteenth switching elements. The sixth switching element comprises a sixth control end, an eleventh path end and a tenth path end, the sixth control end of the sixth switching element receives the first control signal, the eleventh path end of the sixth switching element is connected with the sixth control end of the sixth switching element, and the twelfth path end of the sixth switching element is connected to the second node. The seventh switching element includes a seventh control end, a tenth path end, and a tenth path end, the seventh control end of the seventh switching element receives the first control signal, the thirteenth path end of the seventh switching element receives the first low-level signal, and the fourteenth path end of the seventh switching element is connected to the third node. The eighth switching element comprises an eighth control end, a fifteenth path end and a sixteenth path end, the eighth control end of the eighth switching element receives the second control signal, the fifteenth path end of the eighth switching element is connected to the third node, and the sixteenth path end of the eighth switching element is connected to the eighth control end of the eighth switching element. The ninth switching element includes a ninth control terminal, a seventeenth path terminal and an eighteenth path terminal, the ninth control terminal of the ninth switching element receives the second control signal, the seventeenth path terminal of the ninth switching element is connected to the second node, and the eighteenth path terminal of the ninth switching element receives the first low-level signal. The tenth switching element includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal, the tenth control terminal of the tenth switching element is connected to the first node, the nineteenth path terminal of the tenth switching element receives the first low level signal, and the twentieth path terminal of the tenth switching element is connected to the second node. The eleventh switching element includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal, the eleventh control terminal of the eleventh switching element being connected to the first node, the twenty-first path terminal of the eleventh switching element receiving the first low level signal, the twenty-second path terminal of the eleventh switching element being connected to the third node. The twelfth switching element includes a twelfth control terminal, a twentieth path terminal, and a twentieth path terminal, the twelfth control terminal of the twelfth switching element is connected to the second node, the twentieth path terminal of the twelfth switching element is connected to the first node, and the twentieth path terminal of the twelfth switching element receives the first low level signal. The thirteenth switching element includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal, the thirteenth control terminal of the thirteenth switching element is connected to the third node, the twenty-fifth path terminal of the thirteenth switching element receives the first low level signal, and the twenty-sixth path terminal of the thirteenth switching element is connected to the first node. The fourteenth switching element includes a fourteenth control terminal, a twenty-seventh path terminal, and a twenty-eighth path terminal, the fourteenth control terminal of the fourteenth switching element is connected to the second node, the twenty-seventh path terminal of the fourteenth switching element is connected to the first output terminal, and the twenty-eighth path terminal of the fourteenth switching element receives a second low level signal. The fifteenth switching element includes a fifteenth control terminal, a twenty-ninth path terminal and a thirty-third path terminal, the fifteenth control terminal of the fifteenth switching element is connected to the third node, the twenty-ninth path terminal of the fifteenth switching element receives the second low-level signal, and the thirtieth path terminal of the fifteenth switching element is connected to the first output terminal. The sixteenth switching element comprises a sixteenth control terminal, a thirty-first path terminal and a thirty-second path terminal, the sixteenth control terminal of the sixteenth switching element is connected to the second node, the thirty-first path terminal of the sixteenth switching element is connected to the second output terminal, and the thirty-second path terminal of the sixteenth switching element receives the second low-level signal. The seventeenth switching element comprises a seventeenth control end, a thirtieth path end and a thirtieth path end, the seventeenth control end of the seventeenth switching element is connected to the third node, the thirtieth path end of the seventeenth switching element receives the second low-level signal, and the thirtieth path end of the seventeenth switching element is connected to the second output end. The eighteenth switching element includes an eighteenth control terminal, a thirty-fifth path terminal, and a thirty-sixth path terminal, the eighteenth control terminal of the eighteenth switching element is connected to the second node, the thirty-fifth path terminal of the eighteenth switching element is connected to the third output terminal, and the thirty-sixth path terminal of the eighteenth switching element receives the second low-level signal. The nineteenth switching element includes a nineteenth control terminal, a thirty-seventh pass terminal, and a thirty-eighth pass terminal, the nineteenth control terminal of the nineteenth switching element is connected to the third node, the thirty-seventh pass terminal of the nineteenth switching element receives the second low level signal, and the thirty-eighth pass terminal of the nineteenth switching element is connected to the third output terminal.

Specifically, the first control signal and the second control signal are opposite in polarity, and are each reversed in polarity once per frame.

Specifically, the gate transfer unit further includes a first capacitor and a second capacitor, a first end of the first capacitor is connected to the first node, a second end of the first capacitor is connected to the first output terminal, a first end of the second capacitor is connected to the first node, and a second end of the second capacitor is connected to the second output terminal.

Specifically, the duty ratios of the first clock signal and the second clock signal are both 25%.

The embodiment of the invention also provides a display device which comprises the multi-stage output grid electrode transmission circuit.

The multi-stage output grid electrode transfer circuit and the display device provided by the invention reduce the number of devices used for driving the grid electrode, are beneficial to further reducing the area of a layout, and improve the stability of the circuit.

In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a circuit diagram of a gate pass unit according to an embodiment of the invention.

FIG. 2 is a timing diagram of the multi-level output gate pass unit of the embodiment of FIG. 1.

FIG. 3 is a cascaded block diagram of a multi-stage output gate pass circuit according to an embodiment of the invention.

FIG. 4 is a timing diagram of clock signals and gate signals for the embodiment of FIG. 3.

FIG. 5 is a block diagram of the 8-stage output connections of the multi-stage output gate pass circuit according to an embodiment of the invention.

FIG. 6 is a block diagram of the full stage connections of the multi-stage output gate pass circuit of one embodiment of the invention.

Detailed Description

To further illustrate the technical means and effects of the present invention for achieving the intended purpose, the following detailed description is given to specific embodiments, methods, steps, structures, features and effects of the multi-level output gate transfer circuit and the display device according to the present invention with reference to the accompanying drawings and preferred embodiments.

The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. While the invention has been described in connection with specific embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.

Fig. 1 is a circuit diagram of a gate pass unit according to an embodiment of the invention. Referring to fig. 1, the multi-level output gate transfer circuit of the present embodiment includes multi-level gate transfer units, each of which includes: a precharge module 10, a first output module 20, a second output module 40, a third output module 30, a pull-down module 50, and a stabilization module 60.

In the embodiment of the present invention, it is assumed that the current gate transfer unit is the nth-stage gate transfer unit, G2n-1, G2n, and Zn respectively represent the first gate signal, the second gate signal, and the transfer signal output by the nth-stage gate transfer unit, G2n +1, G2n +2, and Zn +1 respectively represent the first gate signal, the second gate signal, and the transfer signal output by the next-stage (nth + 1-stage) gate transfer unit of the present-stage (nth-stage) gate transfer unit, and G2n-3, G2n-2, and Zn-1 respectively represent the first gate signal, the second gate signal, and the transfer signal output by the previous-stage (nth-1-stage) gate transfer unit of the present-stage (nth-stage) gate transfer unit.

The precharge module 10 is connected to the first node Q, and charges the first node Q according to the transfer signal Zn-1 output from the gate transfer unit of the (n-1) th stage and the second gate signal G2n-2 output from the gate transfer unit of the (n-1) th stage.

The first output module 20 and the precharge module 10 are connected to the first node Q, and output the first gate signal G2n-1 at the first output terminal according to the first clock signal CLK 1.

The second output module 40 is connected to the first node Q with the pre-charge module 10, and outputs a second gate signal G2n at a second output terminal according to a second clock signal CLK2, wherein the periods and duty ratios of the first clock signal CLK1 and the second clock signal CLK2 are the same, and the first gate signal G2n-1 and the second gate signal G2n are transmitted to two adjacent gate lines of the display panel.

The third output module 30 and the precharge module 10 are connected to the first node Q, and output the transfer signal Zn at a third output terminal according to the transfer clock signal CLKA, wherein a high period of the transfer clock signal CLKA includes a high period of the first clock signal CLK1 and a high period of the second clock signal CLK 2.

The pull-down module 50 and the pre-charge module 10 are connected to a first node Q, and pull down the first node Q to a low level according to the transfer signal Zn +1 output by the (n +1) th stage gate transfer unit and the first gate signal G2n +1 output by the (n +1) th stage gate transfer unit.

The stabilizing module 60 is connected to the first node Q, the first output terminal, the second output terminal, and the third output terminal, and the stabilizing module 60 is configured to maintain the first node Q, the first output terminal, the second output terminal, and the third output terminal at a low level when the first node Q is pulled down to the low level.

It is noted that, since the first stage gate transfer unit 110 has no gate transfer unit of the previous stage, the second gate signal G2n-2 outputted by the gate transfer unit of the (n-1) th stage and the transfer signal Zn-1 outputted by the gate transfer unit of the (n-1) th stage required by the precharge module 10 of the first stage gate transfer unit 110 need to be provided by external signal circuits, such as the start signal STV1 and the start signal STV2 provided by the timing control circuit directly or via the source driving circuit. Since the last stage gate transfer unit has no next stage gate transfer unit, the first gate signal G2n +1 output by the (n +1) th stage gate transfer unit and the transfer signal Zn +1 output by the (n +1) th stage gate transfer unit required by the pull-down module 50 of the last stage gate transfer unit need to be provided by external signal circuits, such as the end signal STV3 and the end signal STV4 provided directly by the timing control circuit or provided via the source driving circuit.

In an embodiment of the invention, the precharge module 10 may include a first switching element T1, the first switching element T1 includes a first control terminal, a first pass terminal and a second pass terminal, the first control terminal of the first switching element T1 receives the transfer signal Zn-1 output by the n-1 th stage gate transfer unit, the first pass terminal of the first switching element T1 receives the second gate signal G2n-2 output by the n-1 th stage gate transfer unit, and the second pass terminal of the first switching element T1 is connected to the first node Q.

In an embodiment of the present invention, the first output module 20 may include a second switching element T2, the second switching element T2 including a second control terminal, a third path terminal and a fourth path terminal, the second control terminal of the second switching element T2 being connected to the first node Q, the third path terminal of the second switching element T2 receiving the first clock signal CLK1, the fourth path terminal of the second switching element T2 being connected to the first output terminal.

In an embodiment of the present invention, the second output module 40 may include a third switching element T3, the third switching element T3 including a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switching element T3 being connected to the first node Q, the fifth path terminal of the third switching element T3 receiving the second clock signal CLK2, the sixth path terminal of the third switching element T3 being connected to the second output terminal.

In an embodiment of the present invention, the third output module 30 may include a fourth switching element T4, the fourth switching element T4 includes a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switching element T4 is connected to the first node Q, the seventh path terminal of the fourth switching element T4 receives the transfer clock signal CLKA, and the eighth path terminal of the fourth switching element T4 is connected to the third output terminal.

In an embodiment of the present invention, the pull-down module 50 may include a fifth switching element T5, the fifth switching element T5 includes a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switching element T5 receives the transfer signal Zn +1 output from the (n +1) th stage gate transfer unit, the ninth path terminal of the fifth switching element T5 is connected to the first node Q, and the tenth path terminal of the fifth switching element T5 receives the first gate signal G2n +1 output from the (n +1) th stage gate transfer unit.

In an embodiment of the present invention, the stabilizing module 60 may include: a sixth switching element T6, a seventh switching element T7, an eighth switching element T8, a ninth switching element T9, a tenth switching element T10, an eleventh switching element T11, a twelfth switching element T12, a thirteenth switching element T13, a fourteenth switching element T14, a fifteenth switching element T15, a sixteenth switching element T16, a seventeenth switching element T17, an eighteenth switching element T18 and a nineteenth switching element T19.

The sixth switching element T6 includes a sixth control terminal, an eleventh path terminal and a tenth path terminal, the sixth control terminal of the sixth switching element T6 receives the first control signal V1, the eleventh path terminal of the sixth switching element T6 is connected to the sixth control terminal of the sixth switching element T6, and the twelfth path terminal of the sixth switching element T6 is connected to the second node QB 1. The seventh switching element T7 includes a seventh control terminal, a tenth path terminal and a tenth path terminal, the seventh control terminal of the seventh switching element T7 is connected to the eleventh path terminal of the sixth switching element T6 to receive the first control signal V1, the thirteenth path terminal of the seventh switching element T7 receives the first low-level signal VSQ, and the fourteenth path terminal of the seventh switching element T7 is connected to the third node QB 2. The eighth switching element T8 includes an eighth control terminal, a fifteenth path terminal and a sixteenth path terminal, the eighth control terminal of the eighth switching element T8 receives the second control signal V2, the fifteenth path terminal of the eighth switching element T8 is connected to the third node QB2, and the sixteenth path terminal of the eighth switching element T8 is connected to the eighth control terminal of the eighth switching element T8. The ninth switching element T9 includes a ninth control terminal, a seventeenth path terminal and an eighteenth path terminal, the ninth control terminal of the ninth switching element T9 is connected to the sixteenth path terminal of the eighth switching element T8 and receives the second control signal V2, the seventeenth path terminal of the ninth switching element T9 is connected to the second node QB1, and the eighteenth path terminal of the ninth switching element T9 receives the first low level signal VSQ. The tenth switching element T10 includes tenth, nineteenth and twentieth control terminals, the tenth control terminal of the tenth switching element T10 is connected to the first node Q, the nineteenth path terminal of the tenth switching element T10 receives the first low-level signal VSQ, and the twentieth path terminal of the tenth switching element T10 is connected to the second node QB 1. The eleventh switching element T11 includes an eleventh control terminal, a twenty-first path terminal and a twenty-second path terminal, the eleventh control terminal of the eleventh switching element T11 is connected to the first node Q, the twenty-first path terminal of the eleventh switching element T11 is connected to the nineteenth path terminal of the tenth switching element T10 to receive the first low-level signal VSQ, and the twenty-second path terminal of the eleventh switching element T11 is connected to the third node QB 2.

The twelfth switching element T12 includes a twelfth control terminal, a twentieth path terminal, and a twentieth path terminal, the twelfth control terminal of the twelfth switching element T12 is connected to the second node QB1, the twentieth path terminal of the twelfth switching element T12 is connected to the first node Q, and the twentieth path terminal of the twelfth switching element T12 receives the first low level signal VSQ. The thirteenth switching element T13 includes a thirteenth control terminal, a twenty-fifth path terminal and a twenty-sixth path terminal, the thirteenth control terminal of the thirteenth switching element T13 is connected to the third node QB2, the twenty-fifth path terminal of the thirteenth switching element T13 is connected to the twenty-fourth path terminal of the twelfth switching element T12 to receive the first low level signal VSQ, and the twenty-sixth path terminal of the thirteenth switching element T13 is connected to the first node Q. The fourteenth switching element T14 includes a fourteenth control terminal, a twenty-seventh path terminal, and a twenty-eighth path terminal, the fourteenth control terminal of the fourteenth switching element T14 is connected to the second node QB1, the twenty-seventh path terminal of the fourteenth switching element T14 is connected to the first output terminal, and the twenty-eighth path terminal of the fourteenth switching element T14 receives the second low level signal VGL. The fifteenth switching element T15 includes a fifteenth control terminal, a twenty-ninth path terminal and a thirtieth path terminal, the fifteenth control terminal of the fifteenth switching element T15 is connected to the third node QB2, the twenty-ninth path terminal of the fifteenth switching element T15 is connected to the twenty-eighth path terminal of the fourteenth switching element T14 to receive the second low level signal VGL, and the thirtieth path terminal of the fifteenth switching element T15 is connected to the first output terminal. The sixteenth switching element T16 includes a sixteenth control terminal, a thirty-first path terminal, and a thirty-second path terminal, the sixteenth control terminal of the sixteenth switching element T16 is connected to the second node QB1, the thirty-first path terminal of the sixteenth switching element T16 is connected to the second output terminal, and the thirty-second path terminal of the sixteenth switching element T16 receives the second low level signal VGL. The seventeenth switching element T17 includes a seventeenth control terminal, a thirty-third path terminal, and a thirty-fourth path terminal, the seventeenth control terminal of the seventeenth switching element T17 is connected to the third node QB2, the thirty-third path terminal of the seventeenth switching element T17 is connected to the thirty-second path terminal of the sixteenth switching element T16 to receive the second low level signal VGL, and the thirty-fourth path terminal of the seventeenth switching element T17 is connected to the second output terminal. The eighteenth switching element T18 includes an eighteenth control terminal, a thirty-fifth path terminal, and a thirty-sixth path terminal, the eighteenth control terminal of the eighteenth switching element T18 is connected to the second node QB1, the thirty-fifth path terminal of the eighteenth switching element T18 is connected to the third output terminal, and the thirty-sixth path terminal of the eighteenth switching element T18 receives the second low level signal VGL. The nineteenth switching element T19 includes a nineteenth control terminal, a thirty-seventh path terminal, and a thirty-eighth path terminal, the nineteenth control terminal of the nineteenth switching element T19 is connected to the third node QB2, the thirty-seventh path terminal of the nineteenth switching element T19 is connected to the thirty-sixth path terminal of the eighteenth switching element T18, receives the second low level signal VGL, and the thirty-eighth path terminal of the nineteenth switching element T19 is connected to the third output terminal.

In one embodiment of the present invention, the first control signal V1 and the second control signal V2 are low frequency clock signals (i.e. the frequency thereof is lower than the frequency of the clock signals), and the first control signal V1 and the second control signal V2 are alternately at a high level, so that the second control signal V2 is at a low level when the first control signal V1 is at a high level; when the second control signal V2 is at a high level, the first control signal V1 is at a low level. In one embodiment of the present invention, the first control signal V1 and the second control signal V2 have opposite polarities, and the polarities of the first control signal V1 and the second control signal V2 are inverted once every frame. Then, in a stable stage, the first control signal V1 controls the sixth switching element T6 and the seventh switching element T7 to be in a turn-on state and charge the second node QB1 through the turned-on sixth switching element T6 and the turned-on seventh switching element T7 discharges the third node QB2 to the first low level VSQ, or the second control signal V2 controls the eighth switching element T8 and the ninth switching element T9 to be in a turn-on state and charge the third node QB2 through the turned-on eighth switching element T8 and discharge the second node QB1 to the first low level VSQ through the turned-on ninth switching element T9. Accordingly, the first and second control signals V1 and V2 alternately control the second and third nodes QB1 and QB2 to be high and low levels, so that the twelfth, fourteenth, sixteenth, eighteenth, and thirteenth, fifteenth, seventeenth, and nineteenth switching elements T13, T15, T17, T19 connected to the second node QB1, and the thirteenth, fourteenth, and sixteenth switching elements T12, T14, T16, T18 connected to the third node QB2 are alternately turned on. Accordingly, the first node Q alternately receives the first low level signal VSQ through the connected twelfth and thirteenth switching elements T12 and T13, the first output terminal alternately receives the second low level signal VGL through the connected fourteenth and fifteenth switching elements T14 and T15, the second output terminal alternately receives the second low level signal VGL through the connected sixteenth and seventeenth switching elements T16 and T17, and the third output terminal alternately receives the second low level signal VGL through the connected eighteenth and nineteenth switching elements T18 and T19, thereby achieving a stable low level effect.

In an embodiment of the invention, the gate transfer unit further includes a first capacitor C1 and a second capacitor C2, a first terminal of the first capacitor C1 is connected to the first node Q, a second terminal of the first capacitor C1 is connected to the first output terminal, a first terminal of the second capacitor C2 is connected to the first node Q, and a second terminal of the second capacitor C2 is connected to the second output terminal.

In an embodiment of the invention, the first capacitor C1 may be, but is not limited to, an external capacitor between the first node Q and the first output terminal, and the pull-up effect of the voltage of the first node Q can be improved by using the coupling effect of the capacitor. In an embodiment of the invention, the second capacitor C2 may be, but is not limited to, an external capacitor between the first node Q and the second output terminal, and the effect of pulling up the voltage of the first node Q can be improved by using the coupling effect of the capacitor.

In an embodiment of the invention, the duty cycles of the first clock signal CLK1 and the second clock signal CLK2 may be, but are not limited to, 25% each. Thus, in the multi-stage gate transfer units of the multi-stage output gate transfer circuit, the odd-numbered gate transfer units receive the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA of the first group, and the even-numbered gate transfer units receive the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA of the second group, so that the multi-stage output gate transfer circuit can continuously output four-stage gate signals in one cycle of the clock signals by the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA of the two groups. Other similar technical solutions can be obtained by those skilled in the art according to this embodiment, for example, the duty ratios of the second clock signal CLK2 and the first clock signal CLK1 are set to 33.3%, so that the multi-stage gate transfer units of the multi-stage output gate transfer circuit correspond to three groups of the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA, each three-stage gate transfer unit receives the same group of the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA, and the multi-stage output gate transfer circuit can continuously output six stages of gate signals in one period of the clock signals through the three groups of the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA, which all fall within the protection scope of the present invention.

In an embodiment of the present invention, the first to nineteenth switching elements T1 to T19 may be, but not limited to, N-type TFTs, NMOS transistors, N-type triodes, or the like. The corresponding first to nineteenth control terminals of the first to nineteenth switching elements T1 to T19 are gates. The corresponding pass terminals of the first to nineteenth switching elements T1 to T19 are drains or sources.

The following specifically describes embodiments of the present invention and the operation principle thereof by taking the first to nineteenth switching elements T1 to T19 as N-type TFTs and the duty ratios of the first clock signal CLK1 and the second clock signal CLK2 as 25%.

FIG. 2 is a timing diagram of the multi-level output gate pass unit of the embodiment of FIG. 1. The operation of the gate transfer unit of the present embodiment will be described with reference to fig. 1 and fig. 2, and the operation of the gate transfer unit includes four stages, namely, a precharge stage, an output stage, a pull-down stage, and a stabilization stage:

a pre-charging stage:

at time t1, when the transfer signal Zn-1 output by the gate transfer unit of the (n-1) th stage transitions from the low level to the high level, the precharge module 10 controls the first node Q to receive the second gate signal G2n-2 output by the gate transfer unit of the (n-1) th stage. The first node Q is charged when the second gate signal G2n-2 outputted from the gate transfer unit of the (n-1) th stage transitions from low to high at time t 2. Accordingly, the first node Q may be stably pulled up to a high level, so that the first output module 20, the second output module 40, and the third output module 30 enter the working state.

In one embodiment, at time T1, when the first control terminal of the first switching element T1 receives the transmission signal Zn-1 output from the n-1 th stage gate transmission unit and transits from low to high, the first switching element T1 becomes conductive. Accordingly, the first node Q connected to the second path terminal of the first switching element T1 receives the second gate signal G2n-2 output from the n-1 st stage gate transfer unit at the first path terminal of the first switching element T1 through the turned-on first switching element T1. The first node Q is charged when the second gate signal G2n-2 transitions from low to high at time t 2.

In one embodiment, when the first node Q is charged and pulled up to a high level, the second control terminal of the second switching element T2, the third control terminal of the third switching element T3, and the fourth control terminal of the fourth switching element T4 connected to the first node Q become a high level, and the second switching element T2, the third switching element T3, and the fourth switching element T4 become a conducting state, so that the first output module 20, the second output module 40, and the third output module 30 enter an operating state.

In one embodiment, when the first node Q is charged and pulled up to a high level, the tenth control terminal of the tenth switching element T10 and the eleventh control terminal of the eleventh switching element T11 connected to the first node Q become a high level, and the tenth switching element T10 and the eleventh switching element T11 become a conductive state, so that the second node QB1 connected to the twentieth pass terminal of the tenth switching element T10 receives the first low level signal VSQ at the nineteenth pass terminal of the tenth switching element T10 through the conductive tenth switching element T10, the third node QB2 connected to the twenty pass terminal of the eleventh switching element T11 receives the first low level signal VSQ at the twenty-first pass terminal of the eleventh switching element T11 through the conductive eleventh switching element T11. When the second node QB1 and the third node QB2 are at a low level, the corresponding control terminals of the twelfth switching element T12 to the nineteenth switching element T19 are at a low level, the twelfth switching element T12 to the nineteenth switching element T19 are in an off state, and the stabilizing module 60 enters a non-operating state, and has no influence on the first output terminal, the second output terminal, and the third output terminal.

An output stage:

at time t3, the first node Q is pulled high, and the first output terminal of the first output module 20 receives the first clock signal CLK1 and outputs the first gate signal G2n-1 according to the transition of the first clock signal CLK1 from low to high. In one embodiment, the fourth path terminal of the second switching element T2 is connected to the first output terminal, and the first output terminal receives the first clock signal CLK1 at the third path terminal of the second switching element T2 through the turned-on second switching element T2, so that the first output terminal outputs the first gate signal G2 n-1. In one embodiment, the first node Q is also bootstrapped and pulled up (charge pump) by the first capacitor C1, so that the level of the first node Q is further raised, and the second switching element T2 is fully opened.

At time t4, the second output terminal of the second output module 40 receives the second clock signal CLK2 and outputs the second gate signal G2n according to the transition of the second clock signal CLK2 from low to high. In one embodiment, the sixth path terminal of the third switching element T3 is connected to the second output terminal, and the second output terminal receives the second clock signal CLK2 at the fifth path terminal of the third switching element T3 through the turned-on third switching element T3, so that the second output terminal outputs the second gate signal G2 n. In one embodiment, the first node Q is also bootstrapped up (charge pump) by the second capacitor C2, so that the level of the first node Q is further raised, and the third switching element T3 is fully opened.

Meanwhile, since the high level period of the transfer clock signal CLKA includes the high level period of the first clock signal CLK1 and the high level period of the second clock signal CLK2, the transfer clock signal CLKA may also transition from the low level to the high level according to the low level transition of the first clock, and the transfer clock signal CLKA also transitions from the high level to the low level when the high level of the second clock transitions to the low level. A third output terminal of the third output module 30 receives the transfer clock signal CLKA and outputs a transfer signal Zn at a third output terminal. In an embodiment, the eighth path terminal of the fourth switching element T4 is connected to the third output terminal, and the third output terminal receives the propagation clock signal CLKA at the seventh path terminal of the fourth switching element T4 through the turned-on fourth switching element T4, so that the third output terminal outputs the propagation signal Zn.

A pull-down stage:

at time t5, when the transfer signal Zn +1 output by the gate transfer unit of the (n +1) th stage transitions from the low level to the high level, the pull-down module 50 controls the first node Q to receive the first gate signal G2n +1 output by the gate transfer unit of the (n +1) th stage, and then at time t6, when the first gate signal G2n +1 output by the gate transfer unit of the (n +1) th stage transitions from the high level to the low level, the first node Q is pulled down. Accordingly, the first node Q may be stably pulled down to a low level, so that the first output module 20, the second output module 40, and the third output module 30 enter a non-operation state.

In one embodiment, at time T5, when the fifth control terminal of the fifth switching element T5 receives the transfer signal Zn +1 output from the (n +1) th stage gate transfer unit and jumps from a low level to a high level, the fifth switching element T5 becomes a conducting state. Accordingly, the first node Q connected to the ninth path terminal of the fifth switching element T5 receives the first gate signal G2n +1 output from the (n +1) th stage gate transfer unit on the tenth path terminal of the fifth switching element T5 through the turned-on fifth switching element T5. Then at time t6, when the first gate signal G2n +1 transitions from high to low, the first node Q is pulled down.

In one embodiment, when the first node Q is pulled down to a low level, the second control terminal of the second switching element T2, the third control terminal of the third switching element T3, and the fourth control terminal of the fourth switching element T4 connected to the first node Q become a low level, and the second switching element T2, the third switching element T3, and the fourth switching element T4 become an open state, so that the first output block 20, the second output block 40, and the third output block 30 enter a non-operation state.

In one embodiment, when the first node Q is pulled down to a low level, the tenth control terminal of the tenth switching element T10 and the eleventh control terminal of the eleventh switching element T11 connected to the first node Q become a low level, and the tenth switching element T10 and the eleventh switching element T11 become an off state. Meanwhile, since the first control signal V1 is opposite in polarity to the second control signal V2, the first control signal V1 controls the sixth switching element T6 and the seventh switching element T7 to be in a turn-on state and charges the second node QB1 through the turned-on sixth switching element T6, and the turned-on seventh switching element T7 discharges the third node QB2 to the first low level VSQ, or the second control signal V2 controls the eighth switching element T8 and the ninth switching element T9 to be in a turn-on state and charges the third node QB2 through the turned-on eighth switching element T8, and discharges the second node QB1 to the first low level VSQ through the turned-on and ninth switching element T9. Accordingly, the first and second control signals V1 and V2 alternately control the second and third nodes QB1 and QB2 to be high and low levels, so that the twelfth, fourteenth, sixteenth, eighteenth and thirteenth switching elements T12, T14, T16, T18 connected to the second node QB1 and the thirteenth, fifteenth, seventeenth, nineteenth switching elements T13, T15, T17, T19 connected to the third node QB2 are alternately turned on with each other. Accordingly, the first node Q alternately receives the first low level signal VSQ through the connected twelfth and thirteenth switching elements T12 and T13, the first output terminal alternately receives the second low level signal VGL through the connected fourteenth and fifteenth switching elements T14 and T15, the second output terminal alternately receives the second low level signal VGL through the connected sixteenth and seventeenth switching elements T16 and T17, and the third output terminal alternately receives the second low level signal VGL through the connected eighteenth and nineteenth switching elements T18 and T19, thereby achieving a stable low level effect.

And (3) a stabilization stage:

in two time periods before the time t1 and after the time t7, the transfer signal Zn-1 output by the gate transfer unit of the (n-1) th stage received by the pre-charge module 10 is at a low level, and then the pre-charge module 10 enters the non-operating state, and similarly, the transfer signal Zn +1 output by the gate transfer unit of the (n +1) th stage received by the pull-down module 50 is at a low level, then the pull-down module 50 enters the non-operating state. Accordingly, the pre-charge module 10 and the pull-down module 50 have no influence on the first node Q, and the stabilization module 60 may be used to maintain the first node Q, the first output terminal, the second output terminal, and the third output terminal at a low level.

In one embodiment, two periods before the time T1 and after the time T7, when the first node Q has been pulled down to a low level, the second control terminal of the second switching element T2, the third control terminal of the third switching element T3, and the fourth control terminal of the fourth switching element T4 connected to the first node Q are at a low level, the second switching element T2, the third switching element T3, and the fourth switching element T4 are in an open state, and thus the first output block 20, the second output block 40, and the third output block 30 are brought into a non-operation state.

In one embodiment, two periods before the time T1 and after the time T7, the first node Q has been pulled down to the low level, the tenth control terminal of the tenth switching element T10 and the eleventh control terminal of the eleventh switching element T11 connected to the first node Q are at the low level, and the tenth switching element T10 and the eleventh switching element T11 are in the off state. Meanwhile, since the first control signal V1 is opposite in polarity to the second control signal V2, the first control signal V1 controls the sixth switching element T6 and the seventh switching element T7 to be in a turn-on state and charges the second node QB1 through the turned-on sixth switching element T6 and discharges the third node QB2 to the first low level VSQ through the turned-on seventh switching element T7, or the second control signal V2 controls the eighth switching element T8 and the ninth switching element T9 to be in a turn-on state and charges the third node QB2 through the turned-on eighth switching element T8 and discharges the second node QB1 to the first low level VSQ through the turned-on and ninth switching element T9 to be turned on. Accordingly, the first and second control signals V1 and V2 alternately control the second and third nodes QB1 and QB2 to be high and low levels, so that the thirteenth, fifteenth, seventeenth, and nineteenth switching elements T13, T15, T17, and T19 connected to the second node QB1, the thirteenth, fourteenth, and sixteenth switching elements T12, T14, T16, T18, and QB2, are alternately turned on with each other. Accordingly, the first node Q alternately receives the first low level signal VSQ through the connected twelfth and thirteenth switching elements T12 and T13, the first output terminal alternately receives the second low level signal VGL through the connected fourteenth and fifteenth switching elements T14 and T15, the second output terminal alternately receives the second level signal VGL through the connected sixteenth and seventeenth switching elements T16 and T17, and the third output terminal alternately receives the second low level signal VGL through the connected eighteenth and nineteenth switching elements T18 and T19, thereby achieving a stable low level effect.

Thus, in the stable phase, regardless of the variations of the transfer signal Zn-1 output from the gate transfer unit of the (n-1) th stage received by the precharge module 10 and the second gate signal G2n-2 output from the gate transfer unit of the (n-1) th stage, the transfer signal Zn +1 output from the gate transfer unit of the (n +1) th stage received by the pull-down module 50 and the first gate signal G2n +1 output from the gate transfer unit of the (n +1) th stage, and how the first clock signal CLK1, the second clock signal CLK2, and the transfer clock signal CLKA vary, the stabilization block 60 may maintain the first node Q, the first output terminal, the second output terminal, and the third output terminal at a low level, charges such as coupling of parasitic capacitance of the second switching element T2 due to clock feedthrough and the like can be discharged, ensuring stability of the first node Q and the outputted first gate signal G2n-1 and second gate signal G2 n. In addition, in the pre-charging stage, each time the voltage on the first node Q is pulled up is performed on the first low level signal VSQ, the pull-up voltage is relatively stable, the voltage drift phenomenon of the first node Q is prevented, the voltage of the first node Q is more stable, the stability of the circuit is increased, and the reliability of display is improved. In one embodiment, the voltages of the second node QB1 and the third node QB2 are more stable, so that the operating state of the connected switching elements is more stable, and the influence of the ambient temperature on the circuit is reduced, that is, the voltage drift does not exceed a certain threshold value due to the original drift phenomenon, so that the operation of the connected switching elements is abnormal when the temperature is too high or too low; in addition, the voltages of the second and third nodes QB1 and QB2 are more stable, which also broadens the relative timing design of the second and third nodes QB1 and QB 2.

FIG. 3 is a cascaded block diagram of a multi-stage output gate pass circuit according to an embodiment of the invention. FIG. 4 is a timing diagram of clock signals and gate signals for the embodiment of FIG. 3. As shown in fig. 3, the gate transfer circuit includes a plurality of gate transfer units in the embodiment of fig. 1, and the gate transfer circuit includes four gate transfer units as an example. The transfer signal Zn-1 output from the n-1 th stage gate transfer unit and the second gate signal G2n-2 output from the n-1 th stage gate transfer unit required by the precharge module 10 in the first stage gate transfer unit 110 may be replaced by the start signal STV1 and the start signal STV2, respectively, and the first stage gate transfer unit 110 receives the transfer clock signal CLKA, the first clock signal CLK1, the second clock signal CLK2, the first control signal V1, the second control signal V2, the first low level signal VSQ, the second low level signal VGL, the start signal STV1, the start signal STV2, and the first gate signal G3 and the transfer signal Z2 output from the second stage gate transfer unit 120, and outputs the first gate signal G1, the second gate signal G2, and the transfer signal Z1 of the present stage. The second stage gate transfer unit 120 receives the transfer clock signal CLKA, the first clock signal CLK1, the second clock signal CLK2, the first control signal V1, the second control signal V2, the first low level signal VSQ, the second low level signal VGL, the second gate signal G2 and the transfer signal Z1 output from the first stage gate transfer unit 110, and the first gate signal G5 and the transfer signal Z3 output from the third stage gate transfer unit 130, and outputs the first gate signal G3, the second gate signal G4, and the transfer signal Z2 of the present stage. The third stage gate transfer unit 130 receives the transfer clock signal CLKA, the first clock signal CLK1, the second clock signal CLK2, the first control signal V1, the second control signal V2, the first low level signal VSQ, the second low level signal VGL, the second gate signal G4 and the transfer signal Z2 output from the second stage gate transfer unit 120, and the first gate signal G7 and the transfer signal Z4 output from the fourth stage gate transfer unit 140, and outputs the first gate signal G5, the second gate signal G6, and the transfer signal Z3 of the present stage. The transfer signal Zn +1 output from the (n +1) th stage gate transfer unit and the first gate signal G2n +1 output from the (n +1) th stage gate transfer unit, which are required by the pull-down module 50 of the fourth stage gate transfer unit 140, may be replaced by the end signal STV3 and the end signal STV4, respectively, the fourth stage gate transfer unit 140 receives the transfer clock signal CLKA, the first clock signal CLK1, the second clock signal CLK2, the first control signal V1, the second control signal V2, the first low level signal VSQ, the second low level signal VGL, the second gate signal G6 and the transfer signal Z3 output from the third stage gate transfer unit 130, the end signal STV3 and the end signal STV4, and outputs the first gate signal G7, the second gate signal G8 and the transfer signal Z4 of the present stage.

In the present embodiment, as shown in fig. 4, the multi-stage output gate transfer circuit may receive six clock signals VA, VB, VC, VD, VE, and VF. The odd-numbered gate transfer units receive the first group of the first clock signal CLK1 as the clock signal VA, the first group of the second clock signal CLK2 as the clock signal VB and the first group of the transfer clock signal CLKA as the clock signal VE, the even-numbered gate transfer units receive the second group of the first clock signal CLK1 as the clock signal VC, the second group of the second clock signal CLK2 as the clock signal VD and the second group of the transfer clock signal VF. As shown in fig. 4, the clock periods of the six clock signals are the same, and the first clock signal CLK1 of the first group, the second clock signal CLK2 of the first group, the first clock signal CLK1 of the second group, and the second clock signal CLK2 of the second group, may all be clock signals with a duty ratio of 25%, the second clock signal CLK2 of the first group is one phase later than the first clock signal CLK1 of the first group, the second clock signal CLK2 of the second group is one phase later than the first clock signal CLK1 of the second group, the first clock signal CLK1 of the second group is one phase later than the second clock signal CLK2 of the first group, one phase is T/4, and T is the period of the clock signals; the first group of transfer clock signals CLKA and the second group of transfer clock signals CLKA may each be a clock signal with a duty cycle of 50%, the second group of transfer clock signals CLKA being two phases later than the first group of transfer clock signals CLKA.

In this embodiment, the operation manner of the gate transfer unit in the gate transfer circuit can refer to the gate transfer unit in the embodiment of fig. 1, and is not described herein again. As shown in fig. 4, the gate signals output by the gate transmission circuit are separated from each other by the same time, have the same signal shape, and can be quickly pulled up to a high level and then quickly pulled down to a low level, so that the gate signals can be stably provided to the gate lines of the display panel.

Further, as can be seen from the cascade connection of the multi-stage output gate transfer circuits in fig. 3, in the multi-stage output gate transfer circuit of the present embodiment, the gate transfer unit of the present stage needs to receive the second gate signal G2n-2 output from the gate transfer unit of the (n-1) th stage and the transfer signal Zn-1 output from the gate transfer unit of the (n-1) th stage, and the first gate signal G2n +1 output from the gate transfer unit of the (n +1) th stage and the transfer signal Zn +1 output from the gate transfer unit of the (n +1) th stage. Therefore, the first gate transmission unit above can be taken as the first-stage gate transmission unit from top to bottom, and the start signal STV1 and the start signal STV2 are provided, so that the multi-stage output gate transmission circuit can output gate signals from top to bottom to perform forward scanning of the display panel; alternatively, the first gate transmission unit below can be used as the first stage gate transmission unit from bottom to top, and the start signal STV1 and the start signal STV2 are provided, so that the multi-stage output gate transmission circuit can output gate signals from bottom to top to perform the reverse scanning of the display panel. Therefore, the multi-stage output gate transfer circuit of the present embodiment can be used for forward and backward scanning of the display panel.

FIG. 5 is a block diagram of the 8-stage output connections of the multi-stage output gate pass circuit according to an embodiment of the invention. As shown in fig. 5, the multi-stage output gate transfer circuit of the present embodiment may be configured with a plurality of gate transfer units on the left side of the display panel, and may also be configured with a plurality of gate transfer units on the right side of the display panel, for example, with 8-stage output connection, four gate transfer units may be configured on the left side of the display panel, and four gate transfer units may also be configured on the right side of the display panel, and provide 4 clock signals with duty ratio of 25% as the corresponding first clock signal CLK1 and second clock signal CLK2, and 2 clock signals with duty ratio of 50% as the corresponding transfer clock signal CLKA, a first low level signal VSQ, a second low level signal VGL, a first control signal V1, a second control signal V2, two start signals STV1 and STV2, and two end signals STV3 and STV4, respectively. The operation of the multi-stage output gate transfer circuit of this embodiment can refer to the multi-stage output gate transfer circuit in the embodiment of fig. 3, and details thereof are not repeated herein.

In an embodiment, the gate transfer unit on the left side and the gate transfer unit on the right side can provide gate signals to different gate lines of the display panel, and the gate signals are provided on a single side, so that an overlarge layout area on one side can be avoided.

In an embodiment, the left gate transfer unit and the right gate transfer unit may provide the gate signals to the left side and the right side of the same gate line of the display panel, and provide the gate signals to a single side, so that image abnormality caused by a voltage drop of the gate signals on the gate line may be avoided, and all thin film transistors connected to the gate line may be turned on quickly, which is beneficial to fast display of images.

FIG. 6 is a block diagram of the full stage connections of the multi-stage output gate pass circuit of one embodiment of the invention. As shown in fig. 6, the multi-stage output gate transmission circuit of the present embodiment may further include a signal providing module 200, where the signal providing module 200 is configured to provide corresponding input signals for the plurality of gate transmission units, and the signal providing module 200 may be composed of a multi-stage substrate gate driving circuit and signal lines. In one embodiment, the signal providing module 200 is disposed at the middle of the plurality of gate transfer units, so that the plurality of gate transfer units may be connected upward and downward, respectively, and/or may be connected leftward and rightward, respectively. Taking the multi-stage output gate transfer circuit shown in fig. 6 as an example, four gate transfer units are disposed on the upper left side, the lower left side, the upper right side and the lower right side of the signal providing module 200, and the four gate transfer units on each of the four sides are all in 8-stage output connection, so that the signal providing module 200 may connect the gate transfer units on each side and provide input signals for each side, including 4 clock signals with a duty ratio of 25% as the corresponding first clock signal CLK1 and second clock signal CLK2, 2 clock signals with a duty ratio of 50% as the corresponding transfer clock signal CLKA, a first low-level signal VSQ, a second low-level signal VGL, a first control signal V1, and a second control signal V2. In one embodiment, the signal providing module 200 may further provide two end signals STV3 and STV4 for the fourth gate transfer units at the upper left side and the upper right side, and may provide two start signals STV1 and STV2 for the first gate transfer units at the lower left side and the lower right side; accordingly, the first gate transfer cells at the upper left and upper right sides need to be supplied with two start signals STV1 and STV2 by other external signal circuits, and the fourth gate transfer cells at the lower left and lower right sides need to be supplied with two end signals STV3 and STV4 by other external signal circuits. The operation of the multi-stage output gate transfer circuit of this embodiment can refer to the multi-stage output gate transfer circuit in the embodiment of fig. 3, and details thereof are not repeated herein.

Based on the same inventive concept, embodiments of the present invention further provide a display device, including the multi-stage output gate transfer circuit provided in the above embodiments, for providing gate signals to gate lines of a display panel. The implementation of the display device can be referred to the embodiment of the multi-stage output gate transfer circuit, and repeated details are not repeated.

According to the multi-stage output grid transmission circuit and the display device, each stage of grid transmission unit can output two stages of grid signals and transmission signals, the number of devices used for grid driving can be reduced, the stability of the circuit can be improved, and the multi-stage output grid transmission circuit and the display device can be used for forward and reverse scanning of a display panel.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A multi-stage output gate transfer circuit comprising a multi-stage gate transfer unit, wherein each stage of the gate transfer unit comprises:

a precharge module (10), the precharge module (10) being connected to a first node (Q), and charging the first node (Q) according to a transfer signal (Zn-1) output from the (n-1) th stage gate transfer unit and a second gate signal (G2n-2) output from the (n-1) th stage gate transfer unit;

a first output module (20), the first output module (20) and the precharge module (10) being connected at the first node (Q) for outputting a first gate signal (G2n-1) at a first output according to a first clock signal (CLK 1);

a second output module (40), wherein the second output module (40) is connected to the precharge module (10) at the first node (Q), and outputs a second gate signal (G2n) at a second output end according to a second clock signal (CLK2), the period and duty cycle of the first clock signal (CLK1) and the second clock signal (CLK2) are the same, and the first gate signal (G2n-1) and the second gate signal (G2n) are transmitted to two adjacent gate lines of a display panel;

a third output module (30), the third output module (30) being connected to the precharge module (10) at the first node (Q), and outputting a transfer signal (Zn) at a third output terminal according to a transfer clock signal (CLKA), a high period of the transfer clock signal (CLKA) including a high period of the first clock signal (CLK1) and a high period of the second clock signal (CLK 2);

a pull-down module (50), wherein the pull-down module (50) and the precharge module (10) are connected to the first node (Q), and the pull-down module pulls down the first node (Q) to a low level according to a transfer signal (Zn +1) output by the (n +1) th stage gate transfer unit and a first gate signal (G2n +1) output by the (n +1) th stage gate transfer unit;

a stabilizing module (60), the stabilizing module (60) being connected to the first node (Q), the first output terminal, the second output terminal, and the third output terminal, the stabilizing module (60) being configured to maintain the first node (Q), the first output terminal, the second output terminal, and the third output terminal at a low level simultaneously when the first node (Q) is pulled down to a low level.

2. The multi-stage output gate transfer circuit of claim 1, wherein the precharge module (10) comprises a first switching element (T1), the first switching element (T1) comprises a first control terminal, a first pass terminal and a second pass terminal, the first control terminal of the first switching element (T1) receives the transfer signal (Zn-1) output by the gate transfer unit of the (n-1) th stage, the first pass terminal of the first switching element (T1) receives the second gate signal (G2n-2) output by the gate transfer unit of the (n-1) th stage, and the second pass terminal of the first switching element (T1) is connected to the first node (Q).

3. The multi-stage output gate pass circuit of claim 1, wherein the first output module (20) comprises a second switching element (T2), the second switching element (T2) comprising a second control terminal, a third pass terminal and a fourth pass terminal, the second control terminal of the second switching element (T2) being connected to the first node (Q), the third pass terminal of the second switching element (T2) receiving the first clock signal (CLK1), the fourth pass terminal of the second switching element (T2) being connected to the first output terminal.

4. The multi-stage output gate transfer circuit of claim 1, wherein the second output block (40) comprises a third switching element (T3), the third switching element (T3) comprising a third control terminal, a fifth pass terminal and a sixth pass terminal, the third control terminal of the third switching element (T3) being connected to the first node (Q), the fifth pass terminal of the third switching element (T3) receiving the second clock signal (CLK2), the sixth pass terminal of the third switching element (T3) being connected to the second output terminal.

5. The multi-level output gate pass circuit of claim 1, wherein the third output module (30) includes a fourth switching element (T4), the fourth switching element (T4) includes a fourth control terminal, a seventh pass terminal, and an eighth pass terminal, the fourth control terminal of the fourth switching element (T4) is connected to the first node (Q), the seventh pass terminal of the fourth switching element (T4) receives the pass clock signal (CLKA), and the eighth pass terminal of the fourth switching element (T4) is connected to the third output terminal.

6. The multi-stage output gate pass circuit of claim 1, wherein the pull-down module (50) comprises a fifth switching element (T5), the fifth switching element (T5) comprises a fifth control terminal, a ninth pass terminal and a tenth pass terminal, the fifth control terminal of the fifth switching element (T5) receives the pass signal (Zn +1) output by the gate pass unit of the (n +1) th stage, the ninth pass terminal of the fifth switching element (T5) is connected to the first node (Q), and the tenth pass terminal of the fifth switching element (T5) receives the first gate signal (G2n +1) output by the gate pass unit of the (n +1) th stage.

7. The multi-stage output gate pass circuit of claim 1, wherein the stabilization module (60) comprises:

a sixth switching element (T6), the sixth switching element (T6) including a sixth control terminal, an eleventh path terminal and a tenth path terminal, the sixth control terminal of the sixth switching element (T6) receiving the first control signal (V1), the eleventh path terminal of the sixth switching element (T6) being connected to the sixth control terminal of the sixth switching element (T6), the twelfth path terminal of the sixth switching element (T6) being connected to the second node (QB 1);

a seventh switching element (T7), the seventh switching element (T7) including a seventh control terminal, a tenth path terminal and a tenth path terminal, the seventh control terminal of the seventh switching element (T7) being connected to the eleventh path terminal of the sixth switching element (T6) to receive the first control signal (V1), the tenth path terminal of the seventh switching element (T7) receiving the first low level signal (VSQ), the fourteenth path terminal of the seventh switching element (T7) being connected to the third node (QB 2);

an eighth switching element (T8), the eighth switching element (T8) including an eighth control terminal, a fifteenth control terminal, and a sixteenth control terminal, the eighth control terminal of the eighth switching element (T8) receiving a second control signal (V2), the fifteenth control terminal of the eighth switching element (T8) being connected to the third node (QB2), the sixteenth control terminal of the eighth switching element (T8) being connected to the eighth control terminal of the eighth switching element (T8);

a ninth switching element (T9), the ninth switching element (T9) including a ninth control terminal, a seventeenth path terminal and an eighteenth path terminal, the ninth control terminal of the ninth switching element (T9) being connected to the sixteenth path terminal of the eighth switching element (T8) to receive the second control signal (V2), the seventeenth path terminal of the ninth switching element (T9) being connected to the second node (QB1), the eighteenth path terminal of the ninth switching element (T9) receiving the first low level signal (VSQ);

a tenth switching element (T10), the tenth switching element (T10) including a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal, the tenth control terminal of the tenth switching element (T10) being connected to the first node (Q), the nineteenth path terminal of the tenth switching element (T10) receiving the first low level signal (VSQ), the twentieth path terminal of the tenth switching element (T10) being connected to the second node (QB 1);

an eleventh switching element (T11), the eleventh switching element (T11) including an eleventh control terminal, a twenty-first path terminal and a twenty-second path terminal, the eleventh control terminal of the eleventh switching element (T11) being connected to the first node (Q), the twenty-first path terminal of the eleventh switching element (T11) being connected to the nineteenth path terminal of the tenth switching element (T10) to receive the first low level signal (VSQ), the twenty-second path terminal of the eleventh switching element (T11) being connected to the third node (QB 2);

a twelfth switching element (T12), the twelfth switching element (T12) including a twelfth control terminal, a twentieth pass terminal and a twentieth pass terminal, the twelfth control terminal of the twelfth switching element (T12) being connected to the second node (QB1), the twentieth pass terminal of the twelfth switching element (T12) being connected to the first node (Q), the twentieth pass terminal of the twelfth switching element (T12) receiving the first low level signal (VSQ);

a thirteenth switching element (T13), the thirteenth switching element (T13) including a thirteenth control terminal, a twenty-fifth path terminal and a twenty-sixth path terminal, the thirteenth control terminal of the thirteenth switching element (T13) being connected to the third node (QB2), the twenty-fifth path terminal of the thirteenth switching element (T13) being connected to the twenty-fourth path terminal of the twelfth switching element (T12) to receive the first low level signal (VSQ), the twenty-sixth path terminal of the thirteenth switching element (T13) being connected to the first node (Q);

a fourteenth switching element (T14), the fourteenth switching element (T14) including a fourteenth control terminal, a twenty-seventh path terminal and a twenty-eighth path terminal, the fourteenth control terminal of the fourteenth switching element (T14) being connected to the second node (QB1), the twenty-seventh path terminal of the fourteenth switching element (T14) being connected to the first output terminal, the twenty-eighth path terminal of the fourteenth switching element (T14) receiving a second low level signal (VGL);

a fifteenth switching element (T15), the fifteenth switching element (T15) including a fifteenth control terminal, a twenty-ninth path terminal and a thirtieth path terminal, the fifteenth control terminal of the fifteenth switching element (T15) being connected to the third node (QB2), the twenty-ninth path terminal of the fifteenth switching element (T15) being connected to the twenty-eighth path terminal of the fourteenth switching element (T14) to receive the second low level signal (VGL), the thirtieth path terminal of the fifteenth switching element (T15) being connected to the first output terminal;

a sixteenth switching element (T16), the sixteenth switching element (T16) including a sixteenth control terminal, a thirty-first path terminal, and a thirty-second path terminal, the sixteenth control terminal of the sixteenth switching element (T16) being connected to the second node (QB1), the thirty-first path terminal of the sixteenth switching element (T16) being connected to the second output terminal, the thirty-second path terminal of the sixteenth switching element (T16) receiving the second low level signal (VGL);

a seventeenth switching element (T17), the seventeenth switching element (T17) including a seventeenth control terminal, a thirty-third path terminal and a thirty-fourth path terminal, the seventeenth control terminal of the seventeenth switching element (T17) being connected to the third node (QB2), the thirty-third path terminal of the seventeenth switching element (T17) being connected to the thirty-third path terminal of the sixteenth switching element (T16) to receive the second low level signal (VGL), the thirty-fourth path terminal of the seventeenth switching element (T17) being connected to the second output terminal;

an eighteenth switching element (T18), the eighteenth switching element (T18) including an eighteenth control terminal, a thirty-fifth path terminal, and a thirty-sixth path terminal, the eighteenth control terminal of the eighteenth switching element (T18) being connected to the second node (QB1), the thirty-fifth path terminal of the eighteenth switching element (T18) being connected to the third output terminal, the thirty-sixth path terminal of the eighteenth switching element (T18) receiving the second low level signal (VGL);

a nineteenth switching element (T19), the nineteenth switching element (T19) including a nineteenth control terminal, a thirty-seventh path terminal, and a thirty-eighth path terminal, the nineteenth control terminal of the nineteenth switching element (T19) being connected to the third node (QB2), the thirty-seventh path terminal of the nineteenth switching element (T19) being connected to the thirty-sixth path terminal of the eighteenth switching element (T18) to receive the second low level signal (VGL), the thirty-eighth path terminal of the nineteenth switching element (T19) being connected to the third output terminal.

8. The multi-stage output gate pass circuit of claim 7, wherein the first control signal (V1) and the second control signal (V2) are opposite in polarity and are each reversed in polarity once per frame.

9. The multi-stage output gate pass circuit of claim 1, wherein the gate pass unit further comprises a first capacitor (C1) and a second capacitor (C2), a first terminal of the first capacitor (C1) is connected to the first node (Q), a second terminal of the first capacitor (C1) is connected to the first output terminal, a first terminal of the second capacitor (C2) is connected to the first node (Q), and a second terminal of the second capacitor (C2) is connected to the second output terminal.

10. A display device comprising the multi-level output gate pass circuit of any one of claims 1 to 9.