CN109243371B

CN109243371B - Drive circuit unit, drive circuit and display device

Info

Publication number: CN109243371B
Application number: CN201811268929.7A
Authority: CN
Inventors: 张盛东; 黄杰; 廖聪维; 雷腾腾
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2018-10-29
Filing date: 2018-10-29
Publication date: 2020-06-16
Anticipated expiration: 2038-10-29
Also published as: CN109243371A

Abstract

The application relates to a driving circuit unit, a driving circuit and a display device, which can be applied to an AMOLED display, a TFT-LCD and the like. The drive circuit unit in this application can satisfy the requirement of AMOLED pixel circuit polymorphic type scanning signal, through adopting disconnect-type input structure, forms the two bootstrap nodes of separation, has solved the charge-coupled problem between the different bootstrap nodes that clock feed-through effect leads to, has restrained the bootstrap node voltage decline that thin-film transistor electric leakage leads to, makes the pulse shape of output scanning signal more complete and have symmetry, shorter rise fall time. And then by introducing a feedback transistor, when the threshold voltage of the transistor is negative, the low level maintaining node can still maintain the high level, and the scanning signal of the output end is maintained at the corresponding low level. The driving method can improve the electrical performance of the AMOLED pixel circuit, so that the stability and uniformity of the AMOLED display are better.

Description

Drive circuit unit, drive circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a driving circuit unit, a driving circuit and a display device.

Background

Organic Light-Emitting Diode (OLED) displays have been widely researched in recent years due to their advantages of high brightness, high Light-Emitting efficiency, wide viewing angle, low power consumption, etc., and are rapidly applied to new generation display devices. The driving method of the OLED display may be Passive Matrix OLED (PMOLED) or Active Matrix OLED (AMOLED). The passive matrix driving is low in cost, but it cannot realize high-resolution display due to cross-talk, and the passive matrix driving current is large, and the service life of the OLED is short. In contrast, in the active matrix driving mode, transistors with different numbers are arranged on each pixel to serve as current sources, cross talk is avoided, the required driving current is small, power consumption is low, the service life of the OLED is prolonged, high-resolution display can be achieved, and the requirements of large-area and high-gray-scale display are met more easily. The AMOLED display array is composed of simple Thin Film Transistors (TFTs) and pixels of organic light emitting elements, and compared with the traditional TFT-LCD (TFT-LCD) technology, the AMOLED technology has the advantages of high color saturation, high contrast, short response time, low power consumption and the like. In addition, the AMOLED technology is beneficial to realizing flexible display and can cover a wider application range.

Integrated Gate drive (GOA) technology has been widely used in TFT-LCDs. Compared with a traditional Gate driver IC (integrated circuit) driving mode, the GOA technology reduces binding procedures in the process production process, reduces the production cost of products, and is beneficial to narrowing the frame. For the same reason, the GOA technology can also be applied to AMOLED display. However, the driving signals required by the AMOLED are complex, and the conventional GOA circuit has difficulty in providing the required signals. This is mainly because, unlike the display principle of the TFT-LCD, the AMOLED is a display device based on a current driving mode. The AMOLED display has problems of anode voltage drift and a reduction in light emission efficiency during a long period of light emission. Meanwhile, due to factors such as process and voltage stress, parameters such as mobility and threshold voltage of the backboard pixel circuit of the AMOLED are not uniform or drift. In response to these problems, the pixel circuit must adopt a complex structure and timing sequence to perform compensation improvement, thereby ensuring the stability and uniformity of the AMOLED display. However, in order to make a display device applying the AMOLED technology have a narrow bezel, each integrated gate driving unit needs to generate a plurality of scan signals. The integrated gate driving unit in the prior art has the problem of insufficient bootstrap capability of a bootstrap node or electric leakage when various complex signals are generated, and particularly, the problem of electric leakage of a low-level maintaining node is serious when the threshold voltage is biased to be negative.

Disclosure of Invention

The application provides a drive circuit unit, a drive circuit and a display device, which solve the technical problems existing in the prior art.

According to a first aspect, there is provided in an embodiment a driving circuit unit comprising:

the device comprises an input module (21), a driving pull-up module (22), a bootstrap node pull-down module (23), an output pull-down module (24) and a low level maintaining module (25); further comprising:

a first signal input for receiving a first clock signal (CLK 1);

a second signal input for receiving a second clock signal (CLK 2);

a third signal input for receiving a third clock signal (CLK 3);

a fourth signal input for receiving a fourth clock signal (CLK 4);

a fifth signal input for receiving a first complex clock signal (CLKW);

an input signal input terminal (CIN) for receiving a preceding stage cascade control signal;

a first potential input terminal for input of a first low potential (VSS);

a second potential input terminal for input of a second low potential (VSSL);

a third potential input terminal for an input terminal of the first high potential (VH);

a first signal output terminal (GA) for outputting a first scan pulse driving signal;

a second signal output terminal (GB) for outputting a second scanning pulse driving signal;

a third signal output terminal (COUT) for outputting the present stage cascade control signal;

the input module (21) is connected between a fourth signal input end or a third potential input end, an input signal input end (CIN), the bootstrap node pull-down module (23) and the driving pull-up module (22); the input module (21) is used for pre-charging a connection node between the driving pull-up module (22) and the input module (21) so as to start the driving pull-up module (22);

the drive pull-up module (22) is connected among a first signal input end, a second signal input end, a fifth signal input end, the input module (21), a first signal output end (GA), a second signal output end (GB) and a third signal output end (COUT); the drive pull-up module (22) is configured to transmit the potentials of the first signal input end, the second signal input end and the fifth signal input end to the second signal output end (GB), the third signal output end (COUT) and the first signal output end (GA) respectively when a connection node between the drive pull-up module (22) and the input module (21) is a high potential;

the low level maintaining module (25) is connected among a third potential input end, a third signal input end, a second potential input end, the output pull-down module (24) and the input module (21); the low level maintaining module (25) is used for maintaining the potential of a connecting node between the low level maintaining module (25) and the output pull-down module (24) not lower than a second low potential (VSSL) of a second potential input end so as to turn on or turn off the output pull-down module (24);

the bootstrap node pull-down module (23) is connected among a third signal input end, a second potential input end and the input module (21); the bootstrap node pull-down module (23) is configured to lower a potential of a connection node between the bootstrap node pull-down module (23) and the input module (21) to a second low potential (VSSL);

the output pull-down module (24) is connected among the first potential input end, the second potential input end, the first signal output end (GA), the second signal output end (GB), the third signal output end (COUT), the low level maintaining node (QB) and the input module (21); the output pull-down module (24) is used for pulling down the electric potentials of the first signal output end (GA) and the second signal output end (GB) to the electric potential of the first electric potential input end; the output pull-down module (24) is further configured to drop a potential of a connection node between the output pull-down module (24) and the input module (21) and a potential of a third signal output terminal (COUT) to a second low potential (VSSL) of a second potential input terminal.

According to a second aspect, an embodiment provides a driving circuit including a first clock line (CLK1), a second clock line (CLK2), a third clock line (CLK3), a fourth clock line (CLK4), a fifth clock line (CLKW1), a sixth clock line (CLKW2), and a first low potential line (VSS), a second low potential line (VSSL), a first high potential line (VH), an input signal input line (CIN), a cascade signal output line (COUT);

the driving circuit further comprises the driving circuit unit of the first aspect cascaded in N +1 stages, wherein N is a positive integer;

the first clock line (CLK1), second clock line (CLK2), third clock line (CLK3) and fourth clock line (CLK4) transmit clock signals for the driving circuit unit;

the input signal input (CIN) of the driver circuit unit of the first stage is used for coupling a start Signal (STV); the input signal input end (CIN) of the second stage drive circuit unit and the input signal input end (CIN) of the last stage drive circuit unit are coupled with the cascade signal output end (COUT) of the last stage drive circuit unit;

said fifth clock line (CLKW1) is coupled to said fifth signal input of odd stage drive circuit units; said sixth clock line (CLKW2) is coupled to said fifth signal input of even stage drive circuit units;

the first low potential line (VSS), the second low potential line (VSSL), and the first high potential line (VH) are the driving circuit unit input voltage signals.

According to a third aspect, there is provided in one embodiment a display comprising:

a panel including a two-dimensional pixel array constituted by a plurality of pixels, and a plurality of data lines in a first direction and a plurality of gate scan lines in a second direction connected to each pixel in the array, further comprising:

the driving circuit of the second aspect provides a gate driving signal to the gate scan line.

According to the driving circuit unit, the driving circuit and the display device of the embodiment, the separate input ends are adopted to respectively generate the mutually independent dual bootstrap nodes, so that charge coupling between different bootstrap nodes caused by clock feed-through effect is avoided, the problem of voltage reduction of the bootstrap nodes caused by electric leakage of the thin film transistor is solved, and the pulse shape of the output scanning signal is more complete and has symmetrical and shorter rising and falling time. By introducing the diode-connected feedback transistor, when the threshold voltage of the transistor is negative, the low-level maintaining node can still maintain high level, and the scanning signal of the output end is maintained at corresponding low level. The two methods ensure that the pixel circuit works normally, and the stability and uniformity of the AMOLED display are better.

Drawings

FIG. 1 is a schematic diagram of a pixel circuit and an operation timing sequence of a typical IGZO TFT for realizing an AMOLED;

FIG. 2 is a schematic diagram of a common bootstrap node circuit;

FIG. 3 is a schematic diagram of a circuit structure of a diode isolation-connected bootstrap node;

FIG. 4 is a schematic circuit diagram of a split bootstrap node;

FIG. 5 is a circuit diagram of a low-level sustain portion of a driving circuit;

FIG. 6 is a schematic circuit diagram of a driving circuit unit according to an embodiment;

FIG. 7 is a schematic circuit diagram of a driving circuit unit according to an embodiment;

FIG. 8 is a circuit diagram of an input module of a driving circuit unit according to an embodiment;

FIG. 9 is a circuit diagram of a bootstrap node pull-down module of the driving circuit unit according to an embodiment;

FIG. 10 is a circuit diagram of an output pull-down module of the driving circuit unit according to an embodiment;

FIG. 11 is a circuit diagram of an output pull-down module of the driving circuit unit according to an embodiment;

FIG. 12 is a circuit diagram of a low-level keeper module of the driving circuit unit according to an embodiment;

FIG. 13 is a circuit diagram of a low level hold module of the driving circuit unit according to an embodiment;

FIG. 14 is a timing diagram illustrating the operation of the driving circuit unit according to one embodiment;

FIG. 15 is a comparison graph of complex signals generated by the driving circuit unit disclosed in one embodiment;

FIG. 16 is a comparison graph of complex signals generated by the driving circuit unit disclosed in one embodiment;

FIG. 17 is a diagram illustrating output signals of a driving circuit unit according to an embodiment;

fig. 18 is a schematic structural diagram of a driving circuit in an embodiment.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).

The compensation method of the AMOLED can be divided into two types of pixel circuit internal compensation and external chip compensation. At present, a small-sized display screen using the AMOLED technology generally adopts a pixel circuit internal compensation technology, such as a mobile phone display. And the display screen applying the AMOLED technology adopts an external chip compensation technology. Such as a television display. Whether an internal compensation technique or an external compensation technique is adopted, the pixel circuit requires a grid drive circuit to provide more complex scanning signals even with ultra-wide pulse width. These scanning signals put new requirements on the GOA. It is conventional practice to use different GOA cells to generate different driving signals, respectively. However, this conventional approach requires a larger bezel and is not conducive to narrow bezel and full screen designs. Ideally, a single GOA unit is capable of generating multiple different classes of drive signals.

In the GOA circuit design of AMOLED, there are two key issues. First, there is a problem that internal nodes such as bootstrap nodes interfere with each other in response to different output scan signals. Next, when the threshold voltage of the TFT is negative, a leakage current exists at the low-level hold control node of the GOA circuit. Aiming at the problem of multi-output signal interference, the application provides a structure of separating bootstrap nodes, so that a plurality of bootstrap nodes of a plurality of different scanning signals are mutually independent, and the coupling relation between different bootstrap processes is eliminated. Through the structure of separating the bootstrap node, a series of problems of insufficient driving capability, bootstrap node leakage, threshold loss and the like in the second bootstrap process can be avoided, so that the rising and falling time symmetry of the two scanning output signals is good, and the rising (or falling) time of the scanning signals can be reduced. The application also provides a feedback structure for continuously charging the low-level maintaining node, and the ripple phenomenon of the low level of the low-level maintaining stage of the scanning signal is suppressed.

As shown in fig. 1, an AMOLED pixel circuit and operation timing diagram for a typical IGZO TFT implementation. The pixel circuit includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a capacitor, and a light emitting diode OLED. Control electrode of transistor T1And is connected to the Scan signal line Scan1 for inputting the Scan signal Scan 1. The first pole of the transistor T1 is for the data signal V_DATAOr a reference voltage V_REFIs input. The second pole of the transistor T1 is connected to the control pole of the transistor T3. A control electrode of the transistor T2 is connected to the emission control signal line EM for input of the emission control signal EM. The first electrode of the transistor T2 and the high-level power line ELV of the pixel circuit_DDAnd a connection for providing power to the pixel circuit. The second pole of the transistor T2 is connected to the first pole of the transistor T3. The light emitting diode OLED is connected in series to the second electrode of the transistor T3 and the low level terminal power line ELV_SSOr in series between the second pole of transistor T3 and ground. A capacitor is connected in series between the second and control electrodes of transistor T3. A gate of the transistor T4 is connected to the Scan signal line Scan2, and is used for inputting the Scan signal Scan 2. A first pole of the transistor T4 and a second pole of the transistor T3 are connected. The second pole of the transistor T4 is connected to the input power line V_INIAnd (4) connecting.

As shown in the timing chart of fig. 1, the pixel circuit line scanning time is divided into an initialization phase, a compensation phase (threshold voltage extraction) and a data writing and light emitting phase. The Scan signal Scan1 is a single pulse signal, the Scan signal Scan2 is a complex signal having two different pulse widths, and the enable signal EM is a complex signal having multiple pulses and being at a high potential for a long time. In the embodiment of the present application, one gate driving circuit unit generates two scan signals, excluding the enable signal. Igzo (indium Gallium Zinc oxide) is an abbreviation for indium Gallium Zinc oxide, which is a semiconductor material used for conducting electric charges as an active layer thin film of a transistor.

In order to generate different Scan signals Scan1 and Scan2, a common bootstrap node structure as shown in fig. 2 is generally adopted. Including transistor T5, transistor T6, and transistor T7. A control electrode of the transistor T5 is connected to the input signal input terminal CIN for inputting the scanning signal outputted from the previous stage driving circuit unit. A first pole of transistor T5 is used to receive clock signal CLKA. The control electrodes of the transistor T6 and the transistor T7 are connected to the second electrode of the transistor T5, which is the bootstrap node Q. First poles of the transistor T6 and the transistor T7 are used to receive the clock signal CLKB and the clock signal CLKW, respectively. The second poles of the transistor T6 and the transistor T7 are used to output the pulse signal GB and the pulse signal GA, respectively.

Or, a structure of adding a diode connection to isolate the bootstrap nodes as shown in fig. 3 is adopted to separate the two bootstrap nodes. In addition to the circuit shown in fig. 2, a transistor T8 is further included, the first and second poles of which are connected in series between the second pole of the transistor T5 and the control pole of the transistor T7. The transistor T8 is diode connected with its control electrode shorted to the first. The common bootstrapping node Q is further divided into two bootstrapping nodes QR and QL. In order to provide a stronger driving current, the driving thin film transistor for driving the load is generally large in size. Therefore, the value of the parasitic capacitance of the driving thin film transistor is also large. Meanwhile, due to the clock feed-through effect, when the driving thin film transistors respectively connected with the simple signal and the complex signal share the bootstrap node, the bootstrap node generates large fluctuation, so that the secondary bootstrap voltage is insufficient when the complex signal is generated, and the output voltage with full amplitude can not be reached within the pulse width time even when the rising time of the scanning signal is too long. Similarly, there is the electric leakage problem in diode connection thin film transistor isolation bootstrap node structure's second bootstrap node QR, leads to bootstrap node voltage drop very fast, makes the driving force of drive tube weak, and unable the great drive tube of make full use of size carries out the pull-down and discharges, leads to scanning signal decline time overlength. Meanwhile, the diode connection has the problem of threshold loss, for example, when the threshold voltage is increased, the bootstrap node precharge voltage is too low, so that the problems of insufficient first bootstrap voltage, too long rise time of the scanning signal, incapability of reaching full amplitude within the pulse width time and the like are caused.

As shown in fig. 4, the circuit structure of the separated bootstrap node disclosed in the present application is schematically illustrated, and includes a transistor T5, a transistor T6, a transistor T7, and a transistor T8. The control electrodes of the transistor T5, the transistor T6, and the transistor T7 are connected to an input signal input terminal CIN for inputting a scanning signal output from the previous stage of the driving circuit unit. A first pole of the transistor T5 and the transistor T6 is used to receive the clock signal CLKA. The second pole of the transistor T5 is connected to the control pole of the transistor T7. The second pole of the transistor T6 is connected to the control pole of the transistor T8, which is the bootstrap node Q. A first pole of transistor T7 is used to receive clock signal CLKC. A first pole of transistor T8 is used to receive clock signal CLKB. The second poles of the transistor T8 and the transistor T7 are used to output the pulse signal GB and the pulse signal GA, respectively.

As shown in fig. 5, it is a low-level sustain part of the conventional integrated gate driving circuit. Including transistor T9 and transistor T10. The control electrode of the transistor T9 is shorted with the first electrode for input of the high potential VH. The second pole of the transistor T9 is connected to the first pole of the transistor T10. The control electrode of the transistor T10 is connected to the bootstrap node Q. The second pole of the transistor T10 is connected to the low potential VSSL. Or, a transistor T11 and a transistor T12 are included. The control electrode of the transistor T11 is shorted with the first electrode for the input of the clock signal CLK. The second pole of the transistor T11 is connected to the first pole of the transistor T12. The control electrode of the transistor T11 is connected to the bootstrap node Q. The second pole of the transistor T12 is connected to the low potential VSSL. The grid of the pull-up thin film transistor is connected with high level or clock signals. The former can ensure that the low level maintains the node at the high level, but has a direct current path and high power consumption. The latter connection is more commonly used. However, when the clock signal is at a low level, the low level sustain node is in a floating state, and if the threshold voltage of the thin film transistor is negative, the voltage of the floating low level sustain node drops due to leakage, the pull-down tube is in a weak off state, and the voltage ripple at the output end is correspondingly increased.

Therefore, when a single GOA unit generates various complex signals of the AMOLED, the existing single bootstrap node structure has the problems of insufficient bootstrap capacity or suspension of a low-level maintaining part of circuits and the like.

Some terms referred to in the present application will be described first.

The transistors in the present application may be transistors of any structure, such as Bipolar Junction Transistors (BJTs) or Field Effect Transistors (FETs). When the transistor is a bipolar transistor, the control electrode of the transistor refers to the gate electrode of the bipolar transistor, and the first electrode of the transistor may be the collector electrode of the bipolar transistorOr the emitter, the corresponding second pole can be the emitter or the collector of the bipolar transistor, and in the practical application process, the "emitter" and the "collector" can be interchanged according to the signal flow direction; when the transistor is a field effect transistor, the control electrode refers to a gate electrode of the field effect transistor, the first electrode may be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode may be a source electrode or a drain electrode of the field effect transistor, and in an actual application process, "source electrode" and "drain electrode" may be interchanged according to a signal flow direction. The transistor in the display device is typically a Thin Film Transistor (TFT), and in this case, the control electrode of the transistor refers to the source electrode of the thin film transistor. The Light Emitting element may be an Organic Light-Emitting Diode (OLED), an electrodeless Light-Emitting Diode, a quantum dot Light-Emitting Diode, or the like, and in other embodiments, may be another Light Emitting element. The first end of the light emitting element may be a cathode or an anode, and correspondingly, the second end of the light emitting element is an anode or a cathode. Those skilled in the art will understand that: current should flow from the anode to the cathode of the light emitting element, and thus, the anode and the cathode of the light emitting element can be determined based on the flow direction of current. The active level can be a high level or a low level, and can be adaptively replaced according to the function implementation of a specific component. The first potential terminal, the second potential terminal and the third potential terminal are power supplies for the driving circuit to work. In one embodiment, the first potential terminal may be a low potential terminal V_SSOr ground, the second potential terminal may be a low potential terminal V_SSLOr ground, the third potential terminal may be a high potential terminal V_HIn other embodiments, the substitution may be made adaptively. It should be noted that: for the pixel circuit, the first potential terminal (e.g., the low-level terminal V)_SSOr ground) and a third potential terminal (e.g., high-level terminal V)_H) The first potential terminal and the second potential terminal are specifically introduced for better understanding of the technical solution of the present application, and are not a part of the pixel circuit of the present application.

It should be noted that, for convenience of description and to make those skilled in the art more clearly understand the technical solution of the present application, the first bootstrap node QL, the second bootstrap node QR, the third bootstrap node QC and the low level maintenance node QB are introduced in this document to identify relevant parts of the circuit structure, and cannot be considered as terminals additionally introduced in the circuit.

For convenience of description, the high level adopts V_HCharacterisation, low level using V_SSAnd V_SSLAnd (4) showing. In the embodiments of the present application, the "complex pulse signal" refers to a general term of other common pixel circuit driving signals in which the number of pulse transition edges in a pulse signal is greater than that of a single pulse signal, and in the embodiments of the present application, the pulse signals received at the fifth signal input terminal and the sixth signal input terminal are complex pulse signals. Diode-connected means that the first and control electrodes of the thin film transistor are connected.

In the embodiment of the invention, the integrated gate drive circuit adopts a separated bootstrap structure to ensure the stability and the bootstrap capability of the bootstrap node, and simultaneously adopts a feedback thin film transistor structure to ensure that the low level maintaining node keeps high level and the output end scanning signal keeps low level when the thin film transistor is in a negative threshold value.

The first embodiment is as follows:

referring to fig. 6, a circuit structure of a driving circuit unit according to an embodiment is shown, where the driving circuit unit includes an input module 21, a driving pull-up module 22, a bootstrap node pull-down module 23, a low level maintaining module 25, and an output pull-down module 24. The driving circuit unit further includes:

a first signal input for receiving a first clock signal CLK 1;

a second signal input for receiving a second clock signal CLK 2;

a third signal input for receiving a third clock signal CLK 3;

a fourth signal input for receiving a fourth clock signal CLK 4;

a fifth signal input terminal for receiving the first complex clock signal CLKW;

an input signal input terminal CIN for receiving a preceding stage cascade control signal;

a first potential input terminal for inputting a first low potential VSS;

a second potential input terminal for inputting a second low potential VSSL;

a third potential input terminal for an input terminal of the first high potential VH;

a first signal output end GA, which is used for outputting a first pulse driving signal;

a second signal output terminal GB for outputting a second pulse driving signal;

and a third signal output terminal COUT for outputting the current stage cascade control signal.

The driving pull-up module 22 is connected among the first signal input terminal, the second signal input terminal, the fifth signal input terminal, the input module 21, the first signal output terminal GA, the second signal output terminal GB, and the third signal output terminal COUT. The driving pull-up module 22 is configured to transmit the potentials of the first signal input terminal, the second signal input terminal, and the fifth signal input terminal to the second signal output terminal GB, the third signal output terminal COUT, and the first signal output terminal GA, respectively, when a connection node between the driving pull-up module 22 and the input module 21 is a high potential. The number of the connection nodes between the input module 21 and the driving pull-up module 22 is not less than 1. The connection node between the input module 21 and the driving pull-up module 22 includes a first bootstrap node QL and a second bootstrap node QR. That is, when the first bootstrap node QL and the second bootstrap node QR of the driving circuit unit are at high potentials, potentials of the fifth signal input terminal, the second signal input terminal, and the first signal input terminal are respectively transmitted to the first signal output terminal GA, the third signal output terminal COUT, and the second signal output terminal GB. Specifically, when the first bootstrap node QL and the second bootstrap node QR are at high potential, the potentials of the first signal input terminal CLK1, the second signal input terminal CLK2, and the fifth signal input terminal CLKW1 are respectively transmitted to the second signal output terminal GB, the present-stage cascade signal output terminal COUT, and the first signal output terminal GA of the present driving unit, and when the two scan signal output terminals GA and GB jump from low level to high level, the bootstrap capacitors C2 and C1 couple the potentials of the internal second bootstrap node QR and the first bootstrap node QL to higher potentials, thereby improving the driving speed.

The input module 21 is connected between the fourth signal input terminal or the third potential input terminal, the input signal input terminal CIN, and the bootstrap node pull-down module 23. The input module 21 is configured to pre-charge a first bootstrap node QL and a second bootstrap node QR of a connection node between the input module 21 and the driving pull-up module 22, so as to turn on the driving pull-up module 22. Specifically, the internal second bootstrap node QR and the first bootstrap node QL are precharged, so that the sixth transistor T201, the seventh transistor T202, and the eighth transistor T203 of the pull-up driving module 22 are turned on to prepare for outputting the scan signal. Meanwhile, the control circuit of the output pull-down module 24 is activated to pull down the potential of the internal low level maintaining node QB to the voltage VSSL of the second potential input terminal, so that the eleventh transistor T401, the twelfth transistor T402, the thirteenth transistor T403, the fourteenth transistor T404 and the fifteenth transistor T405 of the pull-down transistor are turned off before outputting the scan pulse, thereby avoiding the pull-down discharge of the scan signal output terminal in the pull-up stage, and thus improving the driving speed and reducing the power consumption.

The bootstrap node pull-down module 23 is connected between the third signal input terminal, the second potential input terminal, and the input module 21. The connection node of the input module 21 and the bootstrap node pull-down module 23 is a first bootstrap node QL. The bootstrap node pull-down module 23 is configured to drop the potential of the first bootstrap node QL to a second low potential VSSL. All transistors driving the pull-up module 22 are fully utilized to discharge the scan signal output terminal and the cascade signal output terminal COUT. In order to slow down the pull-down speed of the internal first bootstrap node QL, the transistor of the bootstrap node pull-down module 23 is diode-connected. The advantage of adopting the diode connection method is that the on-resistance is larger on the premise of not changing the size of the thin film transistor.

The low level maintaining module 25 is connected between the third potential input terminal, the third signal input terminal, the second potential input terminal, the output pull-down module 24 and the input module 21. The connection node of the low level maintaining block 25 and the output pull-down block 24 is a low level maintaining node QB. The connection node of the low level maintaining module 25 and the input module 21 is the first bootstrap node QL or the second bootstrap node QR. The low level maintaining module 25 is used for maintaining the electric potential of the low level maintaining node QB not lower than the electric potential of the second electric potential input terminal. The driving circuit unit maintains the QB node at the internal low level to be pulled down to the second low level by the twenty-first transistor T503 and the twenty-second transistor T504 during the precharge and pull-up stages, ensuring that the transistors of the output pull-down module 24 are in a fully turned-off state. In the pull-down and low level maintaining stages, the nineteenth transistor T501 periodically charges the internal low level maintaining node QB, so that the voltage of the low level maintaining node QB is always at a high level, the transistor of the output pull-down module 24 is ensured to be in a fully open state, and the two scan signal output terminals GA and GB and the cascade signal output terminal COUT are maintained at corresponding low levels. In particular, when the transistor voltage is negative, the low level maintaining node QB will face the leakage problem, and the twentieth transistor T502 will be continuously turned on to charge the low level maintaining node QB, ensuring that the potential of the low level maintaining node QB maintains the high level.

The output pull-down module 24 is connected between the first potential input terminal, the second potential input terminal, the first signal output terminal GA, the second signal output terminal GB, the third signal output terminal COUT, the low level maintaining module 25, and the input module 21. The connection node of the low level maintaining module 25 and the input module 21 is the first bootstrap node QL or the second bootstrap node QR. The output pull-down module 24 is configured to pull down the potentials of the first signal output end GA and the second signal output end GB to the potential of the first potential input end. The output pull-down module 24 is further configured to pull down the potentials of the first bootstrap node QL, the third signal output terminal COUT, and the second bootstrap node QR to the potential of the second potential input terminal.

The shift register unit shown in fig. 6 employs two bootstrap nodes, a first bootstrap node QL and a second bootstrap node QR, where the third signal output terminal COUT may share a bootstrap node with the first signal output terminal GA or the second signal output terminal GB, and specifically, a control electrode of the seventh transistor T202 may be connected with the first signal output terminal GA or the second signal output terminal GB.

As shown in fig. 6, the connection nodes between the input module 21 and the driving pull-up module 22 include a first bootstrap node QL and a second bootstrap node QR. The input block 21 includes a first transistor T101 and a second transistor T102. Control electrodes of the first transistor T101 and the second transistor T102 are connected to an input signal input terminal CIN for receiving a cascade control signal of a previous stage. First poles of the first transistor T101 and the second transistor T102 are connected to a fourth signal input terminal or a third potential input terminal. The second pole of the first transistor T101 is connected to the first bootstrap node QL. A second pole of the second transistor T102 is connected to the second bootstrapping node QR.

As shown in fig. 7, a schematic circuit structure diagram of a driving circuit unit according to an embodiment is shown, where the driving circuit unit uses three bootstrap nodes, a first bootstrap node QL, a second bootstrap node QR, and a third bootstrap node QC, that is, connection nodes between the input module 21 and the driving pull-up module 22 include the first bootstrap node QL, the second bootstrap node QR, and the third bootstrap node QC. The third bootstrap node QC is used for connecting the third signal output terminal COUT. The control electrodes of the first transistor T101, the second transistor T102, the third transistor T103, and the fourth transistor T104 are connected to an input signal input terminal CIN. The first pole of the first transistor T101 is connected to the fourth signal input terminal or the third potential input terminal. The second pole of the first transistor T101 is connected to the first pole of the second transistor T102, the first pole of the third transistor T103, the first pole of the fifth transistor T105, and the first pole of the fourth transistor T104. The second pole of the second transistor T102 is connected to the first bootstrap node QL. A second pole of the fourth transistor T104 is connected to the third bootstrap node QC. The second pole of the third transistor T103 and the control pole of the fifth transistor T105 are connected and are connected to the second bootstrap node QR. A second pole of the fifth transistor T105 is connected to the first signal output terminal GA, the second signal output terminal GB, or the third signal output terminal COUT.

Further, when the connection node between the input block 21 and the driving pull-up block 22 includes only the first bootstrap node QL and the second bootstrap node QR, the input block 21 of the driving circuit unit may eliminate the fourth transistor T104. That is, the input module 21 may further include a first transistor T101, a second transistor T102, a third transistor T103, and a fifth transistor T105. The control electrodes of the first transistor T101, the second transistor T102, and the third transistor T103 are connected to an input signal input terminal CIN. The first pole of the first transistor T101 is connected to the fourth signal input terminal or the third potential input terminal. The second pole of the first transistor T101 is connected to the first pole of the second transistor T102, the first pole of the third transistor T103, and the first pole of the fifth transistor T105. The second pole of the second transistor T102 is connected to the first bootstrap node QL. The second pole of the third transistor T103 and the control pole of the fifth transistor T105 are connected and are connected to the second bootstrap node QR. A second pole of the fifth transistor T105 is connected to the first signal output terminal GA, the second signal output terminal GB, or the third signal output terminal COUT.

As shown in fig. 8, which is a schematic circuit diagram of an input module of a circuit driving unit in an embodiment, connection nodes between the input module 21 and the driving pull-up module 22 include a first bootstrap node QL, a second bootstrap node QR, and a third bootstrap node QC. The input module 21 includes first and second transistors T101 and T102 and a third transistor T103. The control electrodes of the first transistor T101, the second transistor T102, and the third transistor T103 are connected to an input signal input terminal CIN. The second poles of the first transistor T101, the second transistor T102, and the third transistor T103 are connected to the fourth signal input terminal or the third potential input terminal. The second pole of the first transistor T101 is connected to the first bootstrap node QL. A second pole of the second transistor T102 is connected to the second bootstrapping node QR. The second pole of the third transistor T103 is connected to the third bootstrap node QC.

As shown in fig. 6, the driving pull-up module 22 specifically includes a sixth transistor T201, a seventh transistor T202, an eighth transistor T203, a first capacitor C1, and a third capacitor C3. A first pole of the sixth transistor T201 is connected to the fifth signal input terminal. The second pole of the sixth transistor T201 is connected to the first signal output terminal GA. A first pole of the seventh transistor T202 is connected to the second signal input terminal. A second pole of the seventh transistor T202 is connected to the third signal output terminal COUT. A first pole of the eighth transistor T203 is connected to the first signal input terminal. The second pole of the eighth transistor T203 is connected to the second signal output terminal GB. A control electrode of the eighth transistor T203 is connected to the second bootstrapping node QR. A control electrode of the sixth transistor T201 is connected to the first bootstrap node QL. A control electrode of the seventh transistor T202 is connected to the first bootstrap node QL, the second bootstrap node QR, or the third bootstrap node QC. The first capacitor C1 is connected in series between the control electrode and the second electrode of the sixth transistor T201. The third capacitor C3 is connected in series between the control electrode and the second electrode of the eighth transistor T203. Further, the driving pull-up module 22 may further include a second capacitor C2, which is connected in series between the control electrode and the second electrode of the seventh transistor T202 as shown in fig. 7.

As shown in fig. 6, the bootstrap node pull-down module 23 includes a ninth transistor T301. A control electrode of the ninth transistor T301 is connected to the third signal input terminal. A first pole of the ninth transistor T301 is connected to the first bootstrap node QL, the second bootstrap node QR, or the third bootstrap node QC. A second pole of the ninth transistor T301 is connected to the second potential input.

As shown in fig. 9, which is a circuit schematic diagram of the bootstrap node pull-down module of the driving circuit unit according to an embodiment, the bootstrap node pull-down module 23 may further include a ninth transistor T301 and a tenth transistor T302. A control electrode of the ninth transistor T301 is connected to the third signal input terminal. A first pole of the ninth transistor T301 is connected to the first bootstrap node QL, the second bootstrap node QR, or the third bootstrap node QC. A control electrode of the tenth transistor T302 is shorted with the first electrode and connected with the second electrode of the ninth transistor T301. A second pole of the tenth transistor T302 is connected to the second potential input terminal.

As shown in fig. 6, the connection node between the low level maintaining module 25 and the output pull-down module 24 includes a low level maintaining node QB. The output pull-down block 24 includes an eleventh transistor T401, a twelfth transistor T402, a thirteenth transistor T403, a fourteenth transistor T404, and a fifteenth transistor T405. The gates of the eleventh, twelfth, thirteenth, fourteenth and fifteenth transistors T401, T402, T403, T404 and T405 are connected to the low level maintenance node QB. The second pole of the eleventh transistor T401, the thirteenth transistor T403 and the fourteenth transistor T404 is connected to the second potential input terminal. The second poles of the twelfth transistor T402 and the fifteenth transistor T405 are connected to the first potential input terminal. A first pole of the eleventh transistor T401 is connected to the first bootstrap node QL. A first pole of the twelfth transistor T402 is connected to the first signal output terminal GA. A first pole of the thirteenth transistor T403 is connected to the third signal output terminal COUT. A first pole of the fourteenth transistor T404 is connected to the second bootstrapping node QR. A first pole of the fifteenth transistor T405 is connected to the second signal output terminal GB.

As shown in fig. 7, the connection node between the low level maintaining module 25 and the output pull-down module 24 includes a low level maintaining node QB. The output pull-down block 24 includes an eleventh transistor T401, a twelfth transistor T402, a thirteenth transistor T403, a fourteenth transistor T404, a fifteenth transistor T405, and a sixteenth transistor T406. The control electrodes of the eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth transistors T401, T402, T403, T404, T405 and T406 are connected to the low level maintaining node QB. A first pole of the eleventh transistor T401 is connected to the first bootstrap node QL. A first pole of the twelfth transistor T402 is connected to the first signal output terminal GA. A first pole of the thirteenth transistor T403 is connected to the third bootstrap node QC. A first pole of the fourteenth transistor T404 is connected to the third signal output terminal COUT. A first pole of the fifteenth transistor T405 is connected to the second bootstrap node QR. A first pole of the sixteenth transistor T406 is connected to the second signal output terminal GB. A second pole of the eleventh transistor T401, the thirteenth transistor T403, the fourteenth transistor T404, and the fifteenth transistor T405 is connected to the second potential input terminal. The second poles of the twelfth transistor T402 and the sixteenth transistor T406 are connected to the first potential input terminal.

Fig. 10 is a circuit schematic diagram of an output pull-down module of a driving circuit unit according to an embodiment, and the output pull-down module 24 includes an eleventh transistor T401, a twelfth transistor T402, a fourteenth transistor T404, a fifteenth transistor T405, a sixteenth transistor T406, a seventeenth transistor T407, and an eighteenth transistor T408. The gates of the eleventh, twelfth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth transistors T401, T402, T404, T405, T407, and T408 are connected to the low level maintenance node QB. A first pole of the eleventh transistor T401 is connected to the first bootstrap node QL. A first pole of the twelfth transistor T402 is connected to the first signal output terminal GA. A first pole of the fourteenth transistor T404 is connected to the third signal output terminal COUT. A first pole of the fifteenth transistor T405 is connected to the second bootstrap node QR. A first pole of the sixteenth transistor T406 is connected to the second signal output terminal GB. The second poles of the eleventh, fourteenth and fifteenth transistors T401, T404 and T405 are connected to the first pole of the seventeenth transistor T407. The second poles of the twelfth transistor T402 and the sixteenth transistor T406 are connected to the first pole of the eighteenth transistor T408. The second pole of the seventeenth transistor T407 is connected to the second potential input terminal. The second pole of the eighteenth transistor T408 is connected to the first potential input terminal.

Fig. 11 is a circuit diagram of an output pull-down module of a driving circuit unit according to an embodiment, which has one more thirteenth transistor T403 compared with the circuit of the output pull-down module shown in fig. 10. The output pull-down block 24 includes an eleventh transistor T401, a twelfth transistor T402, a thirteenth transistor T403, a fourteenth transistor T404, a fifteenth transistor T405, a sixteenth transistor T406, a seventeenth transistor T407, and an eighteenth transistor T408. The control electrodes of the eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth transistors T401, T402, T403, T404 are connected to the low level maintaining node QB. A first pole of the eleventh transistor T401 is connected to the first bootstrap node QL. A first pole of the twelfth transistor T402 is connected to the first signal output terminal GA. A first pole of the thirteenth transistor T403 is connected to the third bootstrap node QC. A first pole of the fourteenth transistor T404 is connected to the third signal output terminal COUT. A first pole of the fifteenth transistor T405 is connected to the second bootstrap node QR. A first pole of the sixteenth transistor T406 is connected to the second signal output terminal GB. The second poles of the eleventh, thirteenth, fourteenth and fifteenth transistors T401, T403, T404 and T405 are connected to the first pole of the seventeenth transistor T407. The second poles of the twelfth transistor T402 and the sixteenth transistor T406 are connected to the first pole of the eighteenth transistor T408. The second pole of the seventeenth transistor T407 is connected to the second potential input terminal. The second pole of the eighteenth transistor T408 is connected to the first potential input terminal.

As shown in fig. 7, the low level maintaining module 25 includes a nineteenth transistor T501, a twentieth transistor T502, a twenty-first transistor T503, and a twenty-second transistor T504. The control electrode and the first electrode of the nineteenth transistor T501 are connected to the third signal input terminal or the third potential input terminal. The second pole of the nineteenth transistor T501 is connected to the second pole of the twentieth transistor T502. The control electrode and the second electrode of the twentieth transistor T502 are shorted and connected to the low level maintenance node QB. A first pole of the twentieth transistor T502 is connected to the third potential input terminal. A control electrode of the twenty-first transistor T503 is connected to the first bootstrapping node QL or the second bootstrapping node QR. A first pole of the twenty-first transistor T503 is connected to a second pole of the nineteenth transistor T501. A second pole of the twenty-first transistor T503 is connected to the second potential input terminal. The control stage of the twentieth transistor T504 is connected to the input signal input CIN. The first pole of the twentieth transistor T504 is connected to the low level maintenance node QB. The second pole of the twentieth transistor T504 is connected to the second potential input terminal.

Fig. 12(a) is a circuit schematic diagram of a low level maintaining module of the circuit driving unit according to an embodiment, and the low level maintaining module 25 includes a nineteenth transistor T501, a twentieth transistor T502, and a twenty-first transistor T503. The control electrode and the first electrode of the nineteenth transistor T501 are connected to the third signal input terminal. The second pole of the nineteenth transistor T501 is connected to the second pole of the twentieth transistor T502. The control electrode and the second electrode of the twentieth transistor T502 are shorted and connected to the low level maintaining node QB. A first pole of the twentieth transistor T502 is connected to the third potential input terminal. A control electrode of the twenty-first transistor T503 is connected to the first bootstrapping node QL or the second bootstrapping node QR. A first pole of the twenty-first transistor T503 is connected to a second pole of the nineteenth transistor T501. A second pole of the twenty-first transistor T503 is connected to the second potential input terminal.

Fig. 12(b) is a circuit schematic diagram of the low level maintaining module of the circuit driving unit according to an embodiment, and the low level maintaining module 25 may further include a nineteenth transistor T501, a twentieth transistor T502, a twenty-first transistor T503, a twenty-fourth transistor T506, and a twenty-third transistor T505. The control electrode and the first electrode of the nineteenth transistor T501 are connected to the third signal input terminal. The second pole of the nineteenth transistor T501 is connected to the second pole of the twentieth transistor T502. The control electrode and the second electrode of the twentieth transistor T502 are shorted and connected to the second electrode of the nineteenth transistor T501. A first pole of the twentieth transistor T502 is connected to the third potential input terminal. A control electrode of the twenty-first transistor T503 is connected to the first bootstrapping node QL or the second bootstrapping node QR. A first pole of the twenty-first transistor T503 is connected to a second pole of the nineteenth transistor T501. A second pole of the twenty-first transistor T503 is connected to the second potential input terminal. A control electrode of the twenty-fourth transistor T506 is connected to the first bootstrapping node QL or the second bootstrapping node QR. A first pole of the twenty-fourth transistor T506 is connected to the low level maintenance node QB. A second pole of the twenty-fourth transistor T506 is connected to the second potential input. A control electrode of the twenty-third transistor T505 is connected to the second electrode of the nineteenth transistor T501. A first pole of the twenty-third transistor T505 is connected to the third potential input terminal. The second pole of the twenty-third transistor T505 is connected to the low level maintenance node QB.

Fig. 12(c) is a circuit schematic diagram of the low level maintaining module of the circuit driving unit according to an embodiment, and the low level maintaining module 25 may further include a nineteenth transistor T501, a twenty-first transistor T503, a twenty-third transistor T505, a twenty-fourth transistor T506, and a twenty-fifth transistor T507. The control electrode and the first electrode of the nineteenth transistor T501 are connected to the third signal input terminal. The second pole of the nineteenth transistor T501 is connected to the first pole of the twenty-first transistor T503. A control electrode and a second electrode of the twenty-fifth transistor T507 are shorted and connected to the low level maintaining node QB. A first pole of the twenty-fifth transistor T507 is connected to the third potential input terminal. A control electrode of the twenty-first transistor T503 is connected to the first bootstrapping node QL or the second bootstrapping node QR. A second pole of the twenty-first transistor T503 is connected to the second potential input terminal. A control electrode of the twenty-fourth transistor T506 is connected to the first bootstrapping node QL or the second bootstrapping node QR. A first pole of the twenty-fourth transistor T506 is connected to the low level maintenance node QB. A second pole of the twenty-fourth transistor T506 is connected to the second potential input. A control electrode of the twenty-third transistor T505 is connected to a second electrode of the nineteenth transistor T501. A first pole of the twenty-third transistor T505 is connected to the third potential input terminal. The second pole of the twenty-third transistor T505 is connected to the low level maintenance node QB.

Fig. 13 is a circuit schematic diagram of a low level maintaining module of the circuit driving unit according to an embodiment, and the low level maintaining module 25 may further include a nineteenth transistor T501, a twentieth transistor T502, a twenty-first transistor T503, and a twenty-second transistor T504. A control electrode of the nineteenth transistor T501 is connected to the third signal input terminal. A first pole of the nineteenth transistor T501 is connected to the third signal input terminal or the third potential input terminal. The second pole of the nineteenth transistor T501 and the second pole of the twentieth transistor T502 are connected. The control electrode of the twentieth transistor T502 is shorted with the second electrode of the twentieth transistor T502 and connected to the low level maintenance node QB. A first pole of the twentieth transistor T502 is connected to the third potential input terminal. A control electrode of the twenty-first transistor T503 is connected to the first bootstrapping node QL or the second bootstrapping node QR. A first pole of the twenty-first transistor T503 is connected to a second pole of the nineteenth transistor T501. A second pole of the twenty-first transistor T503 is connected to the second potential input terminal. The control electrode of the twentieth transistor T504 is connected to the input signal input terminal CIN. A first pole of the twentieth transistor T504 is connected to a second pole of the nineteenth transistor T501. The second pole of the twentieth transistor T504 is connected to the second potential input terminal.

Further, the low level maintaining module 25 further includes a fourth capacitor CS connected in series between the low level maintaining node QB and the second potential input terminal.

In the driving circuit unit as described above, the third signal output terminal COUT is connected to the input signal input terminal CIN of the next driving circuit unit. The third signal output terminal COUT outputs the cascade signal of this stage for inputting the preceding stage cascade signal of the driving circuit unit of the next stage. The input signal input terminal CIN is connected to the signal output terminal COUT of the previous stage driving circuit unit, and is configured to receive an input of the previous stage cascade signal output by the previous stage driving circuit unit.

Fig. 14 is a timing diagram illustrating an operation of the driving circuit unit according to an embodiment, wherein the operation of the driving circuit unit shown in fig. 6 is divided into four stages, including:

(1) during the precharge phase, the input signal input terminal CIN is at a high level, and the fourth signal input terminal CLK4 is at a high level. The first transistor T101, the second transistor T102, and the third transistor T103 are turned on, and precharge the internal first bootstrap node QL and the second bootstrap node QR. The high level of the fourth signal input terminal CLK4 is transferred to the first bootstrap node QL and the second bootstrap node QR. The sixth transistor T201, the seventh transistor T202, and the eighth transistor T203 are turned on. The low levels of the second signal input terminal CLK2 and the fifth signal input terminal CLKW1 are transmitted to the cascade signal output terminal COUT and the first signal output terminal GA of the present driving unit. The low level of the first signal input terminal CLK1 is transferred to the present stage second signal output terminal GB. The twenty-first transistor T503 is turned on by the high level of the input signal input terminal CIN, transmits the low level of the second potential input terminal to the low level maintaining node QB, and turns off all the transistors of the output pull-down module 24. Since the transistors need a certain time to turn off, if all the transistors of the output pull-down module 24 can be controlled to turn off in advance, the leakage phenomenon occurring when the pull-up stage starts to pull up can be avoided, thereby improving the driving speed and reducing the power consumption.

(2) In the pull-up stage, the fourth signal input terminal CLK4 and the input signal input terminal CIN are at low level, the high levels of the second signal input terminal CLK2 and the fifth signal input terminal CLKW1 are respectively transmitted to the current stage cascade signal output terminal COUT and the current stage first signal output terminal GA, and the high level of the first signal input terminal CLK1 is transmitted to the current stage second signal output terminal GB. When the first signal output terminal GA and the second signal output terminal GB are stepped to a high level, the first bootstrap node QL and the second bootstrap node QR are raised to a higher potential due to the bootstrap effect of the bootstrap capacitors C1 and C2, so as to further improve the pull-up speed. The bootstrap node potential variation is:

specifically, the Scan signal output by the first signal output GA has two pulses, so that the corresponding first bootstrap node QL will be bootstrapped twice, and the two bootstrap node voltage variations are the same.

(3) In the pull-down stage, in order to fully utilize the sixth transistor T201 and the eighth transistor T203 of the driving transistor to discharge the first signal output end GA and the second signal output end GB, the pull-down speed is increased, so that the discharge of the first bootstrap node QL and the second bootstrap node QR lags behind the discharge of the first signal output end GA and the second signal output end GB. The low levels of the second signal input terminal CLK2 and the fifth signal input terminal CLKW1 are transmitted to the current stage first signal output terminal GA and the cascade signal output terminal COUT, and the low level of the first signal input terminal CLK1 is transmitted to the current stage second signal output terminal GB. Meanwhile, the nineteenth transistor T501 of the low level maintaining module 25 transmits the high level of the high level terminal to the low level maintaining node QB, so that all the transistors of the output pull-down module 24 are turned on. In particular, since the low-level rising speed of the internal low-level maintaining node QB is slow, and the high-level falling speed of the first bootstrap node QL and the second bootstrap node QR is slow, the speed of the pull-down discharging of the first signal output GA, the second signal output GB, and the cascade signal output of the current stage by the output pull-down module 24 is slower than the speed of the pull-up module 22.

(4) In the low level maintaining stage, in any clock pulse width of this stage, the third signal input terminal CLK3 is at a high level, the high level output terminal transmits the high level to the low level maintaining node QB, all transistors of the output pull-down module 24 are turned on, and the first signal output terminal GA and the second signal output terminal GB, the third signal output terminal COUT, the first bootstrap node QL, and the second bootstrap node QR of this stage are continuously pulled down. When the nineteenth transistor T501 has a positive threshold voltage, the twenty-first transistor T503 and the twenty-second transistor T504 are turned off, and the pull-down transistor continues to pull down the output because the low level sustain node QB has no discharge path to be maintained at the high level. In addition, under the control of the clock signal at the third signal input terminal CLK3, the bootstrap node pull-down module 23 discharges the internal first bootstrap node QL periodically, maintains the low voltage level at the first bootstrap node QL, and further stabilizes the output. When the transistors exhibit the negative threshold characteristic, when the third signal input terminal CLK3 is at a low level, the low level hold node QB is discharged to a low level due to leakage of the twenty-first transistor T503 and the twenty-second transistor T504. At this time, the circuit charges the low level maintaining node QB point continuously by using the twentieth transistor T502 which is continuously turned on, so that all the transistors of the output pull-down module 24 are still in the on state.

As shown in fig. 15, a comparison diagram of complex signals generated by the driving circuit unit disclosed in the embodiment is a comparison of simulation results of the first bootstrap node QL, the second bootstrap node QR, the first signal output end GA, and the second signal output end GB in the common bootstrap node structure shown in fig. 2, the increased diode connection isolation bootstrap node structure shown in fig. 3, and the dual bootstrap node structure shown in fig. 5 of the embodiment. The abscissa is time, the ordinate is a voltage value, the common bootstrap node shown in fig. 2 is represented by a dot-and-dash line, the added diode connection method shown in fig. 3 is represented by a dotted line, and the dual bootstrap node connection method shown in fig. 5 is represented by a solid line. The rising time of the output scanning signal depends on the electric potential of the bootstrap node before and after the upward jump of the scanning pulse, and similarly, the falling time of the output scanning signal depends on the electric potential of the bootstrap node before and after the downward jump of the scanning pulse. For the second scanning signal output end GB, the rising time of the output scanning signals of the three structures is similar, the common bootstrap node structure is 1.52 mu s, the diode connection isolation bootstrap node is 1.81 mu s, and the double bootstrap node structure is 1.65 mu s. The fall times of the output scan signals of the three configurations are widely different. The shared bootstrap node structure is 1.09 mus, the diode connection isolation bootstrap node structure is 2.46 mus, and the double bootstrap node structure is 1.49 mus. This difference results from the fact that the potential changes of the second bootstrap node QR (the common bootstrap node structure has only one bootstrap node Q, and the curve is shown in the node QR graph) are not the same. The first bootstrap nodes QR of the three structures are bootstrapped to a high level of about 45V in the pull-up stage, so that the rising time of the output scanning signals is similar.

Under the clock feed-through effect of the complex clock signal, the bootstrap node Q of the shared bootstrap node structure maintains the electric potential at 31.33V within a pulse width time when the first output scanning pulse jumps to a low level, the driving thin film transistor has a high driving voltage continuously, and the pull-down discharging capability is strong.

The potential of the second bootstrap node QR of the diode-connected isolation bootstrap node structure leaks to the first bootstrap node QL, the voltage jumps from 45.17V to 29.65V, and then jumps from 29.65V to 4.02V under the clock feedthrough effect, which results in that the discharge capability of the driving transistor of the driving pull-up module 22 is weaker than that of the other two structures, and the falling time of the scanning signal output of the second signal output terminal GB is prolonged.

The potential of the second bootstrap node QR of the double bootstrap node structure is reduced from 45.17V to 13.56V due to the clock feedthrough effect within a pulse width time when the scanning pulse jumps to the low level, and the falling time of the scanning pulse is in the middle of the three structures.

The analysis method is similar for the first signal output GA. Since the scanning signal has two pulses, the output scanning signal has two rising and falling times respectively. The rise-fall time of the first pulse of the three structures output scanning signals is not greatly different, but the rise-fall time of the second pulse is obviously different. The second pulse of the common bootstrap node has a rise time of 2.64 mus and a fall time of 1.68 mus. The rise time and the fall time of the second pulse of the diode-connected isolation bootstrap node structure are respectively 1.25 mus and 1.13 mus. The second pulse of the dual bootstrap node structure has a rise time of 1.61 mus and a fall time of 1.68 mus.

The difference of the rise and fall times of the first pulse is not caused by the difference of the potentials of the first bootstrap node QL (the structure of the common bootstrap node is Q, and the curve is shown in the node QR diagram) before and after the first pulse jump. The first bootstrap node QL has a significant potential difference before and after the second pulse makes an upward or downward transition. When the second pulse jumps up or down, the potential of the bootstrap node Q of the shared bootstrap node structure is maintained at 31.33V, no obvious second bootstrap exists, and the rising time of the second pulse jumping up is excessively long. The first bootstrap node QL of the diode-connected isolation bootstrap node structure is charged to 46.27V in half the pulse width after the first pulse jumps down due to leakage of the second bootstrap node QR, and when the second pulse jumps up, the first bootstrap node QL is bootstrapped to 56.53V under the second bootstrap action and is maintained until the second pulse jumps down, so that the rise-fall time of the second pulse of the diode-connected isolation bootstrap node structure is shorter compared with the other two structures. The first bootstrap node QL of the dual bootstrap node structure has similar two bootstrap potentials, so that the rising and falling times of two pulses are similar.

Fig. 16 is a comparison diagram of complex signals generated by the driving circuit unit disclosed in the embodiment, which is a comparison of simulation results of the first bootstrap node QL, the second bootstrap node QR, the first signal output end GA, and the second signal output end GB in the common bootstrap node structure shown in fig. 2, the additional diode connection isolation bootstrap node structure shown in fig. 3, and the dual bootstrap node structure shown in fig. 5 of the present embodiment, respectively. The abscissa is time, the ordinate is a voltage value, the common bootstrap node shown in fig. 2 is represented by a dot-and-dash line, the added diode connection method shown in fig. 3 is represented by a dotted line, and the dual bootstrap node connection method shown in fig. 5 is represented by a solid line. When the threshold of the thin film transistor driven by the integrated gate shifts forwards by 4V, that is, the threshold voltage is Vth equal to 5V, the problem of insufficient second pulse bootstrap capability of the common bootstrap node structure and the problem of QR leakage of the second bootstrap node of the diode-connected isolation bootstrap node structure are more obvious. For the second signal output end GB, the falling time of a scanning signal of the first output signal end GB of the diode connection isolation bootstrap node structure is as long as 5.12 mu s, and is far greater than 1.26 mu s of the common bootstrap node structure and 2.25 mu s of the double bootstrap node structure. The overlong fall time of the diode-connected isolation bootstrap node structure is caused by the fact that the QR potential of the second bootstrap node of the diode-connected isolation bootstrap node structure is reduced to 25.13V from 40.96V in a leakage mode, and jumps to 1.04V under the action of clock feed-through, and the discharge capacity of the driving thin film transistor is reduced. For the first signal output end GA, the common bootstrap node structure is only 25.52V because the bootstrap node Q cannot be bootstrapped for the second time, and the driving capability of the driving thin film transistor is weak, so that the rise time of the second pulse is too long, and the pulse is charged to 14.18V within one pulse width time, which is less than 20.00V of the other two structures. Additionally, there is another problem in the diode-connected isolated bootstrap node structure, that is, there are two threshold voltage losses during the pre-charging process of the first bootstrap node QL, and the pre-charging potential is only 2.32V, which results in that the rising time of the first pulse is long, and the maximum potential is 13.65V, which is lower than 18.08V of the common bootstrap node structure and 16.99V of the dual bootstrap node structure. Further, the larger the threshold voltage, the larger the threshold loss. The longer the rise time of the first pulse, the lower the maximum potential.

With the simulation results shown in fig. 15 and fig. 16, compared with the three bootstrap node structures, the independent dual bootstrap node method in this embodiment has a more stable bootstrap node, and has no problems of insufficient second bootstrap capacity, multiple threshold voltage losses, and bootstrap node leakage, good symmetry of rising and falling times of two scan output signals, and no problem of too long rising (or falling) time of a scan signal.

Fig. 17 is a schematic diagram of output signals of the driving circuit unit in an embodiment. When the threshold value is shifted in the negative direction, that is, when the threshold voltage Vth is-5V, the presence or absence of the single-stage scanning signal output of the gate driving unit of the twentieth transistor T502 is compared. In the absence of the twentieth transistor T502, when the third signal input terminal CLK3 is at a low level, the low-level sustain node QB is pulled down to-7.6V due to leakage of the twenty-first transistor T503 and the twenty-second transistor T504, which causes the scan signal level of the first signal output terminal GA to jump from-10.2V to-7.1V, the scan signal level of the second signal output terminal GB to jump from-10.1V to-6.2V, and the signal level of the present stage cascade signal output terminal COUT to jump from-15.0V to-7.2V. Therefore, the twentieth transistor T502 can well stabilize the low level to maintain the high level of the low level maintaining node, and stabilize the scan output terminal and the current stage cascade signal output terminal COUT at the corresponding low level.

As described above, the present application discloses a design of a driver circuit cell with separate bootstrap nodes, where a single integrated driver cell outputs two kinds of scan signals. The new drive circuit has output scanning signals with full amplitude, short rising and falling time of the scanning signals and good symmetry of rising and falling waveforms of the scanning pulses. Meanwhile, a feedback structure is introduced into the low-level maintaining module part, and the grid electrode of the pull-down transistor of the low-level maintaining part is coupled to the high level through a diode connection method, so that the low-level maintaining part can still normally work when the threshold voltage of the transistor is negative. The driving circuit unit disclosed by the application can be applied to the field of flat panel display, the field of AMOLED display and the field of TFT-LCD display.

The drive circuit unit in this application can satisfy AMOLED pixel circuit to the requirement of two kinds of scanning signal, through adopting the separation input to produce mutually independent two bootstrap nodes, avoids the clock feed-through effect to lead to taking place charge coupling between the different bootstrap nodes, solves the problem that thin-film transistor electric leakage leads to bootstrap node voltage to descend, makes the pulse shape of output scanning signal more complete and have symmetry, shorter rise fall time. And further, the normal work of the pixel circuit is ensured, and the stability and the uniformity of the AMOLED display are better. And then by introducing a feedback transistor connected with a diode, when the threshold voltage of the transistor is negative, the low level maintaining node can still maintain high level, and the scanning signal of the output end is maintained at corresponding low level, so that the normal work of the pixel circuit is ensured.

Example two:

fig. 18 is a schematic diagram of a driving circuit structure in an embodiment, where the driving circuit structure includes a plurality of driving circuit units in the first embodiment, and each of the driving circuit units is connected in cascade. Specifically, the clock line includes a first clock line CLK1, a second clock line CLK2, a third clock line CLK3, a fourth clock line CLK4, a fifth clock line CLKW1, a sixth clock line CLKW2, a first low potential line VSS, a second low potential line VSSL, a first high potential line VH, an input signal input line CIN, and a cascade signal output line COUT. The driving circuit further comprises driving circuit units in the first embodiment of the N + 1-stage cascade, wherein N is a positive integer. The first clock line CLK1, the second clock line CLK2, the third clock line CLK3 and the fourth clock line CLK4 transmit clock signals for the driving circuit unit. The input signal input CIN of the driver circuit unit of the first stage is used for coupling the start signal STV. The input signal input end CIN of the second-stage driving circuit unit and the input signal input end CIN of the last-stage driving circuit unit are coupled with the cascade signal output end COUT of the last-stage driving circuit unit. A fifth clock line CLKW1 is coupled to the fifth signal input terminal of the odd-stage driver circuit unit for input of the complex pulse signal CLKW 1. A sixth clock line CLKW2 is coupled to the fifth signal input terminal of the even stage driver circuit unit for input of the complex pulse signal CLKW 2. The first low potential line VSS, the second low potential line VSSL, and the first high potential line VH are the drive circuit unit input voltage signals.

The application also discloses a display, which comprises a panel and the driving circuit. The panel includes a two-dimensional pixel array composed of a plurality of pixels, and a plurality of data lines in a first direction and a plurality of gate scan lines in a second direction connected to each pixel in the array. The driving circuit as described above supplies the gate driving signal to the gate scan line.

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims

1. A driving circuit unit is characterized by comprising an input module (21), a driving pull-up module (22), a bootstrap node pull-down module (23), an output pull-down module (24) and a low level maintaining module (25); further comprising:

a first signal input for receiving a first clock signal (CLK 1);

a second signal input for receiving a second clock signal (CLK 2);

a third signal input for receiving a third clock signal (CLK 3);

a fourth signal input for receiving a fourth clock signal (CLK 4);

a fifth signal input for receiving a first complex clock signal (CLKW);

a first potential input terminal for input of a first low potential (VSS);

a second potential input terminal for input of a second low potential (VSSL);

the output pull-down module (24) is connected among a first potential input end, a second potential input end, a first signal output end (GA), a second signal output end (GB), a third signal output end (COUT), the low level maintaining module (25) and the input module (21); the output pull-down module (24) is used for pulling down the electric potentials of the first signal output end (GA) and the second signal output end (GB) to the electric potential of the first electric potential input end; the output pull-down module (24) is further configured to drop a potential of a connection node between the output pull-down module (24) and the input module (21) and a potential of a third signal output terminal (COUT) to a second low potential (VSSL) of a second potential input terminal.

2. The driving circuit unit according to claim 1, wherein the number of connection nodes between the input module (21) and the driving pull-up module (22) is not less than 1.

3. The driver circuit cell of claim 1, wherein a connection node between the input module (21) and the driving pull-up module (22) comprises a first bootstrap node (QL) and a second bootstrap node (QR);

the input module (21) comprises a first transistor (T101) and a second transistor (T102);

the control electrodes of the first transistor (T101) and the second transistor (T102) are connected to the input signal input (CIN); the first poles of the first transistor (T101) and the second transistor (T102) are connected to the fourth signal input or the third potential input; a second pole of the first transistor (T101) is connected to the first bootstrap node (QL); a second pole of the second transistor (T102) is connected to the second bootstrap node (QR);

or the like, or, alternatively,

the connection node between the input module (21) and the driving pull-up module (22) comprises a first bootstrap node (QL) and a second bootstrap node (QR);

the input module (21) comprises a first transistor (T101), a second transistor (T102), a third transistor (T103) and a fifth transistor (T105);

the control electrodes of the first transistor (T101), the second transistor (T102) and the third transistor (T103) are connected to the input signal input terminal (CIN); a first pole of the first transistor (T101) is connected to the fourth signal input or the third potential input; a second pole of the first transistor (T101) is connected to a first pole of the second transistor (T102), a first pole of the third transistor (T103), and a first pole of the fifth transistor (T105); a second pole of the second transistor (T102) is connected to the first bootstrap node (QL); a second pole of the third transistor (T103) and a control pole of the fifth transistor (T105) are connected, and connected to a second bootstrap node (QR); a second pole of the fifth transistor (T105) is connected to the first signal output (GA), the second signal output (GB) or the third signal output (COUT).

4. The driving circuit unit of claim 3, wherein the driving pull-up module (22) comprises a sixth transistor (T201), a seventh transistor (T202), an eighth transistor (T203), a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3);

a first pole of the sixth transistor (T201) is connected to the fifth signal input; a second pole of the sixth transistor (T201) is connected to the first signal output (GA);

a first pole of the seventh transistor (T202) is connected to the second signal input; a second pole of the seventh transistor (T202) is connected to a third signal output terminal (COUT);

a first pole of the eighth transistor (T203) is connected to the first signal input; a second pole of the eighth transistor (T203) is connected to the second signal output (GB);

the first capacitor (C1) is connected in series between the control electrode and the second electrode of the sixth transistor (T201);

the second capacitor (C2) is connected in series between the control electrode and the second electrode of the seventh transistor (T202);

the third capacitor (C3) is connected in series between the control electrode and the second electrode of the eighth transistor (T203);

a control electrode of the eighth transistor (T203) is connected to the second bootstrap node (QR);

a control electrode of the sixth transistor (T201) is connected to the first bootstrap node (QL);

a control electrode of the seventh transistor (T202) is connected to the first bootstrap node (QL) or the second bootstrap node (QR).

5. The driver circuit unit according to claim 3, wherein the bootstrap node pull-down module (23) comprises a ninth transistor (T301);

a control electrode of the ninth transistor (T301) is connected to the third signal input terminal;

a first pole of the ninth transistor (T301) and the first bootstrap node (QL) or the second bootstrap node (QR);

a second pole of the ninth transistor (T301) is connected to the second potential input;

or the like, or, alternatively,

the bootstrap node pull-down module (23) comprises a ninth transistor (T301) and a tenth transistor (T302);

a control electrode of the ninth transistor (T301) is connected to the third signal input terminal; a first pole of the ninth transistor (T301) and the first bootstrap node (QL) or the second bootstrap node (QR);

a control electrode of the tenth transistor (T302) is shorted with the first electrode and connected to the second electrode of the ninth transistor (T301); a second pole of the tenth transistor (T302) is connected to the second potential input.

6. The driving circuit unit according to claim 3, wherein the connection node between the low level maintaining module (25) and the output pull-down module (24) comprises a low level maintaining node (QB);

the output pull-down module (24) includes an eleventh transistor (T401), a twelfth transistor (T402), a thirteenth transistor (T403), a fourteenth transistor (T404), and a fifteenth transistor (T405);

the control electrodes of the eleventh transistor (T401), the twelfth transistor (T402), the thirteenth transistor (T403), the fourteenth transistor (T404), and the fifteenth transistor (T405) are connected to the low level maintaining node (QB);

a second pole of the eleventh transistor (T401), the thirteenth transistor (T403), and the fourteenth transistor (T404) is connected to the second potential input terminal; a second pole of the twelfth transistor (T402) and the fifteenth transistor (T405) is connected to the first potential input terminal;

a first pole of the eleventh transistor (T401) is connected to the first bootstrap node (QL); a first pole of the twelfth transistor (T402) is connected to the first signal output (GA); a first pole of the thirteenth transistor (T403) is connected to the third signal output terminal (COUT); a first pole of the fourteenth transistor (T404) is connected to the second bootstrap node (QR); a first pole of the fifteenth transistor (T405) is connected to the second signal output terminal (GB);

or the like, or, alternatively,

the output pull-down module (24) includes an eleventh transistor (T401), a twelfth transistor (T402), a fourteenth transistor (T404), a fifteenth transistor (T405), a sixteenth transistor (T406), a seventeenth transistor (T407), and an eighteenth transistor (T408);

control electrodes of the eleventh transistor (T401), the twelfth transistor (T402), the fourteenth transistor (T404), the fifteenth transistor (T405), the sixteenth transistor (T406), the seventeenth transistor (T407), and the eighteenth transistor (T408) are connected to the low-level maintenance node (QB);

a first pole of the eleventh transistor (T401) is connected to the first bootstrap node (QL); a first pole of the twelfth transistor (T402) is connected to the first signal output (GA); a first pole of the fourteenth transistor (T404) is connected to the third signal output terminal (COUT); a first pole of the fifteenth transistor (T405) is connected to the second bootstrap node (QR); a first pole of the sixteenth transistor (T406) is connected to the second signal output terminal (GB);

a second pole of the eleventh transistor (T401), the fourteenth transistor (T404) and the fifteenth transistor (T405) is connected to a first pole of the seventeenth transistor (T407); the second poles of the twelfth transistor (T402) and the sixteenth transistor (T406) are connected to the first pole of the eighteenth transistor (T408); a second pole of the seventeenth transistor (T407) is connected to the second potential input terminal; a second pole of the eighteenth transistor (T408) is connected to the first potential input.

7. The driving circuit unit according to claim 3, wherein the connection node between the low level maintaining module (25) and the output pull-down module (24) comprises a low level maintaining node (QB);

the low level maintaining module (25) includes a nineteenth transistor (T501), a twentieth transistor (T502), and a twenty-first transistor (T503);

a control electrode of the nineteenth transistor (T501) is connected to the first electrode and to the third signal input terminal; a second pole of the nineteenth transistor (T501) is connected to a second pole of the twentieth transistor (T502);

a control electrode and a second electrode of the twentieth transistor (T502) are shorted and connected to the low-level maintenance node (QB); a first pole of the twentieth transistor (T502) is connected to the third potential input terminal or the third signal input terminal;

a control electrode of the twenty-first transistor (T503) is connected to the first bootstrap node (QL) or the second bootstrap node (QR); a first pole of the twenty-first transistor (T503) is connected to a second pole of the nineteenth transistor (T501); a second pole of the twenty-first transistor (T503) is connected to the second potential input;

or the like, or, alternatively,

the low level maintaining module (25) includes a nineteenth transistor (T501), a twentieth transistor (T502), a twenty-first transistor (T503), and a twenty-second transistor (T504);

a control electrode of the nineteenth transistor (T501) is connected to the third signal input terminal; a first pole of the nineteenth transistor (T501) is connected to the third signal input or the third potential input; a second pole of the nineteenth transistor (T501) and a second pole of the twentieth transistor (T502) are connected;

a control electrode of the twentieth transistor (T502) is shorted with a second electrode of the twentieth transistor (T502) and connected to the low level maintaining node (QB); a first pole of the twentieth transistor (T502) is connected to the third potential input terminal;

a control electrode of the twenty-second transistor (T504) is connected to the input signal input (CIN); a first pole of the twentieth transistor (T504) is connected to a second pole of the nineteenth transistor (T501); a second pole of the twenty-second transistor (T504) is connected to the second potential input;

or the like, or, alternatively,

the low level maintaining module (25) includes a nineteenth transistor (T501), a twentieth transistor (T502), a twenty-first transistor (T503), a twenty-third transistor (T505), and a twenty-fourth transistor (T506);

a control electrode and a first electrode of the nineteenth transistor (T501) are connected to the third signal input terminal; a second pole of the nineteenth transistor (T501) is connected to a second pole of the twentieth transistor (T502);

the control electrode and the second electrode of the twentieth transistor (T502) are short-circuited and connected with the second electrode of the nineteenth transistor (T501); a first pole of the twentieth transistor (T502) is connected to the third potential input terminal;

a control electrode of the twenty-fourth transistor (T506) is connected to the first bootstrap node (QL) or the second bootstrap node (QR); a first pole of the twenty-fourth transistor (T506) is connected with the low level maintenance node (QB); a second pole of the twenty-fourth transistor (T506) is connected to the second potential input;

a control electrode of the twenty-third transistor (T505) and a second electrode of the nineteenth transistor (T501) are connected; a first pole of the twenty-third transistor (T505) is connected to the third potential input terminal; a second pole of the twenty-third transistor (T505) is connected with the low level maintenance node (QB);

or the like, or, alternatively,

the low level maintaining module (25) includes a nineteenth transistor (T501), a twenty-first transistor (T503), a twenty-second transistor (T504), a twenty-third transistor (T505), a twenty-fourth transistor (T506), and a twenty-fifth transistor (T507);

a control electrode and a first electrode of the nineteenth transistor (T501) are connected to the third signal input terminal; a second pole of the nineteenth transistor (T501) is connected to a first pole of the twenty-first transistor (T503);

a control electrode and a second electrode of the twenty-fifth transistor (T507) are shorted and connected to the low-level maintenance node (QB); a first pole of the twenty-fifth transistor (T507) is connected to the third potential input terminal;

a control electrode of the twenty-first transistor (T503) is connected to the first bootstrap node (QL) or the second bootstrap node (QR); a second pole of the twenty-first transistor (T503) is connected to the second potential input;

a control electrode of the twenty-third transistor (T505) is connected to a second electrode of the nineteenth transistor (T501); a first pole of the twenty-third transistor (T505) is connected to the third potential input terminal; a second pole of the twenty-third transistor (T505) is connected to the low level maintenance node (QB).

8. The driver circuit unit according to claim 1, wherein the connection nodes between the input module (21) and the driver pull-up module (22) comprise a first bootstrap node (QL), a second bootstrap node (QR), and a third bootstrap node (QC);

the input module (21) comprises a first transistor (T101), a second transistor (T102) and a third transistor (T103);

the control electrodes of the first transistor (T101), the second transistor (T102) and the third transistor (T103) are connected to the input signal input terminal (CIN); first poles of the first transistor (T101), the second transistor (T102), and the third transistor (T103) are connected to the fourth signal input terminal or a third potential input terminal; a second pole of the first transistor (T101) is connected to the first bootstrap node (QL); a second pole of the second transistor (T102) is connected to the second bootstrap node (QR); a second pole of the third transistor (T103) is connected to the third bootstrap node (QC);

or the like, or, alternatively,

the connection nodes between the input module (21) and the drive pull-up module (22) comprise a first bootstrap node (QL), a second bootstrap node (QR) and a third bootstrap node (QC);

the input module (21) comprises a first transistor (T101), a second transistor (T102), a third transistor (T103), a fourth transistor (T104) and a fifth transistor (T105);

the control electrodes of the first transistor (T101), the second transistor (T102), the third transistor (T103) and the fourth transistor (T104) are connected to the input signal input terminal (CIN); a first pole of the first transistor (T101) is connected to the fourth signal input or the third potential input; a second pole of the first transistor (T101) is connected to a first pole of the second transistor (T102), a first pole of the third transistor (T103), a first pole of the fifth transistor (T105), and a first pole of the fourth transistor (T104); a second pole of the second transistor (T102) is connected to the first bootstrap node (QL); a second pole of the fourth transistor (T104) is connected to the third bootstrap node (QC); a second pole of the third transistor (T103) and a control pole of the fifth transistor (T105) are connected, and connected to a second bootstrap node (QR); a second pole of the fifth transistor (T105) is connected to the first signal output (GA), the second signal output (GB) or the third signal output (COUT).

9. The driving circuit unit of claim 8, wherein the driving pull-up module (22) comprises a sixth transistor (T201), a seventh transistor (T202), an eighth transistor (T203), a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3);

a control electrode of the seventh transistor (T202) is connected to the first bootstrap node (QL), the second bootstrap node (QR), or the third bootstrap node (QC).

10. The driver circuit unit according to claim 8, wherein the bootstrap node pull-down module (23) comprises a ninth transistor (T301);

a first pole of the ninth transistor (T301) is connected to the first bootstrap node (QL), the second bootstrap node (QR), or the third bootstrap node (QC);

or the like, or, alternatively,

a control electrode of the ninth transistor (T301) is connected to the third signal input terminal; a first pole of the ninth transistor (T301) is connected to the first bootstrap node (QL), the second bootstrap node (QR), or the third bootstrap node (QC);

11. The driving circuit unit according to claim 8, wherein the connection node between the low level maintaining module (25) and the output pull-down module (24) comprises a low level maintaining node (QB);

or the like, or, alternatively,

the output pull-down module (24) includes an eleventh transistor (T401), a twelfth transistor (T402), a thirteenth transistor (T403), a fourteenth transistor (T404), a fifteenth transistor (T405), and a sixteenth transistor (T406);

control electrodes of the eleventh transistor (T401), the twelfth transistor (T402), the thirteenth transistor (T403), the fourteenth transistor (T404), the fifteenth transistor (T405), and the sixteenth transistor (T406) are connected to the low level maintaining node (QB);

a first pole of the eleventh transistor (T401) is connected to the first bootstrap node (QL); a first pole of the twelfth transistor (T402) is connected to the first signal output (GA); a first pole of the thirteenth transistor (T403) is connected to the third bootstrap node (QC); a first pole of the fourteenth transistor (T404) is connected to the third signal output terminal (COUT); a first pole of the fifteenth transistor (T405) is connected to the second bootstrap node (QR); a first pole of the sixteenth transistor (T406) is connected to the second signal output terminal (GB);

a second pole of the eleventh transistor (T401), the thirteenth transistor (T403), the fourteenth transistor (T404), and the fifteenth transistor (T405) is connected to the second potential input terminal; a second pole of the twelfth transistor (T402) and the sixteenth transistor (T406) is connected to the first potential input;

or the like, or, alternatively,

a second pole of the eleventh transistor (T401), the fourteenth transistor (T404) and the fifteenth transistor (T405) is connected to a first pole of the seventeenth transistor (T407); the second poles of the twelfth transistor (T402) and the sixteenth transistor (T406) are connected to the first pole of the eighteenth transistor (T408); a second pole of the seventeenth transistor (T407) is connected to the second potential input terminal; a second pole of the eighteenth transistor (T408) is connected to the first potential input;

or the like, or, alternatively,

the output pull-down module (24) includes an eleventh transistor (T401), a twelfth transistor (T402), a thirteenth transistor (T403), a fourteenth transistor (T404), a fifteenth transistor (T405), a sixteenth transistor (T406), a seventeenth transistor (T407), and an eighteenth transistor (T408);

control electrodes of the eleventh transistor (T401), the twelfth transistor (T402), the thirteenth transistor (T403), the fourteenth transistor (T404), the fifteenth transistor (T405), the sixteenth transistor (T406), the seventeenth transistor (T407), and the eighteenth transistor (T408) are connected to the low level maintaining node (QB);

a second pole of the eleventh transistor (T401), the thirteenth transistor (T403), the fourteenth transistor (T404), and the fifteenth transistor (T405) is connected to a first pole of the seventeenth transistor (T407); the second poles of the twelfth transistor (T402) and the sixteenth transistor (T406) are connected to the first pole of the eighteenth transistor (T408); a second pole of the seventeenth transistor (T407) is connected to the second potential input terminal; a second pole of the eighteenth transistor (T408) is connected to the first potential input.

12. The driving circuit unit according to claim 8, wherein the connection node between the low level maintaining module (25) and the output pull-down module (24) comprises a low level maintaining node (QB);

a control electrode of the twenty-first transistor (T503) is connected to the first bootstrap node (QL), the second bootstrap node (QR), or the third bootstrap node (QC); a first pole of the twenty-first transistor (T503) is connected to a second pole of the nineteenth transistor (T501); a second pole of the twenty-first transistor (T503) is connected to the second potential input;

or the like, or, alternatively,

13. The driver circuit unit according to any of claims 1 to 12, wherein the third signal output terminal (COUT) is connected to an input signal input terminal (CIN) of a driver circuit unit of a next stage; the third signal output end (COUT) outputs the cascade signal of the current stage for inputting the preceding stage cascade signal of the next stage of driving circuit unit; the input signal input end (CIN) is connected with the signal output end (COUT) of the previous-stage driving circuit unit and is used for receiving the input of the previous-stage cascade signal output by the previous-stage driving circuit unit.

14. A driver circuit, comprising a first clock line (CLK1), a second clock line (CLK2), a third clock line (CLK3), a fourth clock line (CLK4), a fifth clock line (CLKW1), a sixth clock line (CLKW2), and a first low potential line (VSS), a second low potential line (VSSL), a first high potential line (VH), an input signal input line (CIN), a cascade signal output line (COUT);

the driving circuit further comprising N +1 cascaded stages of the driving circuit unit of claim 13, wherein N is a positive integer;

15. A display, comprising:

the display device comprises a panel, a display panel and a control circuit, wherein the panel comprises a two-dimensional pixel array formed by a plurality of pixels, a plurality of data lines in a first direction and a plurality of grid scanning lines in a second direction, and the data lines are connected with each pixel in the array; it is characterized by also comprising:

the driving circuit as claimed in claim 14, providing a gate driving signal to the gate scan line.