KR20170039115A - Shift register - Google Patents

Abstract

The present invention relates to a shift register capable of preventing the leakage of charges from voltage at a set node to stabilize an output from a stage. The shift register includes a plurality of stages sequentially outputting scan pulses. Each stage includes a node control unit which controls signal states of a set node and a reset node, and an output unit receiving any one of a plurality of clock pulses having mutually different phases to output the received clock pulse in the form of a scan pulse through its output terminal based on the signal states of the set node and the reset node. The control unit of each stage includes a first discharge switching device and a second discharge switching device. The first discharge switching device is controlled to be turned on or turned off according to a scan pulse received from a next stage or the next following stage. The first discharge switching device is connected between any one of a plurality of clock transmission lines transmitting the clock pulses and the set node. The second discharge switching device is controlled to be turned on or turned off according to a scan pulse generated from the preceding stage or a stage before the preceding stage. The second discharge switching device is connected between any one of a plurality of clock transmission lines for transmitting the clock pulses and the reset node.

Description

SHIFT REGISTER {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly to a shift register capable of stabilizing the output from the stage by preventing leakage of charge from the voltage of the set node.

The shift register sequentially outputs a plurality of scan pulses to sequentially drive gate lines of a display device such as a liquid crystal display device. For this purpose, the shift register includes a plurality of switching elements therein, and an oxide semiconductor transistor may be used as the switching element.

 1 is a graph showing a relationship between a gate voltage and a drain current according to a temperature of a conventional oxide semiconductor transistor.

When an N-type oxide semiconductor transistor is used in a shift register, it is preferable that its threshold voltage has a positive value. However, as shown in FIG. 1, as the temperature increases, the threshold voltage of the oxide semiconductor transistor shifts in the negative direction. As a result, the N-type oxide semiconductor transistor to be turned off in the output period of the shift register The leakage current does not normally turn on at a high temperature and the voltage of the set node is lowered due to the leakage current and the output of the shift register is not normally generated.

FIG. 2 is a view showing voltage and scan pulse voltage of a set node according to a change in threshold voltage of a conventional oxide semiconductor transistor.

As shown in FIG. 2A, when the threshold voltage of the oxide semiconductor transistor is -1, the voltage of the set node is lowered rapidly due to the leakage current of the oxide semiconductor transistor, so that the output, that is, the voltage of the scan pulse, It can be seen that it is descending.

Also, as shown in FIG. 2B, when the threshold voltage of the oxide semiconductor transistor is -3, the leakage current of the oxide semiconductor transistor is further increased, so that the voltage of the set node is not even raised. As a result, no scan pulse is generated at all .

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a method for supplying a set- And the scan driver can normally generate the scan pulse by turning off the switch in the output period.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages sequentially outputting scan pulses, each stage including a node controller for controlling signal states of a set node and a reset node, And outputting the supplied clock pulse as a scan pulse through its output terminal according to a signal state of the set node and the reset node; The node controller of each stage is controlled to turn on and off according to a scan pulse from the next stage, and is connected between any one of the plurality of clock transmission lines transmitting the plurality of clock pulses and the set node And a first discharging switching element connected to the first discharging switching element.

The node controller of each stage is controlled to turn on and off according to a scan pulse from the previous stage and to connect between any one of the plurality of clock transmission lines transmitting the plurality of clock pulses and the reset node And a second discharge-dedicated switching element.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-2) th stage, and turns on the first node electrically connecting the set node and the charging power supply line A switching element; A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ; A third switching element that is turned on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the reset node when the power supply line is turned on; Further comprising a fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on, The first discharging switching element provided in the control unit is turned on or off in response to a scan pulse from the (n + 2) th stage, and when the set node and the one clock transmission line are turned on electrically Connect; The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage. When the reset node and any one of the clocks The transmission lines are electrically connected to each other, and the discharge power supply line transmits a discharge voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other when turned on .

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-2) th stage, and turns on the first node electrically connecting the set node and the charging power supply line A switching element; A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ; A third switching element that is turned on or turned off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when turned on; A fourth switching device that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the discharge power supply line to each other when the switch is turned on; A fifth switching device that turns on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the common node to each other when the power supply line is turned on; And a sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when the first switch is turned on, The first set of switching elements is turned on or off in response to a scan pulse from the (n + 2) th stage, and when the set node is turned on, any one of the clock transmission lines is electrically connected ; The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other; Wherein the discharge power supply line transmits a discharge voltage and the discharge voltage is smaller than the charge voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other when turned on .

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-2) th stage, and turns on the first node electrically connecting the set node and the charging power supply line A switching element; A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ; A third switching element that is turned on or turned off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when turned on; A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the first discharge power supply line to each other when the first switch is turned on; A fifth switching device that turns on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the common node to each other when the power supply line is turned on; Further comprising a sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the common node and the first discharging power supply line to each other when the first switch is turned on, The first discharge switching element provided in the node control unit of the node control unit is turned on or turned off in response to a scan pulse from the (n + 2) th stage, and when the set node and any one of the clock transmission lines are turned on Electrically connected; The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other; Wherein the first discharging power line transmits a first discharging voltage and the first discharging voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the second discharge power supply line to each other ; The second discharge power line transmits a second discharge voltage and the second discharge voltage is equal to or greater than the first discharge voltage.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-2) th stage, and turns on the first node electrically connecting the set node and the charging power supply line A switching element; A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ; A third switching element that is turned on or turned off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when turned on; A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the first discharge power supply line to each other when the first switch is turned on; A fifth switching device that turns on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the common node to each other when the power supply line is turned on; A sixth switching device that is turned on or off in response to a voltage supplied to the set node and electrically connects the common node and the first discharge power supply line to each other when the first switch is turned on; And a seventh switching element that is turned on or turned off in response to a scan pulse from the n-2 stage and electrically connects the reset node and the first discharge power supply line to each other at the turn- The first discharge switching element provided in the node control unit of the nth stage is turned on or off in response to a scan pulse from the (n + 2) th stage, and when turned on, Electrically connecting the lines to each other; Wherein the first discharging power line transmits a first discharging voltage and the first discharging voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the second discharge power supply line to each other ; The second discharging power line transmits a second discharging voltage; And the second discharge voltage is equal to or greater than the first discharge voltage.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-2) th stage, and turns on the first node electrically connecting the set node and the charging power supply line A switching element; A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ; A third switching element that is turned on or turned off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when turned on; A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the second discharge power supply line to each other when the switch is turned on; A fifth switching device that turns on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the common node to each other when the power supply line is turned on; Further comprising a sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the common node and the first discharge power supply line to each other when the first switch is turned on, The first discharge switching element provided in the node control unit is turned on or turned off in response to a scan pulse from the (n + 2) th stage. When the set node and any one of the clock transmission lines are turned on Lt; / RTI > The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other; Wherein the first discharging power line transfers a first discharging voltage and the second discharging power line transmits a second discharging voltage; Wherein the first and second discharge voltages are less than the charging voltage and the first discharge voltage is less than or equal to a second discharge voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the second discharge power supply line to each other And the second discharging power line transmits a second discharging voltage; And the second discharge voltage is equal to or greater than the first discharge voltage.

The reset node is divided into a first reset node and a second reset node, and the node controller provided in the n-th stage is turned on or off in response to a scan pulse from the (n-2) A first switching element for electrically connecting the set node and the charging power supply line to each other when turned on; A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ; A third switching element that is turned on or turned off in response to a voltage supplied to the first common node and electrically connects the first AC power supply line and the first reset node when the first AC power supply line is turned on; A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the first reset node and the first discharge power supply line to each other when the first switch is turned on; A fifth switching device that is turned on or off in response to a first AC voltage from the first AC power supply line and electrically connects the first AC power supply line and the first common node when the first AC power supply line is turned on; A sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the first common node and the first discharge power supply line to each other when the first switch is turned on; A seventh switching device which is turned on or off in response to a scan pulse from the n-2 stage and electrically connects the first reset node and the first discharge power supply line when turned on; An eighth switching device that is turned on or turned off in response to a voltage supplied to the second common node and electrically connects the second AC power supply line and the second reset node to each other when the second AC power supply is turned on; A ninth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the second reset node and the first discharging power supply line to each other when turned on; A tenth switching device that turns on or off in response to a second AC voltage from the second AC power supply line and electrically connects the second AC power supply line and the second common node to each other when the second AC power supply line is turned on; An eleventh switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the second common node and the first discharge power supply line to each other when the first switch is turned on; And a twelfth switching element that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the second reset node and the first discharging power supply line to each other And the first discharging switching element included in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 2) th stage, Electrically connecting the clock transmission lines to each other; The first discharging power line transmits a first discharging voltage; The first discharge voltage is smaller than the charging voltage; And the phase of the first AC voltage is inverted by 180 degrees with respect to the phase of the second AC voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; A first pull-down switching device for turning on or off in response to a voltage supplied to the first reset node and electrically connecting an output terminal of the n-th stage to a second discharge power supply line, ; A second pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And a second pull-down switching element for turning on or off the output terminal in response to a voltage supplied to the second reset node and electrically connecting the output terminal of the n-th stage and the second discharge power- And the second discharging power line transmits a second discharging voltage; And the second discharge voltage is equal to or greater than the first discharge voltage.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-2) th stage, and turns on the first node electrically connecting the set node and the charging power supply line A switching element; A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ; And is turned on or off in response to a clock pulse of either a clock pulse supplied to the output of the (n + 2) -th stage and a clock pulse supplied to the output of the (n + 3) A third switching device electrically connecting the power supply line and the common node to each other; On or off in response to any one of a clock pulse supplied to the output of the (n-1) -th stage and a clock pulse supplied to the output of the (n-2) -th stage, A fourth switching device for electrically connecting the node and the first discharge power source line to each other; A fifth switching element that is turned on or off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when the power supply line is turned on; And a sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the first discharge power supply line to each other when the first switch is turned on; The first discharge switching element provided in the node control unit of the nth stage is turned on or off in response to a scan pulse from the (n + 2) th stage, and when turned on, Electrically connecting the lines to each other; The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other; Wherein the first discharging power line transfers a first discharging voltage and the second discharging power line transmits a second discharging voltage; Wherein the first and second discharge voltages are less than the charging voltage and the first discharge voltage is less than or equal to a second discharge voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the second discharge power supply line to each other ; The second discharging power line transmits a second discharging voltage; And the second discharge voltage is equal to or greater than the first discharge voltage.

The node controller provided in the n-th stage turns on or off in response to a scan pulse from the (n-2) th stage, and when the common node and any one of the clock transmission lines are electrically connected A third discharging switching element for discharging; And a seventh switching element that is turned on or turned off in response to a voltage supplied to the set node and electrically connects the reset node and the second discharge power supply line to each other when the first switch is turned on .

The nodal control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the output terminal of the n-1th stage and the set node electrically A first switching element connected to the first switching element; A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on; A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when turned on; Further comprising: a capacitor connected between any one of the clock transmission lines and the common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The reset node is connected to any one of the clock transmission lines; The first discharging switching element, the capacitor and the pull-up switching element are all connected to the same clock transmission line.

The nodal control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the output terminal of the n-1th stage and the set node electrically A first switching element connected to the first switching element; A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on; A third switching element that is turned on or off according to a scan pulse from the (n-1) th stage and electrically connects the common node and the discharge power supply line when turned on; Further comprising: a capacitor connected between any one of the clock transmission lines and the common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The reset node is connected to any one of the clock transmission lines; The first discharging switching element, the capacitor and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on; A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when turned on; A fourth switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and the discharge power supply line to each other when the switch is turned on; A first capacitor connected between any one of the clock transmission lines and the common node; Further comprising a second capacitor connected between any one of the clock transmission lines and the reset node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; The charging power supply line transmits a charging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The first discharging switching element, the first capacitor, the second capacitor, and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on; A third switching device that turns on or off according to a scan pulse from the (n-1) th stage and electrically connects the common node and any one of the clock transmission lines to each other; A fourth switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and the discharge power supply line to each other when the switch is turned on; A first capacitor connected between any one of the clock transmission lines and the common node; Further comprising a second capacitor connected between any one of the clock transmission lines and the reset node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; The charging power supply line transmits a charging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The first discharge switching element, the third switching element, the first capacitor, the second capacitor, and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on; A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when turned on; Further comprising: a capacitor connected between any one of the clock transmission lines and the common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; The charging power supply line transmits a charging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The reset node and the common node are connected to each other; The first discharging switching element, the capacitor and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on; A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when turned on; A fourth switching element that is turned on or off according to a scan pulse from the (n-1) th stage and electrically connects the first common node and the discharge power supply line to each other at turn-on; Further comprising: a capacitor connected between any one of the clock transmission lines and the common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; The charging power supply line transmits a charging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The reset node and the common node are connected to each other; The first discharging switching element, the capacitor and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the first common node and electrically connects the output terminal of the set node and the nth stage when turned on; A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the first common node and a discharge power supply line to each other when the first node is turned on; A fourth switching device for turning on or off according to a voltage supplied to the second common node and electrically connecting the reset power supply line and the reset node at the turn-on time; A fifth switching device that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on; A sixth switching element that is turned on according to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the second common node to each other; A seventh switching device that turns on or off according to a voltage supplied to the set node and electrically connects the second common node and the discharge power supply line to each other when the first switch is turned on; Further comprising: a capacitor connected between any one of the clock transmission lines and the first common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; The charging power supply line transmits a charging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The first discharging switching element, the capacitor and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the first common node and electrically connects the output terminal of the set node and the nth stage when turned on; A third switching device that is turned on or off according to a scan pulse from the (n-1) th stage and electrically connects the first common node and the discharge power supply line to each other when the first common node is turned on; A fourth switching device for turning on or off according to a voltage supplied to the second common node and electrically connecting the reset power supply line and the reset node at the turn-on time; A fifth switching device that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on; A sixth switching element that is turned on according to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the second common node to each other; A seventh switching device that turns on or off according to a voltage supplied to the set node and electrically connects the second common node and the discharge power supply line to each other when the first switch is turned on; Further comprising: a capacitor connected between any one of the clock transmission lines and the first common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; The charging power supply line transmits a charging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The first discharging switching element, the capacitor and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the first common node and electrically connects the output terminal of the set node and the nth stage when turned on; A third switching device that turns on or off according to a scan pulse from the (n-1) th stage and electrically connects the first common node and one of the clock transmission lines to each other; A fourth switching device for turning on or off according to a voltage supplied to the second common node and electrically connecting the reset power supply line and the reset node at the turn-on time; A fifth switching device that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on; A sixth switching element that is turned on according to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the second common node to each other; A seventh switching device that turns on or off according to a voltage supplied to the set node and electrically connects the second common node and the discharge power supply line to each other when the first switch is turned on; Further comprising: a capacitor connected between any one of the clock transmission lines and the first common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; The charging power supply line transmits a charging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The first discharging switching element, the third discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the first common node and electrically connects the output terminal of the set node and the nth stage when turned on; A third switching device that turns on or off according to a scan pulse from the (n-1) th stage and electrically connects the first common node and one of the clock transmission lines to each other; A fourth switching device for turning on or off according to a voltage supplied to the second common node and electrically connecting the reset power supply line and the reset node at the turn-on time; A fifth switching device that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on; A sixth switching element that is turned on according to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the second common node to each other; A seventh switching device that turns on or off according to a voltage supplied to the set node and electrically connects the second common node and the discharge power supply line to each other when the first switch is turned on; An eighth switching device that turns on or off according to a voltage supplied to the reset node and electrically connects an output terminal of the (n-1) th stage and a discharge power supply line to each other; Further comprising: a capacitor connected between any one of the clock transmission lines and the first common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The discharging power line transmits a discharging voltage; The charging power supply line transmits a charging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The first discharging switching element, the third discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line.

The node control unit provided in the n-th stage turns on or off in response to a scan pulse from the (n-1) th stage, and turns on the first power supply line and the set node electrically connected to each other A switching element; A second switching device that is turned on or off according to a voltage supplied to the node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on; A third switching element that is turned on or off according to a scan pulse from the (n-1) th stage and electrically connects the common node and the discharge power supply line when turned on; Further comprising: a capacitor connected between any one of the clock transmission lines and the common node; The first discharge switching element provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage, and when turned on, To each other; The charging power supply line transmits a charging voltage; The discharging power line transmits a discharging voltage; And the discharge voltage is smaller than the charging voltage.

The output section of the n-th stage is turned on or off in response to a voltage supplied to the set node, and when one of the clock transmission lines and the output terminal of the n-th stage is electrically connected Up switching device; And a pulldown switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects an output terminal of the n-th stage and a discharge power supply line to each other at the turn-on time; The reset node is connected to any one of the clock transmission lines; The first discharging switching element, the third discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line.

And the low voltage of the clock pulse supplied to each of the clock transmission lines is larger than the discharge voltage.

In the present invention, a clock pulse having a voltage value larger than that of the discharge voltage is supplied to the source electrode of the switching element for discharging the set node, and the switching element is turned completely during the output period in which the clock pulse is output as the scan pulse The scan pulse can be normally generated.

1 is a graph showing a relationship between a gate voltage and a drain current according to the temperature of a conventional oxide semiconductor transistor;
2 is a graph showing a voltage and a scan pulse voltage of a set node according to a change in threshold voltage of a conventional oxide semiconductor transistor
3 is a view illustrating a shift register according to an embodiment of the present invention.
Fig. 4 is a timing chart of output signals of various signals supplied to the shift register of Fig. 1 and various signals outputted therefrom
5 is a diagram showing a circuit configuration of a stage according to the first embodiment of the present invention;
6 is a diagram showing a circuit configuration of a stage according to a second embodiment of the present invention
7 is a diagram showing a circuit configuration of a stage according to a third embodiment of the present invention
8 is a diagram showing a circuit configuration of a stage according to a fourth embodiment of the present invention
9 is a diagram showing a circuit configuration of a stage according to a fifth embodiment of the present invention
10 is a diagram showing a circuit configuration of a stage according to a sixth embodiment of the present invention
11 is a diagram showing a circuit configuration of a stage according to a seventh embodiment of the present invention
12 is a diagram showing a circuit configuration of a stage according to an eighth embodiment of the present invention
13 and 14 are diagrams showing voltage waveforms of a set node and a scan pulse generated by a shift register according to an embodiment of the present invention
15 is a view showing another shift register according to the embodiment of the present invention
16 is an output timing diagram of various signals supplied to the shift register of FIG. 15 and various signals outputted therefrom.
17 is a diagram showing a circuit configuration of a stage according to a ninth embodiment of the present invention
18 is a diagram showing a circuit configuration of a stage according to a tenth embodiment of the present invention
19 is a diagram showing a circuit configuration of a stage according to an eleventh embodiment of the present invention
20 is a view showing another shift register according to the embodiment of the present invention
21 is a diagram showing a circuit configuration of a stage according to a twelfth embodiment of the present invention
22 is a diagram showing a circuit configuration of a stage according to a thirteenth embodiment of the present invention
23 is a diagram showing a circuit configuration of a stage according to a fourteenth embodiment of the present invention
24 is a diagram showing a circuit configuration of a stage according to a fifteenth embodiment of the present invention
25 is a diagram showing a circuit configuration of a stage according to a sixteenth embodiment of the present invention;
26 is a diagram showing a circuit configuration of a stage according to a seventeenth embodiment of the present invention
27 is a diagram showing a circuit configuration of a stage according to an eighteenth embodiment of the present invention
28 is a diagram showing a circuit configuration of a stage according to a nineteenth embodiment of the present invention
29 is a diagram showing waveforms of a voltage of a set node, a voltage of a scan pulse, a voltage of a clock pulse, and a voltage of a common node generated by a shift register according to a ninth embodiment of the present invention
30 is a view showing waveforms of a voltage of a set node, a voltage of a scan pulse, a voltage of a clock pulse, and a voltage of a common node generated by the shift register according to the tenth embodiment of the present invention
31 is a view showing a waveform of a voltage of a set node, a voltage of a scan pulse, and a voltage of a reset node generated by a shift register according to a twelfth embodiment of the present invention
FIG. 32 is a view showing waveforms of a set node voltage, a scan pulse voltage, a common node voltage, and a reset node voltage generated by the shift register according to the thirteenth embodiment of the present invention.
FIG. 33 is a diagram showing the waveforms of the voltage of the set node Q, the voltage of the scan pulse, and the voltage of the common node CN generated by the shift register according to the fourteenth embodiment of the present invention (FIG. 23).
FIG. 34 shows waveforms of a set node voltage, a scan pulse voltage, and a common node voltage generated by the shift register according to the fifteenth embodiment of the present invention.
FIG. 35 is a diagram showing waveforms of a voltage of a set node, a voltage of a scan pulse, a reset node, and a voltage of a first common node generated by a shift register according to a sixteenth embodiment of the present invention.
FIG. 36 is a diagram showing waveforms of a voltage of a set node, a voltage of a scan pulse, a reset node, and a voltage of a first common node generated by a shift register according to a seventeenth embodiment of the present invention.
FIG. 37 is a diagram showing waveforms of a voltage of a set node, a voltage of a scan pulse, a reset node, and a voltage of a first common node generated by a shift register according to an eighteenth embodiment of the present invention.
38 is a view showing waveforms of a voltage of a set node, a voltage of a scan pulse, a reset node, and a voltage of a first common node generated by a shift register according to a nineteenth embodiment of the present invention

FIG. 3 is a diagram illustrating a shift register according to an embodiment of the present invention. FIG. 4 is an output timing diagram of various signals supplied to the shift register of FIG. 1 and various signals output therefrom.

The shift register according to the embodiment of the present invention includes n stages ST1 to STn and two dummy stages STn + 1 and STn + 2 as shown in FIG. Here, each of the stages ST1 to STn + 2 outputs one scan pulse (SP1 to SPn + 2) for one frame period through each output terminal OT.

Each of the stages ST1 to STn drives a gate line connected thereto by using a scan pulse. In addition, all the stages ST1 to STn + 2 including the first and second dummy stages control the operation of the stage located at the rear end from itself and the stage located at the front end from the stage itself.

The stages ST1 to STn + 2 sequentially output scan pulses in the order of the first stage ST1 to the second dummy stage STn + 2. That is, the first stage ST1 outputs the first scan pulse SP1, the second stage ST2 outputs the second scan pulse SP2, and the third stage ST3 outputs the second scan pulse SP2. (N + 1) -th dummy stage (STn + 1) outputs a scan pulse (SP3) and outputs n + 1 scan pulse (SPn + 1). Finally, the second dummy stage STn + 2 outputs the (n + 2) th scan pulse SPn + 2.

The scan pulses output from the stages ST1 to STn except for the first and second dummy stages STn + 1 and STn + 2 are sequentially supplied to the gate lines of the liquid crystal panel (not shown) The lines are scanned sequentially. The scan pulse output from the stages is supplied only to the stage located at the previous stage from the stage itself, or to the stage located at the front stage and to the stage located at the rear stage, or to the stage located at the rear stage.

Such a shift register can be incorporated in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

The entire stages ST1 to STn + 2 of the shift register constructed as described above are supplied with the charging voltage VDD, the discharging voltage VSS and the first to fourth clock pulses CLK1 to CLK4 Or the like). The first stage, the second stage, the first dummy stage and the second dummy stage ST1 and ST2 among the stages ST1 to STn + 2 further include first and second start pulses Vst1 and Vst2, It is supplied.

The charging voltage VDD is mainly used to charge the nodes of each of the stages ST1 to STn + 2 and the discharging voltage VSS is mainly used for the nodes of the stages ST1 to STn + 1 and the output terminals OT Is discharged.

The charging voltage VDD and the discharging voltage VSS are both DC voltages, the charging voltage VDD is positive and the discharging voltage VSS is negative. Here, the discharge voltage VSS may be a ground voltage.

On the other hand, according to the circuit configuration of the stage, the entire stage can be further supplied with the first and second AC voltages Vac1 and Vac2.

The first and second AC voltages Vac1 and Vac2 are mainly AC signals for controlling the charging and discharging of the reset nodes among the nodes of each of the stages ST1 to STn + And inverted by 180 degrees with respect to the second AC voltage (Vac2). The voltage value of the first and second AC voltages Vac1 and Vac2 in the high state may be the same as the voltage value of the charging voltage VDD and the voltage value of the first and second AC voltages Vac1 and Vac2 May be the same as the voltage value of the discharge voltage (VSS). The first and second AC voltages (Vac1, Vac2) are inverted in their p-frame periods. Here, p is a natural number.

The first to fourth clock pulses CLK1 to CLK4 are signals used to generate the scan pulses SP1 to SPn of the stages ST1 to STn + 1, and the stages ST1 to STn + 1 to the fourth clock pulses CLK1 to CLK4 and outputs the scan pulses SP1 to SPn. For example, the (4j + 1) -th stage outputs a scan pulse using the first clock pulse CLK1 and the scan pulse using the second clock pulse CLK2 for the (4j + 2) The fourth j + 4 stage outputs a scan pulse using the third clock pulse CLK3 and the fourth j + 4 stage outputs the scan pulse using the fourth clock pulse CLK4. Here, j represents a natural number.

Although four clock pulses having different phase differences are used in the present invention, the number of clock pulses may be two or more.

As shown in FIG. 4, the clock pulses CLK1 to CLK4 are outputted such that the high period between the clock pulses output in the adjacent periods overlaps with each other for a certain period of time. For example, the first clock pulse CLK1 and the second clock pulse CLK2 which are adjacent to each other may be output so that their high-level portions overlap for a time corresponding to about 1 / 2H (horizontal period). The time of the overlapping horizontal period may be 1 / 3H. As the high period of the adjacent clock pulses is overlapped, the scan pulses have the same characteristics as those of the clock pulses. That is, as shown in FIG. 9, the scan pulses are outputted so that the high period between the scan pulses output in the adjacent periods overlaps with each other for a predetermined period. The first and second start pulses Vst1 and Vst2 may also overlap each other.

As shown in Fig. 3, the k-th stage is enabled in response to the scan pulses from the (k-2) th and (k-1) th stages. Here, k is a natural number. However, the first stage ST1 is enabled in response to the first start pulse Vst1 from the timing controller, and the second stage is enabled in response to the second start pulse from the timing controller. Here, the second stage ST2 may be enabled by the first start pulse Vst1 instead of the second start pulse Vst2.

The k < th > stage is disabled in response to the scan pulse from the (k + 2) th stage. However, the first and second dummy stages STn + 1 and STn + 2 are disabled in response to the first start pulse Vst1 or the second start pulse Vst2 from the timing controller.

Here, the circuit configuration of each stage will be described in detail as follows.

1st In the embodiment  Following Shift  register

5 is a diagram showing a circuit configuration of a stage according to the first embodiment of the present invention.

Each stage according to the first embodiment of the present invention includes a node control unit and an output unit OB as shown in Fig. The node control unit controls the signal states of the set node and the reset node of the stage. The output part OB receives any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its output terminal according to the signal states of the set node Q and the reset node QB As a scan pulse.

The node controller provided in the n-th stage includes a set node Q, a reset node QB, first and second discharge switching elements TD1 and TD2, and first through fourth switching elements Tr1- Tr4).

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 2) th stage and is turned on when the set node Q and any one of the clocks The transmission lines are electrically connected to each other. However, the first discharge switching element TD1 provided in the first dummy stage STn + 1 is controlled by the first start pulse Vst1 of the timing controller instead of the scan pulse from the (n + 2) th stage. Similarly, the first discharge switching element TD1 provided in the second dummy stage STn + 2 is controlled by the second start pulse Vst2 of the timing controller instead of the scan pulse from the (n + 2) th stage.

The second discharge-dedicated switching element TD2 of the n-th stage is turned on or off in response to a scan pulse from the (n-2) -th stage provided in the node control section of the n-th stage, And electrically connects the set node (QB) and any one of the clock transmission lines to each other. However, the second discharge switching element TD2 provided in the first stage ST1 is controlled by the first start pulse Vst1 of the timing controller instead of the scan pulse from the (n-2) th stage. Similarly, the second discharge-dedicated switching element TD2 provided in the second stage ST2 is controlled by the second start pulse Vst2 of the timing controller instead of the scan pulse from the n-2th stage.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the n-2 stage, and the set node Q and the charging power supply line are electrically connected to each other . However, the first switching device Tr1 provided in the first stage ST1 is controlled by the first start pulse Vst1 of the timing controller instead of the scan pulse from the (n-2) th stage. Similarly, the first switching device Tr1 provided in the second stage ST2 is controlled by the first start pulse Vst2 of the timing controller instead of the scan pulse from the (n-2) th stage.

The second switching device Tr2 of the n-th stage is turned on or off in response to a clock pulse supplied to the output OB of the (n-1) -th stage, and the output And electrically connects the terminal OT and the set node Q to each other. The clock pulse supplied to the output section OB of the (n-1) th stage means a clock pulse supplied to the pull-up switching element Uc in the output section.

The third switching device Tr3 of the n-th stage is turned on or off in response to the charging voltage from the charging power supply line, and when the charging power supply line and the reset node QB are turned on, Are electrically connected to each other.

The fourth switching device Tr4 of the n-th stage is turned on or off according to the signal state of the set node Q. When the reset node QB is turned on, .

The output section QB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching device Uc of the n-th stage is turned on or off according to the signal state of the set node Q and is turned on at any one of the clock transmission lines and the output terminal OT of the n-th stage, Are electrically connected to each other.

The pull-down switching device Ds of the n-th stage is turned on or off according to the signal state of the reset node QB and is turned on when the output terminal OT of the n- Are electrically connected to each other.

The operation of the shift register including stages according to the first embodiment of the present invention will now be described in detail. For the convenience of explanation, the n-th stage in Fig. 5 is replaced with the fourth stage ST4. In addition, the following description of the operation describes the operation in the non-overlapping period of the first and second start pulses and the clock pulses, and the operations in the overlapped periods are simultaneously generated during the overlap period. For example, in the 1 / 3H period in which the first clock pulse CLK1 and the second clock pulse CLK2 overlap with each other, the operation by the first clock pulse CLK1 and the operation by the second clock pulse CLK2 Occurs simultaneously.

First, the operation in the first set period of the fourth stage ST4, that is, the enable operation will be described as follows. For example, the first set period of the fourth stage ST4 is the second 1 / 3H period of the second clock pulse CLK2 (when the pulse width of the second clock pulse is divided into three equal parts, 3H period), and the first set period is a period corresponding to the second clock pulse CLK2 (i.e., a period corresponding to the third clock pulse CLK2) 1 and the third clock pulse).

In this first set period, the second scan pulse SP2 output from the second stage ST2 is input to the fourth stage ST4.

That is, the second scan pulse SP2 is supplied to the gate terminal of the first switching device Tr1 and the gate terminal of the second discharge switching device TD2 included in the fourth stage ST4.

The first switching device Tr1 and the second switching devices Tr1 and Tr5 are turned on and the charging voltage VDD is supplied through the first switching device Tr1 turned on. Is applied to the set node (Q). Thus, the pull-up switching device Uc and the fourth switching device Tr4 of the fourth stage ST4, in which the set node Q is charged and the gate terminal is connected to the charged set node Q, - Turns on.

Here, the discharge voltage VSS is supplied to the reset node QB of the first stage ST1 through the turned-on fourth switching device Tr4, and the turn-on voltage of the second discharge- The fourth clock pulse CLK4 in the low voltage state is supplied to the reset node QB through the reset node QB. Then, the reset node QB is discharged. Accordingly, the pull-down switching device Ds to which the gate terminal is connected to the reset node QB is turned off.

Since the third switching device Tr3 is in the form of a diode connected to the gate terminal and the drain terminal of the third switching device Tr3, the third switching device Tr3 is always kept in the turn-on state by the charging voltage VDD supplied thereto have. The charging voltage VDD is supplied to the reset node QB by the third switching element Tr3 turned on so that the negative discharge voltage VSS is applied to the reset node QB, And the positive charging voltage VDD are supplied together with the fourth clock pulse CLK4 in the low voltage state while the area of the second discharging device TD2 and the fourth switching device Tr4 is the third switching Is larger than the area of the element Tr3, the reset node QB is kept in a discharged state.

On the other hand, since the output from the sixth stage ST6 during the first set period is the sixth scan pulse in the low voltage state, the first discharge switching element TD1 provided in the fourth stage ST4 is turned off - Off state.

Next, the operation in the second set period of the fourth stage ST4 will be described as follows. For example, the second set period of the fourth stage ST4 is the second 1 / 3H period of the third clock pulse CLK3 (when the pulse width of the third clock pulse is divided into three equal parts, 3H period). This second set period is a period corresponding to the third clock pulse CLK3 (i.e., a period corresponding to the third clock pulse CLK3) 2 and the fourth clock pulse).

In this second set period, the third clock pulse CLK3 in the high voltage state is supplied to the gate terminal of the second switching element Tr2 provided in the fourth stage ST3, and the third clock pulse CLK3 from the third stage ST3 The third scan pulse SP3 is supplied to the gate terminal of the second switching device Tr2 provided in the fourth stage ST4. Accordingly, the second switching element Tr2 is turned on and the third scan pulse SP3 in the high voltage state is supplied to the set node Q through the turned-on second switching element Tr2. Accordingly, the set node Q of the fourth stage ST4 is charged in the first set period subsequent to the second set period.

On the other hand, since the output from the sixth stage ST6 during the second set period is the sixth scan pulse in the low voltage state, the first discharge switching element TD1 provided in the fourth stage ST4 is turned off - Off state.

Next, the operation in the output period of the fourth stage ST4 will be described as follows. For example, the output period of the fourth stage ST4 is the second 1 / 3H period of the fourth clock pulse CLK4 (the second 1 / 3H period when the pulse width of the fourth clock pulse CLK4 is divided by 3) / 3H period). This output period is a period corresponding to the clock pulses adjacent to the fourth clock pulse CLK4 in the entire pulse width section of the fourth clock pulse CLK4 And the first clock pulse).

In the output period of the fourth stage ST4, as the set node Q of the fourth stage ST1 is continuously held in the charged state by the charging voltage VDD applied during the first and second set periods , The pull-up switching device Uc of the fourth stage ST4 maintains the turn-on state. At this time, as the fourth clock pulse CLK4 is applied to the drain terminal of the turn-on pull-up switching device Uc, the charging voltage (for example, 0 V) charged in the set node Q in the floating state of the fourth stage ST4 VDD) is amplified by bootstrapping.

Therefore, the fourth clock pulse CLK4 applied to the drain terminal of the pull-up switching element Uc of the fourth stage ST4 is stably outputted through its source terminal (output terminal OT).

Here, the fourth clock pulse CLK4 outputted through the pull-up switching element Uc is the fourth scan pulse SP4. Particularly, in order for the output of the fourth stage ST4, that is, the fourth scan pulse SP4, to be normally output in the output period of the fourth stage ST4, the output of the set node Q of the fourth stage ST4 The voltage must be stably maintained. To this end, the first discharging switching device TD1 must remain in a completely turned-off state during the output period of the fourth stage ST4. To this end, the source terminal of the first discharge-only switching element TD1 in the present invention is supplied with a clock pulse having a higher voltage than the existing discharge voltage VSS. For example, the fourth clock pulse (CLK4) is supplied to the source terminal of the first discharge switching element (TD1) provided in the fourth stage (ST4). That is, the same fourth clock pulse CLK4 is applied to the drain terminal of the pull-up switching device Uc of the fourth stage ST4 and the source terminal of the first discharge-only switching device TD1 of the fourth stage ST4 .

Since the sixth scan pulse in the low voltage state output from the sixth stage ST6 is still supplied to the gate terminal of the first discharge switching element TD1 of the fourth stage ST4, The discharge switching element TD1 is in the turn-off state. However, when the discharge voltage VSS is supplied to the source terminal of the first discharge-only switching element TD1 as in the prior art, the first discharge-dedicated switching element TD1 is not completely turned off, Lt; / RTI > That is, when the voltage of the sixth scan pulse in the low voltage state and the discharge voltage VSS are all about -5 [V] and the voltage of the set node Q is charged to 20 [V] The gate-source terminal voltage Vgs of this first discharging switching element TD1 is maintained at 0 [V] while the voltage of both the gate terminal and the source terminal of the discharging switching element TD1 is kept at -5 [V] . At this time, the threshold voltage of the first discharge switching element TD1, which is an N-type oxide semiconductor transistor, moves in the negative direction due to the temperature described above, and may not be completely turned off in the output period. To prevent this, in the present invention, a clock pulse having a voltage value higher than the discharge voltage VSS is supplied to the source terminal of the first discharge switching element TD1. For example, the first to fourth clock pulses CLK1 to CLK4 all have a high value of about 20 [V] in a high voltage state and about -5 [V] in a low voltage state. Up switching element Uc of the fourth stage ST4 during the output period of the fourth stage ST4 because the fourth clock pulse CLK4 shows a high voltage state in the output period of the fourth stage ST4. And the first discharge-dedicated switching element TD1 are supplied with the fourth clock pulse CLK4 in the high voltage state. Therefore, according to the present invention, the gate-source voltage of the first discharging device TD1 is maintained at a high negative value during the output period in which the pull-up switching device Uc outputs the fourth clock pulse CLK4. For example, if the fourth clock pulse CLK4 in a high voltage state has a voltage of 20 [V] and the sixth scan pulse in a low voltage state has a voltage of -5 [V] The gate-source voltage of the first stage TD1 becomes -25 [V], so that the first discharge switching device TD1, which is an N-type oxide semiconductor transistor, is turned off completely during the output period of this fourth stage ST4 .

During this output period, the second discharging switching element TD2 also operates in the same manner as the first discharging switching element TD1. In this output period, the voltage of the reset node QB (about -5 [V ] Is lower than the fourth clock pulse CLK4 in the high voltage state, the source and drain terminals of the second discharging switching element TD2 are opposite to the source and drain terminals of the first discharging switching element TD1 . Therefore, during the output period of the fourth stage ST4, the gate-to-source voltage of the second discharging switching element becomes about 0 [V], so that the second discharging switching element TD2 generates a leakage current The voltage of the reset node QB can be increased. However, since the area of the fourth switching device Tr4 is made larger than that of the second discharging switching device TD2 and the third switching device Tr3 to improve the discharge capability of the fourth switching device Tr4, The voltage reduction of the reset node QB due to the leakage current of the dedicated switching element TD2 can be canceled. As will be described later, the second discharge-dedicated switching element TD2 serves to stably maintain the voltage of the reset node QB after the reset period.

The fourth scan pulse SP4 is stably outputted from the fourth stage ST4 as the clock pulse is supplied to the source terminal of the first discharge switching element TD1. Is supplied to the fourth gate line to drive the fourth gate line and the fourth scan pulse SP4 is supplied to the drain terminal of the second switching element provided in the fifth stage ST5, And the fourth scan pulse SP4 allows the first switching element Tr1 and the second discharge switching element TD2 provided in the sixth stage ST6 to perform the second set operation, To the gate terminal of the sixth stage ST6 so that the sixth stage ST6 can perform the primary set operation. The fourth scan pulse SP4 is supplied to the gate terminal of the first discharge switching element TD1 provided in the second stage ST2 so that the second stage ST2 can perform the reset operation .

Next, the operation in the reset period of the fourth stage ST4, that is, the disable operation will be described. For example, the reset period of the fourth stage ST4 is the second 1 / 3H period of the second clock pulse CLK2 (when the pulse width of the second clock pulse CLK2 is divided into three equal parts, 1 / 3H period) of the second clock pulse CLK2. This reset period is a period corresponding to the clock pulses CLK2 adjacent to the second clock pulse CLK2 in the entire pulse width section of the second clock pulse CLK2, The first and third clock pulses).

In this reset period, the sixth stage ST6 outputs the second clock pulse CLK2 as the sixth scan pulse SP6. The sixth scan pulse SP6 is supplied to the gate terminal of the first discharge-dedicated switching element TD1 provided in the fourth stage ST4.

Then, the first discharge-dedicated switching element TD1 is turned on and the fourth clock pulse CLK4 in the low voltage state is applied to the fourth stage ST4 (ST4) through the turned- To the set node Q of the set node Q. Thus, the set node Q is discharged, and the pull-up switching element Uc and the fourth switching element Tr4 connected to the discharged set node Q through the gate terminal are turned off. Thus, the charging voltage VDD is supplied to the reset node QB through the third switching element Tr3 turned on. Thus, the reset node QB is charged and the pulldown switching element Ds connected to the charged reset node QB via the gate terminal is turned off. Then, the discharge voltage VSS is output through the output terminal OT through the turn-on pull-down switching element Ds.

On the other hand, every time the fourth clock pulse CLK4 has a high voltage state after the reset period of the fourth stage ST4, the second discharge-dedicated switching element TD2 is completely turned off , So that the reset node QB of the fourth stage ST4 after the reset period is periodically stabilized.

In the overlap period located between the first set period and the second set period, the operation in the first set period and the operation in the second set period described above occur simultaneously, and in the overlap period located between the second set period and the output period, The operation in the second set period and the operation in the output period occur at the same time, and in the overlap period positioned between the output period and the reset period, the operation in the above described output period and the operation in the reset period occur simultaneously.

Second In the embodiment  Following Shift  register

6 is a diagram showing a circuit configuration of a stage according to a second embodiment of the present invention.

Each stage according to the second embodiment of the present invention includes a node control unit and an output unit OB as shown in Fig. The node control unit controls the signal states of the set node and the reset node of the stage. The output part OB receives any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its output terminal according to the signal states of the set node Q and the reset node QB As a scan pulse.

The node control unit provided in the nth stage includes the set node Q, the reset node QB, the first and second discharge switching elements TD1 and TD2, and the first to sixth switching elements Tr1 to Tr6 ).

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 2) th stage and is turned on when the set node Q and any one of the clocks The transmission lines are electrically connected to each other.

The second discharge-dedicated switching element TD2 of the n-th stage is turned on or off in response to a scan pulse from the n-2-th stage provided in the n-th stage node control unit, And electrically connects the node QB with any one of the clock transmission lines.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the n-2 stage, and the set node Q and the charging power supply line are electrically connected to each other .

The second switching device Tr2 of the n-th stage is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage, and the output terminal of the n- And electrically connects the set nodes Q to each other.

The third switching device Tr3 of the n-th stage is turned on or off according to the signal state of the common node CN. When the third switching device Tr3 is turned on, the charging power supply line and the reset node QB are electrically .

The fourth switching device Tr4 of the n-th stage is turned on or off according to the signal state of the set node Q. When the reset node QB and the discharging power supply line are electrically connected to each other .

The fifth switching device Tr5 of the n-th stage is turned on or off in response to the charging voltage VDD from the charging power supply line, and when the charging power supply line and the common node CN are turned on, Are electrically connected to each other.

The sixth switching element Tr6 of the n-th stage is turned on or turned off according to the signal state of the set node Q. When the common node CN is turned on, do.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching device Uc of the n-th stage is turned on or off according to the signal state of the set node Q and is turned on at any one of the clock transmission lines and the output terminal OT of the n-th stage, Are electrically connected to each other.

The pull-down switching device Ds of the n-th stage is turned on or off according to the signal state of the reset node QB and is turned on when the output terminal OT of the n- Are electrically connected to each other.

The third to sixth switching elements Tr3 to Tr6 in the second embodiment correspond to the third and fourth switching elements Tr3 and Tr4 in the first embodiment. In the second embodiment, The fifth and sixth switching elements Tr5 and Tr6 of the fifth switching element Tr5 control the voltage magnitude of the common node CN and are turned on and off according to the magnitude of the voltage supplied to the common node CN. Whether or not it is turned on is determined.

Third In the embodiment  Following Shift  register

7 is a diagram showing a circuit configuration of a stage according to the third embodiment of the present invention.

Each stage according to the third embodiment of the present invention includes a node control unit and an output unit OB as shown in Fig. The node control unit controls the signal states of the set node and the reset node of the stage. The output unit receives one of a plurality of clock pulses having different phases and outputs the supplied clock pulse as a scan pulse through its output terminal according to a signal state of the set node and the reset node.

The n-th stage node control section includes first and second discharge switching elements TD1 and TD2, and first to sixth switching elements Tr1 to Tr6.

The first discharge switching element TD1 provided in the node control unit of the n-th stage is turned on or off in response to the scan pulse from the (n + 2) th stage, And one of the clock transmission lines is electrically connected to each other.

The second discharging switching element TD1 provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the n-2 stage, One clock transmission line is electrically connected to each other.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the n-2 stage, and the set node Q and the charging power supply line are electrically connected to each other .

The second switching device Tr2 of the n-th stage is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage, and the output terminal OT And the set node Q are electrically connected to each other.

The third switching element Tr3 of the n-th stage is turned on or turned off in response to a voltage supplied to the common node CN and is turned on when the charging power supply line and the reset node QB are turned on They are electrically connected to each other.

The fourth switching device Tr4 of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q. When the reset node QB and the first discharging power source Connect the lines electrically to each other.

The fifth switching device Tr5 of the n-th stage is turned on or off in response to the charging voltage VDD from the charging power supply line. When the charging power supply line and the common node CN ) Are electrically connected to each other.

The sixth switching element Tr6 of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q. When the common node CN and the first discharging power source Connect the lines electrically to each other.

The output unit OB provided in the n-th stage includes a pull-up switching unit Uc and a pull-down switching unit Ds.

The pull-up switching element Uc is turned on or off in response to a voltage supplied to the set node Q. When the turn-on state of one of the clock transmission lines and the output terminal of the n-th stage is electrically connected .

The pull-down switching element Ds is turned on or off in response to a voltage supplied to the reset node QB and is turned on when the output terminal OT of the nth stage and the second discharge power supply line Are electrically connected to each other.

The first discharging power line transmits the first discharging voltage VSS1, and the first discharging voltage is smaller than the charging voltage VDD.

The second discharging power line transmits a second discharging voltage VSS2 and the second discharging voltage VSS2 is less than or equal to the first discharging voltage VSS1. This second discharge specific voltage VSS2 is equal to the discharge specific voltage VSS in the above-described first embodiment.

In the third embodiment of the present invention, by setting the size of the first discharge voltage VSS1 supplied to the fourth and fifth switching elements Tr4 and Tr5 to be smaller than or equal to the second discharge voltage VSS2, And the fifth switching elements Tr4 and Tr5 can be prevented.

Fourth In the embodiment  Following Shift  register

8 is a diagram showing a circuit configuration of a stage according to the fourth embodiment of the present invention.

Each stage according to the fourth embodiment of the present invention includes a node control unit and an output unit OB as shown in Fig. The node control unit controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The n-th stage node control section includes a first discharging switching element TD1, and first through seventh switching elements Tr1 through Tr7.

The first discharge switching element TD1 provided in the node control unit of the n-th stage is turned on or off in response to the scan pulse from the (n + 2) th stage, And one of the clock transmission lines is electrically connected to each other.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the n-2 stage, and the set node Q and the charging power supply line are electrically connected to each other .

The second switching device Tr2 of the n-th stage is turned on or off in response to a clock pulse supplied to the output OB of the (n-1) -th stage, and the output Terminal and the set node Q are electrically connected to each other.

The third switching element Tr3 of the n-th stage is turned on or turned off in response to a voltage supplied to the common node CN and is turned on when the charging power supply line and the reset node QB are turned on They are electrically connected to each other.

The fourth switching device Tr4 of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q. When the reset node QB and the first discharging power source Connect the lines electrically to each other.

The fifth switching device Tr5 of the n-th stage is turned on or off in response to the charging voltage VDD from the charging power supply line, and when the charging power supply line and the common node CN are turned on, Are electrically connected to each other.

The sixth switching element Tr6 of the n-th stage is turned on or off in response to the voltage supplied to the set node Q. When the common node CN is turned on, Are electrically connected to each other.

The seventh switching device Tr7 of the n-th stage is turned on or off in response to a scan pulse from the n-2 stage, and when the turn-on, the reset node QB and the first discharging power source Connect the lines electrically to each other.

The output section provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q. When the turn-on state of one of the clock transmission lines and the output terminal of the n-th stage Electrical connection.

The pull-down switching device Ds of the n-th stage is turned on or turned off in response to the voltage supplied to the reset node QB and is turned on when the output terminal OT of the n- Connect the dedicated power lines to each other electrically.

The first and second discharge voltages VSS1 and VSS2 in the fourth embodiment of the present invention are the same as the first and second discharge voltages VSS1 and VSS2 in the third embodiment described above.

Fifth In the embodiment  Following Shift  register

9 is a diagram showing a circuit configuration of a stage according to a fifth embodiment of the present invention.

Each stage according to the fifth embodiment of the present invention includes a node control unit and an output unit OB as shown in Fig. The node control unit controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The n-th stage node control section includes first and second discharge switching elements TD1 and TD2, and first to sixth switching elements Tr1 to Tr6.

The first discharge switching element TD1 provided in the node control unit of the n-th stage is turned on or off in response to a scan pulse from the (n + 2) th stage, Of the clock transmission lines.

The second discharging switching element TD2 provided in the node control unit of the n-th stage is turned on or off in response to the scan pulse from the n-2 stage and is turned on when the reset node QB is turned on. And any one of the clock transmission lines are electrically connected to each other.

The first switching element Tr1 of the n-th stage is turned on or off in response to a scan pulse from the n-2 stage, and electrically connects the set node and the charging power supply line to each other at turn-on .

The second switching device Tr2 of the n-th stage is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage, and the output terminal of the n- And electrically connects the set nodes Q to each other.

The third switching element Tr3 of the n-th stage is turned on or turned off in response to a voltage supplied to the common node CN and is turned on when the charging power supply line and the reset node QB are turned on They are electrically connected to each other.

The fourth switching device Tr4 of the n-th stage is turned on or off in response to the voltage supplied to the set node Q, and is turned on when the reset node QB and the second discharge- Connect power lines to each other electrically.

The fifth switching device Tr5 of the n-th stage is turned on or turned off in response to the charging voltage from the charging power supply line. When the charging power supply line and the common node CN are turned on Connect electrically.

The sixth switching element Tr6 of the n-th stage is turned on or off in response to the voltage supplied to the set node Q. When the common node CN is turned on, Are electrically connected to each other.

The output section provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching device Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and when turned on, the output terminal OT of the n- Connect the dedicated power lines to each other electrically.

The first and second discharge voltages VSS1 and VSS2 in the fifth embodiment of the present invention are the same as the first and second discharge voltages VSS1 and VSS2 in the third embodiment described above.

6th In the embodiment  Following Shift  register

10 is a diagram showing a circuit configuration of a stage according to a sixth embodiment of the present invention.

Each stage according to the sixth embodiment of the present invention includes a node control unit and an output unit OB as shown in Fig. The node control unit controls the signal states of the set node (Q), the first reset node (QB1) and the second reset node (QB2) of the stage. The output is supplied to any one of a plurality of clock pulses having different phases and is responsive to a voltage supplied to the set node (Q), the first reset node (QB1) and the second reset node (QB2) And outputs the received clock pulse as its own scan pulse through its output terminal (OT).

The node controller included in the n-th stage includes a first discharging switching element TD1 and first through twelfth switching elements Tr1 through Tr12.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 2) th stage and is turned on when the set node Q and any one of the clocks The transmission lines are electrically connected to each other.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the n-2 stage, and the set node Q and the charging power supply line are electrically connected to each other .

The second switching device Tr2 of the n-th stage is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage, and the output terminal of the n- And electrically connects the set nodes Q to each other.

The third switching device Tr3 of the n-th stage is turned on or off in response to a voltage supplied to the first common node CN1, and is turned on when the first AC power supply line and the first reset node (QB1) are electrically connected to each other.

The fourth switching device Tr4 of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q. When the first reset node QB1 and the first switching device Tr2 turn on, Connect the dedicated power lines to each other electrically.

The fifth switching device Tr5 of the n-th stage is turned on or off in response to the first AC voltage Vac1 from the first AC power supply line, 1 common node CN1 are electrically connected to each other.

The sixth switching element Tr6 of the n-th stage is turned on or off in response to the voltage supplied to the set node Q. When the first common node CN1 is turned on, Connect power lines to each other electrically.

The seventh switching device Tr7 of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage and is turned on when the first reset node QB1 and the first Connect the dedicated power lines to each other electrically.

The eighth switching element Tr8 of the n-th stage is turned on or off in response to the voltage supplied to the second common node CN2, and when the second AC power supply line and the second reset And electrically connects the node QB2 to each other.

The ninth switching element Tr9 of the n-th stage is turned on or off in response to the voltage supplied to the set node Q, and is turned on when the second reset node QB2 and the first Connect the dedicated power lines to each other electrically.

The tenth switching device Tr10 of the n-th stage is turned on or off in response to the second AC voltage Vac2 from the second AC power supply line, and when the second AC power supply line and the second And electrically connects the common node CN2 to each other.

The eleventh switching element Tr11 of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q. When the second common node CN2 is turned on, Connect power lines to each other electrically.

The twelfth switching element Tr12 of the n-th stage is turned on or turned off in response to a scan pulse from the n-2 stage, and the second reset node QB2 and the first Connect the dedicated power lines to each other electrically.

The output section OB provided in the n-th stage includes a pull-up switching device Uc, a first pull-down switching device Ds1, and a second pull-down switching device Ds2.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The first pull-down switching device Ds1 of the n-th stage is turned on or off in response to the voltage supplied to the first reset node QB1, and the output terminal OT of the n-th stage ) And the second discharge power supply line are electrically connected to each other.

The second pull-down switching device Ds2 of the n-th stage is turned on or off in response to the voltage supplied to the set node Q, and when turned on, the output of one of the clock transmission lines and the n-th stage Terminals OT are electrically connected to each other.

The second pull-down switching device Ds2 of the n-th stage is turned on or off in response to the voltage supplied to the second reset node QB2, and the output terminal OT ) And the second discharge power supply line are electrically connected to each other.

The stage according to the sixth embodiment of the present invention includes first and second reset nodes QB1 and QB2, and the first reset node QB1 and the second reset node QB2 are connected in a frame period And are charged alternately. For example, in the odd-numbered frame period, the first reset node QB1 is charged and the second reset node QB2 is discharged. In the odd-numbered frame period, the first reset node QB1 is discharged, The reset node QB2 is charged.

Specifically, during the set period in which the set node QB is charged, all of the first and second reset nodes QB1 and QB2 are maintained in a discharged state. In the reset period in which the set node QB is discharged, Either one of the first and second reset nodes QB1 and QB2 is charged and one of them is discharged. At this time, in the reset period, the first and second reset nodes QB1 and QB2 are alternately charged in frame units. Accordingly, when the first pull-down switching device Ds1 connected to the first reset node QB1 during the reset period in the odd-numbered frame period is turned on, the second pull-down switch Q2 connected to the second reset node QB2 The switching element Ds2 is turned off. Conversely, when the first pull-down switching element Ds1 connected to the first reset node QB1 during the reset period in the odd-numbered frame period is turned off, the second pull-down switching element Ds2 connected to the second reset node QB2 The pulldown switching element Ds2 is turned on.

The first AC voltage Vac1 is supplied to the third and fifth switching elements Tr3 and Tr5 instead of the charging voltage VDD and the first AC voltage Vac1 is inverted by 180 degrees The second alternating-current voltage Vac2 is supplied to the eighth and tenth switching elements Tr8 and Tr10.

The first and second discharge voltages VSS1 and VSS2 in the sixth embodiment of the present invention are the same as the first and second discharge voltages VSS1 and VSS2 in the third embodiment described above.

Seventh In the embodiment  Following Shift  register

11 is a diagram showing a circuit configuration of a stage according to a seventh embodiment of the present invention.

Each stage according to the fifth embodiment of the present invention includes a node control unit and an output unit OB as shown in Fig. The node control unit controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller included in the n-th stage includes first and second discharge switching elements TD1 and TD2, and first through sixth switching elements Tr1 through Tr6.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 2) th stage and is turned on when the set node Q and any one of the clocks The transmission lines are electrically connected to each other.

The second discharge-dedicated switching element TD2 of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage, and the reset node QB and the one The clock transmission lines are electrically connected to each other.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the n-2 stage, and the set node Q and the charging power supply line are electrically connected to each other .

The second switching device Tr2 of the n-th stage is turned on or off in response to a clock pulse supplied to the output OB of the (n-1) -th stage, and the output And electrically connects the terminal OT and the set node Q to each other.

The third switching element Tr3 of the n-th stage is turned on or turned off in response to a voltage supplied to the common node CN and is turned on when the charging power supply line and the reset node QB are turned on They are electrically connected to each other.

The fourth switching device Tr4 of the n-th stage is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage, and the reset node QB and the second And the discharge power supply line VSS2 are electrically connected to each other.

The fifth switching device Tr5 of the n-th stage is turned on or off in response to the clock pulse CLK (n + 2) supplied to the output of the (n + 2) And the common node (CN) are electrically connected to each other.

The sixth switching element Tr6 of the n-th stage is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage. When the sixth node Tr6 is turned on, And the one dedicated power supply line (VSS1) are electrically connected to each other.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching device Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and when turned on, the output terminal OT of the n- Connect the dedicated power lines to each other electrically.

The fifth switching device Tr5 in the seventh embodiment is supplied with the clock pulse supplied to the next single stage pull-up switching device Uc. For example, the clock pulse supplied to the fifth switching element Tr5 provided in the fourth stage ST4 is the second clock pulse CLK2 supplied to the pull-up switching element Uc provided in the sixth stage ST4 )to be.

The first and second discharge voltages VSS1 and VSS2 in the seventh embodiment of the present invention are the same as the first and second discharge voltages VSS1 and VSS2 in the third embodiment described above.

Eighth In the embodiment  Following Shift  register

12 is a diagram showing a circuit configuration of a stage according to an eighth embodiment of the present invention.

Each stage according to the eighth embodiment of the present invention includes a node control unit and an output unit OB as shown in Fig. The node control unit controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. Terminal as a scan pulse.

The node controller included in the n-th stage includes the first to third switching elements TD1 to TD3, and the first to seventh switching elements Tr1 to Tr7.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 2) th stage and is turned on when the set node Q and any one of the clocks The transmission lines are electrically connected to each other.

The second discharge-dedicated switching element TD2 of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage, and the reset node QB and the one The clock transmission lines are electrically connected to each other.

The third discharging switching element of the n-th stage is turned on or off in response to a scan pulse from the (n-2) th stage, and when the common node CN and any one of the clock transmission lines are turned on They are electrically connected to each other.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the n-2 stage, and the set node Q and the charging power supply line are electrically connected to each other .

The second switching device Tr2 of the n-th stage is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage, and the output terminal OT And the set node Q are electrically connected to each other.

The third switching device Tr3 of the n-th stage is turned on or turned off in response to a voltage supplied to the common node CN, and when the charging power supply line and the fourth switching device Tr4 are turned on They are electrically connected to each other.

The fourth switching device Tr4 of the nth stage is connected to one of the clock pulses supplied to the output part OB of the (n-1) -th stage and the clock pulse supplied to the output part OB of the n- And turns on or off in response to the pulse, and electrically connects the third switching device Tr3 and the first discharging power supply line VSS1 to each other at the turn-on time.

The fifth switching device Tr5 of the n-th stage is turned on or off in response to a clock pulse supplied to the output part OB of the (n + 2) -th stage, And electrically connects the common nodes CN to each other.

The sixth switching element Tr6 of the n-th stage is turned on or off in response to a clock pulse supplied to the output part OB of the (n-1) -th stage, and when the common node CN is turned on, And the first discharging power line VSS1 are electrically connected to each other.

The seventh switching device Tr7 of the n-th stage is turned on or off in response to the voltage supplied to the set node Q, and is turned on when the reset node QB and the second discharge Connect power lines to each other electrically.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or off in response to the voltage supplied to the set node Q. When the turn-on state of one of the clock transmission lines and the n-th stage And are electrically connected to each other.

The pull-down switching device Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and when turned on, the output terminal OT of the n- Connect the dedicated power lines to each other electrically.

The fifth switching device Tr5 in the seventh embodiment is supplied with the clock pulse supplied to the next single stage pull-up switching device Uc. For example, the clock pulse supplied to the fifth switching element Tr5 provided in the fourth stage ST4 is the second clock pulse CLK2 supplied to the pull-up switching element Uc provided in the sixth stage ST4 )to be.

The first and second discharge voltages VSS1 and VSS2 in the seventh embodiment of the present invention are the same as the first and second discharge voltages VSS1 and VSS2 in the third embodiment described above.

13 and 14 are graphs showing voltage waveforms of the set node and the scan pulse generated by the shift register according to the embodiment of the present invention. As shown in FIGS. 13 and 14, the voltage Vq ) And the scan pulse voltage (Vsp) are normally output.

On the other hand, in all the embodiments, when the voltages to be compared with each other have the same polarity, the magnitudes of the respective voltages are not compared with the absolute value of the voltage but are compared with the values themselves. For example, both the second discharging voltage VSS2 and the first discharging voltage VSS1 in the third embodiment may have a negative polarity. In this case, the second discharging voltage VSS2 may be negative Means that the first discharge voltage VSS1 is -5 [V] if the second discharge voltage VSS2 is -10 [V], for example.

FIG. 15 is a diagram illustrating another shift register according to the embodiment of the present invention. FIG. 16 is an output timing diagram of various signals supplied to the shift register of FIG. 15 and various signals output therefrom.

The shift register according to the embodiment of the present invention includes n stages ST1 to STn and one dummy stage STn + 1 as shown in Fig. Here, each of the stages ST1 to STn + 2 outputs one scan pulse (SP1 to SPn + 1) for one frame period through each output terminal OT.

Each of the stages ST1 to STn drives a gate line connected thereto by using a scan pulse. In addition, all the stages ST1 to STn + 1 including the dummy stage control the operation of the stage located at the rear end from itself and the stage located at the front end from the stage itself.

The stages ST1 to STn + 1 sequentially output scan pulses in the order from the first stage ST1 to the dummy stage STn + 2. That is, the first stage ST1 outputs the first scan pulse SP1, the second stage ST2 outputs the second scan pulse SP2, and the third stage ST3 outputs the second scan pulse SP2. And the n-th stage STn outputs the n-th scan pulse SPn and finally the dummy stage STn + 1 outputs the (n + 1) -th scan pulse SP3. And outputs one scan pulse (SPn + 1).

The scan pulses output from the stages ST1 to STn except for the dummy stage STn + 1 are sequentially supplied to the gate lines of the liquid crystal panel (not shown), thereby sequentially scanning the gate lines. The scan pulse output from the stages is supplied only to the stage located at the previous stage from the stage itself, or to the stage located at the front stage and to the stage located at the rear stage, or to the stage located at the rear stage.

Such a shift register can be incorporated in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

The entire stages ST1 to STn + 1 of the shift register constructed as described above are supplied with the charging voltage VDD, the discharging voltage VSS and the first to fourth clock pulses CLK1 to CLK4 ) Are supplied. On the other hand, the first stage ST1 and the dummy stage STn + 1 of the stages ST1 to STn + 1 are further supplied with the start pulse Vst.

The charging voltage VDD, the discharging voltage VSS, and the first to fourth clock pulses CLK1 to CLK4 described above are the same as those previously described, and therefore, are omitted. However, the first to fourth clock pulses CLK1 to CLK4 shown in Fig. 16 are not overlapped. Of course, the start pulse Vst is not overlapped with these clock pulses CLK1 to CLK4.

Although four clock pulses having different phase differences are used in the present invention, the number of clock pulses may be two or more.

As shown in Fig. 15, the k-th stage is enabled in response to the scan pulse from the (k-1) th stage. Here, k is a natural number. However, the first stage ST1 is enabled in response to the start pulse Vst from the timing controller.

The k < th > stage is disabled in response to the scan pulse from the (k + 1) th stage. However, the dummy stage STn + 1 is disabled in response to the start pulse Vst from the timing controller.

Here, the circuit configuration of each stage shown in FIG. 15 will be described in detail as follows.

9th In the embodiment  Following Shift  register

17 is a diagram showing a circuit configuration of a stage according to a ninth embodiment of the present invention.

Each stage according to the ninth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller NC provided in the n-th stage includes a first discharging switching element TD1, first through third switching elements Tr1 through Tr3, and a capacitor C.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 2) th stage and is turned on when the set node Q and any one of the clocks The transmission lines are electrically connected to each other.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the (n-1) th stage, And electrically connects the nodes Q to each other.

The second switching element Tr2 of the n-th stage is turned on or turned off according to the voltage supplied to the common node CN, and the output terminal OT of the set node Q and the n-th stage ) Are electrically connected to each other.

The third switching device Tr3 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the common node CN and the discharge power supply line are electrically connected to each other .

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the common node CN.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other. Here, this reset node QB is connected to any one of the clock transmission lines. That is, this clock transmission line becomes the reset node QB.

The clock pulse CLKn supplied to the pull-up switching element Uc of the n-th stage and the clock pulse CLKn + 1 supplied to the pull-down switching element Ds of the n-th stage are not superimposed, . For example, if the first clock pulse CLK1 of FIG. 16 is supplied to the pull-up switching element Uc of the n-th stage, the pull-down switching element Ds of the n-th stage is supplied with the second clock pulse CLK2 Is supplied.

The clock pulse CLKn + 1 supplied to the pull-down switching element Ds of the n-th stage is the same as the clock pulse CLKn supplied to the pull-up switching element Uc of the n + 1-th stage.

At this time, the first discharging switching element TD1, the capacitor C and the pull-up switching element Uc are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

According to the ninth embodiment, the reset node QB connected to the gate terminal of the pull-down switching element Ds is held low and the set node Q connected to the gate terminal of the pull-up switching element Uc is high The clock pulse supplied to the drain terminal of the pull-up switching device Uc is output as a scan pulse. On the other hand, when the reset node QB goes high and the set node Q goes low, the gate line (output terminal OT) is turned on even though the clock pulse supplied to the drain terminal of the pull- And remains in a low state. That is, even if the clock pulse supplied to the drain terminal of the pull-up switching device Uc becomes high again, the set node Q is kept in the low state unless the output is required, so that the pull-up switching device Uc does not operate, .

At this time, noise is generated by the coupling voltage at the set node Q by the parasitic capacitor C of the pull-up switching device Uc because the voltage of the clock pulse supplied to the pull-up switching device Uc is high The voltage of the common node CN also rises while the second switching element Tr2 is turned on and the voltage of the set node Q is held low by the second switching element Tr2 turned on.

On the other hand, the magnitude of the voltage applied to the gate terminal of the second switching device Tr2 is set according to the capacitance of the capacitor C. At this time, it is preferable that the size of the capacitor C is equal to or larger than Cox (the accumulated capacitance of the gate oxide film) of the second switching device Tr2.

The current is prevented from leaking from the set node Q because the second switching element Tr2 is kept in the turn-off state while the set pulse is output by the clock pulse in the state that the set node Q is high.

Article 10 In the embodiment  Following Shift  register

18 is a diagram showing a circuit configuration of a stage according to a tenth embodiment of the present invention.

Each stage according to the tenth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller NC provided in the n-th stage includes a first discharging switching element TD1, first through third switching elements Tr1 through Tr3, and a capacitor C.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or turned off in response to a scan pulse from the (n-1) th stage, And electrically connects the nodes Q to each other.

The second switching element Tr2 of the n-th stage is turned on or turned off according to the voltage supplied to the common node CN, and the output terminal OT of the set node Q and the n-th stage ) Are electrically connected to each other.

The third switching element Tr3 of the n-th stage is turned on or off according to the scan pulse from the (n-1) th stage. When the common node CN is turned on, .

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the common node CN.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other. Here, this reset node QB is connected to any one of the clock transmission lines. That is, this clock transmission line becomes the reset node QB.

The clock pulse supplied to the pull-up switching element Uc of the n-th stage and the clock pulse supplied to the pull-down switching element of the n-th stage are not superposed and have a phase difference of one clock pulse width. For example, if the first clock pulse of Fig. 16 is supplied to the pull-up switching element Uc of the n-th stage, the pull-down switching element Ds of the n-th stage is supplied with the second clock pulse of Fig.

The clock pulse supplied to the pull-down switching element Ds of the n-th stage is the same as the clock pulse supplied to the pull-up switching element Uc of the (n + 1) -th stage.

At this time, the first discharging switching element TD1, the capacitor C and the pull-up switching element are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

According to the tenth embodiment, since the second switching element Tr2 is kept in the turn-off state while the scan pulse is output by the clock pulse in the state where the set node Q is high, the set node Q voltage Leakage is prevented. Since the voltage of the common node CN rises while the scan pulse is output but the voltage of the set node Q and the voltage of the scan pulse are higher, the set node Q Is suppressed.

Eleventh In the embodiment  Following Shift  register

19 is a diagram showing a circuit configuration of a stage according to an eleventh embodiment of the present invention.

Each stage according to the eleventh embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller NC provided in the n-th stage includes a first discharging switching element TD1, first through third switching elements Tr1 through Tr3, and a capacitor C.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or turned off according to the voltage supplied to the common node CN, and the output terminal OT of the set node Q and the n-th stage ) Are electrically connected to each other.

The third switching element Tr3 of the n-th stage is turned on or off according to the scan pulse from the (n-1) th stage. When the common node CN is turned on, .

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the common node CN.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other. Here, this reset node QB is connected to any one of the clock transmission lines. That is, this clock transmission line becomes the reset node QB.

The clock pulse supplied to the pull-up switching element Uc of the n-th stage and the clock pulse supplied to the pull-down switching element of the n-th stage are not superposed and have a phase difference of one clock pulse width. For example, if the first clock pulse CLK1 of FIG. 16 is supplied to the pull-up switching element Uc of the n-th stage, the pull-down switching element Ds of the n-th stage is supplied with the second clock pulse CLK2 Is supplied.

The clock pulse supplied to the pull-down switching element Ds of the n-th stage is the same as the clock pulse supplied to the pull-up switching element Uc of the (n + 1) -th stage.

At this time, the first discharge-dedicated switching element TD1, the third switching element Tr3, the capacitor C and the pull-up switching element Uc are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

On the other hand, the low voltage (low voltage) of the clock pulse supplied to each of the clock transmission lines may be set to be larger than the discharge voltage VSS.

20 is a view illustrating another shift register according to an embodiment of the present invention. The signals applied to the shift register shown in FIG. 20 and the signals outputted therefrom are the same as those shown in FIG. 16 described above.

The shift register according to the embodiment of the present invention includes n stages ST1 to STn and one dummy stage STn + 1 as shown in Fig. Here, each of the stages ST1 to STn + 2 outputs one scan pulse (SP1 to SPn + 1) for one frame period through each output terminal OT.

Each of the stages ST1 to STn drives a gate line connected thereto by using a scan pulse. In addition, all the stages ST1 to STn + 1 including the dummy stage control the operation of the stage located at the rear end from itself and the stage located at the front end from the stage itself.

The stages ST1 to STn + 1 sequentially output scan pulses in the order from the first stage ST1 to the dummy stage STn + 2. That is, the first stage ST1 outputs the first scan pulse SP1, the second stage ST2 outputs the second scan pulse SP2, and the third stage ST3 outputs the second scan pulse SP2. And the n-th stage STn outputs the n-th scan pulse SPn and finally the dummy stage STn + 1 outputs the (n + 1) -th scan pulse SP3. And outputs one scan pulse (SPn + 1).

The scan pulses output from the stages ST1 to STn except for the dummy stage STn + 1 are sequentially supplied to the gate lines of the liquid crystal panel (not shown), thereby sequentially scanning the gate lines. The scan pulse output from the stages is supplied only to the stage located at the previous stage from the stage itself, or to the stage located at the front stage and to the stage located at the rear stage, or to the stage located at the rear stage.

Such a shift register can be incorporated in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

The entire stages ST1 to STn + 1 of the shift register constructed as described above are supplied with the charging voltage VDD, the discharging voltage VSS and the first to fourth clock pulses CLK1 to CLK4 ). ≪ / RTI > On the other hand, the first stage ST1 and the dummy stage STn + 1 of the stages ST1 to STn + 1 are further supplied with the start pulse Vst.

The charging voltage VDD, the discharging voltage VSS, and the first to fourth clock pulses CLK1 to CLK4 described above are the same as those previously described, and therefore, are omitted. However, the first to fourth clock pulses CLK1 to CLK4 shown in Fig. 16 are not overlapped. Of course, the start pulse Vst is not overlapped with these clock pulses.

Although four clock pulses having different phase differences are used in the present invention, the number of clock pulses may be two or more.

As shown in Fig. 15, the k-th stage is enabled in response to the scan pulse from the (k-1) th stage. Here, k is a natural number. However, the first stage ST1 is enabled in response to the start pulse Vst from the timing controller.

The k < th > stage is disabled in response to the scan pulse from the (k + 1) th stage. However, the dummy stage STn + 1 is disabled in response to the start pulse Vst from the timing controller.

Here, the circuit configuration of each stage shown in FIG. 20 will be described in detail as follows.

Article 12 In the embodiment  Following Shift  register

21 is a diagram showing a circuit configuration of a stage according to a twelfth embodiment of the present invention.

Each stage according to the twelfth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller NC provided in the nth stage includes a first discharging switching element TD1, first through fourth switching elements Tr1 through Tr4, a first capacitor C1 and a second capacitor C2 do.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or turned off according to the voltage supplied to the common node CN, and the output terminal OT of the set node Q and the n-th stage ) Are electrically connected to each other.

The third switching device Tr3 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the common node CN and the discharge power supply line are electrically connected to each other .

The fourth switching device Tr4 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the reset node QB and the power supply line for power supply are turned on Connect electrically.

The first capacitor C1 of the n-th stage is connected between any one of the clock transmission lines and the common node CN.

The second capacitor C2 of the n-th stage is connected between any one of the clock transmission lines and the reset node QB.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other.

At this time, the first discharging switching element TD1, the first capacitor C1, the second capacitor C2 and the pull-up switching element are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

According to the twelfth embodiment, the voltage of the reset node QB is kept high during a period in which the scan pulse is not output, as in the case of the voltage of the common node CN, so that the voltage fluctuation of the output terminal OT is suppressed. On the other hand, since the second switching device Tr2 and the pulldown switching device Ds are kept in the turn-off state during the period in which the scan pulse is output, the leakage current from the set node Q is suppressed.

Thirteenth In the embodiment  Following Shift  register

22 is a diagram showing a circuit configuration of a stage according to a thirteenth embodiment of the present invention.

Each stage according to the thirteenth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller NC provided in the nth stage includes a first discharging switching element TD1, first through fourth switching elements Tr1 through Tr4, a first capacitor C1 and a second capacitor C2 do.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or turned off according to the voltage supplied to the common node CN, and the output terminal OT of the set node Q and the n-th stage ) Are electrically connected to each other.

The third switching device Tr3 of the n-th stage is turned on or off according to the scan pulse from the (n-1) th stage. When the common node CN and any one of the clock transmission lines are turned on Connect electrically.

The fourth switching device Tr4 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the reset node QB and the power supply line for power supply are turned on Connect electrically.

The first capacitor C1 of the n-th stage is connected between any one of the clock transmission lines and the common node CN.

The second capacitor C2 of the n-th stage is connected between any one of the clock transmission lines and the reset node QB.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other.

At this time, all of the first discharging switching element TD1, the third switching element Tr3, the first capacitor C1, the second capacitor C2 and the pull-up switching element Uc are connected to the same clock transmission line do.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

According to the thirteenth embodiment, the voltage of the reset node QB is kept high during a period in which the scan pulse is not output, as in the voltage of the common node CN, so that the voltage fluctuation of the output terminal OT is suppressed. On the other hand, since the second switching device Tr2 and the pulldown switching device Ds are kept in the turn-off state during the period in which the scan pulse is output, the leakage current from the set node Q is suppressed. That is, the voltage of the reset node QB is kept low during the period when the scan pulse is output. At this time, although the voltage of the common node CN rises, since the voltage of the set node Q and the output terminal OT is higher, the leakage current due to the second switching element Tr2 is suppressed.

14th In the embodiment  Following Shift  register

23 is a diagram showing a circuit configuration of a stage according to a fourteenth embodiment of the present invention.

Each stage according to the fourteenth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller NC provided in the n-th stage includes a first discharging switching element TD1, first through third switching elements Tr1 through Tr3, and a capacitor C.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or turned off according to the voltage supplied to the common node CN, and the output terminal OT of the set node Q and the n-th stage ) Are electrically connected to each other.

The third switching device Tr3 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the common node CN and the discharge power supply line are electrically connected to each other .

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the common node CN.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching device Ds of the n-th stage is turned on or off in response to a voltage supplied to the common node CN. When the n-th stage output terminal OT is turned on, The lines are electrically connected to each other.

At this time, the above-described first discharging switching element, (TD1) capacitor C and pull-up switching element are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

The voltage of the common node CN is held high during a period in which the scan pulse is not outputted, so that the voltage fluctuation of the output terminal OT is suppressed. On the other hand, since the second switching device Tr2 and the pulldown switching device Ds are kept in the turn-off state during the period in which the scan pulse is output, the leakage current from the set node Q is suppressed.

Article 15 In the embodiment  Following Shift  register

24 is a diagram showing a circuit configuration of a stage according to a fifteenth embodiment of the present invention.

Each stage according to the fifteenth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller NC included in the n-th stage includes a first discharging switching element TD1, first through third switching elements Tr1 through Tr4, and a capacitor C. [

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or turned off according to the voltage supplied to the common node CN, and the output terminal OT of the set node Q and the n-th stage ) Are electrically connected to each other.

The third switching device Tr3 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the common node CN and the discharge power supply line are electrically connected to each other .

The fourth switching device Tr4 of the n-th stage is turned on or off according to the scan pulse from the (n-1) th stage, and when turning on, the common node CN and the discharge power supply line are electrically connected Connect.

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the common node CN.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching device Ds of the n-th stage is turned on or off in response to a voltage supplied to the common node CN. When the n-th stage output terminal OT is turned on, The lines are electrically connected to each other.

At this time, the first discharging switching element TD1, the capacitor C and the pull-up switching element are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

The voltage of the common node CN is held high during a period in which the scan pulse is not outputted, so that the voltage fluctuation of the output terminal OT is suppressed. On the other hand, since the second switching device Tr2 and the pulldown switching device Ds are kept in the turn-off state during the period in which the scan pulse is output, the leakage current from the set node Q is suppressed.

16th In the embodiment  Following Shift  register

25 is a diagram showing a circuit configuration of a stage according to a sixteenth embodiment of the present invention.

Each stage according to the sixteenth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node control unit NC provided in the n-th stage includes a first discharging switching element TD1, first through seventh switching elements Tr1 through Tr7, and a capacitor C.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or off according to the voltage supplied to the first common node CN1, and is turned on when the turn-on of the set node Q and the n-th stage output terminal (OT) are electrically connected to each other.

The third switching element Tr3 of the n-th stage is turned on or off according to the voltage supplied to the set node Q, and when the first common node CN1 is turned on, They are electrically connected to each other.

The fourth switching device Tr4 of the n-th stage is turned on or off according to the voltage supplied to the second common node CN2, and the power supply line for charge and the reset node QB are turned on Connect electrically.

The fifth switching element Tr5 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the reset node QB and the power supply line for power supply are turned on Connect electrically.

The sixth switching element Tr6 of the n-th stage is turned on in accordance with the charging voltage VDD from the charging power supply line to electrically connect the charging power supply line and the second common node CN2 to each other .

The seventh switching device Tr7 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the second common node CN2 is turned on, They are electrically connected to each other.

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the first common node CN1.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other.

At this time, the first discharging switching element TD1, the capacitor C and the pull-up switching element are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

The voltages of the first common node CN1 and the reset node QB are held high during the period in which the scan pulse is not output, so that the voltage fluctuation of the set node Q and the output terminal OT is suppressed. Meanwhile, the leakage current from the set node Q is suppressed because the second switching device Tr2 and the pulldown switching device are kept in the turn-off state during the period in which the scan pulse is output.

Article 17 In the embodiment  Following Shift  register

26 is a diagram showing a circuit configuration of a stage according to a seventeenth embodiment of the present invention.

Each stage according to the seventeenth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node control unit NC provided in the n-th stage includes a first discharging switching element TD1, first through seventh switching elements Tr1 through Tr7, and a capacitor C.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or off according to the voltage supplied to the first common node CN1, and is turned on when the turn-on of the set node Q and the n-th stage output terminal (OT) are electrically connected to each other.

The third switching element Tr3 of the n-th stage is turned on or off according to the scan pulse from the (n-1) th stage. When the first common node CN1 is turned on, Connect electrically.

The fourth switching device Tr4 of the n-th stage is turned on or off according to the voltage supplied to the second common node CN2, and the power supply line for charge and the reset node QB are turned on Connect electrically.

The fifth switching element Tr5 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the reset node QB and the power supply line for power supply are turned on Connect electrically.

The sixth switching element Tr6 of the n-th stage is turned on in accordance with the charging voltage VDD from the charging power supply line to electrically connect the charging power supply line and the second common node CN2 to each other .

The seventh switching device Tr7 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the second common node CN2 is turned on, They are electrically connected to each other.

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the first common node CN1.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other.

At this time, the first discharging switching element TD1, the capacitor C and the pull-up switching element are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

The voltage of the first common node CN1 rises while the voltage of the set node Q and the output terminal OT are higher during the period in which the scan pulse is output and therefore the leakage current through the second switching element Tr2 Is suppressed.

Article 18 In the embodiment  Following Shift  register

27 is a diagram showing a circuit configuration of a stage according to an eighteenth embodiment of the present invention.

Each stage according to the eighteenth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node control unit NC provided in the n-th stage includes a first discharging switching element TD1, first through seventh switching elements Tr1 through Tr7, and a capacitor C.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or off according to the voltage supplied to the first common node CN1, and is turned on when the turn-on of the set node Q and the n-th stage output terminal (OT) are electrically connected to each other.

The third switching element Tr3 of the n-th stage is turned on or off according to a scan pulse from the n-1st stage. When the third switching element Tr3 is turned on, Connect the lines electrically to each other.

The fourth switching device Tr4 of the n-th stage is turned on or off according to the voltage supplied to the second common node CN2, and the power supply line for charge and the reset node QB are turned on Connect electrically.

The fifth switching element Tr5 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the reset node QB and the power supply line for power supply are turned on Connect electrically.

The sixth switching element Tr6 of the n-th stage is turned on in accordance with the charging voltage VDD from the charging power supply line to electrically connect the charging power supply line and the second common node CN2 to each other .

The seventh switching device Tr7 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the second common node CN2 is turned on, They are electrically connected to each other.

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the first common node CN1.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other.

At this time, the first discharge-dedicated switching element TD1, the third switching element Tr3, the capacitor C and the pull-up switching element Uc are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

The voltage of the first common node CN1 rises while the voltage of the set node Q and the output terminal OT are higher during the period in which the scan pulse is output and therefore the leakage current through the second switching element Tr2 Is suppressed.

Article 19 In the embodiment  Following Shift  register

28 is a diagram showing a circuit configuration of a stage according to a nineteenth embodiment of the present invention.

Each stage according to the nineteenth embodiment of the present invention includes a node control unit (NC) and an output unit (OB) as shown in Fig. The node control unit (NC) controls the signal states of the set node (Q) and the reset node (QB) of the stage. The output part OB is supplied with any one of a plurality of clock pulses having different phases and outputs the supplied clock pulse to its own output in response to a voltage supplied to the set node Q and the reset node QB. And outputs it as a scan pulse through the terminal OT.

The node controller NC provided in the n-th stage includes a first discharging switching element TD1, first through eighth switching elements Tr1 through Tr8, and a capacitor C.

The first discharging switching element TD1 of the n-th stage is turned on or off in response to a scan pulse from the (n + 1) th stage and is turned on when the set node Q is turned on Connect the lines electrically to each other.

The first switching device Tr1 of the n-th stage is turned on or off in response to the scan pulse from the (n-1) th stage, and the charge power supply line and the set node Q are electrically connected to each other Connect.

The second switching element Tr2 of the n-th stage is turned on or off according to the voltage supplied to the first common node CN1, and is turned on when the turn-on of the set node Q and the n-th stage output terminal (OT) are electrically connected to each other.

The third switching element Tr3 of the n-th stage is turned on or off according to a scan pulse from the n-1st stage. When the third switching element Tr3 is turned on, Connect the lines electrically to each other.

The fourth switching device Tr4 of the n-th stage is turned on or off according to the voltage supplied to the second common node CN2, and the power supply line for charge and the reset node QB are turned on Connect electrically.

The fifth switching element Tr5 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the reset node QB and the power supply line for power supply are turned on Connect electrically.

The sixth switching element Tr6 of the n-th stage is turned on in accordance with the charging voltage VDD from the charging power supply line to electrically connect the charging power supply line and the second common node CN2 to each other .

The seventh switching device Tr7 of the n-th stage is turned on or off according to the voltage supplied to the set node Q. When the second common node CN2 is turned on, They are electrically connected to each other.

The eighth switching element Tr8 of the nth stage is turned on or off according to the voltage supplied to the reset node QB and is turned on when the output terminal OT of the n- Connect the dedicated power lines to each other electrically.

The capacitor C of the n-th stage is connected between any one of the clock transmission lines and the first common node CN1.

The output section OB provided in the n-th stage includes a pull-up switching device Uc and a pull-down switching device Ds.

The pull-up switching element Uc of the n-th stage is turned on or turned off in response to the voltage supplied to the set node Q, and is turned on at any one of the clock transmission lines and the n-th stage output terminal OT) are electrically connected to each other.

The pull-down switching element Ds of the n-th stage is turned on or off in response to the voltage supplied to the reset node QB, and is turned on and off at the output terminal OT of the n- The power lines are electrically connected to each other.

At this time, the first discharge-dedicated switching element TD1, the third switching element Tr3, the capacitor C and the pull-up switching element Uc are all connected to the same clock transmission line.

The charging voltage VDD and the discharging voltage VSS are the same as those in the first embodiment.

The voltage of the first common node CN1 rises while the voltage of the set node Q and the output terminal OT are higher during the period in which the scan pulse is output and therefore the leakage current through the second switching element Tr2 Is suppressed.

29 shows the waveforms of the voltage of the set node Q, the voltage of the scan pulse, the voltage of the clock pulse and the voltage of the common node CN generated by the shift register according to the ninth embodiment of the present invention (Fig. 17) Fig.

29, noises due to coupling occur in the set node Q when the clock pulse goes high, and the voltage of the common node CN also rises, and thereby the second switching It can be seen that the voltage of the set node Q is held low by the element Tr2 and the stable state is maintained.

30 shows waveforms of the voltage of the set node Q, the voltage of the scan pulse, the voltage of the clock pulse, and the voltage of the common node CN generated by the shift register according to the tenth embodiment of the present invention (Fig. 18) Fig.

31 is a diagram showing the waveforms of the voltage of the set node Q, the voltage of the scan pulse and the voltage of the reset node QB generated by the shift register according to the twelfth embodiment of the present invention (Fig. 21).

32 is a graph showing the relationship between the voltage of the set node Q, the voltage of the scan pulse, the voltage of the common node CN, and the voltage of the reset node QB generated by the shift register according to the thirteenth embodiment of the present invention Voltage waveforms.

FIG. 33 is a diagram showing the waveforms of the voltage of the set node Q, the voltage of the scan pulse, and the voltage of the common node CN generated by the shift register according to the fourteenth embodiment of the present invention (FIG. 23).

FIG. 34 is a diagram showing the waveforms of the voltage of the set node Q, the voltage of the scan pulse, and the voltage of the common node CN generated by the shift register according to the fifteenth embodiment of the present invention (FIG. 24).

FIG. 35 is a graph showing the relationship between the voltage of the set node Q, the voltage of the scan pulse, the reset node QB, and the voltage of the first common node CN1 generated by the shift register according to the sixteenth embodiment of the present invention Voltage waveforms.

36 is a graph showing the relationship between the voltage of the set node Q generated by the shift register according to the seventeenth embodiment of the present invention (Fig. 26), the voltage of the scan pulse, the reset node QB, Voltage waveforms.

37 is a graph showing the relationship between the voltage of the set node Q generated by the shift register according to the eighteenth embodiment of the present invention (Fig. 27), the voltage of the scan pulse, the reset node QB, Voltage waveforms.

38 is a graph showing the relationship between the voltage of the set node Q generated by the shift register according to the nineteenth embodiment of the present invention (Fig. 28), the voltage of the scan pulse, the reset node QB, Voltage waveforms.

On the other hand, in all the embodiments, the first switching device Tr1 is turned on or off in response to a scan pulse from the n-1-th stage (or the n-2-th stage) The configuration can be changed so as to electrically connect the line and the set node Q to each other. In other words, the drain terminal of the first switching device Tr1 may be connected to the charging power supply line instead of the output terminal OT of the (n-1) th stage.

Further, each stage in the ninth to nineteenth embodiments receives a scan pulse from the (n-2) th stage instead of the (n-1) th stage and a scan pulse from the The configuration may be changed to receive the supply. In this case, each stage in the ninth to nineteenth embodiments is supplied with the overlapped clock pulses CLK1 to CLK4 and the start pulses Vst1 and Vst2 as shown in FIG. 4, Output. If the clock pulse supplied to the pull-up switching device Uc in the ninth to eleventh embodiments is the first clock pulse CLK1, the clock pulse supplied to the pull-down switching device Ds is the third clock pulse CLK3 ).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Tri: i-th switching device TDi: i-th switching device
Q: set node QB: reset node
Uc: Pull-up switching element Ds: Pull-down switching element
OB: output unit VDD: charging voltage
VSS: discharge voltage CLKi: i-th clock pulse

Claims (39)

A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal; And,
The node control unit of each stage controls either turn-on and turn-off according to a scan pulse from the next stage or the next stage, and any one of a plurality of clock transmission lines transmitting the plurality of clock pulses, A first discharging switching element connected between the nodes; And
And a control circuit for controlling the turn-on and turn-off according to a scan pulse from a pre-stage or a front-end stage and for controlling the turn-on and turn-off of a second room connected between the reset node and any one of a plurality of clock transmission lines transmitting the plurality of clock pulses And a dedicated switching element. The method according to claim 1,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the set node and the charging power supply line when turned on;
A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ;
A third switching element that is turned on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the reset node when the power supply line is turned on;
Further comprising a fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the discharge power supply line to each other when the switch is turned on;
The first discharge switching element provided in the node control unit of the nth stage is turned on or off in response to a scan pulse from the (n + 2) th stage, and when turned on, Electrically connecting the lines to each other;
The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the n-2 stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other;
Wherein the discharge power supply line transmits a discharge voltage and the discharge voltage is less than the charge voltage. 3. The method of claim 2,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element which is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other when the turn- . The method according to claim 1,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the set node and the charging power supply line when turned on;
A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ;
A third switching element that is turned on or turned off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when turned on;
A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the discharge power supply line to each other when the switch is turned on;
A fifth switching device that turns on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the common node to each other when the power supply line is turned on;
Further comprising a sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line to each other at the time of turn-
The first discharge switching element provided in the node control unit of the nth stage is turned on or off in response to a scan pulse from the (n + 2) th stage, and when turned on, Electrically connecting the lines to each other;
The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the n-2 stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other;
The discharging power line transmits a discharging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 5. The method of claim 4,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element which is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other when the turn- . The method according to claim 1,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the set node and the charging power supply line when turned on;
A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ;
A third switching element that is turned on or turned off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when turned on;
A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the first discharge power supply line to each other when the first switch is turned on;
A fifth switching device that turns on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the common node to each other when the power supply line is turned on;
Further comprising a sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the common node and the first discharging power supply line to each other when the first switch is turned on;
The first discharge switching element provided in the node control unit of the nth stage is turned on or off in response to a scan pulse from the (n + 2) th stage, and when turned on, Electrically connecting the lines to each other;
The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the n-2 stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other;
The first discharging power line transmits a first discharging voltage;
Wherein the first discharging voltage is smaller than the charging voltage. The method according to claim 6,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the second discharge power supply line to each other;
The second discharging power line transmits a second discharging voltage;
Wherein the second discharge voltage is greater than or equal to the first discharge voltage. The method according to claim 1,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the set node and the charging power supply line when turned on;
A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ;
A third switching element that is turned on or turned off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when turned on;
A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the second discharge power supply line to each other when the first switch is turned on;
A fifth switching device that turns on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the common node to each other when the power supply line is turned on;
And a sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the common node and the first discharge power supply line to each other when the first switch is turned on;
The first discharge switching element provided in the node control unit of the nth stage is turned on or off in response to a scan pulse from the (n + 2) th stage, and when turned on, Electrically connecting the lines to each other;
The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the n-2 stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other;
Wherein the first discharging power line transfers a first discharging voltage and the second discharging power line transmits a second discharging voltage;
Wherein the first and second discharge voltages are less than the charging voltage;
Wherein the first discharging voltage is less than or equal to the second discharging voltage. 9. The method of claim 8,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the second discharge power supply line to each other;
The second discharging power line transmits a second discharging voltage;
Wherein the second discharge voltage is greater than or equal to the first discharge voltage. The method according to claim 1,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the set node and the charging power supply line when turned on;
A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ;
A third switching element that turns on or off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the common node to each other when the power supply is turned on;
A fourth switching device that is turned on or off in response to a clock pulse supplied to the output of the (n-1) th stage and electrically connects the reset node and the second discharge power supply line to each other when turned on;
A fifth switching device that turns on or off in response to a clock pulse supplied to the output of the (N + 2) stage and electrically connects the charging power supply line and the common node when turned on;
A sixth switching element for turning on or off the first node in response to a clock pulse supplied to the output of the n-1th stage and electrically connecting the common node and the first discharge power supply line to each other when the first node is turned on; Further comprising;
The first discharge switching element provided in the node control unit of the nth stage is turned on or off in response to a scan pulse from the (n + 2) th stage, and when turned on, Electrically connecting the lines to each other;
The second discharging switching element provided in the node controller of the n-th stage is turned on or off in response to a scan pulse from the n-2 stage. When the reset node and any one of the clocks Electrically connecting transmission lines to each other;
Wherein the first discharging power line transfers a first discharging voltage and the second discharging power line transmits a second discharging voltage;
Wherein the first and second discharge voltages are less than a voltage of the charging power supply line;
Wherein the first discharging voltage is less than or equal to the second discharging voltage. 11. The method of claim 10,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the second discharge power supply line to each other, ;
The second discharging power line transmits a second discharging voltage;
Wherein the second discharge voltage is greater than or equal to the first discharge voltage. 11. The method of claim 10,
The node control unit provided in the n < th >
A third discharging switching element turned on or off in response to a scan pulse from the n-2 th stage and electrically connecting the common node and the one clock transmission line to each other when turned on; And
And a seventh switching element that is turned on or off in response to a voltage supplied to the set node and that electrically connects the reset node and the second discharge power supply line when turned on . A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the set node and the charging power supply line when turned on;
A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ;
A third switching element that is turned on or turned off in response to a voltage supplied to the common node and electrically connects the charging power supply line and the reset node when turned on;
A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the reset node and the first discharge power supply line to each other when the first switch is turned on;
A fifth switching device that turns on or off in response to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the common node to each other when the power supply line is turned on;
A sixth switching device that is turned on or off in response to a voltage supplied to the set node and electrically connects the common node and the first discharge power supply line to each other when the first switch is turned on;
A seventh switching device that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the reset node and the first discharge power supply line when turned on; And
And a first discharging switching element that is turned on or off in response to a scan pulse from the (n + 2) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The first discharging power line transmits a first discharging voltage;
Wherein the first discharging voltage is smaller than the charging voltage. 14. The method of claim 13,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the second discharge power supply line to each other;
The second discharging power line transmits a second discharging voltage;
Wherein the second discharge voltage is greater than or equal to the first discharge voltage. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The reset node is divided into a first reset node and a second reset node;
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-2) th stage and electrically connects the set node and the charging power supply line when turned on;
A second switching element which is turned on or off in response to a clock pulse supplied to the output of the (n-1) -th stage and electrically connects the output terminal of the (n-1) ;
A third switching element that is turned on or turned off in response to a voltage supplied to the first common node and electrically connects the first AC power supply line and the first reset node to each other at the turn-
A fourth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the first reset node and the first discharge power supply line to each other when the first switch is turned on;
A fifth switching device that is turned on or off in response to a first AC voltage from the first AC power supply line and electrically connects the first AC power supply line and the first common node when the first AC power supply line is turned on;
A sixth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the first common node and the first discharge power supply line to each other when the first switch is turned on;
A seventh switching device which is turned on or off in response to a scan pulse from the n-2 stage and electrically connects the first reset node and the first discharge power supply line when turned on;
An eighth switching device that is turned on or off in response to a voltage supplied to the second common node and electrically connects the second AC power supply line and the second reset node to each other upon turning on;
A ninth switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the second reset node and the first discharging power supply line to each other when turned on;
A tenth switching device that is turned on or off in response to a second AC voltage from the second AC power supply line and electrically connects the second AC power supply line and the second common node to each other when the first AC power supply line is turned on;
An eleventh switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the second common node and the first discharge power supply line to each other when the first switch is turned on;
A twelfth switching element that is turned on or turned off in response to a scan pulse from the n-2 stage and electrically connects the second reset node and the first discharge power supply line to each other; And,
And a first discharging switching element that is turned on or off in response to a scan pulse from the (n + 2) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The first discharging power line transmits a first discharging voltage;
The first discharge voltage is lower than the voltage of the charging power supply line;
Wherein the phase of the first AC voltage is inverted by 180 degrees with respect to the phase of the second AC voltage. 16. The method of claim 15,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on;
A first pull-down switching device for turning on or off in response to a voltage supplied to the first reset node and electrically connecting an output terminal of the n-th stage to a second discharge power supply line, ;
A second pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on;
And a second pull-down switching element for turning on or off the output terminal in response to a voltage supplied to the second reset node and electrically connecting the output terminal of the n-th stage and the second discharge power- ;
The second discharging power line transmits a second discharging voltage;
Wherein the second discharge voltage is greater than or equal to the first discharge voltage. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that is turned on or off in response to a scan pulse from the (n-1) th stage and electrically connects the output terminal of the (n-1) th stage and the set node when turned on;
A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on;
A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when turned on;
A capacitor connected between any one of the clock transmission lines and the common node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
Wherein the discharge voltage is smaller than a charging voltage. 18. The method of claim 17,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
The reset node is connected to any one of the clock transmission lines;
Wherein the first discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that is turned on or off in response to a scan pulse from the (n-1) th stage and electrically connects the output terminal of the (n-1) th stage and the set node when turned on;
A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on;
A third switching element that is turned on or off according to a scan pulse from the (n-1) th stage and electrically connects the common node and the discharge power supply line when turned on;
A capacitor connected between any one of the clock transmission lines and the common node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
Wherein the discharge voltage is smaller than a charging voltage. 20. The method of claim 19,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
The reset node is connected to any one of the clock transmission lines;
Wherein the first discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on;
A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when turned on;
A fourth switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and the discharge power supply line to each other when the switch is turned on;
A first capacitor connected between any one of the clock transmission lines and the common node;
A second capacitor connected between any one of the clock transmission lines and the reset node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
The charging power supply line transmits a charging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 22. The method of claim 21,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
Wherein the first discharging switching element, the first capacitor, the second capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on;
A third switching device that turns on or off according to a scan pulse from the (n-1) th stage and electrically connects the common node and any one of the clock transmission lines to each other;
A fourth switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and the discharge power supply line to each other when the switch is turned on;
A first capacitor connected between any one of the clock transmission lines and the common node;
A second capacitor connected between any one of the clock transmission lines and the reset node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
The charging power supply line transmits a charging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 24. The method of claim 23,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
Wherein the first discharging switching element, the third switching element, the first capacitor, the second capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on;
A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when turned on;
A capacitor connected between any one of the clock transmission lines and the common node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
The charging power supply line transmits a charging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 26. The method of claim 25,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
The reset node and the common node are connected to each other;
Wherein the first discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on;
A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the common node and the discharge power supply line when turned on;
A fourth switching device that is turned on or off according to a scan pulse from the (n-1) th stage and electrically connects the common node and the discharge power supply line to each other when turned on;
A capacitor connected between any one of the clock transmission lines and the common node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
The charging power supply line transmits a charging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 28. The method of claim 27,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
The reset node and the common node are connected to each other;
Wherein the first discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the first common node and electrically connects the output terminal of the set node and the nth stage when turned on;
A third switching element that is turned on or off according to a voltage supplied to the set node and electrically connects the first common node and a discharge power supply line to each other when the first node is turned on;
A fourth switching device for turning on or off according to a voltage supplied to the second common node and electrically connecting the reset power supply line and the reset node at the turn-on time;
A fifth switching device that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on;
A sixth switching element that is turned on according to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the second common node to each other;
A seventh switching device that turns on or off according to a voltage supplied to the set node and electrically connects the second common node and the discharge power supply line to each other when the first switch is turned on;
A capacitor connected between any one of the clock transmission lines and the first common node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
The charging power supply line transmits a charging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 30. The method of claim 29,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
Wherein the first discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the first common node and electrically connects the output terminal of the set node and the nth stage when turned on;
A third switching device that is turned on or off according to a scan pulse from the (n-1) th stage and electrically connects the first common node and the discharge power supply line to each other when the first common node is turned on;
A fourth switching device for turning on or off according to a voltage supplied to the second common node and electrically connecting the reset power supply line and the reset node at the turn-on time;
A fifth switching device that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on;
A sixth switching element that is turned on according to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the second common node to each other;
A seventh switching device that turns on or off according to a voltage supplied to the set node and electrically connects the second common node and the discharge power supply line to each other when the first switch is turned on;
A capacitor connected between any one of the clock transmission lines and the first common node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
The charging power supply line transmits a charging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 32. The method of claim 31,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
Wherein the first discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the first common node and electrically connects the output terminal of the set node and the nth stage when turned on;
A third switching device that turns on or off according to a scan pulse from the (n-1) th stage and electrically connects the first common node and one of the clock transmission lines to each other;
A fourth switching device for turning on or off according to a voltage supplied to the second common node and electrically connecting the reset power supply line and the reset node at the turn-on time;
A fifth switching device that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on;
A sixth switching element that is turned on according to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the second common node to each other;
A seventh switching device that turns on or off according to a voltage supplied to the set node and electrically connects the second common node and the discharge power supply line to each other when the first switch is turned on;
A capacitor connected between any one of the clock transmission lines and the first common node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
The charging power supply line transmits a charging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 34. The method of claim 33,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
Wherein the first discharging switching element, the third discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the first common node and electrically connects the output terminal of the set node and the nth stage when turned on;
A third switching device that turns on or off according to a scan pulse from the (n-1) th stage and electrically connects the first common node and one of the clock transmission lines to each other;
A fourth switching device for turning on or off according to a voltage supplied to the second common node and electrically connecting the reset power supply line and the reset node at the turn-on time;
A fifth switching device that is turned on or off according to a voltage supplied to the set node and electrically connects the reset node and a discharge power supply line to each other when the switch is turned on;
A sixth switching element that is turned on according to a charging voltage from the charging power supply line and electrically connects the charging power supply line and the second common node to each other;
A seventh switching device that turns on or off according to a voltage supplied to the set node and electrically connects the second common node and the discharge power supply line to each other when the first switch is turned on;
An eighth switching device that turns on or off according to a voltage supplied to the reset node and electrically connects an output terminal of the (n-1) th stage and a discharge power supply line to each other;
A capacitor connected between any one of the clock transmission lines and the first common node; And
And a first discharging switching element which is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The discharging power line transmits a discharging voltage;
The charging power supply line transmits a charging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 36. The method of claim 35,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or turned off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
Wherein the first discharging switching element, the third discharging switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. A plurality of stages for sequentially outputting scan pulses;
Each of the stages receiving a clock signal of a set node and a reset node and a plurality of clock pulses having different phases, And an output section for outputting the pulse as a scan pulse through its output terminal,
The node control unit provided in the n < th >
A first switching device that turns on or off in response to a scan pulse from the (n-1) th stage and electrically connects the set power supply line and the set node at the turn-on time;
A second switching device that is turned on or off according to a voltage supplied to the common node and electrically connects the output terminal of the set node to the output terminal of the nth stage when the switch is turned on;
A third switching element that is turned on or off according to a scan pulse from the (n-1) th stage and electrically connects the common node and the discharge power supply line when turned on;
A capacitor connected between any one of the clock transmission lines and the common node; And
And a discharging switching element that is turned on or off in response to a scan pulse from the (n + 1) th stage and electrically connects the set node and any one of the clock transmission lines to each other,
The charging power supply line transmits a charging voltage,
The discharging power line transmits a discharging voltage;
Wherein the discharge voltage is smaller than the charging voltage. 39. The method of claim 37,
Wherein the output unit provided in the n < th >
A pull-up switching element that is turned on or off in response to a voltage supplied to the set node and electrically connects the output terminal of one of the clock transmission lines and the n-th stage in turn on; And
And a pull-down switching element that is turned on or off in response to a voltage supplied to the reset node and electrically connects the output terminal of the n-th stage and the discharge power supply line to each other;
The reset node is connected to any one of the clock transmission lines;
Wherein the discharge switching element, the third switching element, the capacitor, and the pull-up switching element are all connected to the same clock transmission line. 39. The method of claim 38,
And a low voltage of a clock pulse supplied to each of the clock transmission lines is larger than the discharge voltage.

Images