CN113920937B

CN113920937B - Display substrate and display device

Info

Publication number: CN113920937B
Application number: CN202111235749.0A
Authority: CN
Inventors: 刘苗; 郝学光; 许静波; 姚星; 王景泉; 吴新银; 李新国; 王志冲
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2022-09-09
Anticipated expiration: 2041-07-09
Also published as: CN113241040B; US12080226B2; US20240112623A1; KR20240032702A; EP4280202A1; WO2023280314A1; CN113241040A; JP2024528768A; CN113920937A; EP4280202A4

Abstract

A display substrate, comprising: a scan drive control circuit. The scan drive control circuit includes: input circuit, output control circuit and output circuit. The input circuit is configured to transmit a signal of the signal input terminal to the output control circuit and transmit a signal of the first clock signal terminal or the first voltage terminal to the output control circuit under control of the first clock signal terminal. The output control circuit is configured to store a signal of the first signal terminal under the control of the input circuit and transmit a signal of the second signal terminal to the first node under the control of the input circuit and the second clock signal terminal; or, under the control of the input circuit, storing the signal of the second clock signal terminal, and under the control of the second node, transmitting the signal of the second voltage terminal to the first node. The output circuit is configured to output a signal of the first voltage terminal to the signal output terminal under control of the second node or output a signal of the second voltage terminal to the signal output terminal under control of the first node.

Description

Display substrate and display device

The present application is a divisional application of the application entitled "display substrate and display device" with an application date of 2021, 7/9/h and an application number of 202110774729.4.

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and more particularly, to a display substrate and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and using a Thin Film Transistor (TFT) for signal control has become a mainstream product in the Display field.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a display substrate and a display device.

In one aspect, an embodiment of the present disclosure provides a display substrate, including: the liquid crystal display device includes a base substrate and a scan drive control circuit disposed in a non-display region of the base substrate. The scanning drive control circuit includes: input circuit, output control circuit and output circuit. The output control circuit is connected with the input circuit and the output circuit. The output control circuit includes: the first node controls the capacitance and the second node controls the capacitance. First node controlLength L of capacitor in first direction _C1k The second node controls the length L of the capacitor in the first direction _C2k And the length L of the scan drive control circuit in the first direction _Y Satisfies the following conditions:

in some exemplary embodiments, the first node control capacitance includes: a first capacitor and a third capacitor. The lengths of the first capacitor, the third capacitor, the second node control capacitor and the scanning drive control circuit in a first direction satisfy:

wherein L is _C1 Is the length of the first capacitor in a first direction, L _C3 Is the length of the third capacitor in the first direction, L _C2k Controlling the length of the capacitance in a first direction, L, for said second node _Y The length of the scanning driving control circuit in the first direction is used.

In some exemplary embodiments, the first capacitance and the scan drive control circuit have a length in the first direction that satisfies:

the length of the second node control capacitor and the length of the scanning drive control circuit in the first direction meet the following conditions:

the length of the third capacitor and the scanning drive control circuit in the first direction satisfies the following conditions:

in some of the exemplary embodiments, the first and second electrodes are,

is one of the following: 0.09, 0.10, 0.14;

is one of the following: 0.22, 0.35, 0.48;

is one of the following: 0.07, 0.06, 0.05.

In some of the exemplary embodiments, the first and second electrodes are,

in some of the exemplary embodiments, the first and second electrodes are,

in some of the exemplary embodiments, the first and second electrodes are,

in some exemplary embodiments, the lengths of the first capacitance, the second node control capacitance, and the third capacitance in the first direction satisfy:

in some exemplary embodiments, the third capacitor is connected to a first power line; the third capacitor is overlapped with the projection of the first power line on the substrate base plate, and the overlapping area meets the following requirements:

wherein S is _C3 Is the projected area of the third capacitor on the substrate, S _C3-1 The overlapping area of the projection of the third capacitor and the first power line on the substrate base plate is defined; the second node control capacitor comprises a second capacitor, S _C2 The projection area of the second capacitor on the substrate base plate is shown.

In some exemplary embodiments, the second node control capacitance overlaps with a projection of the first power line on the substrate, and an overlapping area satisfies:

wherein S is _C2k-1 An overlapping area of the second node control capacitance and a projection of the first power line on the substrate is defined, X2 is a length of the first power line in a first direction, and L5 is a length of an overlapping region of one of the second node control capacitances and the projection of the first power line on the substrate in a second direction; the second direction intersects the first direction.

In some exemplary embodiments, the input circuit is connected to a second power line; the second node control capacitor and the projection of a second power line on the substrate are overlapped, and the overlapping area meets the following requirements:

wherein S is _C2k-2 Controlling capacitance and second power line location for the second nodeAn overlapping area of projections on the substrate base plate, X3 being a length of the second power supply line in a first direction, and L6 being a length of an overlapping region of one of the second node control capacitances and a projection of the second power supply line on the substrate base plate in a second direction; the second direction intersects the first direction.

In some exemplary embodiments, a projection of the first capacitance on the substrate base is located between projections of the first and second power supply lines on the substrate base. The distance L7 between the center of the first capacitor in the first direction and the side of the first power line far away from the first capacitor in the first direction is greater than the distance L8 between the center of the first capacitor in the first direction and the side of the second power line near the first capacitor in the first direction, and L7 is greater than or equal to 2L 8.

In some exemplary embodiments, the input circuit includes: a first transistor; and the control electrode of the first transistor is connected with a first clock signal line, the first electrode of the first transistor is connected with a signal input end, and the second electrode of the first transistor is connected with a second node. The active layer of the first transistor is adjacent to the second power supply line. A distance L2 between a side of the channel region of the active layer of the first transistor close to the second power supply line and a side of the second power supply line far from the first transistor satisfies: l2 is more than or equal to 0 and less than or equal to 4W _PL2 (ii) a Wherein, W _PL2 Is the width of the second power line.

In some exemplary embodiments, the input circuit includes: a third transistor; and a control electrode of the third transistor is connected with the first clock signal line, a first electrode of the third transistor is connected with the second power line, and a second electrode of the third transistor is connected with the third node. The second power supply line is located on a side of the third transistor away from the first clock signal line or the second clock signal line. A distance L3 between a side of the channel region of the active layer of the third transistor close to the second power supply line and a side of the second power supply line away from the third transistor satisfies: l3 is more than or equal to 0 and less than or equal to 4W _PL2 (ii) a Wherein, W _PL2 Is the width of the second power line.

In some examplesIn an exemplary embodiment, the input circuit is connected to a first clock signal line and a second power line, and the output control circuit is connected to a second clock signal line; the input circuit includes: a second transistor; and the control electrode of the second transistor is connected with the second node, the first electrode of the second transistor is connected with the first clock signal line, and the second electrode of the second transistor is connected with the third node. The second power line is located on a side of the second transistor away from the first clock signal line. An active layer of the second transistor is adjacent to the second power supply line; a distance L4 between a side of the channel region of the active layer of the second transistor close to the second power supply line and a side of the second power supply line far from the second transistor satisfies: l4 is more than or equal to 0 and less than or equal to 3W _PL2 (ii) a Wherein, W _PL2 Is the width of the second power line.

In some exemplary embodiments, the output control circuit includes: the first output controls the sub-circuit. The first output control sub-circuit includes: a fourth transistor and a fifth transistor; a control electrode of the fourth transistor is connected with the second node, a first electrode of the fourth transistor is connected with a second electrode of the fifth transistor, and the second electrode of the fourth transistor is connected with the second clock signal line; and a control electrode of the fifth transistor is connected with the third node, and a first electrode of the fifth transistor is connected with the first power line. The fourth transistor and the fifth transistor are located on one side of the second power line away from the second clock signal line. An included angle between the extending direction of the active layer of the fourth transistor and the extending direction of the active layer of the fifth transistor is larger than 85 degrees and smaller than 95 degrees.

In some exemplary embodiments, a width W of a channel region of an active layer of the fourth transistor _T4 And a width W of a channel region of an active layer of the fifth transistor _T5 Satisfies the following conditions: 2W _T4 <W _T5 。

In some exemplary embodiments, an angle between an extending direction of an active layer of the fourth transistor and an extending direction of an active layer of the first transistor of the input circuit is greater than 85 ° and less than 95 °.

In some exemplary embodiments, the output control circuit includes a second output control sub-circuit including a seventh transistor. And a control electrode of the seventh transistor is connected with the second electrode of the first capacitor, and a first electrode of the seventh transistor is connected with the first node. The seventh transistor is adjacent to the first capacitor, and the seventh transistor is located between the first capacitor and a first power line.

In some exemplary embodiments, the second output control sub-circuit further comprises: a sixth transistor; and a control electrode of the sixth transistor is connected with the first electrode of the first capacitor, a second electrode of the sixth transistor is connected with the second electrode of the seventh transistor, and a first electrode of the sixth transistor is connected with the second signal end. An extending direction of an active layer of the seventh transistor is approximately parallel to an extending direction of an active layer of the sixth transistor.

In some exemplary embodiments, the output control circuit includes: a third output control sub-circuit comprising an eighth transistor and a third capacitor; a control electrode of the eighth transistor is connected with the second node, a first electrode of the eighth transistor is connected with the first power line, and a second electrode of the eighth transistor is connected with the first node; and the first pole of the third capacitor is connected with the first node, and the second pole of the third capacitor is connected with the first power line. The input circuit includes a first transistor. The first transistor, the eighth transistor and the third capacitor are sequentially arranged along a first direction, and the extending direction of the active layer of the first transistor is approximately parallel to the extending direction of the active layer of the eighth transistor.

In some exemplary embodiments, a distance L9 between a side of the active layer of the eighth transistor close to the third capacitor and a side of the third capacitor close to the eighth transistor satisfies: w _CLK <L9≤W _PL1 (ii) a Wherein, W _CLK Is the width of the clock signal line, W _PL1 Is the width of the first power line.

In some exemplary embodiments, the input circuit is connected to a first clock signal line; the output control circuit is connected with a second clock signal line and a first power line; the output circuit is connected to the first power line and the third power line. The first clock signal line, the second clock signal line, the initial signal line, the first power line and the third power line are sequentially arranged along a first direction.

In some exemplary embodiments, the capacitance values of the first capacitance, the third capacitance and the second node control capacitance satisfy:

C ₁ ＜C ₃ ＜C _2k ；

wherein, C ₁ Is the capacitance value of the first capacitor, C ₃ Is the capacitance value of the third capacitor, C _2k The capacitance value of the capacitor is controlled for the second node.

In some exemplary embodiments, the first pole of the first capacitor is connected to a third node, and the second pole of the first capacitor is connected to a seventh transistor. The first pole of the third capacitor is connected with the first node, and the second pole of the third capacitor is connected with the first power line. The second node controls the first pole of the capacitor to be connected with the second node. The sum of the capacitance values of the first capacitor and the third capacitor is smaller than the capacitance value of the second node control capacitor.

In some exemplary embodiments, the second node control capacitor includes a second capacitor, a first pole of the second capacitor is connected to the second node, and a second pole of the second capacitor is connected to the signal output terminal.

In some exemplary embodiments, the second node control capacitance further comprises: and a first pole of the fourth capacitor is connected with the second node, and a second pole of the fourth capacitor is connected with the fourth transistor and the fifth transistor.

In some exemplary embodiments, the first pole of the second capacitor of the scan drive control circuit of the present stage and the first pole of the fourth capacitor of the scan drive control circuit of the next stage are of an integral structure.

In some exemplary embodiments, the output circuit includes a tenth transistor; the second node control capacitor comprises a second capacitor, and a first electrode of the second capacitor and a control electrode of the tenth transistor are of an integral structure.

In another aspect, an embodiment of the present disclosure provides a display device including the display substrate as described above.

In another aspect, an embodiment of the present disclosure provides a display substrate including a scan driving control circuit. The scan driving control circuit includes: input circuit, output control circuit and output circuit. The input circuit is connected with the signal input end, the first clock signal end, the first voltage end and the output control circuit, and is configured to transmit a signal of the signal input end to the output control circuit and transmit a signal of the first clock signal end or the first voltage end to the output control circuit under the control of the first clock signal end. The output control circuit is connected with the first signal end, the second clock signal end, the second voltage end, the first node, the second node and the input circuit, and is configured to store the signal of the first signal end under the control of the input circuit and transmit the signal of the second signal end to the first node under the control of the input circuit and the second clock signal end; or, under the control of the input circuit, storing the signal of the second clock signal terminal, and under the control of the second node, transmitting the signal of the second voltage terminal to the first node. The output circuit is connected with the first voltage end, the second voltage end, the signal output end, the first node and the second node, and is configured to output a signal of the first voltage end to the signal output end under the control of the second node, or output a signal of the second voltage end to the signal output end under the control of the first node.

In some exemplary embodiments, the input circuit includes: a first input sub-circuit and a second input sub-circuit; the output control circuit includes: a first output control sub-circuit, a second output control sub-circuit, and a third output control sub-circuit; the output circuit includes: a first output sub-circuit and a second output sub-circuit. The first input sub-circuit is connected with the signal input end, the first clock signal end and the first output control sub-circuit, and is configured to transmit a signal of the signal input end to the first output control sub-circuit under the control of the first clock signal end. The second input sub-circuit is connected with the first voltage end, the first clock signal end, the first input sub-circuit and the second output control sub-circuit, and is configured to transmit the signal of the first clock signal end or the first voltage end to the second output control sub-circuit under the control of the first input sub-circuit or the first clock signal end. The first output control sub-circuit is connected with the first signal terminal, the second clock signal terminal, the second node, the first input sub-circuit and the second input sub-circuit, and is configured to store a signal of the first signal terminal or the second clock signal terminal under the control of the first input sub-circuit or the second input sub-circuit. The second output control sub-circuit is connected with the second signal terminal, the second clock signal terminal, the first node and the second input sub-circuit, and is configured to transmit a signal of the second signal terminal to the first node under the control of the second input sub-circuit and the second clock signal terminal. And the third output control sub-circuit is connected with the second voltage end, the first node and the second node and is configured to transmit a signal of the second voltage end to the first node under the control of the second node. The first output sub-circuit is connected with the first voltage end, the signal output end and the second node, and is configured to output a signal of the first voltage end to the signal output end under the control of the second node. The second output sub-circuit is connected with the second voltage end, the signal output end and the first node, and is configured to output a signal of the second voltage end to the signal output end under the control of the first node.

In some exemplary embodiments, the first input sub-circuit comprises: a first transistor; and the control electrode of the first transistor is connected with the first clock signal end, the first electrode of the first transistor is connected with the signal input end, and the second electrode of the first transistor is connected with the second node. The second input sub-circuit comprises: a second transistor and a third transistor; a control electrode of the second transistor is connected with a second node, a first electrode of the second transistor is connected with a first clock signal end, and a second electrode of the second transistor is connected with a third node; and a control electrode of the third transistor is connected with the first clock signal end, a first electrode of the third transistor is connected with the first voltage end, and a second electrode of the third transistor is connected with the third node. The first output control sub-circuit includes: a fourth transistor and a fifth transistor; a control electrode of the fourth transistor is connected with a second node, a first electrode of the fourth transistor is connected with a second clock signal end, and a second electrode of the fourth transistor is connected with a second electrode of the fifth transistor; and a control electrode of the fifth transistor is connected with the third node, and a first electrode of the fifth transistor is connected with the first signal end. The first output sub-circuit includes: a tenth transistor; and a control electrode of the tenth transistor is connected with the second node, a first electrode of the tenth transistor is connected with the first voltage end, and a second electrode of the tenth transistor is connected with the signal output end.

In some exemplary embodiments, the first input sub-circuit comprises: a first transistor; and a control electrode of the first transistor is connected with a first clock signal end, a first electrode of the first transistor is connected with a signal input end, and a second electrode of the first transistor is connected with a fourth node. The second input sub-circuit comprises: a second transistor and a third transistor; a control electrode of the second transistor is connected with the fourth node, a first electrode of the second transistor is connected with the first clock signal end, and a second electrode of the second transistor is connected with the third node; and a control electrode of the third transistor is connected with the first clock signal end, a first electrode of the third transistor is connected with the first voltage end, and a second electrode of the third transistor is connected with the third node. The first output control sub-circuit includes: a fourth transistor, a fifth transistor, and an eleventh transistor; a control electrode of the fourth transistor is connected with a second node, a first electrode of the fourth transistor is connected with a second clock signal end, and a second electrode of the fourth transistor is connected with a second electrode of the fifth transistor; a control electrode of the fifth transistor is connected with the third node, and a first electrode of the fifth transistor is connected with the first signal end; and a control electrode of the eleventh transistor is connected with the first voltage end, a first electrode of the eleventh transistor is connected with the fourth node, and a second electrode of the eleventh transistor is connected with the second node. The first output sub-circuit includes: a tenth transistor; and a control electrode of the tenth transistor is connected with the second node, a first electrode of the tenth transistor is connected with the first voltage end, and a second electrode of the tenth transistor is connected with the signal output end.

In some exemplary embodiments, the second output control sub-circuit further comprises: a fourth capacitor; and the first pole of the fourth capacitor is connected with the control poles of the fourth transistor and the tenth transistor.

In some exemplary embodiments, the second pole of the fourth capacitor is connected to a fifth transistor.

In some exemplary embodiments, the first output control sub-circuit further comprises: a second capacitor; the first pole of the second capacitor is connected to a second node.

In some exemplary embodiments, the second pole of the second capacitor is connected to the signal output terminal.

In some exemplary embodiments, the second input sub-circuit is connected to a third node. The second output control sub-circuit includes: a sixth transistor, a seventh transistor, and a first capacitor. A control electrode of the sixth transistor is connected with the third node, a first electrode of the sixth transistor is connected with the second signal end, and a second electrode of the sixth transistor is connected with a second electrode of the seventh transistor; and a control electrode of the seventh transistor is connected with the second clock signal end, and a first electrode of the seventh transistor is connected with the first node. And the first pole of the first capacitor is connected with the control pole of the sixth transistor, and the second pole of the first capacitor is connected with the seventh transistor.

In some exemplary embodiments, the second input sub-circuit is connected to a fifth node. The second output control sub-circuit includes: a first capacitor, a sixth transistor, a seventh transistor, and a twelfth transistor. A control electrode of the sixth transistor is connected with the third node, a first electrode of the sixth transistor is connected with the second signal end, and a second electrode of the sixth transistor is connected with a second electrode of the seventh transistor; and a control electrode of the seventh transistor is connected with the second clock signal end, and a first electrode of the seventh transistor is connected with the first node. And a control electrode of the twelfth transistor is connected with the first voltage end, a first electrode of the twelfth transistor is connected with the fifth node, and a second electrode of the twelfth transistor is connected with the third node. And a first pole of the first capacitor is connected with a control pole of the sixth transistor, and a second pole of the first capacitor is connected with the seventh transistor.

In some exemplary embodiments, the third output control sub-circuit includes: an eighth transistor and a third capacitor. And a control electrode of the eighth transistor is connected with the second node, a first electrode of the eighth transistor is connected with the second voltage end, and a second electrode of the eighth transistor is connected with the first node. And the first pole of the third capacitor is connected with the first node, and the second pole of the third capacitor is connected with the second voltage end. The second output sub-circuit includes: a ninth transistor; and a control electrode of the ninth transistor is connected with the first node, the first electrode of the ninth transistor is connected with the second voltage end, and the second electrode of the ninth transistor is connected with the signal output end.

In some exemplary embodiments, the first signal terminal is connected to a second voltage terminal or a first clock signal terminal.

In some exemplary embodiments, the second signal terminal is connected to the first voltage terminal or the second clock signal terminal.

In another aspect, an embodiment of the present disclosure provides a driving method of a display substrate, where the driving method is applied to the display substrate, and the driving method includes: the input circuit transmits a signal of the signal input end to the output control circuit under the control of the first clock signal end, and transmits a signal of the first clock signal end or the first voltage end to the output control circuit; the output control circuit stores a signal of a first signal end under the control of the input circuit, transmits a signal of a second signal end to a first node under the control of the input circuit and a second clock signal end, and outputs a signal of a second voltage end to a signal output end under the control of the first node; the output control circuit stores a signal of a second clock signal end under the control of the input circuit and transmits a signal of a second voltage end to the first node under the control of a second node; the output circuit outputs a signal of the first voltage end to the signal output end under the control of the second node.

Other aspects will be apparent upon reading and understanding the attached figures and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of one or more of the elements in the drawings are not to be considered as true scale, but rather are merely intended to illustrate the present disclosure.

Fig. 1 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure;

fig. 3 is an equivalent circuit diagram of the first input sub-circuit, the second input sub-circuit, the first output control sub-circuit and the first output sub-circuit of the scan driving control circuit according to at least one embodiment of the disclosure;

fig. 4 is another equivalent circuit diagram of the first input sub-circuit, the second input sub-circuit, the first output control sub-circuit and the first output sub-circuit of the scan driving control circuit according to at least one embodiment of the disclosure;

fig. 5 is an equivalent circuit diagram of a second output control sub-circuit of the scan driving control circuit according to at least one embodiment of the disclosure;

FIG. 6 is another equivalent circuit diagram of a second output control sub-circuit of the scan driving control circuit according to at least one embodiment of the present disclosure;

fig. 7 is an equivalent circuit diagram of a third output control sub-circuit and a second output sub-circuit of the scan driving control circuit according to at least one embodiment of the disclosure;

fig. 8 is an equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure;

FIG. 9 is a timing diagram illustrating the operation of the scan driving control circuit shown in FIG. 8;

FIG. 10 is a timing diagram illustrating another operation of the scan driving control circuit shown in FIG. 8;

FIG. 11 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure;

fig. 12 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure;

fig. 13 is a flowchart of a driving method of a display substrate according to at least one embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a cascade of scan driving control circuits according to at least one embodiment of the present disclosure;

FIG. 15 is a top view of a scan driving control circuit according to at least one embodiment of the present disclosure;

FIG. 16 is a schematic partial cross-sectional view taken along the line P-P' in FIG. 15;

fig. 17 is a top view of a scan driving control circuit after forming a first semiconductor layer according to at least one embodiment of the present disclosure;

fig. 18 is a top view of a scan driving control circuit after forming a first conductive layer in accordance with at least one embodiment of the present disclosure;

fig. 19 is a top view of a scan driving control circuit after forming a second conductive layer according to at least one embodiment of the present disclosure;

fig. 20 is a top view of a scan driving control circuit after forming a third insulating layer according to at least one embodiment of the present disclosure;

fig. 21 is a top view of a scan driving control circuit after a third conductive layer is formed in accordance with at least one embodiment of the present disclosure;

FIG. 22 is a top view of two cascaded scan drive control circuits according to at least one embodiment of the present disclosure;

FIG. 23 is a top view of the first conductive layer of FIG. 22;

fig. 24 is another top view of a scan driving control circuit according to at least one embodiment of the present disclosure;

fig. 25 is another top view of a scan driving control circuit according to at least one embodiment of the present disclosure;

fig. 26 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure;

fig. 27 is another schematic structural diagram of a display device according to at least one embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. One of ordinary skill in the art will readily recognize the fact that the manner and content may be altered into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size, the thickness of a layer, or a region of one or more components may be exaggerated for clarity. Accordingly, one aspect of the disclosure is not necessarily limited to the dimensions, and the shapes and sizes of one or more components in the drawings are not to reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are provided to avoid confusion of the constituent elements, and are not limited in number. "plurality" in this disclosure means two or more.

In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise explicitly specified or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood as appropriate to one of ordinary skill in the art. Here, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical action" is not particularly limited as long as it can transmit an electrical signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, another element having one or more functions, and the like.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode (gate), a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, in order to distinguish two electrodes of a transistor except for a gate electrode, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source electrode or a drain electrode, the second electrode may be a drain electrode or a source electrode, and the gate electrode of the transistor is referred to as a control electrode. In the case of using transistors of opposite polarities, or in the case where the direction of current flow during circuit operation changes, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other.

In the present disclosure, "parallel" refers to a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and thus, may include a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" means a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus may include a state in which an angle is 85 ° or more and 95 ° or less.

In the present disclosure, "film" and "layer" may be interchanged with one another. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

"about," "approximately," and "approximately" in this disclosure refer to situations where there is no strict limit to the tolerances allowed for processing and measurement.

In some exemplary embodiments, the display substrate may include: a display area and a non-display area. For example, the non-display area may be located at the periphery of the display area. However, this embodiment is not limited to this. The display area includes at least: the pixel circuit includes a plurality of pixel circuits arranged regularly, a plurality of gate lines (including, for example, a scan line, a reset line, a light emission control line) extending in a first direction, a plurality of data lines extending in a second direction, and a power supply line. The first direction and the second direction are located in the same plane, and the first direction intersects with the second direction, for example, the first direction is perpendicular to the second direction.

In some exemplary embodiments, the non-display region is provided with a plurality of scan driving control circuits, and the scan driving control circuits may be configured to supply gate driving signals to the pixel circuits of the display region.

Fig. 1 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the disclosure. As shown in fig. 1, the scan drive control circuit provided in the present embodiment includes: input circuit, output control circuit and output circuit.

An input circuit connected to the signal input terminal IN, the first clock signal terminal CK, the first voltage terminal V1 and the output control circuit, and configured to transmit a signal of the signal input terminal IN to the output control circuit and transmit a signal of the first clock signal terminal CK or the first voltage terminal V1 to the output control circuit under the control of the first clock signal terminal CK.

An output control circuit connected to the first signal terminal SIG1, the second signal terminal SIG2, the second clock signal terminal CB, the second voltage terminal V2, the first node N1, the second node N2, and the input circuit, and configured to store a signal of the first signal terminal SIG1 under control of the input circuit and to transmit a signal of the second signal terminal SIG2 to the first node N1 under control of the input circuit and the second clock signal terminal CB; alternatively, the signal of the second clock signal terminal CB is stored under the control of the input circuit, and the signal of the second voltage terminal V2 is transferred to the first node N1 under the control of the second node N2.

And an output circuit connected to the first voltage terminal V1, the second voltage terminal V2, the signal output terminal OUT, the first node N1 and the second node N2, and configured to output a signal of the first voltage terminal V1 to the signal output terminal OUT under the control of the second node N2, or output a signal of the second voltage terminal V2 to the signal output terminal OUT under the control of the first node N1.

IN some exemplary embodiments, the input signals of the signal input terminal IN, the first clock signal terminal CK, and the second clock signal terminal CB may be pulse signals. The first voltage terminal V1 may continuously provide a low level signal, and the second voltage terminal V2 may continuously provide a high level signal. However, this embodiment is not limited to this.

In some exemplary embodiments, the first signal terminal SIG1 may be connected with the second voltage terminal V2 or the first clock signal terminal CK. The second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB. However, this embodiment is not limited to this.

In some exemplary embodiments, the output signal of the scan drive control circuit provided in the present embodiment may be provided as a gate drive signal (e.g., a scan signal or a reset signal, or a light emission control signal) to the pixel circuit of the display region. In some examples, the scan driving control circuit of the present embodiment may be applied to a Low Temperature Polycrystalline Oxide (LTPO) display substrate, and may provide a gate driving signal to an N-type transistor in a pixel circuit in a display region. However, this embodiment is not limited to this.

The scan driving control circuit provided by this embodiment can improve the stability of the first node N1 and the second node N2 through the output control circuit, thereby improving the output stability of the output circuit.

Fig. 2 is a schematic diagram of an exemplary structure of a scan driving control circuit according to at least one embodiment of the disclosure. In some exemplary embodiments, as shown in fig. 2, the input circuit includes: a first input sub-circuit and a second input sub-circuit; the output control circuit includes: a first output control sub-circuit, a second output control sub-circuit and a third output control sub-circuit; the output circuit includes: a first output sub-circuit and a second output sub-circuit. The first input sub-circuit is connected with the signal input end IN, the first clock signal end CK and the first output control sub-circuit, and is configured to transmit a signal of the signal input end IN to the first output control sub-circuit under the control of the first clock signal end CK. The second input sub-circuit is connected with the first voltage terminal V1, the first clock signal terminal CK, the first input sub-circuit and the second output control sub-circuit, and is configured to transmit the signal of the first clock signal terminal CK or the first voltage terminal V1 to the second output control sub-circuit under the control of the first input sub-circuit or the first clock signal terminal CK. And the first output control sub-circuit is connected with the first signal terminal SIG1, the second clock signal terminal CB, the second node N2, the first input sub-circuit and the second input sub-circuit, and is configured to store a signal of the first signal terminal SIG1 or the second clock signal terminal CB under the control of the first input sub-circuit or the second input sub-circuit. And a second output control sub-circuit connected to the second signal terminal SIG2, the second clock signal terminal CB, the first node N1, and the second input sub-circuit, and configured to transmit a signal of the second signal terminal SIG2 to the first node N1 under the control of the second input sub-circuit and the second clock signal terminal CB. And a third output control sub-circuit connected to the second voltage terminal V2, the first node N1 and the second node N2, and configured to transmit a signal of the second voltage terminal V2 to the first node N1 under the control of the second node N2.

And a first output sub-circuit connected to the first voltage terminal V1, the signal output terminal OUT and the second node N2, and configured to output a signal of the first voltage terminal V1 to the signal output terminal OUT under the control of the second node N2. And the second output sub-circuit is connected with the second voltage terminal V2, the signal output terminal OUT and the first node N1, and is configured to output a signal of the second voltage terminal V2 to the signal output terminal OUT under the control of the first node N1.

In some exemplary embodiments, the first input sub-circuit and the first output control sub-circuit are both connected to the second node N2. The second input sub-circuit, the first output control sub-circuit and the second output control sub-circuit are all connected with the third node. However, the present embodiment is not limited to this.

Fig. 3 is an equivalent circuit diagram of the input circuit, the first output control sub-circuit and the first output sub-circuit of the scan driving control circuit according to at least one embodiment of the disclosure. As shown in fig. 3, the first input sub-circuit of the scan drive control circuit provided by the present exemplary embodiment includes: a first transistor T1. A control electrode of the first transistor T1 is connected to the first clock signal terminal CK, a first electrode thereof is connected to the signal input terminal IN, and a second electrode thereof is connected to the second node N2.

As shown in fig. 3, the second input sub-circuit includes: a second transistor T2 and a third transistor T3. A control electrode of the second transistor T2 is connected to the second node N2, a first electrode thereof is connected to the first clock signal terminal CK, and a second electrode thereof is connected to the third node N3. A control electrode of the third transistor T3 is connected to the first clock signal terminal CK, a first electrode is connected to the first voltage terminal V1, and a second electrode is connected to the third node N3.

As shown in fig. 3, the first output sub-circuit includes: a tenth transistor T10. A control electrode of the tenth transistor T10 is connected to the second node N2, a first electrode thereof is connected to the first voltage terminal V1, and a second electrode thereof is connected to the signal output terminal OUT.

As shown in fig. 3, the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a second capacitor C2 and a fourth capacitor C4. A control electrode of the fourth transistor T4 is connected to the second node N2, a first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and a second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5. A control electrode of the fifth transistor T5 is connected to the third node N3, and a first electrode of the fifth transistor T5 is connected to the first signal terminal SIG 1. A first pole of the second capacitor C2 is connected to the second node N2, and a second pole of the second capacitor C2 is connected to the signal output terminal OUT. A first pole of the fourth capacitor C4 is connected to the control electrode of the fourth transistor T4 and the control electrode of the tenth transistor T10 (i.e., to the second node N2), and a second pole of the fourth capacitor C4 is connected to the second pole of the fifth transistor T5 and the second pole of the fourth transistor T4.

In the present exemplary embodiment, the potential of the second node N2 may be kept stable when the tenth transistor T10 is turned on by the second capacitor C2 and the fourth capacitor C4 arranged in series, so that the first output sub-circuit provides a stable output.

In the present exemplary embodiment, fig. 3 shows one exemplary structure of the input circuit, the first output control sub-circuit, and the first output sub-circuit. It is easily understood by those skilled in the art that the implementation of the input circuit, the first output control sub-circuit and the first output sub-circuit is not limited thereto as long as the functions thereof can be realized.

Fig. 4 is another equivalent circuit diagram of the input circuit, the first output control sub-circuit and the first output sub-circuit of the scan driving control circuit according to at least one embodiment of the disclosure. As shown in fig. 4, the first input sub-circuit of the scan drive control circuit provided by the present exemplary embodiment includes: the first transistor T1. The first transistor T1 has a control electrode connected to the first clock signal terminal CK, a first electrode connected to the signal input terminal IN, and a second electrode connected to the fourth node N4.

As shown in fig. 4, the second input sub-circuit includes: a second transistor T2 and a third transistor T3. A control electrode of the second transistor T2 is connected to the fourth node N4, a first electrode is connected to the first clock signal terminal CK, and a second electrode is connected to the third node N3. A control electrode of the third transistor T3 is connected to the first clock signal terminal CK, a first electrode is connected to the first voltage terminal V1, and a second electrode is connected to the third node N3.

As shown in fig. 4, the first output sub-circuit includes: a tenth transistor T10. The tenth transistor T10 has a control electrode connected to the second node N2, a first electrode connected to the first voltage terminal V1, and a second electrode connected to the signal output terminal OUT.

As shown in fig. 4, the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, an eleventh transistor T11, a second capacitor C2, and a fourth capacitor C4. A control electrode of the fourth transistor T4 is connected to the second node N2, a first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and a second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5. A control electrode of the fifth transistor T5 is connected to the third node N3, and a first electrode thereof is connected to the first signal terminal SIG 1. A control electrode of the eleventh transistor T11 is connected to the first voltage terminal V1, a first electrode thereof is connected to the fourth node N4, and a second electrode thereof is connected to the second node N2. A first pole of the second capacitor C2 is connected to the second node N2, and a second pole of the second capacitor C2 is connected to the signal output terminal OUT. A first pole of the fourth capacitor C4 is connected to the control pole of the fourth transistor T4 and the control pole of the tenth transistor T10 (i.e., to the second node N2), and a second pole of the fourth capacitor C4 is connected to the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5.

In the present exemplary embodiment, the potential of the second node N2 may be kept stable when the tenth transistor T10 is turned on by the second capacitor C2 and the fourth capacitor C4 arranged in series, so that the first output sub-circuit provides a stable output. By providing the eleventh transistor T11, the influence of the second node N2 on the fourth node N4 may be isolated.

In the present exemplary embodiment, fig. 4 shows one exemplary structure of the input circuit, the first output control sub-circuit, and the first output sub-circuit. It is easily understood by those skilled in the art that the implementation of the input circuit, the first output control sub-circuit and the first output sub-circuit is not limited thereto as long as the functions thereof can be realized.

Fig. 5 is an equivalent circuit diagram of the second output control sub-circuit of the scan driving control circuit according to at least one embodiment of the disclosure. As shown in fig. 5, the second output control sub-circuit of the scan drive control circuit provided by the present exemplary embodiment includes: a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. A control electrode of the sixth transistor T6 is connected to the third node N3, a first electrode of the sixth transistor T6 is connected to the second signal terminal SIG2, and a second electrode of the sixth transistor T6 is connected to a second electrode of the seventh transistor T7. A control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and a first electrode thereof is connected to the first node N1. The first electrode of the first capacitor C1 is connected to the control electrode of the sixth transistor T6, and the second electrode is connected to the control electrode of the seventh transistor T7.

In some exemplary embodiments, the second signal terminal SIG2 may provide a low level signal, so that the potential of the first node N1 is kept stable when the transistor of the second output sub-circuit is turned on, so that the second output sub-circuit provides a stable output.

In the present exemplary embodiment, one exemplary structure of the second output control sub-circuit is shown in fig. 5. It is easily understood by those skilled in the art that the implementation of the second output control sub-circuit is not limited thereto as long as the function thereof can be implemented.

Fig. 6 is another equivalent circuit diagram of the second output control sub-circuit of the scan driving control circuit according to at least one embodiment of the disclosure. As shown in fig. 6, the second output control sub-circuit of the scan drive control circuit provided by the present exemplary embodiment includes: a sixth transistor T6, a seventh transistor T7, a twelfth transistor T12, and a first capacitor C1. A control electrode of the sixth transistor T6 is connected to the third node N3, a first electrode of the sixth transistor T6 is connected to the second signal terminal SIG2, and a second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. A control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and a first electrode thereof is connected to the first node N1. The first electrode of the first capacitor C1 is connected to the control electrode of the sixth transistor T6, and the second electrode is connected to the control electrode of the seventh transistor T7. A control electrode of the twelfth transistor T12 is connected to the first power source terminal V1, a first electrode thereof is connected to the fifth node N5, and a second electrode thereof is connected to the third node N3. The fifth node N5 is also connected to the first input sub-circuit and the first output control sub-circuit.

In some exemplary embodiments, the second signal terminal SIG2 may provide a low level signal, so that the potential of the first node N1 is kept stable when the transistor of the second output sub-circuit is turned on, so that the second output sub-circuit provides a stable output. In the present exemplary embodiment, by providing the twelfth transistor T12, the influence of the third node N3 on the fifth node N5 may be isolated.

In the present exemplary embodiment, another exemplary structure of the second output control sub-circuit is shown in fig. 6. It is easily understood by those skilled in the art that the implementation of the second output control sub-circuit is not limited thereto as long as the function thereof can be implemented.

Fig. 7 is an equivalent circuit diagram of a third output control sub-circuit and a second output sub-circuit of a scan driving control circuit according to at least one embodiment of the disclosure. As shown in fig. 7, the third output control sub-circuit of the scan drive control circuit provided by the present exemplary embodiment includes: an eighth transistor T8 and a third capacitor C3. A control electrode of the eighth transistor T8 is connected to the second node N2, a first electrode thereof is connected to the second voltage terminal V2, and a second electrode thereof is connected to the first node N1. The third capacitor C3 has a first pole connected to the first node N1 and a second pole connected to the second voltage terminal V2.

As shown in fig. 7, the second output sub-circuit includes: and a ninth transistor T9. A control electrode of the ninth transistor T9 is connected to the first node N1, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the signal output terminal OUT.

In the present exemplary embodiment, one exemplary structure of the third output control sub-circuit and the second output sub-circuit is shown in fig. 7. It is easily understood by those skilled in the art that the implementation of the third output control sub-circuit and the second output sub-circuit is not limited thereto as long as the functions thereof can be realized.

Fig. 8 is an equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure. As shown in fig. 8, the present exemplary embodiment provides a scan drive control circuit including: the first input sub-circuit, the second input sub-circuit, the first output control sub-circuit, the second output control sub-circuit, the third output control sub-circuit, the first output sub-circuit, and the second output sub-circuit. The first input sub-circuit includes a first transistor T1. The second input sub-circuit includes a second transistor T2 and a third transistor T3. The first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a second capacitor C2, and a fourth capacitor C4. The second output control sub-circuit includes: a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3. The first output sub-circuit includes a tenth transistor T10. The second output sub-circuit includes a ninth transistor T9. In the present exemplary embodiment, the first signal terminal SIG1 is connected to the second voltage terminal V2, and the second signal terminal SIG2 is connected to the first voltage terminal V1.

IN the present exemplary embodiment, the control electrode of the first transistor T1 is connected to the first clock signal terminal CK, the first electrode is connected to the signal input terminal IN, and the second electrode is connected to the second node N2. A control electrode of the second transistor T2 is connected to the second node N2, a first electrode is connected to the first clock signal terminal CK, and a second electrode is connected to the third node N3. A control electrode of the third transistor T3 is coupled to the first clock signal terminal CK, a first electrode thereof is coupled to the first voltage terminal V1, and a second electrode thereof is coupled to the third node N3. A control electrode of the fourth transistor T4 is connected to the second node N2, a first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and a second electrode of the fourth transistor T4 is connected to a second electrode of the fifth transistor T5. A control electrode of the fifth transistor T5 is connected to the third node N3, and a first electrode thereof is connected to the second voltage terminal V2. A control electrode of the sixth transistor T6 is connected to the third node N3, a first electrode of the sixth transistor T6 is connected to the first voltage terminal V1, and a second electrode of the sixth transistor T6 is connected to a first electrode of the seventh transistor T7. A control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and a second electrode is connected to the first node N1. The eighth transistor T8 has a control electrode connected to the second node N2, a first electrode connected to the second voltage terminal V2, and a second electrode connected to the first node N1. The ninth transistor T9 has a control electrode connected to the first node N1, a first electrode connected to the second voltage terminal V2, and a second electrode connected to the signal output terminal OUT. The tenth transistor T10 has a control electrode connected to the second node N2, a first electrode connected to the first voltage terminal V1, and a second electrode connected to the signal output terminal OUT. The first electrode of the first capacitor C1 is connected to the third node N3, and the second electrode is connected to the control electrode of the seventh transistor T7. The first pole of the second capacitor C2 is connected to the second node N2, and the second pole is connected to the signal output terminal OUT. The third capacitor C3 has a first pole connected to the first node N1 and a second pole connected to the second voltage terminal V2. A first pole of the fourth capacitor C4 is connected to the second node N2, and a second pole is connected to the second pole of the fifth transistor T5.

In the present exemplary embodiment, the first node N1, the second node N2, and the third node N3 are junctions representing relevant electrical connections in the circuit diagram. In other words, these nodes are equivalent nodes of the junction of the relevant electrical connections in the circuit diagram.

In some exemplary embodiments, the first to tenth transistors T1 to T10 in the scan driving control circuit may be all P-type thin film transistors, for example, Low Temperature Polysilicon (LTPS) thin film transistors. In addition, the thin film transistor with a bottom gate structure or the thin film transistor with a top gate structure may be selected in the embodiments of the present disclosure as long as a switching function can be achieved. The present embodiment is not limited to this.

The technical solution of the present embodiment is further explained by the working process of the scan driving control circuit. The operation of the first stage scan drive control circuit is described as an example, and the signal input terminal IN of the first stage scan drive control circuit is connected to the initial signal line STV. Fig. 9 is a timing diagram illustrating an operation of the scan driving control circuit shown in fig. 8. As shown IN fig. 8 and 9, the scan drive control circuit of the present exemplary embodiment includes 10 transistor units (e.g., the first to tenth transistors T1 to T10), 4 capacitor units (i.e., the first to fourth capacitors C1 to C4), 3 input terminals (i.e., the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB), 1 output terminal (i.e., the signal output terminal OUT), and 2 power supply terminals (i.e., the first and second voltage terminals V1 and V2). In some examples, the first voltage terminal V1 continuously provides a low level signal, for example, at a voltage of VGL; the second voltage terminal V2 continuously provides a high level signal, for example, the voltage is VGH.

The operation of the scan driving control circuit will be described below by taking the scan driving control circuit of this embodiment as an example to provide a scan signal or a reset signal to the N-type transistor of the pixel circuit. The operation of the scan drive control circuit provided in the present exemplary embodiment includes the following stages.

IN the first stage t11, the first clock signal terminal CK inputs a high level signal, the second clock signal terminal CB inputs a low level signal, and the signal input terminal IN inputs a low level signal.

The first clock signal terminal CK inputs a high level signal, the first transistor T1 and the third transistor T3 are turned off, the second node N2 maintains a low level of a previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on. The high level signal input from the first clock signal terminal CK is transmitted to the third node N3 through the turned-on second transistor T2, so that the fifth transistor T5 and the sixth transistor T6 are turned off. The low level signal inputted from the second clock signal terminal CB is transmitted to the second pole of the fourth capacitor C4 through the turned-on fourth transistor T4, so that the first pole of the fourth capacitor C4 (i.e., the second node N2) maintains a lower potential due to the capacitor holding function. The eighth transistor T8 is turned on so that the potential of the first node N1 is a high potential (e.g., VGH), and the ninth transistor T9 is turned off. The tenth transistor T10 is turned on so that the signal output terminal OUT outputs a low level signal provided from the first voltage terminal V1.

IN the second stage t12, the first clock signal terminal CK inputs a low level signal, the second clock signal terminal CB inputs a high level signal, and the signal input terminal IN inputs a high level signal.

The first clock signal terminal CK inputs a low level signal, the first transistor T1 and the third transistor T3 are turned on, and the turned-on first transistor T1 transmits a high level signal provided from the signal input terminal IN to the second node N2, so that the potential of the second node N2 is pulled up to VGH. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. The turned-on third transistor T3 transmits a low level signal input from the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on. The high level signal provided by the second voltage terminal V2 is transmitted to the second pole of the fourth capacitor C4 through the turned-on fifth transistor T5, and the first pole of the fourth capacitor (i.e., the second node N2) maintains a stable high voltage level under the action of the transition of the fourth capacitor C4. The second clock signal terminal CB inputs a high level signal, the seventh transistor T7 is turned off, the first node N1 is maintained at a high potential supplied from the second voltage terminal V2 by the storage of the third capacitor C3, and the ninth transistor T9 is turned off. Since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal output terminal OUT maintains the previous low level output.

IN the third stage t13, the first clock signal terminal CK inputs a high level signal, the second clock signal terminal CB inputs a low level signal, and the signal input terminal IN inputs a low level signal.

The first clock signal terminal CK inputs a high level signal, the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains a high potential of the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. The second clock signal terminal CB receives a low level signal, and the first electrode (i.e., the third node N3) of the first capacitor C1 transitions from the low level VGL of the previous stage to a lower level 2 VGL-VGH. The fifth transistor T5 and the sixth transistor T6 are turned on. The high level signal provided from the second voltage terminal V2 is transmitted to the second pole of the fourth capacitor C4 through the turned-on fifth transistor T5, so that the second node N2 maintains a stable high potential. The second clock signal terminal CB inputs a low level signal, the seventh transistor T7 is turned on, the low level signal input from the first voltage terminal V1 is transmitted to the first node N1 through the turned-on sixth transistor T6 and seventh transistor T7, the ninth transistor T9 is turned on, and the high level signal provided from the second voltage terminal V2 is output to the signal output terminal OUT.

IN the fourth period t14, the first clock signal terminal CK inputs a low level signal, the second clock signal terminal CB inputs a high level signal, and the signal input terminal IN inputs a low level signal.

The first clock signal terminal CK inputs a low level signal, the first transistor T1 and the third transistor T3 are turned on, and the turned-on first transistor T1 transmits the low level signal input from the signal input terminal IN to the second node N2, so that the potential of the second node N2 is pulled down to VGL. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on. The turned-on eighth transistor T8 transmits the high level signal provided from the second voltage terminal V2 to the first node N1, and the ninth transistor T9 is turned off. The turned-on tenth transistor T10 transmits the low level signal provided from the first voltage terminal V1 to the signal output terminal OUT. The turned-on second transistor T2 transmits the low level signal provided from the first clock signal terminal CK to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on. The second clock signal terminal CB inputs a high level signal and the seventh transistor T7 is turned off.

IN the fifth stage t15, the first clock signal terminal CK inputs a high level signal, the second clock signal terminal CB inputs a low level signal, and the signal input terminal IN inputs a low level signal.

The first clock signal terminal CK inputs a high level signal, and the first transistor T1 and the third transistor T3 are turned off. The second node N2 maintains the low potential of the previous node, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on. The turned-on fourth transistor T4 transmits the low level signal input from the second clock signal terminal CB to the second pole of the fourth capacitor C4, so that the potential of the first pole of the fourth capacitor C4 (i.e., the second node N2) becomes a lower potential than VGL. The turned-on second transistor T2 transmits the high level signal provided from the first clock signal terminal CK to the third node N3, so that the fifth transistor T5 and the sixth transistor T6 are turned off. The turned-on eighth transistor T8 transmits the high level signal provided by the second voltage terminal V2 to the first node N1, the potential of the first node N1 is VGH, and the ninth transistor T9 is turned off. The tenth transistor T10 is turned on to supply the low level signal supplied from the first voltage terminal V1 to the signal output terminal OUT.

After the fifth stage t15, the fourth stage t14 and the fifth stage t15 may be repeated until the signal input terminal IN inputs a high level signal, and then the process may be resumed from the second stage t 12.

As can be seen from the operation process of the scan driving control circuit, in the third stage t13, the signal output terminal OUT outputs a high level signal, and in the rest stages, the signal output terminal OUT outputs a low level signal.

In some exemplary embodiments, the first clock signal input from the first clock signal terminal CK and the second clock signal input from the second clock signal terminal CB are both pulse signals, and the pulse width of the first clock signal and the pulse width of the second clock signal may be substantially the same. The duty cycle of the first clock signal and the second clock signal may be greater than 1/2, and may be approximately 1/3, for example. In this embodiment, the duty ratio refers to a proportion of the high level duration in the entire pulse period within one pulse period (including the high level duration and the low level duration).

Fig. 10 is another operation timing diagram of the scan drive control circuit shown in fig. 8. Next, referring to fig. 8 and fig. 10, the operation of the scan drive control circuit will be described by taking the scan drive control circuit of the present embodiment as an example to provide the pixel circuit with the light emission control signal. The operation process of the scan drive control circuit provided by the present exemplary embodiment may include the following stages.

IN the first stage t21, the first clock signal terminal CK inputs a high level signal, the second clock signal terminal CB inputs a low level signal, and the signal input terminal IN inputs a low level signal.

The first clock signal terminal CK inputs a high level signal, the first transistor T1 and the third transistor T3 are turned off, the second node N2 maintains a low level of a previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on. The high level signal input from the first clock signal terminal CK is transmitted to the third node N3 through the turned-on second transistor T2, so that the fifth transistor T5 and the sixth transistor T6 are turned off. The low level signal inputted from the second clock signal terminal CB is transmitted to the second pole of the fourth capacitor C4 through the turned-on fourth transistor T4, so that the first pole of the fourth capacitor C4 (i.e., the second node N2) maintains a lower potential due to the capacitor holding function. The eighth transistor T8 is turned on so that the potential of the first node N1 is pulled up to VGH, and the ninth transistor T9 is turned off. The tenth transistor T10 is turned on so that the signal output terminal OUT outputs a low level signal provided from the first voltage terminal V1.

IN the second stage t22, the first clock signal terminal CK inputs a low level signal, the second clock signal terminal CB inputs a high level signal, and the signal input terminal IN inputs a high level signal.

The first clock signal terminal CK inputs a low level signal, and the first transistor T1 and the third transistor T3 are turned on. The turned-on first transistor T1 transmits the high level signal provided from the signal input terminal IN to the second node N2, so that the potential of the second node N2 is pulled up to VGH. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. The turned-on third transistor T3 transmits a low level signal input from the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on. The high level signal provided by the second voltage terminal V2 is transmitted to the second pole of the fourth capacitor C4 through the turned-on fifth transistor T5, and the first pole of the fourth capacitor (i.e., the second node N2) maintains a stable high level under the action of the transition of the fourth capacitor C4. The second clock signal terminal CB inputs a high level signal, the seventh transistor T7 is turned off, the first node N1 maintains the high potential VGH supplied from the second voltage terminal V2 by the storage of the third capacitor C3, and the ninth transistor T9 is turned off. Since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal output terminal OUT maintains the previous low level output.

IN the third stage t23, the first clock signal terminal CK inputs a high level signal, the second clock signal terminal CB inputs a low level signal, and the signal input terminal IN inputs a high level signal.

The first clock signal terminal CK inputs a high level signal, the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains a high potential of the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. The second clock signal terminal CB receives a low level signal, and the first electrode (i.e., the third node N3) of the first capacitor C1 transitions from the low level VGL of the previous stage to a lower level 2 VGL-VGH. The fifth transistor T5 and the sixth transistor T6 are turned on. The high level signal provided by the second voltage terminal V2 is transmitted to the second pole of the fourth capacitor C4 through the turned-on fifth transistor T5, so that the second node N2 maintains a stable high potential. The second clock signal terminal CB inputs a low level signal, the seventh transistor T7 is turned on, the low level signal input from the first voltage terminal V1 is transmitted to the first node N1 through the turned-on sixth transistor T6 and seventh transistor T7, the ninth transistor T9 is turned on, and the high level signal provided from the second voltage terminal V2 is provided to the signal output terminal OUT.

IN the fourth period t24, the first clock signal terminal CK inputs a low level signal, the second clock signal terminal CB inputs a high level signal, and the signal input terminal IN inputs a high level signal.

The first clock signal terminal CK inputs a low level signal, and the first transistor T1 and the third transistor T3 are turned on. The turned-on first transistor T1 transmits the high level signal inputted from the signal input terminal IN to the second node N2, and the potential of the second node N2 maintains the high voltage VGH of the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. The turned-on third transistor T3 transmits the low level signal provided from the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on. The turned-on fifth transistor T5 transmits the high-level signal provided by the second voltage terminal V2 to the second pole of the fourth capacitor C4, and the first pole of the fourth capacitor C4 (i.e., the second node N2) keeps a stable high potential under the action of the transition of the fourth capacitor C4. The second clock signal terminal CB inputs a high level signal, the seventh transistor T7 is turned off, the first node N1 is kept at a low level in the previous stage by the storage of the third capacitor C3, the ninth transistor T9 is turned on, and the signal output terminal OUT outputs a high level signal provided by the second voltage terminal V2.

IN the fifth stage t25, the first clock signal terminal CK inputs a high level signal, the second clock signal terminal CB inputs a low level signal, and the signal input terminal IN inputs a low level signal.

The first clock signal terminal CK inputs a high level signal, the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains a high potential of the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. The second clock signal terminal CB inputs a low level signal, the potential of the second pole of the first capacitor C1 changes from VGH in the previous stage to VGL, the potential of the first pole of the first capacitor C1 (i.e., the third node N3) changes from VGL in the previous stage to 2VGL-VGH which is lower due to the jump action of the first capacitor C1, and the fifth transistor T5 and the sixth transistor T6 are turned on. The turned-on fifth transistor T5 transmits the high level signal provided from the second voltage terminal V2 to the second pole of the fourth capacitor C4, so that the second node N2 maintains a stable high potential. The second clock signal terminal CB inputs a low level signal and the seventh transistor T7 is turned on. The turned-on sixth and seventh transistors T6 and T7 transmit a low level signal provided from the first voltage terminal V1 to the first node N1, the ninth transistor T9 is turned on, and the signal output terminal OUT outputs a high level signal provided from the second voltage terminal V2.

IN the sixth stage t26, the first clock signal terminal CK inputs a low level signal, the second clock signal terminal CB inputs a high level signal, and the signal input terminal IN inputs a low level signal.

The first clock signal terminal CK inputs a low level signal, and the first transistor T1 and the third transistor T3 are turned on. The turned-on first transistor T1 transmits the low level signal inputted from the signal input terminal IN to the second node N2, and the potential of the second node N2 is pulled down to VGL. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on. The turned-on eighth transistor T8 transmits the high level signal provided by the second voltage terminal V2 to the first node N1, and the ninth transistor T9 is turned off. The turned-on tenth transistor T10 transmits the low level signal provided from the first voltage terminal V1 to the signal output terminal OUT. The turned-on second transistor T2 transmits a low level signal provided from the first clock signal terminal CK to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on. The second clock signal terminal CB inputs a high level signal and the seventh transistor T7 is turned off.

IN the seventh stage t27, the first clock signal terminal CK inputs a high level signal, the second clock signal terminal CB inputs a low level signal, and the signal input terminal IN inputs a low level signal.

The first clock signal terminal CK inputs a high level signal, and the first transistor T1 and the third transistor T3 are turned off. The second node N2 maintains the low potential of the previous node, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on. The turned-on fourth transistor T4 transmits the low level signal inputted from the second clock signal terminal CB to the second pole of the fourth capacitor C4 so that the potential of the first pole of the fourth capacitor C4 (i.e., the second node N2) becomes a lower potential than VGL. The turned-on second transistor T2 transmits a high level signal provided from the first clock signal terminal CK to the third node N3, so that the fifth transistor T5 and the sixth transistor T6 are turned off. The turned-on eighth transistor T8 transmits the high level signal provided by the second voltage terminal V2 to the first node N1, the potential of the first node N1 is VGH, and the ninth transistor T9 is turned off. The tenth transistor T10 is turned on, and outputs a low level signal provided from the first voltage terminal V1 to the signal output terminal OUT.

After the seventh phase t27, the sixth phase t26 and the seventh phase t27 may be repeated until the signal input terminal OUT inputs a high level signal, and then the process may be resumed from the second phase t 22.

According to the operation process of the scan driving control circuit, in the third stage t23 to the fifth stage t25, the signal output terminal OUT can output a high level signal, and in the remaining stages, the signal output terminal OUT outputs a low level signal.

The scan drive control circuit provided by the present exemplary embodiment can keep the potential of the second node N2 stable when the tenth transistor T10 is turned on by the first output control sub-circuit to improve the output stability of the tenth transistor T10, and can keep the potential of the first node N1 stable when the ninth transistor T9 is turned on by the second output control sub-circuit to improve the output stability of the ninth transistor T9.

Fig. 11 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the disclosure. As shown in fig. 11, the present exemplary embodiment provides a scan drive control circuit including: the first input sub-circuit, the second input sub-circuit, the first output control sub-circuit, the second output control sub-circuit, the third output control sub-circuit, the first output sub-circuit and the second output sub-circuit. The first input sub-circuit includes a first transistor T1. The second input sub-circuit includes a second transistor T2 and a third transistor T3. The first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, an eleventh transistor T11, a second capacitor C2, and a fourth capacitor C4. The second output control sub-circuit includes: a twelfth transistor T12, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3. The first output sub-circuit includes: a tenth transistor T10. The second output sub-circuit includes a ninth transistor T9. In the present exemplary embodiment, the first signal terminal is connected to the second voltage terminal V2, and the second signal terminal is connected to the first voltage terminal V1.

IN the present exemplary embodiment, the control electrode of the first transistor T1 is connected to the first clock signal terminal CK, the first electrode is connected to the signal input terminal IN, and the second electrode is connected to the fourth node N4. A control electrode of the second transistor T2 is connected to the fourth node N4, a first electrode is connected to the first clock signal terminal CK, and a second electrode is connected to the third node N3. A control electrode of the third transistor T3 is connected to the first clock signal terminal CK, a first electrode is connected to the first voltage terminal V1, and a second electrode is connected to the fifth node N5. A control electrode of the fourth transistor T4 is connected to the second node N2, a first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and a second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5. A control electrode of the fifth transistor T5 is connected to the fifth node N5, and a first electrode thereof is connected to the second voltage terminal V2. A control electrode of the sixth transistor T6 is connected to the third node N3, a first electrode of the sixth transistor T6 is connected to the first voltage terminal V1, and a second electrode of the sixth transistor T6 is connected to a first electrode of the seventh transistor T7. A control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and a second electrode is connected to the first node N1. A control electrode of the eighth transistor T8 is connected to the second node N2, a first electrode thereof is connected to the second voltage terminal V2, and a second electrode thereof is connected to the first node N1. The ninth transistor T9 has a control electrode connected to the first node N1, a first electrode connected to the second voltage terminal V2, and a second electrode connected to the signal output terminal OUT. A control electrode of the tenth transistor T10 is connected to the second node N2, a first electrode thereof is connected to the first voltage terminal V1, and a second electrode thereof is connected to the signal output terminal OUT. A control electrode of the eleventh transistor T11 is connected to the first voltage terminal V1, a first electrode thereof is connected to the fourth node N4, and a second electrode thereof is connected to the second node N2. A control electrode of the twelfth transistor T12 is connected to the first voltage terminal V1, a first electrode thereof is connected to the fifth node N5, and a second electrode thereof is connected to the third node N3. The first electrode of the first capacitor C1 is connected to the third node N3, and the second electrode is connected to the control electrode of the seventh transistor T7. The first pole of the second capacitor C2 is connected to the second node N2, and the second pole is connected to the signal output terminal OUT. The third capacitor C3 has a first pole connected to the first node N1 and a second pole connected to the second voltage terminal V2. A first pole of the fourth capacitor C4 is connected to the second node N2, and a second pole is connected to the second pole of the fifth transistor T5.

In the present exemplary embodiment, the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 represent the junction points of the relevant electrical connections in the circuit diagram. In other words, these nodes are equivalent nodes of the junction of the relevant electrical connections in the circuit diagram.

In some exemplary embodiments, the first to twelfth transistors T1 to T12 in the scan driving control circuit may be all P-type thin film transistors, for example, Low Temperature Polysilicon (LTPS) thin film transistors. In addition, the thin film transistor of a bottom gate structure or the thin film transistor of a top gate structure may be selected as long as a switching function can be achieved. This embodiment is not limited to this.

In the scan drive control circuit provided in the present exemplary embodiment, the influence of the second node N2 on the fourth node N4 may be isolated by the eleventh transistor T11, and the influence of the third node N3 on the fifth node N5 may be isolated by the twelfth transistor T12.

The working process of the scan driving control circuit of this embodiment can refer to the description of the previous embodiments, and therefore, the description thereof is omitted.

Fig. 12 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the disclosure. As shown in fig. 12, the present exemplary embodiment provides a scan drive control circuit including: the first input sub-circuit, the second input sub-circuit, the first output control sub-circuit, the second output control sub-circuit, the third output control sub-circuit, the first output sub-circuit and the second output sub-circuit. The first input sub-circuit includes a first transistor T1. The second input sub-circuit includes a second transistor T2 and a third transistor T3. The first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, an eleventh transistor T11, a second capacitor C2, and a fourth capacitor C4. The second output control sub-circuit includes: a twelfth transistor T12, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3. The first output sub-circuit includes: a tenth transistor T10. The second output sub-circuit includes a ninth transistor T9. In the present exemplary embodiment, the first signal terminal is connected to the first clock signal terminal CK, and the second signal terminal is connected to the second clock signal terminal CB. That is, the second pole of the fifth transistor T5 is connected to the first clock signal terminal CK, and the first pole of the sixth transistor T6 is connected to the second clock signal terminal CB.

The circuit structure and the operation process of the scan driving control circuit of this embodiment can refer to the description of the foregoing embodiments, and therefore are not described herein again.

In other exemplary embodiments, the first signal terminal SIG1 of the scan driving control circuit may be connected to the first clock signal terminal CK, and the second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB; alternatively, the first signal terminal SIG1 may be connected to the second voltage terminal V2, and the second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB. However, the present embodiment is not limited to this.

The embodiment of the disclosure also provides a driving method of the display substrate. Fig. 13 is a flowchart illustrating a driving method of a display substrate according to an embodiment of the disclosure. As shown in fig. 13, the driving method of the display substrate provided in this embodiment is applied to the display substrate provided in the above embodiment. The driving method provided by the present embodiment may include the following steps.

Step S101, the input circuit transmits a signal of a signal input end to the output control circuit under the control of a first clock signal end, and transmits a signal of the first clock signal end or a first voltage end to the output control circuit;

step S102, the output control circuit stores the signal of the first signal end under the control of the input circuit, transmits the signal of the second signal end to the first node under the control of the input circuit and the second clock signal end, and the output circuit outputs the signal of the second voltage end to the signal output end under the control of the first node;

step S103, the output control circuit stores the signal of the second clock signal terminal under the control of the input circuit, transmits the signal of the second voltage terminal to the first node under the control of the second node, and the output circuit outputs the signal of the first voltage terminal to the signal output terminal under the control of the second node.

The driving method of the display substrate, the structure of the scan driving control circuit and the working process thereof provided by the present exemplary embodiment have been described in the above embodiments, and are not described herein again.

The embodiment of the disclosure also provides a gate driving circuit. Fig. 14 is a schematic diagram of a gate driving circuit according to at least one embodiment of the disclosure. As shown in fig. 14, the gate driving circuit provided by the present exemplary embodiment includes a plurality of cascaded scan driving control circuits GOA. The scan driving control circuit can be as described in the foregoing embodiments, and the implementation principle and the implementation effect type thereof are not described herein again.

IN the present exemplary embodiment, the signal input terminal IN of the first stage scan drive control circuit is connected to the initial signal line STV, and the signal input terminal of the (n + 1) th stage scan drive control circuit is connected to the signal output terminal of the nth stage scan drive control circuit, where n is an integer.

In some exemplary embodiments, the first clock signal terminal CK of the plurality of scan driving control circuits is connected to the first clock signal line CKL and configured to receive the first clock signal, and the second clock signal terminal CB is connected to the second clock signal line CBL and configured to receive the second clock signal. The first voltage terminal V1 is connected to a power line continuously supplying the low level signal VGL, and the second voltage terminal V2 is connected to a power line continuously supplying the high level signal VGH. However, the present embodiment is not limited to this.

Fig. 15 is a top view of a scan driving control circuit according to at least one embodiment of the present disclosure. Fig. 16 is a partial cross-sectional view taken along the direction P-P' in fig. 15. An equivalent circuit diagram of the scan drive control circuit shown in fig. 15 can be as shown in fig. 8. In the exemplary embodiment, the first signal terminal is connected to the second voltage terminal, the second signal terminal is connected to the first voltage terminal, the first clock signal terminal CK is connected to the first clock signal line CKL, and the second clock signal terminal CB is connected to the second clock signal line CBL. The second voltage terminal is connected to a first power line PL1 supplying a high level signal. A first voltage terminal to which the first output sub-circuit is connected to a third power supply line PL3 supplying a low level signal. A first voltage terminal at which the second input sub-circuit and the second output control sub-circuit are connected is connected to a second power supply line PL2 supplying a low level signal.

In the present exemplary embodiment, a description is given by taking as an example that the plurality of transistors in the scan drive control circuit are all P-type transistors and are low-temperature polysilicon thin film transistors. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 15, the first clock signal line CKL, the second clock signal line CBL, the preliminary signal line STV, the second power line PL2, the first power line PL1, and the third power line PL3 are sequentially arranged in the first direction X in a plane parallel to the display substrate. The first clock signal line CKL, the second clock signal line CBL, the preliminary signal line STV, the second power supply line PL2, the first power supply line PL1, and the third power supply line PL3 all extend in the second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

In some exemplary embodiments, as shown in fig. 15, the signal output terminal OUT is located at a side of the tenth transistor T10 distant from the ninth transistor T9 in the second direction Y in a plane parallel to the display substrate. The signal output terminals OUT may extend in the first direction X. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 15, the second input sub-circuit (including the second transistor T2 and the third transistor T3) is located between the initial signal line STV and the second power line PL2 in the first direction X in a plane parallel to the display substrate. The first output sub-circuit (including the tenth transistor T10) and the second output sub-circuit (including the ninth transistor T9) are located between the first power supply line PL1 and the third power supply line PL3 in the first direction X. The second transistor T2 and the third transistor T3 are adjacent in the second direction Y. The ninth transistor T9 and the tenth transistor T10 are adjacent in the second direction Y. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are located at a side of the second power supply line PL2 away from the second clock signal line CBL. The seventh transistor T7 is adjacent to the first capacitor C1, and the seventh transistor T7 is located between the first capacitor C1 and the first power line PL 1. The sixth transistor T6 is adjacent to the first power supply line PL1, and the sixth transistor T6 is located between the seventh transistor T7 and the first power supply line PL 1. The eighth transistor T8 is located between the first power supply line PL1 and the first transistor T1. The first capacitance C1 is located between the first power supply line PL1 and the second power supply line PL2, the orthographic projection of the first capacitance C1 on the substrate is located between the projections of the first power supply line PL1 and the second power supply line PL2 on the substrate, and the projection of the first capacitance C1 on the substrate does not overlap with the projections of the first power supply line PL1 and the second power supply line PL2 on the substrate. In this embodiment, "a and B are adjacent" means that there is no other transistor or capacitor between a and B.

In some exemplary embodiments, as shown in fig. 16, the non-display area of the display substrate may include, in a plane perpendicular to the display substrate: a substrate 30, a first semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate 30. Wherein the first insulating layer 31 is arranged between the first conductive layer and the first semiconductor layer. A second insulating layer 32 is disposed between the first and second conductive layers. The third insulating layer 33 is provided between the second conductive layer and the third conductive layer. In some examples, the first to third insulating layers 31 to 33 may be all inorganic insulating layers. However, this embodiment is not limited to this.

Fig. 17 is a top view of a scan driving control circuit after forming a first semiconductor layer according to at least one embodiment of the present disclosure. As shown in fig. 15 to 17, the first semiconductor layer of the non-display region at least includes: an active layer of a plurality of transistors of the scan drive control circuit. For example, the first semiconductor layer includes at least: an active layer 110 of the first transistor T1, an active layer 120 of the second transistor T2, an active layer 130 of the third transistor T3, an active layer 140 of the fourth transistor T4, an active layer 150 of the fifth transistor T5, an active layer 160 of the sixth transistor T6, an active layer 170 of the seventh transistor T7, an active layer 180 of the eighth transistor T8, an active layer of the ninth transistor T9, and an active layer of the tenth transistor T10.

In some example embodiments, as shown in fig. 17, the active layer 130 of the third transistor T3, the active layer 110 of the first transistor T1, the active layer 150 of the fifth transistor T5, the active layer 160 of the sixth transistor T6, the active layer 170 of the seventh transistor T7, the active layer 180 of the eighth transistor T8, the active layer of the ninth transistor T9, and the active layer of the tenth transistor T10 may extend in the second direction Y. The active layer 140 of the fourth transistor T4 may extend in the first direction X. In some examples, the extending direction of the active layer 140 of the fourth transistor T4 makes an angle greater than 85 ° and less than 95 ° with the extending direction of the active layer 110 of the first transistor T1. An angle between the extending direction of the active layer 140 of the fourth transistor T4 and the extending direction of the active layer 150 of the fifth transistor T5 is greater than 85 ° and less than 95 °. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 17, the active layer 130 of the third transistor T3 and the active layer 120 of the second transistor T2 are adjacent in the second direction Y. The active layer 110 of the first transistor T1 is located between the active layer 130 of the third transistor T3 and the active layer 180 of the eighth transistor T8 in the first direction X. The active layer 140 of the fourth transistor T4 is positioned between the active layer 110 of the first transistor T1 and the active layer 150 of the fifth transistor T5 in the second direction Y. The active layer 160 of the sixth transistor T6 is located at a side of the active layer 170 of the seventh transistor T7 away from the active layer 150 of the fifth transistor T5 in the first direction X. An active layer of the ninth transistor T9 and an active layer of the tenth transistor T10 are sequentially arranged in the second direction Y. The active layer of the ninth transistor T9 is positioned on a side of the active layer 180 of the eighth transistor T8 away from the active layer 110 of the first transistor T1 in the first direction X, and the active layer of the tenth transistor T10 is positioned on a side of the active layer 160 of the sixth transistor T6 away from the active layer 170 of the seventh transistor T7 in the first direction X.

In some example embodiments, as shown in fig. 17, the active layer of the ninth transistor T9 includes a first partition 190-1 and a second partition 190-2; the active layer of the tenth transistor T10 includes a third partition 200-1 and a fourth partition 200-2. Among them, the first partition 190-1 of the active layer of the ninth transistor T9 and the third partition 200-1 of the active layer of the tenth transistor T10 may be a unitary structure, for example, may be rectangular. The second partition 190-2 of the active layer of the ninth transistor T9 and the fourth partition 200-2 of the active layer of the tenth transistor T10 may be a unitary structure, for example, may be rectangular. In the present exemplary embodiment, by partitioning the active layers of the ninth transistor T9 and the tenth transistor T10, a better heat dissipation effect may be achieved, or overheating may be prevented. However, the present embodiment is not limited to the number of partitions of the active layer of the ninth transistor T9 and the tenth transistor T10 and the shape of at least one partition.

In some example embodiments, as shown in fig. 17, the orthographic projection of the active layer 120 of the second transistor T2 on the base substrate may be U-shaped. The orthographic projection of the active layer 110 of the first transistor T1, the active layer 130 of the third transistor T3, the active layer 140 of the fourth transistor T4, the active layer 150 of the fifth transistor T5 and the active layer 160 of the sixth transistor T6 on the substrate may be a dumbbell type. The active layer 170 of the seventh transistor T7 and the active layer 180 of the eighth transistor T8 may be a unitary structure. However, this embodiment is not limited to this.

In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polysilicon. The active layer may include at least one channel region and a plurality of doped regions. The channel region may be undoped with impurities and have semiconductor characteristics. The plurality of doped regions may be on both sides of the channel region and doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor.

In some exemplary embodiments, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. For example, the source electrode of the first transistor T1 may correspond to the first impurity-doped region 110b doped with impurities at the periphery of the channel region 110a of the active layer 110, and the drain electrode of the first transistor T1 may correspond to the second impurity-doped region 110c doped with impurities at the periphery of the channel region 110a of the active layer 110. In addition, a portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.

In some exemplary embodiments, the transistor's output capability is related to the width-to-length ratio of the transistor's channel region, with the greater of the width-to-length ratio of the channel region for a transistor with greater output capability. As shown in fig. 17, the width of the channel region 140a of the active layer 140 of the fourth transistor T4 (i.e., the length of the channel region 140a in the second direction Y) is W _T4 The width of the channel region 150a of the active layer 150 of the fifth transistor T5 (i.e., the length of the channel region 150a in the first direction X) is W _T5 . The width of the channel region 150a of the active layer 150 of the fifth transistor T5 and the channel region 1 of the active layer 140 of the fourth transistor T440a satisfies the following: 2W _T4 <W _T5 。

In the disclosed embodiments, the "width" of a denotes the characteristic dimension of a perpendicular to the direction of extension.

Fig. 18 is a top view of a scan driving control circuit after a first conductive layer is formed according to at least one embodiment of the disclosure. As shown in fig. 15 to 18, the first conductive layer of the non-display area includes at least: the scanning driving control circuit comprises a plurality of control electrodes of transistors and a plurality of first electrodes of capacitors. For example, the first conductive layer may include: a control electrode 113 of the first transistor T1, a control electrode 123 of the second transistor T2, a control electrode 133 of the third transistor T3, a control electrode 143 of the fourth transistor T4, a control electrode 153 of the fifth transistor T5, a control electrode 163 of the sixth transistor T6, a control electrode 173 of the seventh transistor T7, a control electrode 183 of the eighth transistor T8,

control electrodes

193a and 193b of the ninth transistor T9, a control electrode 203 of the tenth transistor T10, a first electrode C1-1 of the first capacitor C1, a first electrode C2-1 of the second capacitor C2, a first electrode C3-1 of the third capacitor C3, and a first electrode C4-1 of the fourth capacitor C4.

In some exemplary embodiments, as shown in fig. 18, the control electrode 133 of the third transistor T3 and the control electrode 113 of the first transistor T1 may be a unitary structure. The control electrode 123 of the second transistor T2, the control electrode 203 of the tenth transistor T10, and the first electrode C2-1 of the second capacitor C2 may be an integral structure. The gate 153 of the fifth transistor T5, the gate 163 of the sixth transistor T6, and the first electrode C1-1 of the first capacitor C1 may be a unitary structure. The gate 183 of the eighth transistor T8, the gate 143 of the fourth transistor T4, and the first electrode C4-1 of the fourth capacitor C4 may be a unitary structure. The

control electrodes

193a and 193b of the ninth transistor T9 and the first electrode C3-1 of the third capacitor C3 may be a unitary structure. However, this embodiment is not limited to this.

In some example embodiments, the ninth transistor T9 may be a double gate transistor to prevent and reduce the occurrence of leakage current. However, the present embodiment is not limited to this.

Fig. 19 is a top view of a scan driving control circuit after forming a second conductive layer according to at least one embodiment of the present disclosure. As shown in fig. 15 to 19, the second conductive layer of the non-display area includes at least: a second pole of the plurality of capacitors of the scan drive control circuit, a signal input terminal, and a signal input terminal. For example, the second conductive layer may include: a second pole C1-2 of the first capacitor C1, a second pole C2-2 of the second capacitor C2, a second pole C3-2 of the third capacitor C3, a second pole C4-2 of the fourth capacitor C4, a signal input terminal IN and a signal output terminal OUT. The second pole C2-2 of the second capacitor C2 and the signal output terminal OUT may be an integral structure. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 19, there is an overlap between the projection of the second pole C1-2 of the first capacitor C1 on the substrate base plate and the projection of the first pole C1-1 on the substrate base plate. The projection of the second pole C2-2 of the second capacitor C2 on the substrate base plate overlaps with the projection of the first pole C2-1 on the substrate base plate. The projection of the second pole C3-2 of the third capacitor C3 on the substrate has overlap with the projection of the first pole C3-1 on the substrate. The projection of the second pole C4-2 of the fourth capacitor C4 on the substrate base plate overlaps with the projection of the first pole C4-1 on the substrate base plate.

Fig. 20 is a top view of a scan driving control circuit after forming a third insulating layer according to at least one embodiment of the present disclosure. As shown in fig. 15 to 20, a plurality of via holes are formed on the third insulating layer 33 of the non-display region. For example, the plurality of vias may include: the first via holes F1 to F25, the second via holes K1 to K10, and the third via holes D1 to D5. The third insulating layer 33, the second insulating layer 32, and the first insulating layer 31 in the plurality of first vias F1 through F25 are etched away, exposing the surface of the first semiconductor layer. The third insulating layer 33 and the second insulating layer 32 within the plurality of second vias K1 through K10 are etched away, exposing the surface of the first conductive layer. The third insulating layer 33 in the plurality of third vias D1 to D5 is etched away, exposing the surface of the second conductive layer.

Fig. 21 is a top view of a scan driving control circuit after a third conductive layer is formed according to at least one embodiment of the present disclosure. As shown in fig. 15 to 21, the third conductive layer of the non-display area includes at least: first and second poles of a plurality of transistors of a scan drive control circuit, a plurality of clock signal lines, and a plurality of power supply lines. For example, the third conductive layer may include: first and second poles of the first to tenth transistors T1 to T10, a first clock signal line CKL, a second clock signal line CBL, an initial signal line STV, a first power line PL1, a second power line PL2, a third power line PL3, a first connection electrode 211, and a second connection electrode 212.

In some exemplary embodiments, as shown in fig. 21, the first pole 131 of the third transistor T3, the first pole 161 of the sixth transistor T6, and the second power line PL2 may be of a unitary structure. The second pole 121 of the second transistor T2 and the second pole 132 of the third transistor T3 may be a unitary structure. The second pole 142 of the fourth transistor T4 and the second pole 152 of the fifth transistor T5 may be a unitary structure. The first electrode 151 of the fifth transistor T5, the first electrode 181 of the eighth transistor T8, the first electrode 191 of the ninth transistor T9, and the first power line PL1 may be integrally configured. The second pole 162 of the sixth transistor T6 and the second pole 172 of the seventh transistor T7 may be a unitary structure. The second pole 192 of the ninth transistor T9 and the second pole 202 of the tenth transistor T10 may be a unitary structure. The first electrode 201 of the tenth transistor T10 and the third power line PL3 may be integrally configured.

In some exemplary embodiments, as shown in fig. 21, the first connection electrode 211 is connected to the first pole C2-1 of the second capacitor C2 through the second via K9, connected to the first pole C4-1 of the fourth capacitor C4 through the second via K7, connected to the second doping region 110C of the active layer 110 of the first transistor T1 through the first via F6, and connected to the control pole 143 of the fourth transistor T4 through the second via K6. The projection of the first connection electrode 211 on the substrate base is located between the projections of the first power supply line PL1 and the second power supply line PL2 on the substrate base. The second connection electrode 212 is connected to the second pole C1-2 of the first capacitor C1 through the third via D3 and is also connected to the control pole 173 of the seventh transistor T7 through the second via K5. The first power line PL1 is connected to the second pole C3-2 of the third capacitor C3 through a plurality of (e.g., three) third vias D4 arranged in a vertical row. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 15 to 21, the firstThe transistor T1 includes: an active layer 110, a control electrode 113, a first electrode 111, and a second electrode 112. The active layer 110 of the first transistor T1 includes: a channel region 110a, a first doped region 110b, and a second doped region 110 c. The active layer 110 of the first transistor T1 is adjacent to the second power supply line PL 2. A distance L2 between a side of the channel region 110a of the active layer 110 of the first transistor T1 close to the second power line PL2 and a side of the second power line PL2 far from the first transistor T1 satisfies: l2 is more than or equal to 0 and less than or equal to 4W _PL2 (ii) a Wherein, W _PL2 Is the width of the second power supply line PL2 (i.e., the length X3 of the second power supply line PL2 in the first direction X). The first pole 111 of the first transistor T1 is connected to the first doped region 110b of the active layer 110 of the first transistor T1 through the first via F5 and also connected to the signal input terminal IN through the third via D1. The control electrode 113 of the first transistor T1 and the control electrode 133 of the third transistor T3 are integrated, and the first clock signal line CKL is connected to the control electrode 113 of the first transistor T1 through two second vias K1 arranged in a vertical row, so that the control electrode 113 of the first transistor T1 receives the first clock signal.

In the present disclosure, "arranged side by side" may mean arranged in order along the first direction X, and "arranged vertically" may mean arranged in order along the second direction Y.

In some exemplary embodiments, as shown in fig. 15 to 21, the second transistor T2 includes: an active layer 120, a control electrode 123, a first electrode 121, and a second electrode 122. The active layer 120 of the second transistor T2 includes: a channel region 120a, a first doped region 120b, and a second doped region 120 c. The control electrode 123 of the second transistor T2, the first electrode C2-1 of the second capacitor C2, and the control electrode 203 of the tenth transistor T10 are integrated. The first electrode 121 of the second transistor T2 is connected to the first doped region 120b of the active layer 120 of the second transistor T2 through the first via F4, and is also connected to the control electrode 113 of the first transistor T1 through the second via K2, so as to be electrically connected to the first clock signal line CKL. The second pole 122 of the second transistor T2 and the second pole 132 of the third transistor T3 are of a unitary structure. The second pole 122 of the second transistor T2 is connected to the second doped region 120c of the active layer 120 of the second transistor T2 through a first via F3 and is also connected to the control pole 153 of the fifth transistor T5 through a second via K8.

In some examples, the second power line PL2 is located on a side of the second transistor T2 away from the first clock signal line CKL. The active layer 120 of the second transistor T2 is adjacent to the second power line PL 2. A distance L4 between a side of the channel region 120a of the active layer 120 of the second transistor T2 close to the second power line PL2 and a side of the second power line PL2 far from the second transistor T2 satisfies: l4 is more than or equal to 0 and less than or equal to 3W _PL2 (ii) a Wherein, W _PL2 Is the width of second power supply line PL 2.

In some exemplary embodiments, as shown in fig. 15 to 21, the third transistor T3 includes: an active layer 130, a control electrode 133, a first electrode 131, and a second electrode 132. The active layer 130 of the third transistor T3 includes: a channel region 130a, a first doped region 130b, and a second doped region 130 c. The first electrode 131 of the third transistor T3 is integrated with the second power supply line PL 2. The first pole 131 of the third transistor T3 is connected to the first doped region 130b of the active layer 130 of the third transistor T3 through a first via F1. The second pole 132 of the third transistor T3 is connected to the second doped region 130c of the active layer 130 of the third transistor T3 through the first via F2. In some examples, the second power supply line PL2 is located on a side of the third transistor T3 away from the initial signal line STV. A distance L3 between a side of the channel region 130a of the active layer 130 of the third transistor T3 close to the second power supply line PL2 and a side of the second power supply line PL2 far from the third transistor T3 satisfies: l3 is more than or equal to 0 and less than or equal to 4W _PL2 (ii) a Wherein, W _PL2 Is the width of second power supply line PL 2.

In some exemplary embodiments, as shown in fig. 15 to 21, the fourth transistor T4 includes: an active layer 140, a control electrode 143, a first electrode 141, and a second electrode 142. The active layer 140 of the fourth transistor T4 includes: a channel region 140a, a first doped region 140b, and a second doped region 140 c. The control electrode 143 of the fourth transistor T4 and the first electrode C4-1 of the fourth capacitor C4 are of a unitary structure. The first electrode 141 of the fourth transistor T4 is connected to the first doped region 140b of the active layer 140 of the fourth transistor T4 through the first via F7, and is also connected to the control electrode 173 of the seventh transistor T7 through the second via K4. The second pole 142 of the fourth transistor T4 and the second pole 152 of the fifth transistor T5 are of a unitary structure. The second pole 142 of the fourth transistor T4 is connected to the second doped region 140C of the active layer 140 of the fourth transistor T4 through the first via F8, and is also connected to the second pole C4-2 of the fourth capacitor C4 through the third via D2.

In some example embodiments, as shown in fig. 15 to 21, the fifth transistor T5 includes: an active layer 150, a control electrode 153, a first electrode 151, and a second electrode 152. The active layer 150 of the fifth transistor T5 includes: a channel region 150a, a first doped region 150b, and a second doped region 150 c. The gate 153 of the fifth transistor T5 and the gate 163 of the sixth transistor T6 are integrally formed. The first electrode 151 of the fifth transistor T5 is integrated with the first power supply line PL 1. The first pole 151 of the fifth transistor T5 is connected with the first doped region 150b of the active layer 150 of the fifth transistor T5 through a first via F10. The second pole 152 of the fifth transistor T5 is connected with the second doped region 150c of the active layer 150 of the fifth transistor T5 through the first via F9.

In some exemplary embodiments, as shown in fig. 15 to 21, the sixth transistor T6 includes: an active layer 160, a control electrode 163, a first electrode 161, and a second electrode 162. The active layer 160 of the sixth transistor T6 includes: a channel region 160a, a first doped region 160b, and a second doped region 160 c. The first electrode 161 of the sixth transistor T6 is integrated with the second power line PL 2. The first pole 161 of the sixth transistor T6 is connected to the first doped region 160b of the active layer 160 of the sixth transistor T6 through a first via F14. The second pole 162 of the sixth transistor T6 and the second pole 172 of the seventh transistor T7 are of a unitary structure. The second pole 162 of the sixth transistor T6 is connected with the second doped region 160c of the active layer 160 of the sixth transistor T6 through the first via F15.

In some exemplary embodiments, as shown in fig. 15 to 21, the seventh transistor T7 includes: an active layer 170, a control electrode 173, a first electrode 171, and a second electrode 172. The active layer 170 of the seventh transistor T7 and the active layer 180 of the eighth transistor T8 are of an integral structure. The active layer 170 of the seventh transistor T7 includes: a channel region 170a, a first doped region 170b, and a second doped region 170 c. The first doping region 170b of the active layer 170 of the seventh transistor T7 and the second doping region 180c of the active layer 180 of the eighth transistor T8 are connected. The first pole 171 of the seventh transistor T7 is connected to the first doped region 170b of the active layer 170 of the seventh transistor T7 through a first via F12, and is also connected to the first pole C3-1 of the third capacitor C3 through a second via K10. The second pole 172 of the seventh transistor T7 is connected to the second doped region 170c of the active layer 170 of the seventh transistor T7 through a first via F13. The second clock signal line CBL is connected to the gate 173 of the seventh transistor T7 through two second vias K3 arranged in a vertical row.

In some exemplary embodiments, as shown in fig. 15 to 21, the eighth transistor T8 includes: an active layer 180, a control electrode 183, and a first electrode 181. The active layer 180 of the eighth transistor T8 includes: a channel region 180a, a first doped region 180b, and a second doped region 180 c. The control electrode 183 of the eighth transistor T8 and the first electrode C4-1 of the fourth capacitor C4 are integrated. The first electrode 181 of the eighth transistor T8 is integrated with the first power line PL 1. The first pole 181 of the eighth transistor T8 is connected to the first doped region 180b of the active layer 180 of the eighth transistor T8 through a first via F11.

In some example embodiments, as shown in fig. 15 to 21, the ninth transistor T9 includes: an active layer,

control electrodes

193a and 193b, a first electrode 191, and a second electrode 192. The active layer of the ninth transistor T9 includes a first partition 190-1 and a second partition 190-2. The first partition 190-1 of the ninth transistor T9 includes: channel regions 190-1a1 and 190-1a2, first doped region 190-1b, second doped region 190-1c, and third doped region 190-1 d. The second partition 190-2 of the ninth transistor T9 includes: channel regions 190-2a1 and 190-2a2, first doped region 190-2b, second doped region 190-2c, and third doped region 190-2 d. The first electrode 191 of the ninth transistor T9 and the first power supply line PL1 are integrally configured. The first pole 191 of the ninth transistor T9 is connected to the first doped region 190-1b of the first partition 190-1 of the ninth transistor T9 through a plurality of (e.g., three) first vias F18 disposed side by side, and is also connected to the first doped region 190-2b of the second partition 190-2 of the ninth transistor T9 through a plurality of (e.g., three) first vias F19 disposed side by side. The second pole 192 of the ninth transistor T9 and the second pole 202 of the tenth transistor T10 are of a unitary structure. The second pole 192 of the ninth transistor T9 is connected to the second doped region 190-1c of the first partition 190-1 of the ninth transistor T9 through a plurality of (e.g., three) first vias F16 disposed side by side, is also connected to the second doped region 190-2c of the second partition 190-2 of the ninth transistor T9 through a plurality of (e.g., three) first vias F17 disposed side by side, is also connected to the third doped region 190-1d of the first partition 190-1 of the ninth transistor T9 through a plurality of (e.g., three) first vias F20 disposed side by side, and is also connected to the third doped region 190-2d of the second partition 190-2 of the ninth transistor T9 through a plurality of (e.g., three) first vias F21 disposed side by side.

In some exemplary embodiments, as shown in fig. 15 to 21, the tenth transistor T10 includes: an active layer, a control electrode 203, a first electrode 201, and a second electrode 202. The active layer of the tenth transistor T10 includes: a third partition 200-1 and a fourth analysis 200-2. The third section 200-1 of the tenth transistor T10 includes: channel regions 200-1a1 and 200-1a2, first doped region 200-1b, second doped region 200-1c, and third doped region 200-1 d. The fourth section 200-2 of the tenth transistor T10 includes: a channel region 200-2a, a first doped region 200-2b, and a second doped region 200-2 c. The third partition 200-1 of the tenth transistor T10 and the first partition 190-1 of the ninth transistor T9 are of a unitary structure, and the second doped region 200-1c of the third partition 200-1 is connected to the third doped region 190-1d of the first partition 190-1 of the ninth transistor. The fourth partition 200-2 of the tenth transistor T10 and the second partition 190-2 of the ninth transistor T9 are of an integral structure, and the second doped region 200-2c of the fourth partition 200-2 is connected to the third doped region 190-2d of the second partition 190-2 of the ninth transistor T9. The first electrode 201 of the tenth transistor T10 is integrated with the third power supply line PL 3. The first pole 201 of the tenth transistor T10 is connected to the first doped region 200-1b of the third partition 200-1 of the tenth transistor T10 through a plurality of (e.g., three) first vias F22 disposed side by side, and is also connected to the first doped region 200-2b of the fourth partition 200-2 of the tenth transistor T10 through a plurality of (e.g., three) first vias F23 disposed side by side. The second pole 202 of the tenth transistor T10 is connected to the third doped region 200-1d of the third partition 200-1 of the tenth transistor T10 through a plurality of (e.g., three) first vias F24 disposed side by side, and is also connected to the second doped region 200-2c of the fourth partition 200-2 of the tenth transistor T10 through a plurality of (e.g., three) first vias F25 disposed side by side. The second pole 202 of the tenth transistor T10 is also connected to the signal output terminal OUT through two third vias D5 arranged side by side.

In some exemplary embodiments, the output control circuit of the scan driving control circuit includes: the first node controls the capacitance and the second node controls the capacitance. The first node control capacitance may be configured to control a potential of the first node N1, and the second node control capacitance may be configured to control a potential of the second node N2. The first node control capacitance includes a first capacitance C1 and a third capacitance C3. The second node control capacitance includes a second capacitance C2 and a fourth capacitance C4. In the present exemplary embodiment, by the series design of the second capacitor C2 and the fourth capacitor C4, the potential of the second node N2 can be more stabilized, so that the tenth transistor T10 realizes stable output.

In some exemplary embodiments, the capacitance generally functions to stabilize the potential of the node, and the area of the capacitance is related to the range in which the potential of the node controlled by the capacitance needs to be maintained. In order to realize a narrow frame, capacitors need to be reasonably arranged in a smaller space to realize the functions of the capacitor. According to the display substrate provided by the embodiment, by setting the ratio of the width (for example, the length along the first direction) of the capacitor to the width of the scan driving control circuit to meet a certain condition, the performance of the scan driving control circuit can be ensured or even optimized on the premise of efficiently utilizing the space.

In some exemplary embodiments, the first node control capacitance, the second node control capacitance, and the scan drive control circuit have a length in the first direction that satisfies:

wherein L is _C1k Controlling the length of the capacitor in a first direction, L, for a first node _C2k Controlling the length of the capacitor in the first direction, L, for the second node _Y The length of the control circuit in the first direction is scanned.

In some exemplary embodiments, the scan driving control circuitLength L of road in first direction _Y The distance between the side of the clock signal line or the start signal line far away from the display area and the side of the power supply line close to the display area. When the side far away from the display area is provided with the clock signal line and the initial signal line, the routing far away from the side of the display area is taken as the standard. When one side close to the display area has the power line and the other wires (for example, the wires extending from the signal output end to the display area), the wires close to one side of the display area are taken as the reference. In some examples, as shown in fig. 15, the length L of the scan drive control circuit in the first direction X _Y Is the distance between the side of the first clock signal line CKL away from the display area and the side of the third power line PL3 close to the display area.

In some exemplary embodiments, the first node controls a length L of the capacitance in the first direction _C1k May be the greater of the length of the first capacitance C1 in the first direction and the length of the third capacitance C3 in the first direction. The second node controls the length L of the capacitor in the first direction _C2k May be the greater of the length of the second capacitance C2 in the first direction and the length of the fourth capacitance C4 in the first direction. For an irregularly shaped capacitor, the length of the capacitor in the first direction may be a maximum of the length of the capacitor in the first direction.

In some exemplary embodiments, the first capacitor, the third capacitor, the second node control capacitor, and the scan drive control circuit have a length in the first direction that satisfies:

wherein L is _C1 Is the length of the first capacitor in the first direction, L _C3 Is the length of the third capacitor in the first direction, L _C2k Controlling the length of the capacitor in the first direction, L, for the second node _Y To scanA length of the drive control circuit in the first direction.

In some exemplary embodiments, the first capacitance and the length of the scan driving control circuit in the first direction satisfy:

the length of the second node control capacitor and the scanning drive control circuit in the first direction satisfies the following conditions:

in some of the exemplary embodiments, the first and second electrodes are,

is one of the following: 0.09, 0.10, 0.14;

is one of the following: 0.22, 0.35, 0.48;

is one of the following: 0.07, 0.06, 0.05.

In some of the exemplary embodiments, the first and second electrodes are,

in some of the exemplary embodiments, the first and second electrodes are,

in some of the exemplary embodiments, the first and second electrodes are,

further, in order to improve space utilization, the capacitor may overlap with a projection of the power line or the clock signal line on the substrate base plate.

In some exemplary embodiments, the third capacitor overlaps with a projection of the first power line on the substrate base plate, and an overlapping area satisfies:

wherein S is _C3 Is the projected area of the third capacitor on the substrate, S _C3-1 Is the overlap area of the projection of the third capacitor and the first power line on the substrate _C2 Is the projection area of the second capacitor on the substrate base plate.

In some exemplary embodiments, the second node control capacitor overlaps with a projection of the first power line on the substrate, and an overlapping area satisfies:

wherein S is _C2k-1 An overlapping area of the second node control capacitor and a projection of the first power line on the substrate base plate is defined, X2 is a length of the first power line in a first direction, and L5 is a length of an overlapping region of one of the capacitors of the second node control capacitor and the projection of the first power line on the substrate base plate in a second direction. In some exemplary embodiments, the projected area of the second node control capacitance may be a sum of the projected area of the second capacitance and the projected area of the fourth capacitance.

In some exemplary embodiments, as shown in fig. 15, L5' is the length in the second direction Y of the overlapping region of the second capacitance C2 and the projection of the first power supply line PL1 on the substrate base plate. L5 ″ is the length in the second direction Y of the overlapping region of the fourth capacitance C4 and the projection of the first power supply line PL1 on the substrate base plate. A length L5 of an overlapping region of one of the second node control capacitances and a projection of the first power supply line on the substrate base plate in the second direction may be L5' or L5 ″.

In some exemplary embodiments, the second node control capacitance overlaps with a projection of the second power line on the substrate base plate, and an overlapping area satisfies:

wherein S is _C2k-2 An overlapping area of the second node control capacitance and a projection of the second power supply line on the substrate is defined as X3, a length of the second power supply line in the first direction is defined as L6, and a length of an overlapping region of one of the capacitances of the second node control capacitance and the projection of the second power supply line on the substrate in the second direction is defined as L6.

In some exemplary embodiments, as shown in fig. 15, L6' is the length in the second direction Y of the overlapping region of the second capacitance C2 and the projection of the second power supply line PL2 on the substrate base plate. L6 ″ is the length in the second direction Y of the overlapping region of the fourth capacitance C4 and the projection of the second power supply line PL2 on the substrate base plate. A length L6 of an overlapping region of one of the second node control capacitances and a projection of the second power supply line on the substrate base plate in the second direction may be L6' or L6 ″.

In some exemplary embodiments, as shown in fig. 15, a distance L7 between the center of the first capacitor C1 in the first direction X and a side of the first power line PL1 away from the first capacitor C1 in the first direction X is greater than a distance L8 between the center of the first capacitor C1 in the first direction X and a side of the second power line PL2 close to the first capacitor C1 in the first direction X, and L7 ≧ 2 × L8.

In some example embodiments, as shown in fig. 15, a distance L9 between a side of the active layer 180 of the eighth transistor T8 adjacent to the third capacitor C3 and a side of the third capacitor C3 adjacent to the eighth transistor T8 is fullFoot: w _CLK <L9≤W _PL1 (ii) a Wherein, W _CLK Is the width of the clock signal line, W _PL1 Is the width of the first power line. In some examples, W _CLK May be the width of the first clock signal line CKL or may be the width of the second clock signal line CBL. Width W of first power supply line PL1 _PL1 Namely, the length X2 of the first power supply line PL1 in the first direction X. For an irregularly shaped capacitor, the sides of the capacitor are the edgemost sides. For example, the L9 may be a distance between a side of the active layer 180 of the eighth transistor T8 near the third capacitor C3 and a side of the third capacitor C3 closest to the eighth transistor T8.

In some exemplary embodiments, the capacitance values of the first capacitance, the third capacitance, and the second node control capacitance satisfy:

C ₁ ＜C ₃ ＜C _2k ；

wherein, C ₁ Is the capacitance value of the first capacitor, C ₃ Is the capacitance value of the third capacitor, C _2k The capacitance value of the capacitor is controlled for the second node. In some examples, the capacitance value of the second node control capacitance may be the sum of the capacitance values of the second capacitance C2 and the fourth capacitance C4.

Fig. 22 is a top view of a cascaded scan driving control circuit according to at least one embodiment of the present disclosure. Fig. 23 is a schematic view of the first conductive layer shown in fig. 22. In some exemplary embodiments, as shown in fig. 22 and 23, the first pole C2-1 of the second capacitor C2 of the nth stage scan drive control circuit and the first pole C4-1 of the fourth capacitor C4 of the n +1 th stage scan drive control circuit may be a unitary structure. According to the exemplary embodiment, the stability of the second node can be improved while the process is simplified.

IN some exemplary embodiments, as shown IN fig. 22, the signal output terminal OUT of the nth stage scan drive control circuit and the input terminal IN of the (n + 1) th stage scan drive control circuit may be an integral structure.

For the rest of the structure of the scan driving control circuit of this embodiment, reference may be made to the description of the foregoing embodiments, and therefore, the description thereof is omitted here.

Fig. 24 is another top view of a scan driving control circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 24, the signal output terminal OUT is located at a side of the ninth transistor T9 and the tenth transistor T10 away from the first power supply line PL 1. The signal output terminal OUT and the second pole of the second capacitor C2 may be a unitary structure. The signal output terminal OUT may have three projections projecting in the first direction X to a side close to the first power supply line PL 1. The second pole 192 of the ninth transistor T9 may be connected to the first protrusion of the signal output terminal OUT through the third via D6, and may also be connected to the second protrusion of the signal output terminal OUT through the third via D7, and the second pole 202 of the tenth transistor T10 may be connected to the third protrusion of the signal output terminal OUT through the third via D8. However, the present embodiment is not limited to this.

In the present exemplary embodiment, as shown in fig. 24, the length L of the scan drive control circuit in the first direction X _Y The distance between the side of the first clock signal line CKL away from the display area and the side of the extension trace of the signal output terminal OUT close to the display area may be set.

Fig. 25 is another top view of a scan driving control circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 25, the boundary of the first conductive layer of the scan drive control circuit is closer to the display area than the side edge of the third power supply line PL3 in the first direction X. In the present example, the length L of the scan drive control circuit in the first direction X _Y May be a distance between a side edge of the first clock signal line CKL away from the display region and a side edge of the first conductive layer of the scan drive control circuit close to the display region (e.g., a side edge of the gate electrode 203 of the tenth transistor T10 close to the display region).

The structure of the display substrate is explained below by way of an example of a manufacturing process of the display substrate with reference to fig. 15 to 21. The "patterning process" referred to in this disclosure includes processes of depositing a film layer, coating a photoresist, mask exposing, developing, etching, and stripping the photoresist. The deposition may employ any one or more of sputtering, evaporation and chemical vapor deposition, the coating may employ any one or more of spray coating and spin coating, and the etching may employ any one or more of dry etching and wet etching. "thin film" refers to a layer of a material deposited or coated onto a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".

The term "a and B are disposed in the same layer" in the present disclosure means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the "projection of a includes the projection of B", meaning that the boundary of the projection of B falls within the boundary range of the projection of a, or the boundary of the projection of a overlaps with the boundary of the projection of B.

The manufacturing process of the display substrate of the present exemplary embodiment includes the following steps.

(1) And providing a substrate base plate.

In some exemplary embodiments, the substrate base 30 may be a rigid substrate or a flexible substrate. The rigid substrate may comprise one or more of glass, metal foil. The flexible substrate may comprise one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

(2) And forming a first semiconductor layer pattern.

In some exemplary embodiments, a first semiconductor thin film is deposited on the base substrate 30, and the first semiconductor thin film is patterned through a patterning process to form a first semiconductor layer pattern, as shown in fig. 17. The first semiconductor layer pattern includes at least: active layers of a plurality of transistors (e.g., transistors T1 through T10) in the scan drive control circuit. The active layer may include at least one channel region and a plurality of doped regions. The channel region may be undoped with impurities and have semiconductor characteristics. The doped region is doped with impurities and thus has conductivity. The impurity may vary depending on the type of transistor (e.g., N-type or P-type). In some examples, the material of the first semiconductor thin film may be polysilicon.

(3) And forming a first conductive layer pattern.

In some exemplary embodiments, a first insulating film and a first conductive film are sequentially deposited on the base substrate 30 on which the aforementioned patterns are formed, the first conductive film is patterned through a patterning process, and a first insulating layer 31 covering the first semiconductor layer pattern and a first conductive layer pattern disposed on the first insulating layer 31 are formed, as shown in fig. 18. In some examples, the first conductive layer pattern may include: a control electrode of a plurality of transistors (e.g., transistors T1 to T10) of the scan driving control circuit, a first electrode of a plurality of capacitors (e.g., first capacitor C1 to fourth capacitor C4) of the scan driving control circuit.

(4) And forming a second conductive layer pattern.

In some exemplary embodiments, a second insulating film and a second conductive film are sequentially deposited on the base substrate 30 on which the aforementioned patterns are formed, the second conductive film is patterned through a patterning process, and a second insulating layer 32 covering the first conductive layer and a second conductive layer pattern disposed on the second insulating layer 32 are formed, as shown in fig. 19. In some examples, the second conductive layer pattern may include: a second pole of the plurality of capacitors (e.g., the first capacitor C1 to the fourth capacitor C4), the signal input terminal IN, and the signal output terminal OUT of the scan driving control circuit.

(5) And forming a third insulating layer pattern.

In some exemplary embodiments, a third insulating film is deposited on the base substrate 30 on which the aforementioned pattern is formed, and the third insulating film is patterned through a patterning process to form a pattern of a third insulating layer 33 covering the second conductive layer, as shown in fig. 20. In some examples, the third insulating layer 33 has a plurality of vias formed thereon. The plurality of vias includes at least: the first vias F1 to F25, the second vias K1 to K10, and the third vias D1 to D5. The third insulating layer 33, the second insulating layer 32, and the first insulating layer 31 in the plurality of first vias F1 through F25 are etched away, exposing the surface of the first semiconductor layer. The third insulating layer 33 and the second insulating layer 32 within the plurality of second vias K1 through K10 are etched away, exposing the surface of the first conductive layer. The third insulating layer 33 in the plurality of third vias D1 to D5 is etched away, exposing the surface of the second conductive layer.

(6) And forming a third conductive layer pattern.

In some exemplary embodiments, a third conductive film is deposited on the base substrate 30 on which the aforementioned pattern is formed, and the third conductive film is patterned through a patterning process to form a third conductive layer pattern on the third insulating layer 33, as shown in fig. 21. In some examples, the third conductive layer pattern may include: first and second poles of a plurality of transistors (for example, transistors T1 to T10) of the scan drive control circuit, a first connection electrode 211, and a second connection electrode 212.

In some exemplary embodiments, the pixel circuit may be formed in the display region at the same time that the scan driving control circuit is formed in the non-display region. For example, the first semiconductor layer of the display region may include an active layer of a transistor of the pixel circuit, the first conductive layer of the display region may include a control electrode of the transistor of the pixel circuit and a first electrode of the storage capacitor, the second conductive layer of the display region may include at least a second electrode of the storage capacitor of the pixel circuit, and the third conductive layer of the display region may include at least a first electrode and a second electrode of the transistor of the pixel circuit. A second semiconductor layer may be formed in the display region after the first conductive layer is formed, with an insulating layer interposed between the second semiconductor layer and the first conductive layer. The material of the second semiconductor thin film may be a metal oxide, for example, IGZO. However, the present embodiment is not limited to the position of the second semiconductor layer.

In some exemplary embodiments, after the third conductive layer is formed, a fourth insulating layer, an anode layer, a pixel defining layer, an organic light emitting layer, a cathode layer, and an encapsulation layer pattern may be sequentially formed in the display region. In some examples, a fourth insulating film is coated on the substrate base formed with the aforementioned pattern, and a fourth insulating layer pattern is formed by masking, exposing, and developing the fourth insulating film. Then, an anode film is deposited on the substrate of the display region where the pattern is formed, and the anode film is patterned through a patterning process to form an anode pattern on the fourth insulating layer. Then, a Pixel defining film is coated on the substrate base on which the aforementioned pattern is formed, and a Pixel Defining Layer (PDL) pattern is formed through a mask, exposure, and development process, the Pixel defining Layer being formed in each sub-Pixel in the display region, the Pixel defining Layer in each sub-Pixel being formed with a Pixel opening exposing the anode. Subsequently, an organic light emitting layer is formed in the pixel opening formed as described above, and the organic light emitting layer is connected to the anode. Subsequently, a cathode film is deposited and patterned through a patterning process to form a cathode pattern. Subsequently, an encapsulation layer, which may include a stacked structure of inorganic material/organic material/inorganic material, is formed on the cathode.

In some exemplary embodiments, the first, second, and third conductive layers may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may have a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, and the like. The first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The fourth insulating layer may be made of polyimide, acryl, polyethylene terephthalate, or other organic materials. The first and second insulating

layers

31 and 32 are referred to as Gate Insulating (GI) layers, the third insulating layer 33 is referred to as an interlayer Insulating (ILD) layer, and the fourth insulating layer is referred to as a planarization layer. The pixel defining layer can be made of polyimide, acrylic or polyethylene terephthalate. The anode may be made of a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The cathode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals. However, the present embodiment is not limited to this. For example, the anode may be made of a reflective material such as metal, and the cathode may be made of a transparent conductive material.

The structure shown in the present exemplary embodiment and the process for manufacturing the same are merely an exemplary illustration. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs. The preparation process of the exemplary embodiment can be realized by using the existing mature preparation equipment, can be well compatible with the existing preparation process, and has the advantages of simple process realization, easy implementation, high production efficiency, low production cost and high yield.

The embodiment of the present disclosure also provides a display device, which includes the display substrate as described above. In some exemplary embodiments, the display substrate may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be: the display device comprises any product or component with a display function, such as an OLED display device, a watch, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. However, this embodiment is not limited to this.

Fig. 25 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 25, the display device may include: a timing controller, a data driver, a scan driver, a light emission driver, and a pixel array, which may include a plurality of scan lines (e.g., GL1 to GLn), a plurality of data signal lines (e.g., DL1 to DLn), a plurality of light emission control lines (e.g., EL1 to ELn), and a plurality of sub-pixels 10. Each of the sub-pixels 10 may be connected to a corresponding data signal line, a corresponding scan line, and a corresponding light emission control line.

In some exemplary embodiments, the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, may supply a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and may supply a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate data voltages to be supplied to the data signal lines DL1, DL2, DL3, … …, and DLm, which may be an integer, using the gray scale value and the control signal received from the timing controller. For example, the data driver may sample a gray scale value using a clock signal and apply a data voltage corresponding to the gray scale value to the data signal lines DL1 to DLm in units of pixel rows. The scan driver may generate scan signals to be supplied to the scan lines GL1, GL2, GL3, … …, and GLn, n may be an integer, by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan lines GL1 to GLn. For example, the scan driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of the clock signal. The light emission driver may generate emission signals to be supplied to the light emission control lines EL1, EL2, EL3, … …, and ELn by receiving a clock signal, an emission stop signal, or the like from the timing controller. For example, the light emission driver may sequentially supply the emission signals having off-level pulses to the light emission control lines EL1 to ELn. For example, the light emission driver may be configured in the form of a shift register, and may generate the light emission signal in such a manner that the light emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal. In some examples, the light emission driver may include a plurality of cascaded scan drive control circuits provided as in the above embodiments. In this example, the operation timing of the scan drive control circuit can be as shown with reference to fig. 10.

In some exemplary embodiments, the shape of the sub-pixel 10 may be a rectangle, a diamond, a pentagon, or a hexagon. When one pixel unit comprises three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel mode, a vertical parallel mode or a delta-shaped mode; when a pixel unit comprises four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel manner, a vertical parallel manner or a square manner. However, the present embodiment is not limited to this.

In some exemplary embodiments, one pixel unit within the display area may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, one pixel unit may include four sub-pixels, which are a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

In some example embodiments, the timing controller, the data driver, the scan driver, and the light emitting driver may be disposed at the non-display region. Wherein the scan driver and the light emission driver may be respectively disposed at opposite sides of the display area, for example, left and right sides of the display area; the timing controller and the data driver may be disposed at one side of the display area, for example, a lower side of the display area. However, this embodiment is not limited to this.

In some exemplary embodiments, the sub-pixel includes a pixel circuit. The pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. However, the present embodiment is not limited to this. For example, the pixel circuit may include an N-type transistor and a P-type transistor. The N-type transistor may be, for example, an oxide thin film transistor, and the P-type transistor may be, for example, a low temperature polysilicon thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature Polysilicon (LTPS), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The Low-Temperature Polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, the Oxide thin film transistor has the advantages of Low leakage current and the like, the Low-Temperature Polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate to form a Low-Temperature Polycrystalline Oxide (LTPO) display substrate, the advantages of the LTPO and the LTPO can be utilized, Low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

Fig. 27 is another structural schematic diagram of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 27, the scan driver may supply a driving signal to the P-type transistor of the pixel circuit through the first group of scan lines GL1 to GLn, and may also supply a driving signal to the N-type transistor of the pixel circuit through the second group of scan lines SL1 to SLn. The light emission driver may supply a light emission signal to the pixel circuit through the light emission control lines EL1 to ELn. In some examples, the scan driver may include a plurality of scan driving control circuits cascaded as described in the above embodiments to supply driving signals to the N-type transistors of the pixel circuits through the second group of scan lines SL1 to SLn. In this example, the operation timing of the scan drive control circuit can be as shown in fig. 9. For other descriptions of the display device of the present embodiment, refer to the descriptions of the previous embodiments, and therefore, the descriptions thereof are omitted.

The drawings in this disclosure relate only to the structures to which this disclosure relates and other structures may be referred to in the general design. Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments. It will be understood by those skilled in the art that various modifications and equivalent arrangements may be made in the present disclosure without departing from the spirit and scope of the present disclosure, and the scope of the appended claims should be accorded the full scope of the disclosure.

Claims

1. A display substrate comprising a scan drive control circuit, the scan drive control circuit comprising: an input circuit, an output control circuit and an output circuit;

the input circuit is connected with the signal input end, the first clock signal end, the first voltage end and the output control circuit, and is configured to transmit a signal of the signal input end to the output control circuit and transmit a signal of the first clock signal end or the first voltage end to the output control circuit under the control of the first clock signal end;

the output control circuit is connected with the first signal end, the second clock signal end, the second voltage end, the first node, the second node and the input circuit, and is configured to store the signal of the first signal end under the control of the input circuit and transmit the signal of the second signal end to the first node under the control of the input circuit and the second clock signal end; or, under the control of the input circuit, storing the signal of the second clock signal end, and under the control of the second node, transmitting the signal of the second voltage end to the first node;

the output circuit is connected with the first voltage end, the second voltage end, the signal output end, the first node and the second node, and is configured to output a signal of the first voltage end to the signal output end under the control of the second node, or output a signal of the second voltage end to the signal output end under the control of the first node.

2. The display substrate of claim 1, wherein the input circuit comprises: a first input sub-circuit and a second input sub-circuit; the output control circuit includes: a first output control sub-circuit, a second output control sub-circuit and a third output control sub-circuit; the output circuit includes: a first output sub-circuit and a second output sub-circuit;

the first input sub-circuit is connected with the signal input end, the first clock signal end and the first output control sub-circuit and is configured to transmit a signal of the signal input end to the first output control sub-circuit under the control of the first clock signal end;

the second input sub-circuit is connected with the first voltage end, the first clock signal end, the first input sub-circuit and the second output control sub-circuit and is configured to transmit a signal of the first clock signal end or the first voltage end to the second output control sub-circuit under the control of the first input sub-circuit or the first clock signal end;

the first output control sub-circuit is connected with the first signal terminal, the second clock signal terminal, the second node, the first input sub-circuit and the second input sub-circuit and is configured to store a signal of the first signal terminal or the second clock signal terminal under the control of the first input sub-circuit or the second input sub-circuit;

the second output control sub-circuit is connected with the second signal terminal, the second clock signal terminal, the first node and the second input sub-circuit, and is configured to transmit a signal of the second signal terminal to the first node under the control of the second input sub-circuit and the second clock signal terminal;

the third output control sub-circuit is connected with the second voltage end, the first node and the second node and is configured to transmit a signal of the second voltage end to the first node under the control of the second node;

the first output sub-circuit is connected with the first voltage end, the signal output end and the second node and is configured to output a signal of the first voltage end to the signal output end under the control of the second node;

the second output sub-circuit is connected with the second voltage end, the signal output end and the first node, and is configured to output a signal of the second voltage end to the signal output end under the control of the first node.

3. The display substrate of claim 2, wherein the first input sub-circuit comprises: a first transistor; a control electrode of the first transistor is connected with a first clock signal end, a first electrode of the first transistor is connected with a signal input end, and a second electrode of the first transistor is connected with a second node;

the second input sub-circuit comprises: a second transistor and a third transistor; a control electrode of the second transistor is connected with a second node, a first electrode of the second transistor is connected with a first clock signal end, and a second electrode of the second transistor is connected with a third node; a control electrode of the third transistor is connected with a first clock signal end, a first electrode of the third transistor is connected with a first voltage end, and a second electrode of the third transistor is connected with a third node;

the first output control sub-circuit includes: a fourth transistor and a fifth transistor; a control electrode of the fourth transistor is connected with a second node, a first electrode of the fourth transistor is connected with a second clock signal end, and a second electrode of the fourth transistor is connected with a second electrode of the fifth transistor; a control electrode of the fifth transistor is connected with a third node, and a first electrode of the fifth transistor is connected with a first signal end;

the first output sub-circuit includes: a tenth transistor; and a control electrode of the tenth transistor is connected with the second node, a first electrode of the tenth transistor is connected with the first voltage end, and a second electrode of the tenth transistor is connected with the signal output end.

4. The display substrate of claim 2, wherein the first input sub-circuit comprises: a first transistor; a control electrode of the first transistor is connected with a first clock signal end, a first electrode of the first transistor is connected with a signal input end, and a second electrode of the first transistor is connected with a fourth node;

the second input sub-circuit comprises: a second transistor and a third transistor; a control electrode of the second transistor is connected with the fourth node, a first electrode of the second transistor is connected with the first clock signal end, and a second electrode of the second transistor is connected with the third node; a control electrode of the third transistor is connected with a first clock signal end, a first electrode of the third transistor is connected with a first voltage end, and a second electrode of the third transistor is connected with a third node;

the first output control sub-circuit includes: a fourth transistor, a fifth transistor, and an eleventh transistor; a control electrode of the fourth transistor is connected with a second node, a first electrode of the fourth transistor is connected with a second clock signal end, and a second electrode of the fourth transistor is connected with a second electrode of the fifth transistor; a control electrode of the fifth transistor is connected with a third node, and a first electrode of the fifth transistor is connected with a first signal end; a control electrode of the eleventh transistor is connected with a first voltage end, a first electrode of the eleventh transistor is connected with a fourth node, and a second electrode of the eleventh transistor is connected with a second node;

5. The display substrate according to claim 3 or 4, wherein the second output control sub-circuit further comprises: a fourth capacitor; and the first pole of the fourth capacitor is connected with the control poles of the fourth transistor and the tenth transistor.

6. The display substrate of claim 5, wherein the second pole of the fourth capacitor is connected to a fifth transistor.

7. The display substrate of claim 3 or 4, wherein the first output control sub-circuit further comprises: a second capacitor; the first pole of the second capacitor is connected to the second node.

8. The display substrate of claim 7, wherein the second pole of the second capacitor is connected to a signal output terminal.

9. The display substrate of claim 2, wherein the second input sub-circuit is connected to a third node;

the second output control sub-circuit includes: a sixth transistor, a seventh transistor, and a first capacitor;

a control electrode of the sixth transistor is connected with a third node, a first electrode of the sixth transistor is connected with a second signal end, and a second electrode of the sixth transistor is connected with a second electrode of the seventh transistor; a control electrode of the seventh transistor is connected with a second clock signal end, and a first electrode of the seventh transistor is connected with a first node;

a first electrode of the first capacitor is connected to a control electrode of the sixth transistor, and a second electrode of the first capacitor is connected to the seventh transistor.

10. The display substrate of claim 2, wherein the second input sub-circuit is connected to a fifth node;

the second output control sub-circuit includes: a first capacitor, a sixth transistor, a seventh transistor, and a twelfth transistor;

a control electrode of the twelfth transistor is connected with the first voltage end, a first electrode of the twelfth transistor is connected with the fifth node, and a second electrode of the twelfth transistor is connected with the third node;

and the first pole of the first capacitor is connected with the control pole of the sixth transistor, and the second pole of the first capacitor is connected with the seventh transistor.

11. The display substrate of claim 2, wherein the third output control sub-circuit comprises: an eighth transistor and a third capacitor;

a control electrode of the eighth transistor is connected with the second node, a first electrode of the eighth transistor is connected with the second voltage end, and a second electrode of the eighth transistor is connected with the first node;

the first pole of the third capacitor is connected with the first node, and the second pole of the third capacitor is connected with the second voltage end;

the second output sub-circuit includes: a ninth transistor; and a control electrode of the ninth transistor is connected with the first node, the first electrode of the ninth transistor is connected with the second voltage end, and the second electrode of the ninth transistor is connected with the signal output end.

12. The display substrate according to claim 1 or 2, wherein the first signal terminal is connected to a second voltage terminal or a first clock signal terminal.

13. The display substrate of claim 1 or 2, wherein the second signal terminal is connected to the first voltage terminal or the second clock signal terminal.

14. A driving method of a display substrate applied to the display substrate according to any one of claims 1 to 13, the driving method comprising:

the input circuit transmits a signal of the signal input end to the output control circuit under the control of the first clock signal end, and transmits a signal of the first clock signal end or the first voltage end to the output control circuit;

the output control circuit stores a signal of a first signal end under the control of the input circuit, transmits a signal of a second signal end to a first node under the control of the input circuit and a second clock signal end, and outputs a signal of a second voltage end to a signal output end under the control of the first node;

the output control circuit stores a signal of a second clock signal end under the control of the input circuit and transmits a signal of a second voltage end to the first node under the control of a second node; the output circuit outputs a signal of the first voltage end to the signal output end under the control of the second node.

15. A display device comprising the display substrate according to any one of claims 1 to 13.