CN207489447U - A kind of shift register cell, gate driving circuit, display device - Google Patents
A kind of shift register cell, gate driving circuit, display device Download PDFInfo
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- CN207489447U CN207489447U CN201721715303.7U CN201721715303U CN207489447U CN 207489447 U CN207489447 U CN 207489447U CN 201721715303 U CN201721715303 U CN 201721715303U CN 207489447 U CN207489447 U CN 207489447U
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Abstract
The embodiment of the present application provides a kind of shift register cell, gate driving circuit, display device, it is related to display technology field, the multiple and different signal ends for solving OLED pixel circuit correspond to a gate driving circuit respectively, lead to the smaller problem of non-display area wiring space.The shift register cell includes at least two sub-circuits in the first output sub-circuit, the second output sub-circuit and third output sub-circuit.First output sub-circuit is used for by the voltage output of signal output end to reset signal output terminal；Second output sub-circuit is used for the voltage output of signal output end to gating signal output terminal；Third output sub-circuit is used for the voltage output at second voltage end to LED control signal output terminal；Alternatively, for by the voltage output at first voltage end to LED control signal output terminal.The shift register cell is used to provide arbitrary two kinds of signals in reset signal, gating signal and LED control signal to OLED pixel circuit.
Description
Technical field
The utility model is related to display technology field more particularly to a kind of shift register cell, gate driving circuit, show
Showing device.
Background technology
With rapidly improving for display technology, the semiconductor component technology as display device core is also flown therewith
The progress of jump property.For existing display device, Organic Light Emitting Diode (Organic Light Emitting
Diode, OLED) a kind of current mode luminescent device is used as, because of its self-luminous, quick response, wide viewing angle and can make
On flexible substrates the features such as and be applied in high-performance display field more and more.
Pixel circuit is provided in the sub-pix of OLED display, which has multiple and different signal ends.
In the prior art, it for each signal end of the pixel circuit, needs to set one and the signal end phase in non-display area
The driving circuit of connection, the driving circuit are used to provide corresponding voltage to coupled signal end.However, such one
Come, the wiring space that multiple and different driving circuits occupies is larger, is unfavorable for narrow frame design.
Utility model content
The embodiment of the utility model provides a kind of shift register cell, gate driving circuit, display device, solves
Multiple and different signal ends of OLED pixel circuit correspond to a driving circuit respectively, cause non-display area wiring space smaller
The problem of.
To reach in some embodiments, purpose, the embodiment of the utility model adopts the following technical scheme that：
The one side of the embodiment of the present application provides a kind of shift register cell, including：First output sub-circuit, second
Export at least two sub-circuits in sub-circuit and third output sub-circuit；The shift register cell further includes front end electricity
Road；The front-end circuit and signal input part, the first clock signal terminal, second clock signal end, first voltage end, second voltage
End and signal output end connection, the front-end circuit are used to receiving the voltage of the signal input part, and described the
One clock signal terminal, the second clock signal end control under, by the voltage of the second clock signal end or described second
The voltage output of voltage end is to the signal output end；The first output sub-circuit is used in the third clock signal terminal
Under control, by the voltage output of the signal output end to the reset signal output terminal, and by the electricity at the second voltage end
Pressure is exported to the gating signal output terminal；The second output sub-circuit connects the 4th clock signal terminal, the second voltage
End, the signal output end, the reset signal output terminal and the gating signal output terminal；The second output sub-circuit
For under the control of the 4th clock signal terminal, the voltage output of the signal output end to the gating signal to be exported
End, and by the voltage output at the second voltage end to the reset signal output terminal；The third output sub-circuit connection institute
State first voltage end, the signal output end, the second voltage end and LED control signal output terminal；The third output
Sub-circuit is used under the control of the signal output end, and the voltage output at the second voltage end to the light emitting control is believed
Number output terminal；Alternatively, the third output sub-circuit is used under the control at the first voltage end, by the first voltage end
Voltage output to the LED control signal output terminal.
Optionally, the first output sub-circuit includes the first transistor and second transistor；The first transistor
Grid connects the third clock signal terminal, and the first pole connects the signal output end, and the second pole is exported with the reset signal
End is connected；The grid of the second transistor connects the third clock signal terminal, the first extremely described gating signal output terminal
Connection, the second pole is connected with the second voltage end.
Optionally, the second output sub-circuit includes third transistor and the 4th transistor；The third transistor
Grid connects the 4th clock signal terminal, and the first pole connects the signal output end, and the second pole is exported with the gating signal
End is connected；The grid of 4th transistor connects the 4th clock signal terminal, and it is defeated that the first pole connects the reset signal
Outlet, the second pole are connected with the second voltage end.
Optionally, the third output sub-circuit includes the 13rd transistor and the 14th transistor；Described 13rd is brilliant
The grid of body pipe and the first pole connect the first voltage end, and the second pole is connected with the LED control signal output terminal；Institute
The grid for stating the 14th transistor connects the signal output end, and the first pole connects the LED control signal output terminal, and second
Pole is connected with the second voltage end；Wherein, the breadth length ratio of the 14th transistor is more than the 13rd transistor
Breadth length ratio.
Optionally, the front-end circuit includes pull-up control sub-circuit, drop-down control sub-circuit, pull-up sub-circuit, drop-down
Sub-circuit；The pull-up control sub-circuit is connect with signal input part, the first clock signal terminal, pull-up node；The pull-up control
System circuit is used under the control of first clock signal terminal, by the voltage output of the signal input part to the pull-up
Node；The pull-up sub-circuit is connect with second clock signal end, the pull-up node and signal output end；The upper rock
Circuit is used under the control of the pull-up node, and the voltage output of the second clock signal end to the signal is exported
End；The drop-down control sub-circuit and first clock signal terminal, first voltage end, the pull-up node and pull-down node
Connection；The drop-down control sub-circuit is used under the control of first clock signal terminal and the pull-up node, by described in
The voltage of first voltage end and first clock signal terminal is transmitted to the pull-down node；It is described drop-down sub-circuit with it is described under
Draw node, second voltage end and signal output end connection；The drop-down sub-circuit is used for the control in the pull-down node
Under system, the voltage at the second voltage end is transmitted to the signal output end.Optionally, the pull-up control sub-circuit includes
5th transistor；The grid of 5th transistor connects first clock signal terminal, and the first pole connects the signal input
End, the second pole is connected with the pull-up node.
Optionally, the pull-up control sub-circuit is also connected with first voltage end；The pull-up control sub-circuit further includes the
Six transistors；The grid of 6th transistor connects the first voltage end, and the first pole connects the of the 5th transistor
Two poles, the second level are connected with the pull-up node.
Optionally, the shift register cell further includes voltage and keeps sub-circuit；The voltage keeps sub-circuit connection
The pull-down node, the second pole of the 5th transistor, the second clock signal end and the second voltage end；It is described
Voltage keeps sub-circuit to be used under the control of the second clock signal end and the pull-down node, by the second voltage
The voltage of end output is stored, and by the voltage output of storage to the second pole of the 5th transistor.
Optionally, the voltage keeps sub-circuit to include the 7th transistor and the 8th transistor；7th transistor
Grid connects the second clock signal end, and the first pole connects the second pole of the 5th transistor, the second pole and the described 8th
First pole of transistor is connected；The grid of 8th transistor connects the pull-down node, the second pole and the described second electricity
Pressure side is connected.
Optionally, the drop-down control sub-circuit includes the 9th transistor and the tenth transistor；9th transistor
Grid connects first clock signal terminal, and the first pole connects the first voltage end, and the second pole is connected with the pull-down node
It connects；The grid of tenth transistor connects the pull-up node, and the first pole connects first clock signal terminal, the second pole with
The pull-down node is connected.
Optionally, the pull-up sub-circuit includes the 11st transistor and the first capacitance；The grid of 11st transistor
Pole connects the pull-up node, and the first pole connects the second clock signal end, and the first pole is connected with the signal output end；
One end of first capacitance connects the grid of the 11st transistor, the second pole of the other end and the 11st transistor
It is connected.
Optionally, the drop-down sub-circuit includes the tenth two-transistor and the second capacitance；The grid of tenth two-transistor
Pole connects the pull-down node, and the first pole connects the signal output end, and the second pole is connected with the second voltage end；It is described
One end of second capacitance connects the grid of the tenth two-transistor, and the other end is extremely connected with the first of the tenth two-transistor
It connects.
The another aspect of the embodiment of the present application provides a kind of gate driving circuit, including multiple cascade as described above
Any one shift register cell；The signal input part connection initial signal end of first order shift register cell；In addition to institute
It states other than first order shift register cell, the signal output end connection next stage shift LD of upper level shift register cell
The signal input part of device unit.
The another aspect of the embodiment of the present application, provides a kind of display device, including gate driving circuit as described above.
The embodiment of the present application provides a kind of shift register cell, gate driving circuit, display device.What the application provided
Shift register cell includes at least two in the first output sub-circuit, the second output sub-circuit and third output sub-circuit
Sub-circuit, wherein, the reset signal output terminal of the first output sub-circuit connection can be with the reset signal in OLED pixel circuit
End is connected, to provide signal to the reset signal end；The messenger output terminal of second output sub-circuit connection can be with OLED
Gating signal end in pixel circuit is connected, to provide signal to the gating signal end；The hair of third output sub-circuit connection
Optical control signal output terminal can be connected with the LED control signal end in OLED pixel circuit, with to the LED control signal
End provides signal.So, using in some embodiments, gate driving circuit that shift register cell is formed can be down to
Few at least two signal ends to a pixel circuit are (in reset signal end, gating signal end and LED control signal end extremely
It is two few) signal is provided, so as to reduce the quantity of non-display area setting gate driving circuit, and then reach raising wiring
Space and the purpose for realizing narrow frame.
Description of the drawings
It in order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is a kind of structure diagram of shift register cell provided by the embodiments of the present application；
Fig. 2 is the structure diagram of another shift register cell provided by the embodiments of the present application；
Fig. 3 a are the OLED pictures provided by the embodiments of the present application being connected with shift register cell shown in fig. 1 or fig. 2
The structure diagram of plain circuit；
Fig. 3 b are the sequence diagram at part signal end in Fig. 3 a；
Fig. 4 is the concrete structure schematic diagram of each sub-circuit in Fig. 1；
Fig. 5 is the concrete structure schematic diagram of each sub-circuit in Fig. 2；
Fig. 6 is the sequence diagram for controlling each signal of shift register cell shown in fig. 5；
Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12 are that shift register cell shown in fig. 5 distinguishes shown in Fig. 6 the
One stage T1, second stage T2, phase III T3, fourth stage T4, the 5th stage P5, the 6th stage P6 operating diagram；
Figure 13 is the structure diagram of a kind of gate driving circuit that the application provides.
Reference numeral：
01- front-end circuits；10- pull-up control sub-circuits；11- voltages keep sub-circuit；20- drop-down control sub-circuits；30-
Pull up sub-circuit；40- pulls down sub-circuit；50- first exports sub-circuit；60- second exports sub-circuit；70- thirds output son electricity
Road.
Specific embodiment
The following is a combination of the drawings in the embodiments of the present utility model, and the technical scheme in the embodiment of the utility model is carried out
It clearly and completely describes, it is clear that the described embodiments are only a part of the embodiments of the utility model rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are without making creative work
All other embodiments obtained shall fall within the protection scope of the present invention.
Hereinafter, term " first ", " second " are only used for description purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the embodiment of the present application, unless otherwise indicated, " multiples' " contains
Justice is two or more.
The embodiment of the present application provides a kind of shift register cell, as shown in Figure 1, including：First output sub-circuit 50, the
At least two sub-circuits in two output sub-circuits 60 and third output sub-circuit 70.
Specifically, for example as shown in Figure 1, in some embodiments, which includes the first output son electricity
Road 50 and second exports sub-circuit 60；In another example as shown in Figure 2 the shift register cell include first output sub-circuit 50,
Second output sub-circuit 60 and third output sub-circuit 70.Again alternatively, the shift register cell includes the first output son electricity
Road 50, third output sub-circuit 70；Or the shift register cell includes the second output sub-circuit 60, third output
Circuit 70.
In addition, the shift register cell further includes front-end circuit 01, the front-end circuit 01 and signal input part GSTV, the
One clock signal terminal GCK, second clock signal end GCB, first voltage end VGL, second voltage end VGH and signal output end
Gout connections.Above-mentioned front-end circuit is used to receive the voltage of signal input part GSTV, and in the first clock signal terminal GCK, second
Under the control of clock signal terminal GCB, by the voltage output of the voltage of second clock signal end GCB or second voltage end VGH to letter
Number output terminal Gout.
Wherein, which includes pull-up control sub-circuit 10, drop-down control sub-circuit 20, pull-up as shown in Figure 1
Sub-circuit 30, drop-down sub-circuit 40.
Based on this, 10 connection signal input terminal GSTV of pull-up control sub-circuit, the first clock signal terminal GCK, pull-up save
Point PU.Pull-up control sub-circuit 10 is used under the control of the first clock signal terminal GCK, inputs a signal into the voltage of end GSTV
It exports to pull-up node PU.
It pulls up sub-circuit 30 and connects second clock signal end GCB, pull-up node PU and signal output end Gout.The pull-up
Sub-circuit 30 is used under the control of pull-up node PU, by the voltage output of second clock signal end GCB to signal output end
Gout。
Drop-down control sub-circuit 20 connect the first clock signal terminal GCK, first voltage end VGL, pull-up node PU and under
Draw node PD.Drop-down control sub-circuit 20 is used under the control of the first clock signal terminal GCK and pull-up node PU, by first
The voltage of voltage end VGL and the first clock signal terminal GCK are transmitted to pull-down node PD.
It pulls down sub-circuit 40 and connects pull-down node PD, second voltage end VGH and signal output end Gout.The lower rock electricity
Road 40 is used under the control of pull-down node PD, and the voltage of second voltage end VGH is transmitted to signal output end Gout.
First output sub-circuit 50 connect third clock signal terminal GCK1, second voltage end VGH, signal output end Gout,
Reset signal output terminal OUT_RST.The first output sub-circuit 50 is used under the control of third clock signal terminal GCK1, will be believed
The voltage output of number output terminal Gout is to reset signal output terminal OUT_RST.In some embodiments, shift register cell packet
In the case of including the second output sub-circuit 60, which is also connected with gating signal output terminal OUT_Gate, should
First output sub-circuit 50 is additionally operable to the voltage output of second voltage end VGH to gating signal output terminal OUT_Gate.
Second output sub-circuit 60 connect the 4th clock signal terminal GCB1, second voltage end VGH, signal output end Gout with
And gating signal output terminal OUT_Gate.The second output sub-circuit 60 is used under the control of the 4th clock signal terminal GCB1,
By the voltage output of signal output end Gout to gating signal output terminal OUT_Gate.In some embodiments, shift register
In the case that unit includes the first output sub-circuit 50, which is also connected with reset signal output terminal OUT_
RST, the second output sub-circuit 60 are additionally operable to the voltage output of second voltage end VGH to reset signal output terminal OUT_RST.
In some embodiments, in the case where the shift register cell includes third output mould 70, third output
Sub-circuit 70 connects first voltage end VGL, signal output end Gout, second voltage end VGH and LED control signal output terminal
OUT_EMS.Third output sub-circuit 70 is used under the control of signal output end Gout, by the voltage of second voltage end VGH
It exports to LED control signal output terminal OUT_EMS；Alternatively, third output sub-circuit 70 is used for first voltage end VGL's
Under control, by the voltage output of first voltage end VGL to LED control signal output terminal OUT_EMS.
Fig. 3 a illustrate the pixel-driving circuit that a kind of driving OLED shines, which has 7T1C frameworks, packet
Include reset signal end RST, gating signal end Gate and LED control signal end EMS.
In the prior art, it is non-display for the display panel of pixel-driving circuit for including in some embodiments
Region needs to set three kinds of different driving circuits so as in some embodiments, three signal ends provide signal respectively.This reality
It applies in example, the transistor of pixel circuit is illustrated by taking p-type pipe as an example, wherein, reset signal end RST, gating signal end
The sequence diagram of Gate and LED control signal end EMS are as shown in Figure 3b.Specifically, in reseting stage, reset signal end RST is carried
For low level, resetted with the anode of grid g and OLED to driving transistor Md；In data write phase, gating signal
Gate is held to provide low level, by the leakage of the data voltage Vdata source electrode s write driver transistors Md for passing through driving transistor Md
Pole d；In glow phase, LED control signal end EMS provides low level, OLED to be controlled to shine.
In some embodiments, it is defeated that the shift register cell that the application provides includes the first output sub-circuit 50, second
Go out at least two sub-circuits in sub-circuit 60 and third output sub-circuit 70, wherein, what the first output sub-circuit 50 connected
Reset signal output terminal OUT_RST can in some embodiments, reset signal end RST is connected, with to the reset signal
RST is held to provide signal；Second output sub-circuit 60 connect gating signal output terminal OUT_Gate can in some embodiments
In, gating signal end Gate is connected, to provide signal to gating signal end Gate；The hair that third output sub-circuit 70 connects
Optical control signal output terminal OUT_EMS can in some embodiments, LED control signal end EMS is connected, with to the hair
Optical control signal end EMS provides signal.
In some embodiments, the first output sub-circuit 50, second exports sub-circuit 60 and third output sub-circuit 70
It is connected with signal output end Gout, in some embodiments, the first output sub-circuit 50 can choose signal output end
A part for Gout output signals is exported as reset signal, and by reset signal output terminal OUT_RST to OLED pixel circuit
Reset signal end RST；Second output sub-circuit 60 can choose another part conduct of signal output end Gout output signals
Gating signal, and exported by gating signal output terminal OUT_Gate to the gating signal end Gate of OLED pixel circuit；Third is defeated
Going out sub-circuit 70 can make decision the sequential of LED control signal in the control of signal output end Gout output signals, and by shining
Control signal output OUT_EMS is exported to the LED control signal end EMS of OLED pixel circuit.So, using one
In a little embodiments, the gate driving circuit that shift register cell is formed can be at least at least two signals of a pixel circuit
End (at least two in reset signal end RST, gating signal end Gate and LED control signal end EMS) provide signal, from
And the quantity of non-display area setting gate driving circuit can be reduced, and then reach and improve wiring space and realization narrow frame
Purpose.
Specifically, as shown in figure 4, in some embodiments, the first output sub-circuit 50 includes the first transistor M1 and the
Two-transistor M2.
Wherein, the grid connection third clock signal terminal GCK1 of the first transistor M1, the first pole connection signal output terminal
Gout, the second pole are connected with reset signal output terminal OUT_RST.
Grid connection third the clock signal terminal GCK1, the first pole gating signal output terminal OUT_Gate of second transistor M2
Connection, the second pole is connected with second voltage end VGH.
In some embodiments, the second output sub-circuit 60 includes third transistor M3 and the 4th transistor M4.
Wherein, the grid of third transistor M3 connects the 4th clock signal terminal GCB1, the first pole connection signal output terminal
Gout, the second pole are connected with gating signal output terminal OUT_Gate.
The grid of 4th transistor M4 connects the 4th clock signal terminal GCB1, the first pole connection reset signal output terminal OUT_
RST, the second pole are connected with second voltage end VGH.
In the case where shift register cell in some embodiments includes third output sub-circuit 70, the third is defeated
Go out sub-circuit 70 as shown in figure 5, including the 13rd transistor M13 and the 14th transistor M14.
Wherein, the grid of the 13rd transistor M13 and the first pole connection first voltage end VGL, the second pole and light emitting control
Signal output end OUT_EMS is connected.
The grid connection signal output terminal Gout of 14th transistor M14, the first pole connection LED control signal output terminal
OUT_EMS, the second pole are connected with second voltage end VGH.
Wherein, the breadth length ratio of the 14th transistor M14 is more than the breadth length ratio of the 13rd transistor M13.In the case,
The driving force of 14 transistor M14 is more than the driving force of the 13rd transistor M13.In the case, when the 13rd crystal
When pipe M13 and the 14th transistor M14 are both turned on, the current potential of LED control signal output terminal OUT_EMS is determined by the tenth
The voltage potential of second voltage end VGH that four transistor M14 transmission comes.
On this basis, pull-up control sub-circuit 10 includes the 5th transistor M5.Wherein, the grid of the 5th transistor M5
The first clock signal terminal GCK is connected, the first pole connection signal input terminal GSTV, the second pole is connected with pull-up node PU.
Based on this, in some embodiments, shift register cell keeps son electricity as shown in figure 5, can also include voltage
Road 11.The voltage keeps sub-circuit 11 to connect pull-down node PD, the second pole of the 5th transistor M5, second clock signal end GCB
And second voltage end VGH.Wherein, which keeps sub-circuit 11 to be used in second clock signal end GCB and pull-down node
Under the control of PD, the VGH voltages exported in second voltage end are stored, and by the voltage output of storage to the 5th transistor M5
The second pole.So as in some embodiments, the 5th transistor M5 in some embodiments, pull-up node PU is connected
In the case of, sub-circuit 11 can be kept the voltage output of second voltage end VGH to pull-up node PU by the voltage, with stabilization
Pull-up node PU current potential.
Specifically, in some embodiments, voltage keeps sub-circuit 11 to include the 7th transistor M7 and the 8th transistor M8.
Wherein, the grid connection second clock signal end GCB of the 7th transistor M7, the first pole connects the 5th transistor M5's
Second pole, the second pole are connected with the first pole of the 8th transistor M8.
The grid connection pull-down node PD of 8th transistor M8, the second pole is connected with second voltage end VGH.
In some embodiments, pull-up control sub-circuit 10 is also connected with first voltage end VGL, at this point, pull-up control son electricity
Road 10 further includes the 6th transistor M6.
Wherein, the grid connection first voltage end VGL of the 6th transistor M6, the first pole connects the second of the 5th transistor M5
Pole, the second level are connected with pull-up node PU.In the case, when the 6th transistor M6 is connected, the 5th transistor M5's
Second extremely can by the 6th transistor M6 in some embodiments, pull-up node PU is connected.So, at some
In embodiment, in the case that the 6th transistor M6 is P-type transistor, when the voltage of the 6th the second poles of transistor M6 is more than grid electricity
During pressure, the 6th transistor M6 may be at cut-off state, so as to prevent pull-up node PU from leaking electricity.
In some embodiments, drop-down control sub-circuit 20 includes the 9th transistor M9 and the tenth transistor M10.
Wherein, the grid of the 9th transistor M9 connects the first clock signal terminal GCK, the first pole connection first voltage end VGL,
Second pole is connected with pull-down node PD.
The grid connection pull-up node PU of tenth transistor M10, the first pole connects the first clock signal terminal GCK, the second pole
It is connected with pull-down node PD.
In some embodiments, pull-up sub-circuit 30 includes the 11st transistor M11 and the first capacitance C1.
Wherein, the grid connection pull-up node PU of the 11st transistor M11, the first pole connection second clock signal end GCB,
First pole is connected with signal output end Gout.
One end of first capacitance C1 connects the grid of the 11st transistor M11, and the of the other end and the 11st transistor M11
Two poles are connected.
It pulls down sub-circuit 40 and includes the tenth two-transistor M12 and the second capacitance C2.
Wherein, grid connection the pull-down node PD, the first pole connection signal output terminal Gout, the of the tenth two-transistor M12
Two poles are connected with second voltage end VGH.
One end of second capacitance C2 connects the grid of the tenth two-transistor M12, and the of the other end and the tenth two-transistor M12
One pole is connected.
It should be noted that in some embodiments, transistor can be N-type transistor or P-type transistor.Wherein,
The first of transistor can be extremely source electrode, and second extremely drains or first extremely drains, the second extremely source electrode, the application couple
This is not limited.
The application is that constant low level is exported with first voltage end VGL, and second voltage end VGH exports constant high level
For the explanation that carries out.
Hereinafter, in the above-mentioned transistor in the shift register cell and OLED pixel circuit with reset signal end
For the transistor that RST, gating signal end Gate and LED control signal end EMS are connected is P-type transistor, with reference to figure
Signal timing diagram shown in 6, under the working condition in each stage of the shift register cell shown in fig. 5 in a picture frame
It is described in detail.
Wherein, as shown in fig. 6, the first clock signal terminal GCK and the frequency phase of second clock signal end GCB output signals
Together, opposite in phase；Third clock signal terminal GCK1 is identical with the frequency of the 4th clock signal terminal GCB1 output signals, phase phase
Instead；The frequency of first clock signal terminal GCK output signals is the 1/2 of the frequency of third clock signal terminal GCK1 output signals.
In some embodiments, in a picture frame, first stage T1, second stage T2, phase III T3 and fourth order
The duration of section T4 is identical.5th stage P5 and the 6th stage P6 when one times of a length of fourth stage T4 durations.
Specifically, T1, GSTV=0 in the first stage；GCK=0；GCB=1；GCK1=0；GCB1=1.Wherein " 0 " represents
High level, " 1 " represent low level.
In the case, as shown in fig. 7, the first clock signal terminal GCK exports low level, the 5th transistor M5 and the 9th is brilliant
Body pipe M9 is connected.The low level of signal input part GSTV outputs is transmitted to node PU0, then pass through conducting by the 5th transistor M5
The 6th transistor M6 be transmitted to pull-up node PU.Under the control of node PU0, the tenth transistor M10 conductings.First voltage end
The low level of VGL outputs is transmitted to pull-down node PD, the low level of the first clock signal terminal GCK outputs by the 9th transistor M9
Pull-down node PD is transmitted to by the tenth transistor M10.
In some embodiments, the 8th transistor M8 is connected, the 7th transistor M7 cut-offs, second voltage end VGH outputs
After high level is by the 8th transistor M8, it can store to what is be made of the grid and source electrode (or drain electrode) of the 7th transistor M7 and post
The raw capacitance GS and parasitic capacitance GD being made of the grid of the 8th transistor M8 and drain electrode (or source electrode), i.e. high level store
At node N1.
Under the control of pull-up node PU, the 11st transistor M11 conductings, the height that second clock signal end GCB is exported
Level is transmitted to signal output end Gout.Under the control of pull-down node PD, the tenth two-transistor M12 conductings, by second voltage
The high level of end VGH outputs is transmitted to signal output end Gout.
Under the control of third clock signal terminal GCK1, the first transistor M1 and second transistor M2 conductings.Signal exports
The high level of end Gout is transmitted to reset signal output terminal OUT_RST by the first transistor M1.The height electricity of second voltage end VGH
It is flat that gating signal output terminal OUT_Gate is transmitted to by second transistor M2.
Third transistor M3, the 4th transistor M4 and the 14th transistor M14 are in cut-off state.13rd transistor
M13 is connected, and the low level of first voltage end VGL is transmitted to LED control signal output terminal by the 13rd transistor M13
OUT_EMS。
In this stage, reset signal output terminal OUT_RST output high level, therefore be connected with the shift register cell
The reset signal end RST of OLED pixel circuit receive in some embodiments, high level, so in the OLED pixel circuit
The transistor cutoff being connected with reset signal end RST, so the OLED pixel circuit does not enter reseting stage.
In second stage T2, GSTV=0；GCK=0；GCB=1；GCK1=1；GCB1=0.
In the case, as shown in figure 8, due to signal input part GSTV, the first clock signal terminal GCK and second clock
The signal of signal end GCB outputs is identical with first stage T1.The difference lies in third clock signal terminal GCK1 to export high level,
4th clock signal terminal GCB1 exports low level, therefore the stage, the first transistor M1 and second transistor M2 cut-offs.Third is brilliant
Body pipe M3 and the 4th transistor M4 conductings.The on and off state of remaining transistor is identical with first stage T1.
Based on this, by the way that in some embodiments, the high level of third transistor M3, signal output end Gout can transmit
To gating signal output terminal OUT_Gate；By the way that in some embodiments, the height of the 4th transistor M4, second voltage end VGH are electric
It is flat to be transmitted to reset signal output terminal OUT_RST；And LED control signal output terminal OUT_EMS keeps low level output.
Same as above, the OLED pixel circuit being connected at this stage with the shift register cell does not still enter reset
Stage.
In phase III T3, GSTV=1；GCK=1；GCB=0；GCK1=0；GCB1=1.
In the case, as shown in figure 9, the first clock signal terminal GCK exports high level, the 5th transistor M5 and the 9th is brilliant
Body pipe M9 ends.Under the boot strap of the first capacitance C1, the level of pull-up node PU further reduces.At this point, the 11st is brilliant
Body pipe M11 is tended to remain on, and by the low level output of second clock signal end GCB to signal output end Gout.
Under the control of pull-up node PU, the tenth transistor M10 conductings, by the height electricity of the first clock signal terminal GCK outputs
It flates pass and transports to pull-down node PD.At this point, the 8th transistor M8 and the tenth two-transistor M12 cut-offs.
In some embodiments, due to first of the 6th transistor M6 for P-type transistor, at this stage the 6th transistor M6
The level of one end that pole (i.e. with pull-up node PU) is connected further reduces, therefore source electrode (or the leakage of the 6th transistor M6
Pole) voltage be more than grid voltage, the 6th transistor M6 is in cut-off state.
It should be noted that at this stage, node PU0 is low level.This is because in second stage T2, signal input
The low level of end GSTV outputs can be stored in the parasitic capacitance being made of the tenth transistor M10 grids and active layer.Tenth
The parasitic capacitance of transistor M10 is parasitic relative to the parasitic capacitance GS and the 8th transistor M8 of the 7th transistor M7 at node N1
Capacitance GD is larger, so in second stage, the parasitic capacitance of the tenth transistor M10 keeps node PU0 to be in low level ability,
It is greater than ability of the parasitic capacitance at node N1 to node PU0 write-in high level.
On this basis, third clock signal terminal GCK1 exports low level, and the first transistor M1 and second transistor M2 are led
It is logical.4th clock signal terminal GCB1 exports high level, third transistor M3 and the 4th transistor M4 cut-offs.Signal output end Gout
Level can be transmitted to reset signal output terminal OUT_RST by the first transistor M1, can be with and by second transistor M2
The high level of second voltage end VGH is transmitted to gating signal output terminal OUT_Gate.
In some embodiments, the 14th transistor M14 is connected, since the driving force of the 14th transistor M14 is more than
13rd transistor M13, therefore the high level of second voltage end VGH can be transmitted to by the 14th transistor M14 luminous
Control signal output OUT_EMS.
It follows that reset signal output terminal OUT_RST export low level, gating signal output terminal OUT_Gate and shine
Control signal output OUT_EMS exports high level.In the case, be connected OLED pixel electricity with the shift register cell
The reset signal end RST on road receives low level, thus to the corresponding position in the OLED pixel circuit (for example, driving crystal
The positions such as the grid of pipe, the anode of OLED) voltage resetted, which is in reseting stage.
In fourth stage T4, GSTV=1；GCK=1；GCB=0；GCK1=1；GCB=0.
When in the case, as shown in Figure 10, due to signal input part GSTV, the first clock signal terminal GCK and second
The signal of clock signal end GCB outputs is identical with phase III T3.The difference lies in third clock signal terminal GCK1 to export high electricity
It is flat, the 4th clock signal terminal GCB1 output low levels, therefore the stage, the first transistor M1 and second transistor M2 cut-offs.The
Three transistor M3 and the 4th transistor M4 conductings.The on and off state of remaining transistor is identical with phase III T3.
Based on this, in some embodiments, the low level of third transistor M3, signal output end Gout can be transmitted to choosing
Messenger output terminal OUT_Gate；By the way that in some embodiments, the 4th transistor M4, the high level of second voltage end VGH can
To be transmitted to reset signal output terminal OUT_RST；And LED control signal output terminal OUT_EMS keeps high level output.
In some embodiments, gating signal output terminal OUT_Gate exports low level, reset signal output terminal OUT_RST
High level is exported with LED control signal output terminal OUT_EMS.In the case, be connected OLED with the shift register cell
The gating signal end Gate of pixel circuit is received in some embodiments, low level, so as to by data voltage Data be written to
Driving transistor, the OLED pixel circuit are in data write phase.
In the 5th stage P5, GSTV=1；GCK=0；GCB=1；GCK1=0,1；GCB1=1,0.
In the case, as shown in figure 11, under the low level control of the first clock signal terminal GCK outputs, the 5th is brilliant
Body pipe M5 and the 9th transistor M9 conductings, the high level of signal input part GSTV outputs are transmitted to pull-up node PU, and the 11st is brilliant
Body pipe M11 and the tenth transistor M10 cut-offs.
The low level of first voltage end VGL is transmitted to pull-down node PD, the tenth two-transistor M12 by the 9th transistor M9
Conducting, the 8th transistor M8 conductings.Second voltage end VGH is transmitted to signal output end Gout by the tenth two-transistor M12, and
It is stored by the 8th transistor M8 to first node N1.Under the control of second clock signal end GCB, the 7th transistor M7 is cut
Only.
Low level and high level are successively exported in the 5th stage P5, third clock signal terminal GCK1；4th clock signal
Hold GCB2 successively output high level and low level.Based on this, when third clock signal terminal GCK1 exports low level, the 4th clock letter
Number end GCB1 output high level when, as shown in figure 11, the first transistor M1 and second transistor M2 conducting, third transistor M3 and
4th transistor M4 ends.When third clock signal terminal GCK1 exports high level, the 4th clock signal terminal GCB1 output low levels
When, the first transistor M1 and second transistor M2 cut-offs, third transistor M3 and the 4th transistor M4 are connected.No matter third clock
The signal of signal end GCK1 or the 4th clock signal terminal GCB1 outputs is how, since signal output end Gout is high level,
Gating signal output terminal OUT_Gate and reset signal output terminal OUT_RST output high level.
In some embodiments, under the control of signal output end Gout, the 14th transistor M14 cut-offs, therefore the tenth
The low level of first voltage end VGL is transmitted to LED control signal output terminal OUT_EMS by three transistor M13.In the case,
The LED control signal end EMS for the OLED pixel circuit that is connected with the shift register cell receives low level, so as to absent from duty without reason
OLED shines, which is in glow phase.
In the 6th stage P6, GSTV=1；GCK=1；GCB=0；GCK1=0,1；GCB1=1,0.
In the case, as shown in figure 12, under the control of the high level of the first clock signal terminal GCK outputs, the 5th is brilliant
Body pipe M5 and the 9th transistor M9 cut-offs.Control node PD is pulled down under the discharge process of the second capacitance C2, is kept on last stage
Low level.At this point, the tenth two-transistor M12 and the 8th transistor M8 conductings.In the low level control of second clock signal end GCB
Under system, the 7th transistor M7 is connected, and the high level at node N1 is transmitted to node PU0 and pull-up node PU, the 11st transistor
M11 and the tenth transistor M10 cut-offs.
In some embodiments, the high level of second voltage end VGH is transmitted to signal by the tenth two-transistor M12 and exports
Gout, signal output end Gout is held to keep high level output.In the case, LED control signal output terminal OUT_EMS is defeated
Go out low level.
Based on this, signal and the 5th stage phase that third clock signal terminal GCK1 and the 4th clock signal terminal GCB2 are exported
Together, therefore gating signal output terminal OUT_Gate and reset signal output terminal OUT_RST keeps output high level.
It should be noted that before starting after the 6th stage T2 to next image frame, the shift register cell weight
Multiple 5th stage and the 6th stage.
Be above in all transistors in shift register cell and OLED pixel circuit with reset signal end
The transistor that RST, gating signal end Gate and LED control signal end EMS are connected is to carry out for P-type transistor
Illustrate, when in the transistor in shift register cell and OLED pixel circuit with reset signal end RST, gating signal end
When the transistor that Gate and LED control signal end EMS are connected is N-type transistor, need to control the part in Fig. 6
Signal is overturn, and the position of first voltage end VGL and second voltage end VGH are swapped, and the shift register list
The course of work of member can similarly obtain, and details are not described herein again.
The embodiment of the present application provides a kind of gate driving circuit, and as shown in figure 13, which includes multiple grades
Any one shift register cell as described above of connection.
Wherein, the signal input part GSTV connection initial signals end STV of first order shift register cell RS1.Work as starting
After signal end STV input initial signals, which starts to work.
Other than first order shift register cell RS1, the signal output end Gout of upper level shift register cell
Connect the signal input part GSTV of next stage shift register cell.
It should be noted that the first clock signal terminal GCK, the second clock signal of two adjacent shift register cells
End GCB replaces connection with clock signal of system end CK1, CK2 respectively.Such as first order shift register cell RS1 first when
Clock signal end GCK connection clock signal of system end CK1, second clock signal end GCB connection clock signal of system end CK2；Second
The first clock signal terminal GCK connection clock signal of system end CK2, second clock signal end GCB of grade shift register cell RS2
Connect clock signal of system end CK1.
In some embodiments, third clock signal terminal GCK1, the 4th clock of two adjacent shift register cells
Signal end GCB1 replaces connection with clock signal of system end CK3 and CK4 respectively.Such as first order shift register cell RS1
Third clock signal terminal GCK1 connection clock signal of system end CK3, the 4th clock signal terminal GCB1 connection clock signal of system
Hold CK4；The third clock signal terminal GCK1 connection clock signal of system end CK4 of second level shift register cell RS2, when the 4th
Clock signal end GCB1 connection clock signal of system end CK3.The connection mode of remaining shift register cell clock signal terminal is with this
Analogize.
In some embodiments, gate driving circuit has identical with the shift register cell that previous embodiment provides
Technique effect, details are not described herein again.
The embodiment of the present application provides a kind of display device, including any one gate driving circuit as described above.This is aobvious
Gate driving circuit in showing device has the structure and advantageous effect identical with the gate driving circuit that previous embodiment provides.
It is no longer superfluous herein since previous embodiment has been described in detail the structure of gate driving circuit and advantageous effect
It states.
It should be noted that in the utility model embodiment, display device at least can be specifically organic light-emitting diodes
Tube display device, such as the display device can be display, TV, Digital Frame, mobile phone, vehicle-carrying display screen or tablet computer
Etc. any product or component with display function.
The embodiment of the present application provides a kind of method for being used to drive any one shift register cell as described above,
In one picture frame, include pull-up control sub-circuit 10, drop-down control son electricity in the front-end circuit 01 of above-mentioned shift register cell
In the case of road 20, pull-up sub-circuit 30, drop-down sub-circuit 40, this method includes：
Pull-up in first stage T1 as shown in Figure 6, second stage T2, Fig. 2 controls sub-circuit 10 in the first clock
Under the control of signal end GCK, the voltage output of end GSTV is input a signal into pull-up node PU.
Sub-circuit 30 is pulled up under the control of pull-up node PU, by the voltage output of second clock signal end GCB to signal
Output terminal Gout.
Drop-down control sub-circuit 20 is under the control of the first clock signal terminal GCK and pull-up node PU, by first voltage end
The voltage of VGL and the first clock signal terminal GCK are transmitted to pull-down node PD.
Sub-circuit 40 is pulled down under the control of pull-down node PU, the voltage of second voltage end VGH is transmitted to signal output
Hold Gout.
In the case where the shift register cell includes third output sub-circuit 70, which exports sub-circuit 70 the
Under the control of one voltage end VGL, by the voltage output of first voltage end VGL to LED control signal output terminal OUT_EMS.
In some embodiments, in phase III T3, fourth stage T4, in some embodiments, method includes：
Sub-circuit 30 is pulled up under the control of pull-up node PU, by the voltage output of second clock signal end GCB to signal
Output terminal Gout.
The voltage of first clock signal terminal GCK is transmitted to by drop-down control sub-circuit 20 under the control of pull-up node PU
Pull-down node PD.
Sub-circuit 40 is pulled down under the control of pull-down node PD, is closed.
In the case where the shift register cell includes third output sub-circuit 70, third output sub-circuit 70 is being believed
Under the control of number output terminal Gout, by the voltage output of second voltage end VGH to LED control signal output terminal OUT_EMS.
In some embodiments, include the first output sub-circuit 50 and second in the shift register cell and export sub-circuit
In the case of 60, T1, phase III T3 in the first stage, the first output sub-circuit 50 is in the control of third clock signal terminal GCK1
Under, by the voltage output of signal output end Gout to reset signal output terminal OUT_RST, and by the voltage of second voltage end VGH
It exports to gating signal output terminal OUT_Gate.
In second stage T2, fourth stage T4, second exports sub-circuit 20 under the control of the 4th clock signal terminal GCB1,
By the voltage output of signal output end Gout to gating signal output terminal OUT_Gate, and the voltage of second voltage end VGH is defeated
Go out to reset signal output terminal OUT_Gate.
In the 5th stage P5, drop-down control sub-circuit 20 is under the control of the first clock signal terminal GCK, by first voltage end
The voltage of VGL is transmitted to pull-down node PD.
Sub-circuit 40 is pulled down under the control of pull-down node PD, the voltage of second voltage end VGH is transmitted to signal output
Hold Gout.
In the case where pull-up control sub-circuit 10 includes voltage holding sub-circuit 11, in the 5th stage P5, voltage is protected
Sub-circuit 11 is held under the control of second clock signal end CGB and pull-down node PD, the voltage that second voltage end VGH is exported
It is stored.
In the 6th stage P6, drop-down sub-circuit 40 continues the voltage of second voltage end VGH being transmitted to signal output end
Gout。
In the case where pull-up control sub-circuit 10 includes voltage holding sub-circuit 11, in the 6th stage P6, voltage is protected
Sub-circuit 11 is held under the control of second clock signal end CGB and pull-down node PD, by storage voltage output to pull-up node
PU。
In some embodiments, in the 5th stage P5, the 6th stage P6, in some embodiments, the first output sub-circuit
50th, the second output sub-circuit 60 is alternately exported the voltage of signal output end Gout respectively to reset signal output terminal OUT_RST
With gating signal output terminal OUT_Gate.
In the case where the shift register cell includes third output sub-circuit 70, which exports sub-circuit 70 the
Under the control of one voltage end VGL, by the voltage output of first voltage end VGL to LED control signal output terminal OUT_EMS.
On this basis, it before starting after the 6th stage P6 to next image frame, repeats in some embodiments, the
Five stage P5 and the 6th stage P6.
When using each sub-circuit as shown in Figure 5, in each stage of a picture frame, in the shift register cell
The on off operating mode of each transistor is as described above, details are not described herein again.In some embodiments, driving method has and aforementioned reality
The shift register cell for applying example offer has identical technique effect, and details are not described herein again.
One of ordinary skill in the art will appreciate that：Realize that all or part of step of embodiment of the method in this specification can
To be completed by the relevant hardware of program instruction, aforementioned program can be stored in a computer read/write memory medium,
The step of program when being executed, is performed and is included in some embodiments, embodiment of the method；And aforementioned storage medium includes：
The various media that can store program code such as ROM, RAM, magnetic disc or CD.
The above, only specific embodiment of the present utility model, but the scope of protection of the utility model is not limited to
In this, in the technical scope that any one skilled in the art discloses in the utility model, variation can be readily occurred in
Or replace, it should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model should be with the power
Subject to the protection domain of profit requirement.
Claims (14)
1. a kind of shift register cell, which is characterized in that including：First output sub-circuit, the second output sub-circuit and the
At least two sub-circuits in three output sub-circuits；The shift register cell further includes front-end circuit；
The front-end circuit and signal input part, the first clock signal terminal, second clock signal end, first voltage end, the second electricity
Pressure side and signal output end connection, the front-end circuit are used to receive the voltage of the signal input part, and described first
Clock signal terminal, the second clock signal end control under, by the voltage of the second clock signal end or it is described second electricity
The voltage output of pressure side is to the signal output end；
The first output sub-circuit and third clock signal terminal, the second voltage end, the signal output end, reset signal
Output terminal and the connection of gating signal output terminal；The first output sub-circuit is used for the control in the third clock signal terminal
Under, by the voltage output of the signal output end to the reset signal output terminal, and the voltage at the second voltage end is defeated
Go out to the gating signal output terminal；
The second output sub-circuit and the 4th clock signal terminal, the second voltage end, the signal output end, the reset
Signal output end and gating signal output terminal connection；The second output sub-circuit is used in the 4th clock signal
Under the control at end, by the voltage output of the signal output end to the gating signal output terminal, and by the second voltage end
Voltage output to the reset signal output terminal；
It third output sub-circuit and the first voltage end, the signal output end, the second voltage end and shines
Control signal output connects；Third output sub-circuit is used under the control of the signal output end, by the described second electricity
The voltage output of pressure side is to the LED control signal output terminal；Alternatively, the third output sub-circuit is used for described first
Under the control of voltage end, by the voltage output at the first voltage end to the LED control signal output terminal.
2. shift register cell according to claim 1, which is characterized in that the first output sub-circuit includes first
Transistor and second transistor；
The grid connection third clock signal terminal of the first transistor, the first pole connection signal output end, second
Pole is connected with the reset signal output terminal；
The grid of the second transistor connects the third clock signal terminal, and the first pole is connected with the gating signal output terminal
It connects, the second pole is connected with the second voltage end.
3. shift register cell according to claim 1, which is characterized in that the second output sub-circuit includes third
Transistor and the 4th transistor；
Grid connection the 4th clock signal terminal of the third transistor, the first pole connection signal output end, second
Pole is connected with the gating signal output terminal；
The grid of 4th transistor connects the 4th clock signal terminal, and the first pole connects the reset signal output terminal,
Second pole is connected with the second voltage end.
4. shift register cell according to claim 1, which is characterized in that the third output sub-circuit includes the tenth
Three transistors and the 14th transistor；
The grid of 13rd transistor and the first pole connect the first voltage end, the second pole and the LED control signal
Output terminal is connected；
The grid of 14th transistor connects the signal output end, and the first pole connects the LED control signal output
End, the second pole is connected with the second voltage end；
Wherein, the breadth length ratio of the 14th transistor is more than the breadth length ratio of the 13rd transistor.
5. according to claim 1-4 any one of them shift register cells, which is characterized in that the front-end circuit includes upper
Draw control sub-circuit, drop-down control sub-circuit, pull-up sub-circuit, drop-down sub-circuit；
The pull-up control sub-circuit is connect with signal input part, the first clock signal terminal, pull-up node；Pull-up control
Circuit is used under the control of first clock signal terminal, and the voltage output of the signal input part to the pull-up is saved
Point；
The pull-up sub-circuit is connect with second clock signal end, the pull-up node and signal output end；The upper rock
Circuit is used under the control of the pull-up node, and the voltage output of the second clock signal end to the signal is exported
End；
The drop-down control sub-circuit is saved with first clock signal terminal, first voltage end, the pull-up node and drop-down
Point connection；The drop-down control sub-circuit is used under the control of first clock signal terminal and the pull-up node, by institute
The voltage for stating first voltage end and first clock signal terminal is transmitted to the pull-down node；
The drop-down sub-circuit is connect with the pull-down node, second voltage end and the signal output end；The lower rock
Circuit is used under the control of the pull-down node, and the voltage at the second voltage end is transmitted to the signal output end.
6. shift register cell according to claim 5, which is characterized in that the pull-up control sub-circuit includes the 5th
Transistor；The grid of 5th transistor connects first clock signal terminal, and the first pole connects the signal input part, the
Two poles are connected with the pull-up node.
7. shift register cell according to claim 6, which is characterized in that the pull-up control sub-circuit is also connected with the
One voltage end；The pull-up control sub-circuit further includes the 6th transistor；
The grid of 6th transistor connects the first voltage end, and the first pole connects the second pole of the 5th transistor,
The second level is connected with the pull-up node.
8. shift register cell according to claim 6, which is characterized in that the shift register cell further includes electricity
Pressure keeps sub-circuit；
The voltage keeps sub-circuit and the pull-down node, the second pole of the 5th transistor, the second clock signal
End and second voltage end connection；The voltage keep sub-circuit be used for the second clock signal end and it is described under
Under the control for drawing node, the voltage that the second voltage end exports is stored, and by the voltage output of storage to described the
Second pole of five transistors.
9. shift register cell according to claim 8, which is characterized in that the voltage keeps sub-circuit to include the 7th
Transistor and the 8th transistor；
The grid of 7th transistor connects the second clock signal end, and the first pole connects the second of the 5th transistor
Pole, the second pole are connected with the first pole of the 8th transistor；
The grid of 8th transistor connects the pull-down node, and the second pole is connected with the second voltage end.
10. shift register cell according to claim 5, which is characterized in that the drop-down control sub-circuit includes the
Nine transistors and the tenth transistor；
Grid connection first clock signal terminal of 9th transistor, the first pole connection first voltage end, second
Pole is connected with the pull-down node；
The grid of tenth transistor connects the pull-up node, and the first pole connects first clock signal terminal, the second pole
It is connected with the pull-down node.
11. shift register cell according to claim 5, which is characterized in that the pull-up sub-circuit includes the 11st
Transistor and the first capacitance；
The grid connection pull-up node of 11st transistor, the first pole connection second clock signal end, first
Pole is connected with the signal output end；
One end of first capacitance connects the grid of the 11st transistor, and the of the other end and the 11st transistor
Two poles are connected.
12. shift register cell according to claim 5, which is characterized in that the drop-down sub-circuit includes the 12nd
Transistor and the second capacitance；
The grid of tenth two-transistor connects the pull-down node, and the first pole connects the signal output end, the second pole with
The second voltage end is connected；
One end of second capacitance connects the grid of the tenth two-transistor, and the of the other end and the tenth two-transistor
One pole is connected.
13. a kind of gate driving circuit, which is characterized in that including multiple cascade as claim 1-12 any one of them is moved
Bit register unit；
The signal input part connection initial signal end of first order shift register cell；
Other than the first order shift register cell, the signal output end connection of upper level shift register cell is next
The signal input part of grade shift register cell.
14. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 13.
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| CN201721715303.7U CN207489447U (en) | 2017-12-11 | 2017-12-11 | A kind of shift register cell, gate driving circuit, display device |
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| CN201721715303.7U CN207489447U (en) | 2017-12-11 | 2017-12-11 | A kind of shift register cell, gate driving circuit, display device |
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| CN107784977A (en) * | 2017-12-11 | 2018-03-09 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN109698006A (en) * | 2019-02-19 | 2019-04-30 | 京东方科技集团股份有限公司 | Shift register and its driving method, cascade driving circuit and display device |
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| CN113192463A (en) * | 2021-05-11 | 2021-07-30 | 合肥京东方卓印科技有限公司 | Light emitting control shift register, gate driving circuit, display device and method |
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| CN111445851A (en) * | 2020-04-30 | 2020-07-24 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof and display device |
| US11495178B2 (en) | 2020-04-30 | 2022-11-08 | Beijing Boe Technology Development Co., Ltd. | Pixel circuit having a plurality of enable signals and gate signals in opposite phase and driving method thereof |
| CN113192463A (en) * | 2021-05-11 | 2021-07-30 | 合肥京东方卓印科技有限公司 | Light emitting control shift register, gate driving circuit, display device and method |
| CN113920937A (en) * | 2021-07-09 | 2022-01-11 | 北京京东方技术开发有限公司 | Display substrate and display device |
| CN113920937B (en) * | 2021-07-09 | 2022-09-09 | 北京京东方技术开发有限公司 | Display substrate and display device |
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