CN105719613B - array substrate, display panel and display device - Google Patents
array substrate, display panel and display device Download PDFInfo
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- CN105719613B CN105719613B CN201610254962.9A CN201610254962A CN105719613B CN 105719613 B CN105719613 B CN 105719613B CN 201610254962 A CN201610254962 A CN 201610254962A CN 105719613 B CN105719613 B CN 105719613B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
Abstract
This application discloses a kind of array substrate, display panel and display devices.The array substrate includes underlay substrate, the array substrate includes viewing area and non-display area, gate driving circuit is equipped in non-display area, gate driving circuit includes shifting deposit unit, and shifting deposit unit includes the first capacitance and the second capacitance, clock signal input terminal and gate drive signal output terminal；First capacitance and the second capacitance are electrically connected respectively with clock signal input terminal and gate drive signal output terminal；The orthographic projection of any pole plate of first capacitance and any pole plate plane where underlay substrate of the second capacitance is at least partly overlapping.The application reduces the occupied spatial area of shifting deposit unit, is conducive to reduce the frame size of display by the way that two capacitive stacks in shifting deposit unit are set.
Description
Technical field
This application involves display technology fields, and in particular to a kind of array substrate and the display comprising the array substrate
Panel and display device.
Background technology
In display technology field, gate driving circuit is arranged in the range of the frame of liquid crystal display.Gate driving circuit
The shift-register circuit being usually made of thin film transistor (TFT) and capacitance.The development trend of the frame of liquid crystal display is at present
More and more narrow, the electrical parameter of breadth length ratio and capacitance yet with thin film transistor (TFT) in shift-register circuit is (including pole
The area of plate) limitation so that the size of frame is difficult to further reduce in the case where not changing current electrical parameter.
In general, shift-register circuit includes multiple shifting deposit units, each shifting deposit unit is used for display
On a line sub-pixel output scanning signal.In a kind of existing shifting deposit unit design, pass through clock signal control gate
The displacement output of input signal.Specifically, pull-up node, pull-down node and capacitance are included in shifting deposit unit.It is existing to set
The capacitance with difference in functionality is respectively arranged at the different zones of display frame scope in meter, and capacitance is put down with display surface
Projection and no overlap in capable plane.Capacitance occupied area is larger in shifting deposit unit, and due to the limitation of capacitance,
The area of capacitor plate can not be further reduced so that the frame size of display is difficult to further reduce.
The content of the invention
In view of this, it is desired to be able to the further structure design of optimization shift register, so as to reduce the frame of display
Size.In order to solve the above-mentioned technical problem, this application provides a kind of array substrate, display panel and display devices.
The one side of the embodiment of the present invention provides a kind of array substrate, and including underlay substrate, the array substrate includes
Viewing area and non-display area, the non-display area is interior to be equipped with gate driving circuit, and the gate driving circuit includes shift LD
Unit, the shifting deposit unit include the first capacitance and the second capacitance, clock signal input terminal and gate drive signal output
End；First capacitance and second capacitance respectively with the clock signal input terminal and the gate drive signal output terminal
Electrical connection；Any pole plate of any pole plate of first capacitance and second capacitance plane where the underlay substrate
Orthographic projection is at least partly overlapping.
The another aspect of the embodiment of the present invention provides a kind of display panel, including above-mentioned array substrate.
The another aspect of the embodiment of the present invention provides a kind of display device, including above-mentioned display panel.
Array substrate provided in an embodiment of the present invention, display panel and display device, by will be in shifting deposit unit
Capacitive stack is set, and reduces the occupied spatial area of shifting deposit unit, is conducive to reduce the frame size of display.
Description of the drawings
Non-limiting example is described in detail with reference to what the following drawings was made by reading, other features,
Objects and advantages will become more apparent upon：
Fig. 1 is the circuit structure signal of one embodiment of the shifting deposit unit in the array substrate that the application provides
Figure；
Fig. 2 is the schematic side view of the one embodiment for the array substrate that the application provides；
Fig. 3 is the schematic side view of another embodiment of the array substrate that the application provides；
Fig. 4 is the diagrammatic cross-section of capacitance structure in the shifting deposit unit according to the application one embodiment；
Fig. 5 is the diagrammatic cross-section for including one embodiment of the array substrate of capacitance structure shown in Fig. 4；
Fig. 6 is the diagrammatic cross-section of capacitance structure in the shifting deposit unit according to another embodiment of the application；
Fig. 7 is the diagrammatic cross-section for including one embodiment of the array substrate of capacitance structure shown in Fig. 6.
Specific embodiment
The application is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining related invention rather than the restriction to the invention.It also should be noted that in order to
Convenient for description, illustrated only in attached drawing and invent relevant part with related.
It should be noted that in the case where there is no conflict, the feature in embodiment and embodiment in the application can phase
Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
It please refers to Fig.1, one embodiment of the shifting deposit unit in the array substrate provided it illustrates the application
Electrical block diagram.In the present embodiment, array substrate includes gate driving circuit, and gate driving circuit is included by multiple shiftings
Position deposit unit cascades the shift register to be formed.As shown in Figure 1, shifting deposit unit 100 includes the first transistor M1, second
Transistor M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7,
When eight transistor M8 and the 9th transistor M9, the first capacitance C1, the second capacitance C2, the first clock signal input terminal CK, second
Clock signal input part CKB, first grid shift signal input terminal INn, gate drive signal output terminal Gn, reset signal input terminal
RST, second grid shift signal input terminal Gn+1, the first control terminal DIR1, the second control terminal DIR2 and first voltage signal
Input terminal VGL, n are integer and n>0.Wherein, the first grid shift signal input terminal IN1 of first order shifting deposit unit is used for
Receiving grid pole shift signal STV, in addition to first order shifting deposit unit, the first grid displacement of n-th grade of shifting deposit unit
The signal that signal input part INn exports for the gate drive signal output terminal Gn-1 of (n-1)th grade of shifting deposit unit of reception.The
The gate drive signal output terminal Gn+1 that two grid shift signal input terminal Gn+1 are used to receive next stage shifting deposit unit is defeated
The signal gone out.First voltage signal input part VGL inputs constant low level signal.Pull-down node PD in shifting deposit unit
It is connected by the first capacitance C1 with second clock signal input part CKB, pull-up node PU passes through the second capacitance C2 and raster data model
Signal output part Gn connections.
As shown in Figure 1, in shifting deposit unit 100, the first transistor M1 is by second grid shift signal input terminal Gn+
The signal control of 1 input, for connecting the second control terminal DIR2 and pull-up node PU；Second transistor M2 is by pull-down node PD's
Electric potential signal controls, for connecting first voltage signal input part VGL and pull-up node PU；Third transistor M3 is by pull-up node
The electric potential signal control of PU, for connecting first voltage signal input part VGL and pull-down node PD；4th transistor M4 is by pulling up
The electric potential signal control of node PU, for connecting second clock signal input part CKB and gate drive signal output terminal Gn；5th
Transistor M5 is controlled by the electric potential signal of pull-down node PD, is believed for connecting first voltage signal input part VGL with raster data model
Number output terminal Gn；The signal that 6th transistor M6 is inputted by the first clock signal input terminal CK controls, for connecting first voltage
Signal input part VGL and gate drive signal output terminal Gn；The signal that 7th transistor M7 is inputted by reset signal input terminal RST
Control, for connecting first voltage signal input part VGL and pull-up node PU；8th transistor M8 is by reset signal input terminal
The signal control of RST inputs, for connecting first voltage signal input part VGL and gate drive signal output terminal Gn；9th is brilliant
The signal that body pipe M9 is inputted by first grid shift signal input terminal INn controls, for connecting the first control terminal DIR1 and pull-up
Node PU.
With reference to figure 2, it illustrates the schematic side views of one embodiment of the array substrate of the application offer.In embodiment
In, array substrate 200 includes underlay substrate 20.As shown in Fig. 2, array substrate 200 includes viewing area 211 and non-display area 212.
Gate driving circuit is equipped in non-display area 212, gate driving circuit includes shifting deposit unit.Shifting deposit unit can wrap
Include the first capacitance C21 and the second capacitance C22, clock signal input terminal and gate drive signal output terminal.Wherein, the first capacitance
C21 can be that the first capacitance C1, the second capacitance C22 in shifting deposit unit 100 shown in Fig. 1 can be that displacement is posted shown in Fig. 2
The second capacitance C2 in memory cell 100, when clock signal input terminal can be second in shifting deposit unit 100 shown in Fig. 1
Clock signal input part CKB, gate drive signal output terminal can be the raster data model letter in shifting deposit unit 100 shown in Fig. 1
Number output terminal Gn.First capacitance C21 can be electrically connected with clock signal input terminal, and the second capacitance can be defeated with gate drive signal
Outlet is electrically connected.First capacitance C21, which includes the first pole plate C211 and the second pole plate C212, the second capacitance C22, includes tri-electrode
C221 and quadripolar plate C222.In concrete implementation, the first pole plate C211 or the second pole plate C212 of the first capacitance C21 can be with
It is electrically connected with clock signal input terminal, for receiving clock signal；The tri-electrode C221 or quadripolar plate of second capacitance C22
C222 can be electrically connected with gate drive signal output terminal, for exporting gate drive signal.
In the present embodiment, the first pole plate C211 and the second pole plate C212 of the first capacitance C21, the of the second capacitance C22
Tri-electrode C221 and quadripolar plate C222 planar has orthographic projection, any pole plate of the first capacitance C21 in underlay substrate
The orthographic projection of any pole plate (C221 or C222) plane where underlay substrate of (C211 or C212) and the second capacitance C22 is extremely
Small part overlaps.
As shown in Fig. 2, the first pole plate C211 and the second pole plate C212 of the first capacitance C21 are in 20 place plane of underlay substrate
Inside there is the first orthographic projection 21, the tri-electrode C221 and quadripolar plate C222 of the second capacitance C22 is flat where underlay substrate 20
There is the second orthographic projection 22, the first orthographic projection 21 and 22 part of the second orthographic projection overlap in face.
With the array substrate of the existing different zones that first capacitance and the second capacitance are arranged to display frame scope
Compare, the array substrate that the present embodiment is provided can the occupied area of reduction of gate driving circuit, so as to reduce display
The width of frame.The area that first orthographic projection 21 and the second orthographic projection 22 overlap is bigger, the occupied area of gate driving circuit
It is smaller.
In concrete implementation, the capacitance of the first capacitance C21 and the second capacitance C22 can be equal or unequal, and first
The area of any pole plate of capacitance C21 and any pole plate of the second capacitance C22 can also be equal or different, therefore the first capacitance
Any pole plate of C21 and any pole plate of the second capacitance C22 can not phases in the frontal projected area of 20 place plane of underlay substrate
Deng.
Shifting deposit unit in array substrate provided in this embodiment can have circuit structure shown in FIG. 1, also may be used
Think other circuit structures for including two capacitances being connected respectively with clock signal input terminal and gate drive signal output terminal.
It is appreciated that pixel electrode, public electrode, thin film transistor (TFT) array, scan line, number can be equipped in the viewing area of array substrate
According to line etc., the gate driving circuit in array substrate provided in this embodiment is connected with scan line, is the pixel battle array in viewing area
Row provide gate drive signal.
With further reference to Fig. 3, it illustrates the schematic side views of another embodiment of the array substrate of the application offer.
In array substrate shown in Fig. 3, array substrate 300 includes underlay substrate 30.As shown in figure 3, array substrate 300 includes display
Area 311 and non-display area 312.Gate driving circuit is equipped in non-display area 312, gate driving circuit includes shift LD list
Member.Shifting deposit unit can include the first capacitance C31 and the second capacitance C32, clock signal input terminal and gate drive signal
Output terminal.Wherein, the first capacitance C31 can be the first capacitance C1, the second capacitance C32 in shifting deposit unit 100 shown in Fig. 1
Can be the second capacitance C2 in shifting deposit unit 100 shown in Fig. 2, clock signal input terminal can be that displacement is posted shown in Fig. 1
Second clock signal input part CKB in memory cell 100, gate drive signal output terminal can be shift LD list shown in Fig. 1
Gate drive signal output terminal Gn in member 100.First capacitance C31 can be electrically connected with clock signal input terminal, the second capacitance
C32 can be electrically connected with gate drive signal output terminal.First capacitance C31 includes the first pole plate C311 and the second pole plate C312,
Second capacitance C32 includes tri-electrode C321 and quadripolar plate C322.The first pole plate C311 of first capacitance C31 and the second pole plate
C312 has the first orthographic projection 31, the tri-electrode C321 and the second pole plate of the second capacitance C32 in 30 place plane of underlay substrate
C322 has the second orthographic projection 32 in 30 place plane of underlay substrate.
Unlike embodiment illustrated in fig. 2, in array substrate shown in Fig. 3, two pole plates of the second capacitance C32 are in substrate
Second orthographic projection 32 of 30 place plane of substrate covers two pole plates of the first capacitance C31 the of 30 place plane of underlay substrate
One orthographic projection 31.That is, the first capacitance C31 and the second capacitance C32 are opposite disposed on the direction perpendicular to underlay substrate,
The area of at least one pole plate of the area of two pole plates of first capacitance C31 less than the second capacitance C32.With implementation shown in Fig. 2
Example is compared, and array substrate shown in Fig. 3 can reduce the first capacitance C31 to a greater degree and the second capacitance C32 is put down in underlay substrate
The sum of occupied area on face can further reduce the frame size of display.
In further embodiments, two pole plates of the first capacitance C31 are just being thrown the first of 30 place plane of underlay substrate
Shadow 31 can cover second orthographic projection 32 of two pole plates in 30 place plane of underlay substrate of the second capacitance C32.That is,
First capacitance C31 and the second capacitance C32 is opposite disposed on the direction of underlay substrate 30, correspondingly, the first capacitance C31
Two pole plates area more than the second capacitance C32 at least one pole plate area.
In a further embodiment, shifting deposit unit includes be arranged in order on the direction of underlay substrate the
One metal layer, second metal layer and first electrode layer.With further reference to Fig. 4, it illustrates according to the application one embodiment
Shifting deposit unit in capacitance structure diagrammatic cross-section.As shown in figure 4, the first metal layer 41, second metal layer 42, first
Electrode layer 43 is arranged in order on the direction of underlay substrate 40.In the present embodiment, shifting deposit unit further includes
Two electrode layers 44.The shifting deposit unit of the present embodiment can include circuit structure shown in FIG. 1.In Fig. 4, the first capacitance
C41 can be the first capacitance C1 in shifting deposit unit 100 shown in Fig. 1, including the first pole plate C411 and the second pole plate C412,
Second capacitance C42 can be the second capacitance C2 in shifting deposit unit 100 shown in Fig. 1, including tri-electrode C421 and the 4th
Pole plate C422.Wherein, the first metal layer 41 include tri-electrode C421, second metal layer 42 include quadripolar plate C422, first
Electrode layer 43 includes the first pole plate C411, and the second electrode lay 44 includes the second pole plate C412.First pole plate C411, the second pole plate
C412 planar has the first projection in underlay substrate 40, and tri-electrode C421, quadripolar plate C422 are in underlay substrate 40
Planar there is the second projection, the first projection and the second projection are at least partly overlapping.
The first insulating layer 46 is equipped between first pole plate C411 and the second pole plate C412, the first insulating layer 46 can be used as the
Medium between two pole plates of one capacitance C41 is equipped with second insulating layer 47 between tri-electrode C421 and quadripolar plate C422,
Second insulating layer 47 can be as the medium between two pole plates of the second capacitance C42.
Further, organic film 45 can be equipped between the first capacitance C41 and the second capacitance C42.In the present embodiment,
First capacitance C41 and the second capacitance C42 laminations are set, the second pole plate C412 of the first capacitance C41, the second of the second capacitance C42
Pole plate C422 and organic film 45 form capacitance Cgc1.The size of capacitance and the area of two-plate face and Jie of medium
Electric constant is directly proportional, and the distance between two-plate is inversely proportional.In the present embodiment, in order to reduce the capacitance of capacitance Cgc1 with
It is avoided to influence the normal work of shifting deposit unit, the smaller organic matter of dielectric constant can be chosen as organic film 45,
And/or increase the thickness of organic film 45.Further, the dielectric constant of organic film 45 is less than the dielectric of the first insulating layer 46
Constant, and the dielectric constant of organic film 45 is less than the dielectric constant of second insulating layer 47.The thickness of organic film 45 is more than the
The thickness of one insulating layer 46, and the thickness of organic film 45 is more than the thickness of second insulating layer 47.It is organic in concrete implementation
The dielectric constant range of film layer can be with selected as：1.5-4, thickness range can be 1 μm -4 μm with selected as.
With reference to figure 5, it illustrates the section signals of one embodiment of the array substrate comprising capacitance structure shown in Fig. 4
Figure.In the present embodiment, it is equipped with the gate driving circuit comprising shifting deposit unit in the non-display area of array substrate.Such as Fig. 5
Shown, shifting deposit unit can include thin film transistor (TFT).On the direction of underlay substrate 40, shifting deposit unit can
To include the first metal layer 41, second metal layer 42, first electrode layer 43 and the second electrode lay 44.Wherein the first metal layer 41 is used
In the grid for forming thin film transistor (TFT), second metal layer 42 is used to be formed source electrode and the drain electrode of thin film transistor (TFT).First electrode layer
41 and the material of the second electrode lay 42 can be ITO, or other materials, the present embodiment comparison are not particularly limited.
In the present embodiment, shifting deposit unit can also include clock signal input terminal and gate drive signal exports
End, wherein, clock signal input terminal can be the second clock signal input part CKB of shifting deposit unit 100 shown in Fig. 1, grid
Pole driving signal output end can be the gate drive signal output terminal Gn of shifting deposit unit 100 shown in FIG. 1.First capacitance
C41 can be electrically connected with second clock signal input part CKB, and the second capacitance C42 can be with gate drive signal output terminal Gn electricity
Connection.In some embodiments, shifting deposit unit further includes pull-up node (pull-up node PU as shown in Figure 1) and drop-down section
Point (pull-down node PD as shown in Figure 1), wherein, it is high that pull-up node PU can be used for the output of control gate driving signal output end
Level signal, pull-down node PD can be used for control gate driving signal output end and recover low level signal.First capacitance C41 and
Second capacitance C42 is electrically connected respectively with pull-down node PD and pull-up node PU.
In the present embodiment, pixel electrode, public electrode, scan line, data can be equipped in the viewing area of array substrate
Line and thin film transistor (TFT) array.When making array substrate, the first metal layer 41 shown in Fig. 5 can with it is thin in viewing area
The grid of film transistor array is formed on same mask plate, and second metal layer 42 can be with the thin film transistor (TFT) battle array in viewing area
The source electrode of row and drain electrode are formed on same mask plate.First electrode layer 43 can be covered with the pixel electrode in viewing area same
It is formed on diaphragm plate, the second electrode lay 44 can be formed with the public electrode in viewing area on same mask plate.It is that is, aobvious
Show that the grid of the thin film transistor (TFT) in the grid and non-display area of the thin film transistor (TFT) in area is located at same layer, it is thin in viewing area
The source electrode of film transistor, the source electrode of drain electrode and the thin film transistor (TFT) in non-display area, drain electrode are in same layer, non-display area
The first pole plate C411 of first capacitance C41 can be located at same layer with the pixel electrode in viewing area, and first in non-display area
The second pole plate C412 of capacitance C41 can be located at same layer with the pixel electrode in viewing area.
In the embodiment described in above-mentioned combination Fig. 4 and Fig. 5, by the way that the first capacitance C41 and the second capacitance C42 laminations are set
It puts, and organic film is set between the first capacitance C41 and the second capacitance C42, can effectively reduce shared by shifting deposit unit
Frame area, while the normal work of gate driving circuit is not influenced.
In some embodiments, except be arranged in order on the direction perpendicular to underlay substrate the first metal layer, second
Outside metal layer and first electrode layer, shifting deposit unit can also include being arranged between first electrode layer and second metal layer
The 3rd metal layer.In touch array substrate, the public electrode in viewing area can be multiplexed with touch control electrode, except pixel
Touch control electrode line is also provided with outside electrode, public electrode and thin film transistor (TFT) array, in viewing area, for common electrical
Transmit touching signals in pole.When making array substrate, the 3rd metal layer of shifting deposit unit can be with touch array substrate
Touch control electrode line formed on same mask plate, i.e. the 3rd metal layer can be located at same layer with touch control electrode line.
With further reference to Fig. 6, it illustrates capacitance structures in another embodiment of the array substrate of the application offer
Diagrammatic cross-section.Shifting deposit unit includes the first metal layer 61, second being arranged in order on the direction of underlay substrate
Metal layer 62, the 3rd metal layer 64 and first electrode layer 63.The shifting deposit unit of the present embodiment can include shown in FIG. 1
Circuit structure.In figure 6, the first capacitance C61 can be the first capacitance C1 in shifting deposit unit 100 shown in Fig. 1, including the
One pole plate C611 and the second pole plate C612, the second capacitance C62 can be the second capacitance in shifting deposit unit 100 shown in Fig. 1
C2, including tri-electrode C621 and quadripolar plate C622.Wherein, the first metal layer 61 includes tri-electrode C621, the second metal
Layer 62 includes quadripolar plate C622, and first electrode layer 63 includes the first pole plate C611, and the 3rd metal layer 64 includes the second pole plate
C612.First pole plate C611, the second pole plate C612 planar have the first projection, tri-electrode in underlay substrate 60
C621, quadripolar plate C622 planar have the second projection, the first projection and the second projection at least portion in underlay substrate 60
Divide overlapping.
The first insulating layer 66 is equipped between first pole plate C611 and the second pole plate C612, the first insulating layer 66 can be used as the
Medium between two pole plates of one capacitance C61, (i.e. 61 He of the first metal layer between tri-electrode C621 and quadripolar plate C622
Between second metal layer 62) be equipped with second insulating layer 67, second insulating layer 67 can as the second capacitance C62 two pole plates it
Between medium.
Further, organic film 65 can be equipped between the first capacitance C61 and the second capacitance C62.In the present embodiment,
First capacitance C61 and the second capacitance C62 laminations are set, the second pole plate C612 of the first capacitance C61, the second of the second capacitance C62
Pole plate C622 and organic film 65 form capacitance Cgc2.It is similar with embodiment illustrated in fig. 4, in order to reduce the capacitance of capacitance Cgc2
Measure influences the normal work of shifting deposit unit to avoid it, can choose the smaller organic matter of dielectric constant as organic film
65 and/or increase organic film 65 thickness.Further, the dielectric constant of organic film 65 is less than the first insulating layer 66
Dielectric constant, and the dielectric constant of organic film 65 is less than the dielectric constant of second insulating layer 67.The thickness of organic film 65 is big
In the thickness of the first insulating layer 66, and the thickness of organic film 65 is more than the thickness of second insulating layer 67.In concrete implementation,
The dielectric constant range of organic film can be with selected as：1.5-4, thickness range can be 1 μm -4 μm with selected as.
With continued reference to Fig. 7, the section it illustrates one embodiment of the array substrate comprising capacitance structure shown in Fig. 6 shows
It is intended to.In the present embodiment, it is equipped with the gate driving circuit comprising shifting deposit unit in the non-display area of array substrate.Such as figure
Shown in 7, shifting deposit unit can include thin film transistor (TFT), on the direction of underlay substrate 60, shifting deposit unit
It can include the first metal layer 61, second metal layer 62,63 and the 3rd metal layer 64 of first electrode layer.Wherein the first metal layer 61
For forming the grid of thin film transistor (TFT), second metal layer 62 is used to be formed source electrode and the drain electrode of thin film transistor (TFT).First electrode
The material of layer 63 can be ITO.
In the present embodiment, pixel electrode, public electrode, scan line, data can be equipped in the viewing area of array substrate
Line and thin film transistor (TFT) array.When making array substrate, the first metal layer 61 shown in Fig. 7 can with it is thin in viewing area
The grid of film transistor array is formed on same mask plate, and second metal layer 62 can be with the thin film transistor (TFT) battle array in viewing area
The source electrode of row and drain electrode are formed on same mask plate.First electrode layer 63 can be covered with the public electrode in viewing area same
It is formed on diaphragm plate, the 3rd metal layer 64 can be formed with the touch control electrode line in viewing area on same mask plate.That is,
The grid of thin film transistor (TFT) in the grid and non-display area of thin film transistor (TFT) in viewing area is located at same layer, in viewing area
The source electrode of thin film transistor (TFT), the source electrode of drain electrode and the thin film transistor (TFT) in non-display area, drain electrode are in same layer, non-display area
The first pole plate C621 of the second capacitance C62 can be located at same layer with the pixel electrode in viewing area, in non-display area
The second pole plate C622 of two capacitance C62 can be located at same layer with the touch control electrode line in viewing area.
Unlike embodiment illustrated in fig. 5, shifting deposit unit includes the 3rd metal layer 64 in embodiment illustrated in fig. 7,
The second pole plate C612 of first capacitance C61 can be arranged on the 3rd metal layer 64.It, can when making the array substrate of touch
To form the touch control electrode line in the second pole plate and viewing area of the first capacitance using the same process, do not increasing making complexity
While reduce the occupied spatial area of gate driving circuit, be conducive to the design of narrow frame.
The embodiment of the present application additionally provides a kind of display panel, including the described array base of any of the above-described embodiment
Plate.When the display panel is used for liquid crystal display, the color membrane substrates opposite disposed with above-mentioned array substrate can also be included.
The embodiment of the present application additionally provides a kind of display device, includes the display panel of above-described embodiment description.
Array substrate, display panel and the display device of various embodiments above description, by will be in shifting deposit unit
Two capacitive stacks set, reduce the occupied spatial area of shifting deposit unit, be conducive to reduce display frame
Size.
The preferred embodiment and the explanation to institute's application technology principle that above description is only the application.People in the art
Member should be appreciated that invention scope involved in the application, however it is not limited to the technology that the particular combination of above-mentioned technical characteristic forms
Scheme, while should also cover in the case where not departing from the inventive concept, it is carried out by above-mentioned technical characteristic or its equivalent feature
The other technical solutions for being combined and being formed.Such as features described above has similar work(with (but not limited to) disclosed herein
The technical solution that the technical characteristic of energy is replaced mutually and formed.
Claims (14)
1. a kind of array substrate, including underlay substrate, which is characterized in that the array substrate includes viewing area and non-display area,
Gate driving circuit is equipped in the non-display area, the gate driving circuit includes shifting deposit unit, the shift LD
Unit includes the first capacitance and the second capacitance, clock signal input terminal and gate drive signal output terminal；
First capacitance and second capacitance export respectively with the clock signal input terminal and the gate drive signal
End electrical connection；
Pull-down node in the shifting deposit unit is electrically connected by first capacitance with the clock signal input terminal, institute
The pull-up node stated in shifting deposit unit is connected by second capacitance with the gate drive signal output terminal；
First capacitance include the first pole plate and the second pole plate, the first pole plate or the second pole plate of first capacitance with it is described
Clock signal input terminal is electrically connected, and second capacitance includes tri-electrode and quadripolar plate, the 3rd pole of second capacitance
Plate or quadripolar plate are electrically connected with the gate drive signal output terminal；
Plane is being just where the underlay substrate for any pole plate of any pole plate of first capacitance and second capacitance
Projection is at least partly overlapping.
2. array substrate according to claim 1, which is characterized in that the shifting deposit unit is included in perpendicular to described
The first metal layer, second metal layer and the first electrode layer being arranged in order on the direction of underlay substrate.
3. array substrate according to claim 2, which is characterized in that the shifting deposit unit includes thin film transistor (TFT),
The first metal layer is used to be formed the grid of the thin film transistor (TFT)；
The second metal layer is used to be formed source electrode and the drain electrode of the thin film transistor (TFT).
4. array substrate according to claim 3, which is characterized in that first capacitance includes the first pole plate and the second pole
Plate；
Second capacitance includes tri-electrode and quadripolar plate, and the first metal layer includes the tri-electrode, and described the
Two metal layers include the quadripolar plate.
5. array substrate according to claim 4, which is characterized in that the shifting deposit unit further includes second electrode
Layer, the first electrode layer include first pole plate, and the second electrode lay includes second pole plate.
6. array substrate according to claim 4, which is characterized in that the shifting deposit unit further include be arranged at it is described
The 3rd metal layer between first electrode layer and the second metal layer；
3rd metal layer includes first pole plate, and the second electrode lay includes second pole plate.
7. array substrate according to claim 5 or 6, which is characterized in that first capacitance and second capacitance it
Between be equipped with organic film.
8. array substrate according to claim 7, which is characterized in that the is equipped between first pole plate and the second pole plate
One insulating layer；Second insulating layer is equipped between the first metal layer and the second metal layer；
The dielectric constant of the organic film is less than the dielectric constant of first insulating layer, and the dielectric of the organic film is normal
Number is less than the dielectric constant of the second insulating layer.
9. array substrate according to claim 8, which is characterized in that the relative dielectric constant scope of the organic film
For：1.5-4.
10. array substrate according to claim 8, which is characterized in that the thickness of the organic film is more than described first
The thickness of insulating layer, and the thickness of the organic film is more than the thickness of the second insulating layer.
11. array substrate according to claim 10, which is characterized in that the scope of the organic film thickness is 1 μm of -4 μ
m。
12. array substrate according to claim 1, which is characterized in that two pole plates of first capacitance are in the lining
Plane has the first orthographic projection where substrate, and two pole plate planes where the underlay substrate of second capacitance have
Second orthographic projection；First orthographic projection covers the described first positive throwing of second orthographic projection or second orthographic projection covering
Shadow.
13. a kind of display panel, including such as claim 1-12 any one of them array substrate.
14. a kind of display device, including display panel as claimed in claim 13.
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| CN201610254962.9A CN105719613B (en) | 2016-04-22 | 2016-04-22 | array substrate, display panel and display device |
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| CN108573682B (en) * | 2018-03-15 | 2020-12-01 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
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