WO2020220812A1 - Shift register circuit and driving method therefor, gate driving circuit, and display device - Google Patents

Abstract

A shift register circuit and a driving method therefor, a gate driving circuit, and a display device. The shift register circuit (100) comprises: an input circuit (110) which is connected to an input end, a first clock end, a first reference voltage end, a first node and a second node and configured to control, in response to a first clock signal from the first clock end, turning on and turning off of the input end and the first node and turning on and turning off of a first reference voltage end and the second node, and control, in response to a potential of the first node, turning on and turning off of the first clock end and the second node ; a first control circuit (120) connected to the first node, the input end, a second clock end, the first reference voltage end and a third node, and configured to control turning on and turning off of the first node and the third node in response to an input signal from the input end and a second clock signal from the second clock end; a second control circuit (130) electrically connected to the second node, the second clock end, a second reference voltage end and the first node, and configured to control turning on and turning off of the second reference voltage end and the first node in response to the potential of the second node and the second clock signal; a third control circuit (140) connected to the first node, the second node, the second reference voltage end, the second clock end, and a fourth node, and configured to control turning on and turning off of the second reference voltage end and the fourth node in response to the potential of the first node, and control turning on and turning off of the second clock end and the fourth node in response to the potential of the second node and the second clock signal; and an output circuit (150) which is connected to the second reference voltage end, the third node, the fourth node and an output end, and configured to control, in response to the potential of the third node, turning on and turning off of the first reference voltage end and the output end, and control, in response to the potential of the fourth node, turning on and turning off of the second reference voltage end and the output end.

Description

Shift register circuit and driving method thereof, gate driving circuit and display device

Cross references to related applications

This application claims the priority of the Chinese patent application CN201910350434.7 filed on April 28, 2019, the entire disclosure of which is incorporated herein by reference.

Technical field

The present disclosure relates to the field of display technology, and in particular to a shift register circuit and a driving method thereof, a gate driving circuit, and a display device.

Background technique

Array substrate gate drive (GOA, Gate Driver on Array) circuits or shift register circuits are widely used in display products. The GOA circuit is integrated on the array substrate and prepared at the same time as other display electronic components on the array substrate, which can reduce the cost of display products.

In the GOA circuit of the related art, in order to increase the driving capability or output capability of the transistor (taking a P-type transistor as an example) in the shift register and make it repeatedly turn on or turn on, it is usually necessary to pull down the voltage of the transistor gate. At this time, due to the fluctuation of the potential of the adjacent electronic components, the voltage of the gate of the transistor may be unstable, thereby affecting the stability of the driving waveform of the transistor, which may affect the stability of the output waveform of the entire GOA circuit.

Summary of the invention

According to a first aspect of the embodiments of the present disclosure, there is provided a shift register circuit, including:

The input circuit is connected to the input terminal, the first clock terminal, the first reference voltage terminal, the first node, and the second node, and is configured to control the connection between the input terminal and the first node in response to the first clock signal from the first clock terminal On-off and on-off between the first reference voltage terminal and the second node, and in response to the potential of the first node, controlling the on-off of the first clock terminal and the second node;

The first control circuit is connected to the first node, the input terminal, the second clock terminal, the first reference voltage terminal and the third node, and is configured to respond to the input signal from the input terminal and the second clock signal from the second clock terminal, Control the on and off of the first node and the third node;

The second control circuit is electrically connected to the second node, the second clock terminal, the second reference voltage terminal and the first node, and is configured to control the second reference voltage in response to the potential of the second node and the second clock signal The connection between the terminal and the first node;

The third control circuit is connected to the first node, the second node, the second reference voltage terminal, the second clock terminal, and the fourth node, and is configured to control the second reference voltage terminal and the fourth node in response to the potential of the first node The on-off of the fourth node, and in response to the potential of the second node and the second clock signal, controlling the on-off of the second clock terminal and the fourth node; and

The output circuit is connected to the second reference voltage terminal, the third node, the fourth node and the output terminal, and is configured to control the on-off of the first reference voltage terminal and the output terminal in response to the potential of the third node , And in response to the potential of the fourth node, controlling the on-off of the second reference voltage terminal and the output terminal.

In an embodiment, the first control circuit is further configured to disconnect the first node from the third node in response to the third node being at a valid potential, the input signal is valid, and the second clock signal is valid.

In an embodiment, the input circuit includes:

A first transistor, the gate of which is connected to the first clock terminal, the first electrode of which is connected to the input terminal, and the second electrode of which is connected to the first node;

A second transistor having its gate connected to the first node, its first electrode connected to the first clock terminal, and its second electrode connected to the second node; and

The third transistor has its gate connected to the first clock terminal, its first electrode connected to the first reference voltage terminal, and its second electrode connected to the second node.

In an embodiment, the first control circuit includes:

A fourth transistor, its gate is connected to the first reference voltage terminal, its first electrode is connected to the first node, and its second electrode is connected to the third node;

A fifth transistor, the gate of which is connected to the input terminal, the first electrode of which is connected to the fifth node, and the second electrode of which is connected to the first node;

A first capacitor connected between the second clock terminal and the fifth node; and

The second capacitor is connected between the third node and the second clock terminal.

In an embodiment, the second control circuit includes:

A sixth transistor, the gate of which is connected to the second node, the first electrode of which is connected to the second reference voltage terminal, and

The seventh transistor has its gate connected to the second clock terminal, its first electrode connected to the second electrode of the sixth transistor, and its second electrode connected to the first node.

In an embodiment, the third control circuit includes:

An eighth transistor, the gate of which is connected to the second node, the first electrode of which is connected to the second clock terminal, and the second electrode of which is connected to the sixth node;

A ninth transistor, the gate of which is connected to the second clock terminal, the first electrode of which is connected to the sixth node, and the second electrode of which is connected to the fourth node; and

The tenth transistor has its gate connected to the first node, its first electrode connected to the second reference voltage terminal, and its second electrode connected to the fourth node.

In an embodiment, the output circuit includes:

An eleventh transistor, the gate of which is connected to the fourth node, the first electrode of which is connected to the second reference voltage terminal, and the second electrode of which is connected to the output terminal; and

The twelfth transistor has its gate connected to the third node, its first electrode connected to the first reference voltage terminal, and its second electrode connected to the output terminal.

In an embodiment, the output circuit further includes:

The third capacitor is connected between the fourth node and the second reference voltage terminal.

In an embodiment, the third control circuit further includes:

A thirteenth transistor, the gate of which is connected to the first reference voltage terminal, the first electrode of which is connected to the second node, and the second electrode of which is connected to the seventh node; and

The fourth capacitor is connected between the sixth node and the seventh node.

In an embodiment, the input circuit, the output circuit, the first control circuit, the second control circuit, and the third control circuit each include a transistor that is a single gate transistor.

In an embodiment, the transistors are all N-type transistors or all P-type transistors.

According to a second aspect of the embodiments of the present disclosure, there is provided a gate driving circuit including N cascaded shift register circuits, where N is an integer greater than or equal to 2, wherein in the N shift register circuits , The output terminal of the m-th shift register circuit is connected to the input terminal of the m+1-th shift register circuit, m is an integer and 1≤m<N,

Wherein each first reference voltage terminal of the N shift register circuits is connected to a first reference voltage line to receive the first reference voltage,

Wherein each second reference voltage terminal of the N shift register circuits is connected to a second reference voltage line to receive the second reference voltage,

The first clock terminal of the 2k-1th shift register circuit and the second clock terminal of the 2kth shift register circuit in the N shift register circuits are connected to the first clock line to receive the first clock Signal, and

The second clock terminal of the 2k-1th shift register circuit and the first clock terminal of the 2kth shift register circuit in the N shift register circuits are connected to the second clock line to receive the second clock Signal, the first clock signal and the second clock signal have opposite phases, k is a positive integer and 2k≦N.

According to a third aspect of the embodiments of the present disclosure, there is provided a display device including:

The aforementioned gate drive circuit;

A timing controller configured to supply the first clock signal and the second clock signal to the first clock line and the second clock line, respectively, the first clock signal and the second clock signal Have opposite phases; and

A voltage generator connected to the timing controller and configured to supply the first reference voltage and the second reference voltage line to the first reference voltage line and the second reference voltage line under the control of the timing controller The second reference voltage.

According to a fourth aspect of the embodiments of the present disclosure, there is provided a method for driving the above shift register circuit, including:

Providing the input signal to the input terminal;

Providing the first clock signal and the second clock signal to the first clock terminal and the second clock terminal, respectively;

The first reference voltage and the second reference voltage are respectively supplied to the first reference voltage terminal and the second reference voltage terminal, wherein the first reference voltage and the second reference voltage are at different potentials ;as well as

In response to the input signal, the first clock signal, the second clock signal, the first reference voltage, and the second reference voltage, the shift register circuit performs the following operations:

The output signal is output from the output terminal.

In an embodiment, the first reference voltage is at a valid voltage level and the second reference voltage is at an invalid voltage level, and the operation performed by the shift register circuit further includes the following operations performed by the first control circuit:

In response to the third node being at a valid potential, the input signal being valid, and the second clock signal being valid, the first node and the third node are disconnected.

Description of the drawings

According to the following detailed description and the accompanying drawings, it will be easy to understand the various aspects, features and advantages of the present disclosure, in the accompanying drawings:

Fig. 1 schematically shows a structural block diagram of a shift register circuit according to some embodiments of the present disclosure;

FIG. 2 schematically shows a circuit diagram of an example circuit for the shift register circuit shown in FIG. 1 according to some embodiments of the present disclosure;

FIG. 3 schematically shows an example timing diagram for the example shift register circuit shown in FIG. 2;

FIG. 4 schematically shows a circuit diagram of an example circuit used in the shift register circuit shown in FIG. 1 according to other embodiments of the present disclosure;

FIG. 5 schematically shows a block diagram of a gate driving circuit based on the shift register circuit of FIG. 2;

Fig. 6 schematically shows a block diagram of a display device according to some embodiments of the present disclosure; and

FIG. 7 schematically illustrates a method of driving a shift register circuit according to some embodiments of the present disclosure.

It should be noted that the above-mentioned drawings are only schematic and illustrative, and are not necessarily drawn to scale.

Detailed ways

Hereinafter, several embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings in order to enable those skilled in the art to implement the present disclosure. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The embodiments do not limit the present disclosure.

It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components and/or parts, these elements, components and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first element, component or section discussed below may be referred to as the second element, component or section without departing from the teachings of the present disclosure.

The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to also include the plural, unless the context clearly dictates otherwise. It will be further understood that the terms "including" and/or "including" when used in this specification designate the existence of the described features, wholes, steps, operations, elements and/or components, but do not exclude one or more The existence of other features, wholes, steps, operations, elements, components, and/or groups thereof or addition of one or more other features, wholes, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being "connected to another element" or "coupled to another element," it can be directly connected to the other element or directly coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to another element" or "directly coupled to another element," there are no intervening elements present.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and/or the context of this specification, and will not be idealized or excessive Interpreted in a formal sense, unless explicitly defined as such in this article.

FIG. 1 schematically shows a block diagram of a shift register circuit 100 according to some embodiments of the present disclosure. 1, the shift register circuit 100 further includes an input circuit 110, a first control circuit 120, a second control circuit 130, a third control circuit 140, and an output circuit 150 which are illustrated as blocks.

The input circuit 110 may be connected to the input terminal IN, the first clock terminal CK, the first reference voltage terminal VGL, the first node N1 and the second node N2, and is configured to respond to the first clock signal from the first clock terminal CK, Control the on-off between the input terminal IN and the first node N1 and the on-off between the first reference voltage terminal VGL and the second node N2, and in response to the potential of the first node N1, control the first clock terminal CK and the second node N2 On and off. Specifically, for example, the input circuit 110 may be configured to, in response to the first clock signal from the first clock terminal CK being valid, input the input signal to the first node N1 and transfer the first reference signal from the first reference power terminal VGL The voltage is input to the second node N2, and in response to the first node N1 being at an effective potential, the first clock signal is input to the second node N2.

The first control circuit 120 may be connected to the first node N1, the input terminal IN, the second clock terminal CB, the first reference voltage terminal VGL, and the third node N1, and is configured to respond to an input signal from the input terminal IN and a third node N1. The second clock signal of the second clock terminal CB controls the on and off of the first node N1 and the third node N3. Specifically, for example, the first control circuit 120 may be configured to respond to the input signal from the input terminal IN being valid and the second clock signal from the second clock terminal CB when the third node N3 is at the valid potential, so that the first node N1 and the third node N3 are disconnected.

The second control circuit 130 may be connected to the second node N2, the second clock terminal CB, the second reference voltage terminal VGH and the first node N1, and is configured to respond to the potential of the second node N2 and the signal from the second clock terminal CB The second clock signal controls the on-off of the second reference voltage terminal VGH and the first node N1. Specifically, for example, the second control circuit 130 may be configured to connect the second reference voltage terminal VGH to the first node N1 in response to the second node N2 being at a valid potential and the second clock signal from the second clock terminal CB being valid. through.

The third control circuit 140 may be connected to the first node N1, the second node N2, the second reference voltage terminal VGH, the second clock terminal CB, and the fourth node N4, and is configured to control the first node N1 in response to the potential of the first node N1. The connection between the second reference voltage terminal VGH and the fourth node N4, and controlling the connection between the second clock terminal CB and the fourth node N4 in response to the potential of the second node N2 and the second clock signal from the second clock terminal CB Off. Specifically, for example, the third control circuit 140 may be configured to conduct the second clock terminal CB with the fourth node N4 in response to the second node N2 being at a valid potential and the second clock signal from the second clock terminal CB being valid, And in response to the first node N1 being at the effective potential, the second reference voltage terminal VGH is connected to the fourth node N4.

The output circuit 150 may be connected to the second reference voltage terminal VGH, the third node N3, the fourth node N4, and the output terminal OUT, and is configured to control the first reference voltage terminal VGL and the output terminal OUT in response to the potential of the third node N3 The on-off of the second reference voltage terminal VGH and the output terminal OUT are controlled in response to the potential of the fourth node N4. Specifically, for example, the output circuit 150 may be configured to connect the first reference voltage terminal VGL to the output terminal OUT in response to the third node N3 being at an effective potential, and to switch the second reference voltage terminal VGL to the output terminal OUT in response to the fourth node N4 being at an effective potential The voltage terminal VGH is connected to the output terminal OUT.

As used herein, the term "effective potential" refers to the potential at which the electronic component (e.g., transistor) involved is activated, such as the electrical potential applied to the gate of the transistor and turning the transistor on, even if the source and drain are turned on. Potential. The term "ineffective potential" as used herein refers to the potential at which the electronic component involved is disabled, such as a potential applied to the gate of a transistor and turning off the transistor even if the source and drain are disconnected. For n-type transistors, the effective potential is a high potential, and the ineffective potential is a low potential. For p-type transistors, the effective potential is a low potential, and the ineffective potential is a high potential. It will be understood that the effective potential or the ineffective potential is not intended to refer to a specific potential, but may include a range of potentials. In addition, the terms "level voltage", "voltage level", "voltage level" and the like are intended to be used interchangeably with "potential".

In this article, the clock signal valid means that the corresponding clock terminal is at the "active potential", that is, the potential at which the circuit element (for example, transistor) is enabled, and the clock signal invalid means that the corresponding clock terminal is at the "inactive potential" ", that is, the potential at which the circuit element involved is disabled. For some embodiments of the present disclosure, the valid clock signal means that the corresponding clock terminal is at a low potential, and the invalid clock signal means that the corresponding clock terminal is at a high potential.

It is easy to understand that in the shift register circuit 100 shown in FIG. 1 according to some embodiments of the present disclosure, in the first control circuit 120, the third node N3 is at an effective potential and the signal from the second clock terminal CB When the second clock signal is valid and the input terminal IN is at a valid potential, the first node N1 and the third node N3 can be completely disconnected, and at other times, the first node N1 and the third node N3 are kept conductive. In this way, while ensuring the normal operation of the entire shift register circuit 100, when the third node N3 needs to be maintained at an effective potential stably, the first node N1 and the third node N3 can be completely disconnected, thereby making the two potentials completely independent , Do not affect each other, and avoid potential fluctuations of the electronic components adjacent to the first node N1 to damage the stability of the potential of the third node N3. In addition, since the third node N3 is connected to the output circuit 150, keeping the potential of the third node N3 stable can ensure the stable operation of the transistors related to the third node N3 in the output circuit 150 and improve the performance of the entire shift register circuit 100. The stability of the output waveform ensures the quality of the output pulse at the output terminal OUT.

More specifically, the first control circuit 120 enables the first node N1 and the third node N1 to be at the effective potential when the input terminal IN is at the effective potential, and when the second clock signal from the second clock terminal CB is effective. The node N3 is disconnected (or completely cut off), which can prevent the leakage current caused by the incomplete cut-off of the transistor in the related art from adversely affecting the potential at the third node N3, thereby ensuring that the transistor in the output circuit 150 is fully and stably turned on , To ensure the stability of the output waveform and the quality of the output pulse.

FIG. 2 schematically shows the circuit structure of an example circuit 200 of the shift register circuit 100 shown in FIG. 1. An example configuration of the shift register circuit 200 will be described below with reference to FIG. 2.

The input circuit 110 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 has a gate connected to the first clock terminal CK, a first electrode connected to the input terminal IN, and a second electrode connected to the first node N1. The second transistor T2 has a gate connected to the first node N1, a first electrode connected to the first clock terminal CK, and a second electrode connected to the second node N2. The third transistor T3 has a gate connected to the first clock terminal CK, a first electrode connected to the first reference voltage terminal VGL, and a second electrode connected to the second node N2.

The first control circuit 120 includes a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. The fourth transistor T4 has a gate connected to the first reference voltage terminal VGL, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The fifth transistor T5 has a gate connected to the input terminal IN, a first electrode connected to the fifth node N5, and a second electrode connected to the first node N1. The first capacitor C1 is connected between the second clock terminal CB and the fifth node N5. The second capacitor C2 is connected between the second clock terminal CB and the third node N3.

The second control circuit 130 includes a sixth transistor T6 and a seventh transistor T7, wherein the sixth transistor T6 has a gate connected to the second node N2 and a first electrode connected to the second reference voltage terminal VGH, and the seventh transistor T7 has The gate of the second clock terminal CB is connected to the second electrode of the first node N1, and the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 are connected to each other.

The third control circuit 140 includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The eighth transistor T8 has a gate connected to the second node N2, a first electrode connected to the second clock terminal CB, and a second electrode connected to the sixth node N6. The ninth transistor T9 has a gate connected to the second clock terminal CB, a first electrode connected to the sixth node N6, and a second electrode connected to the fourth node N4. The tenth transistor T10 has a gate connected to the first node N1, a first electrode connected to the second reference voltage terminal VGH, and a second electrode connected to the fourth node N4.

The output circuit 120 includes an eleventh transistor T11 and a twelfth transistor T12. The eleventh transistor T11 has a gate connected to the fourth node N4, a first electrode connected to the second reference voltage terminal VGH, and a second electrode connected to the output terminal OUT. The twelfth transistor T12 has a gate connected to the third node N3, a first electrode connected to the first reference voltage terminal VGL, and a second electrode connected to the output terminal OUT.

In an embodiment, as shown in FIG. 2, the input circuit may further include a third capacitor C3, which is connected between the second reference voltage terminal VGH and the fourth node N4. The existence of the third capacitor C3 is advantageous because the potential at the fourth node N4 can be maintained stable by the energy storage effect of the capacitor C3, so that the state of the eleventh transistor T11 is stable, thereby ensuring the stability of the output waveform.

It should be noted that the transistor mentioned in the present disclosure is not limited to a single transistor, and may be a series connection of multiple transistors. In the embodiments of the present disclosure, the term “nth transistor” includes a transistor as an example for illustration, and the above-mentioned transistors may be all P-type transistors or all N-type transistors. In some embodiments according to the present disclosure, when the above-mentioned transistors are all P-type transistors, the term “first electrode of the transistor” specifically refers to the source, and “second electrode of the transistor” specifically refers to the drain. When the above-mentioned transistors are all N-type transistors, the term "first electrode" is the drain, and the term "second electrode" is the source. The embodiments of the present disclosure are described by taking each transistor as a P-type transistor as an example. The gate turn-on voltage is a low-level voltage, and the turn-off voltage is a high-level voltage. Although the transistors are illustrated and described as P-type transistors, N-type transistors are possible. In the case of an N-type transistor, the gate-on voltage has a high level, and the gate-off voltage has a low level. In various embodiments, the transistors may, for example, take the form of thin film transistors, which are typically fabricated such that their first and second electrodes can be used interchangeably.

FIG. 3 schematically shows an example timing diagram for the example shift register circuit 200 shown in FIG. 2. In this example, it can be assumed that the first reference voltage terminal VGL and the second reference voltage terminal VGH are respectively applied with a low-level voltage and a high-level voltage.

The operation process of the example circuit 200 shown in FIG. 2 is described below with reference to FIG. 3. In the following, 1 represents a high level, and 0 represents a low level. As shown in FIG. 3, the operation process of the circuit 200 includes five stages P1-P5. However, since the clock signal of the first clock terminal CK and the clock signal of the second clock terminal CB are not completely synchronously changed, there is still a difference between the above-mentioned stages. There are four small time intervals t1-t4. As shown in the figure, in the waveforms of the first clock signal and the second clock signal output by the first clock terminal CK and the second clock terminal CB, the high level time is slightly longer than the low level time.

First, analyze the working state of the circuit 200 before P1 (before the arrival of the input pulse) in conjunction with FIG. 3. As shown in Figure 3, at various moments before P1, IN always remains 0. When CK=0 and CB=1, the seventh transistor T7 and the fourth transistor T4 are turned off; the first transistor T1 is turned on and transmits the low voltage of the input terminal IN to the first node N1, therefore, N1 is at an effective low potential. In response to N1 being at a low potential, the second transistor T2 and the tenth transistor T10 are turned on, and respectively transmit the low voltage of the first clock terminal CK and the high voltage of the second reference voltage terminal (VGH) to the second node N2 and the Four nodes N4, so the second node N2 is at a low potential and the fourth node N4 is at a high potential. When CK changes from 0 to 1, and CB maintains 1, the first node N1 maintains a low potential, the tenth transistor T10 remains off, and the fourth node N4 maintains a high potential. Therefore, at each time between P1, the fourth node N4 always maintains a high potential and the first node N1 and the third node N3 (because the first reference voltage terminal VGL is applied with a low-level voltage, the fourth transistor T4 is turned on) Always at a low potential, so that the eleventh transistor T11 remains off and the twelfth transistor T12 remains on, thereby ensuring that the output terminal OUT outputs a low voltage.

As shown in Figure 3, in the P1 stage, IN=1, CK=0, and CB=1. Since CK=0 and IN=1, the first transistor T1 is turned on and transmits the high-level voltage from the input terminal IN to the first node N1, so that the first node N1 is set at an invalid potential (high potential); The third transistor is turned on and transmits the low level of the first reference voltage terminal VGL to the second node N2, so that the second node N2 is set at an effective potential; and the fifth transistor T5 is turned off. Since CB=1, the seventh transistor T7 and the ninth transistor T9 are turned off. Accordingly, since N1 is at an invalid potential, the second transistor T2 and the tenth transistor T10 are turned off. Since N2 is at the effective potential, the sixth transistor T6 and the eighth transistor T8 are turned on.

Furthermore, since the first reference voltage terminal VGL is applied with a low-level voltage, the fourth transistor T4 is turned on, so that the high-level voltage at point N1 is transmitted to the third node N3. In this way, the third node N3 has the same potential as the first node N1 and is at an invalid potential (high potential), so that the twelfth transistor T12 is turned off. Since the ninth transistor T9 and the tenth transistor T10 are turned off, the fourth node N4 is suspended and maintains the potential at the previous moment, that is, the high potential (based on the above analysis, the fourth node N4 maintains the high potential before the P1 stage), thus The eleventh transistor T11 is turned off. Therefore, since both T11 and T12 are off, the output voltage of the output terminal OUT should be the output voltage at the previous moment (the moment before P1), that is, the low-level voltage.

During the time interval t1, IN=1, CK changes from 0 to 1, and CB=1. At this time, in response to CK=1, the first clock signal is invalid, and the first transistor T1 and the third transistor T3 are turned off; in response to CB=1, the second clock signal remains invalid, and the seventh transistor T7 and the ninth transistor T9 remain Off state; in response to IN=1, the fifth transistor T5 maintains the off state. Correspondingly, the first node N1 maintains the high potential (inactive potential) of the previous stage (P1 stage), so that the second transistor T2 and the tenth transistor T10 remain in the off state; therefore, the second node N2 maintains the effective potential (low potential) , And the fourth node N4 is still in the floating state, maintaining the high potential of the previous stage (P1), so that the eleventh transistor T11 still remains in the off state. Since the second clock terminal CB maintains a high level, the third node N3 also maintains a high level state, so the twelfth transistor T12 still maintains an off state. Therefore, the output terminal OUT still outputs the low-level voltage of the previous stage.

In the P2 stage, IN=1, CK=1, and CB changes from 1 to 0. In response to CK=1, the first clock signal is invalid, and the first transistor T1 and the third transistor T3 remain in the off state; in response to IN=1, the fifth transistor T5 remains in the off state; in response to CB=0, the second clock signal is valid (At low level), the seventh transistor T7 and the ninth transistor T9 are turned on. Correspondingly, the first node N1 maintains the high potential (inactive potential) of the previous stage (P1 stage), so that the second transistor T2 and the tenth transistor T10 remain in the off state; the second node N2 maintains the effective potential (low potential), so The sixth transistor T6 and the eighth transistor T8 maintain the on state.

Since CB changes from 1 to 0, that is, the second clock terminal CB changes from a high-level state to a low-level state, due to the pull-down effect of the capacitor C2 connected between the second clock terminal CB and the third node N3 (and The principle of the bootstrap action of the capacitor is similar), the voltage of the third node N3 may be pulled down by the second capacitor C2. But at the same time, in response to the sixth transistor T6 and the seventh transistor T7 being turned on at the same time, the second reference voltage terminal VGH will be turned on with the point N1, and then the fourth transistor T4 will be turned on with the third node N3, so the second reference voltage The terminal VGH will charge the first node N1 and the third node N3, so that these two nodes are always at a high potential (because the second reference voltage terminal VGH is applied with a high-level voltage), therefore, the potential of the third node N3 is not Will be pulled low by the second capacitor C2.

It is easy to understand that the function of the sixth transistor T6 and the seventh transistor T7 is that when the N1 and N3 points are at an invalid potential (ie, a high potential), the voltage of the second clock terminal CB becomes low, so that the potential of N3 may be affected by the second capacitor C2. In the case of pulling down, the high voltage of the second reference voltage terminal VGH is used to charge it to keep the potential stable, that is, at a high potential, so as not to affect the normal output of the output terminal OUT.

In response to the third node N3 being at an invalid potential, that is, a high potential, the twelfth crystal T12 maintains an off state. At the same time, in response to the simultaneous turn-on of the eighth transistor T8 and the ninth transistor T9, the low-level voltage of the second clock terminal CB is transferred to the fourth node N4, and the fourth node N4 is set at the effective potential (ie, low potential). ), so that the eleventh transistor T11 is turned on and transmits the high voltage of the second reference voltage terminal VGH to the output terminal OUT. Therefore, in response to the twelfth transistor T12 being turned off and the eleventh transistor T11 being turned on, the output terminal OUT outputs a high-level voltage.

At time interval t2, IN=1, CK=1, and CB= changes from 0 to 1. At this time, in response to CK=1, that is, the first clock signal is invalid, the first transistor T1 and the third transistor T3 still remain off; in response to IN=1, the fifth transistor T5 remains off. In response to CB=1, the second clock signal becomes inactive (ie, high level), and the seventh transistor T7 and the ninth transistor T9 are turned off. Correspondingly, since the first transistor T1, the third transistor T3, and the fifth transistor T5 are still turned off, the first node N1 maintains the inactive potential (high potential) of the previous stage (P2 stage), so that the second transistor T2 and the tenth transistor The transistor T10 still maintains the off state, so the second node N2 maintains the effective potential of the previous stage (P2 stage), that is, the low potential.

In response to the ninth transistor T9 and the tenth transistor T10 being turned off, the fourth node N4 is in a floating state, maintaining the effective potential (low potential) of the previous stage (P2), so that the eleventh transistor T11 still remains in the on state; The three nodes N3 and the first potential N1 are at the same potential (high potential) (because CB remains high, the second capacitor C2 will not pull down the potential of N3), so the twelfth transistor T12 still remains off status. Therefore, in response to the eleventh transistor T11 being kept on and the twelfth transistor T12 being turned off, the output terminal OUT still outputs a high-level voltage.

In the P3 stage, the same as the P1 stage, IN=1, CK changes from 1 to 0, and CB=1. Since CK=0 and IN=1, the first transistor T1 is turned on and transmits the high-level voltage from the input terminal IN to the first node N1, so that the first node N1 is set at an invalid potential (high potential); The third transistor T3 is turned on and transmits the low level of the first reference voltage terminal VGL to the second node N2, so that the second node N2 is set at an effective potential (low potential); and the fifth transistor T5 remains turned off. Since CB=1, the seventh transistor T7 and the ninth transistor T9 are turned off. Accordingly, since N1 is at an invalid potential, the second transistor T2 and the tenth transistor T10 are turned off. Since N2 is at the effective potential, the sixth transistor T6 and the eighth transistor T8 are turned on.

Furthermore, since the first reference voltage terminal VGL is applied with a low-level voltage, the fourth transistor T4 is turned on, so that the high-level voltage at point N1 is transmitted to the third node N3. In this way, the third node N3 has the same potential as the first node N1 and is at an invalid potential (high potential), so that the twelfth transistor T12 is turned off. Since the ninth transistor T9 and the tenth transistor T10 are turned off, the fourth node N4 is suspended and maintains the potential of the previous stage (t2 period), that is, the effective potential (low potential), so that the eleventh transistor T11 remains on. Therefore, in response to the eleventh transistor T11 being turned on and the twelfth transistor T12 being turned off, the output terminal OUT still outputs the high-level voltage transmitted by the second reference voltage terminal VGH.

At time interval t3, IN=1, CK changes from 0 to 1, and CB=1. At this time, in response to CK=1, that is, the first clock signal is invalid, the first transistor T1 and the third transistor T3 are turned off; in response to CB=1, that is, the second clock signal remains inactive, the seventh transistor T7 and the ninth transistor T9 remains in the off state; in response to IN=1, the fifth transistor T5 remains off.

Accordingly, in response to the first transistor T1 being turned off, the first node N1 maintains the high potential (ineffective potential) of the previous stage (P3 stage), so that the second transistor T2 and the tenth transistor T10 maintain the off state; The transistor T3 and the second transistor T2 are turned off, and the second node N2 maintains the effective potential (low potential) of the previous stage (P3), so that the eighth transistor T8 is turned on; and in response to the ninth transistor T9 being turned off, the fourth node N4 remains In the floating state, the low potential (effective potential) of the previous stage (P3) is maintained, so that the eleventh transistor T11 remains on. Since the second clock terminal CB maintains a high level 1, N1 and N3 also maintain a high level state. Although the fifth transistor T5 is turned on, the first capacitor C1 does not pull down the voltage of the N1 node, and the second capacitor C2 does not pull down the voltage of the third node N3. Therefore, the twelfth transistor T12 still remains in the off state. Therefore, the output terminal OUT still outputs the high-level voltage transmitted by the second reference voltage terminal VGH.

In the P4 stage, IN changes from 1 to 0, CK=1, and CB changes from 1 to 0. In response to CK=1, that is, the first clock signal is invalid, the first transistor T1 and the third transistor T3 remain in the off state; in response to IN=0, the fifth transistor T5 remains in the on state; in response to CB=0, the second clock signal Valid (at low level), the seventh transistor T7 and the ninth transistor T9 are turned on.

Correspondingly, in response to the first transistor T1 being turned off, the first node N1 maintains the high potential (inactive potential) of the previous period (t3), so that the second transistor T2 and the tenth transistor T10 maintain the off state; in response to the third transistor T3 and the second transistor T2 are turned off, and the second node N2 maintains the effective potential (low potential) of the previous stage, so the sixth transistor T6 and the eighth transistor T8 remain on.

Similar to the description in the P2 stage, in the P4 stage, since CB changes from 1 to 0, that is, the second clock terminal CB changes from a high level state to a low level state, because it is connected to the second clock terminal CB and the third The pull-down effect of the capacitor C2 between the node N3 (similar to the principle of the bootstrap effect of the capacitor), the voltage of the third node N3 may be pulled down by the second capacitor C2; and since the fifth transistor T5 is turned on, the first node N1 is connected to the fifth node N5. Therefore, similarly due to the pull-down effect of the first capacitor C1, the voltage of the first node N1 (and the fifth node N5) may be pulled down by the first capacitor C1. But at the same time, in response to the sixth transistor T6 and the seventh transistor T7 being turned on at the same time, the second reference voltage terminal VGH will be connected to point N1, and then through the fourth transistor T4 (because the first reference voltage terminal VGL connected to its gate is Low level voltage) is connected to point N3, so the second reference voltage terminal VGH will charge N1 and N3 points, that is, the high level will be transferred to N1 and N3, so that these two nodes are always at high potential (because VGH is High-level voltage is applied), therefore, the potentials of the first node N1 and the third node N3 are not pulled down by the first capacitor C1 and the second capacitor C2, respectively.

As mentioned above, the function of the sixth transistor T6 and the seventh transistor T7 is to cause the second clock signal of the second clock terminal CB to become low when the first node N1 and the third node N3 are at an invalid potential (ie, a high potential). When the potentials may be pulled down by the first capacitor C1 and the second capacitor C2 respectively, charge them to keep their potentials stable, that is, always at a high potential, so as not to affect the second transistor T2, the tenth transistor T10, and the first transistor. The cut-off state of the twelve transistors T12 avoids affecting the normal output of the output terminal OUT.

Thus, in response to the third node N3 being at the inactive potential, that is, the high potential, the twelfth transistor T12 remains in the off state; at the same time, in response to the eighth transistor T8 and the ninth transistor T9 being turned on simultaneously, the second clock terminal CB is at a low level The voltage is transferred to the fourth node N4, and then the fourth node N4 is set at an effective potential (ie, a low potential), so that the eleventh transistor T11 is turned on. Correspondingly, in response to the eleventh transistor T11 being turned on and the twelfth transistor T12 being turned off, the high-level voltage of the second reference voltage terminal VGH is transferred to the output terminal OUT, and thus the output terminal OUT outputs a high-level voltage.

At time interval t4, IN=0, CK=1, and CB= changes from 0 to 1. At this time, in response to CK=1, that is, the first clock signal is invalid, the first transistor T1 and the third transistor T3 still remain off; in response to IN=0, the fifth transistor T5 is turned on; in response to CB=1, the second The clock signal becomes invalid (ie, high level), and the seventh transistor T7 and the ninth transistor T9 are turned off. Correspondingly, since the first transistor T1 and the third transistor T3 are still turned off, the first node N1 maintains the invalid potential (high potential) of the previous stage (P4 stage), so that the second transistor T2 and the tenth transistor T10 still remain off State, the second node N2 maintains the effective potential of the previous stage (P4 stage), that is, the low potential.

In response to the ninth transistor T9 and the tenth transistor T10 being turned off, the fourth node N4 is in a floating state, maintaining the effective potential (low potential) of the previous stage (P5), so that the eleventh transistor T11 still remains in the on state; The three nodes N3 are at the same potential as the first potential N1 and are at an invalid potential (high potential) (because CB remains high, the second capacitor C2 will not pull down the potential of N3, and the first capacitor C1 will not pull down N1. Point potential), so the twelfth transistor T12 remains off. Therefore, in response to the eleventh transistor T11 being kept on and the twelfth transistor T12 being kept off, the output terminal OUT still outputs the high-level voltage transmitted by the second reference voltage terminal VGH.

In the P5 stage, IN=0, CB=1, and CK= changes from 1 to 0. In response to CK=0 and IN=0, the first transistor T1 is turned on and transmits the low-level voltage from the input terminal IN to the first node N1, so that the first node N1 is set at an effective potential (low potential); The third transistor T3 is turned on and transmits the low level of the first reference voltage terminal VGL to the second node N2, so that the second node N2 is set at the effective potential (low potential); and the fifth transistor T5 is turned on, The first node N1 and the fifth node N5 are connected. In response to CB=1, the seventh transistor T7 and the ninth transistor T9 are kept off.

In response to the first node N1 being at an effective potential, the second transistor T2 is turned on and the tenth transistor T10 is turned on and transmits the high-level voltage of the second reference voltage terminal VGH to the fourth node N4, so that the fourth node N4 is set Set at an invalid potential (high potential), so that the eleventh transistor T11 is turned off. In response to the effective low voltage of the first reference voltage terminal VGL, the fourth transistor T4 is turned on and transmits the low voltage at point N1 to the third node N3, so that N3 is at a low potential, and the twelfth transistor T12 is turned on. Therefore, in response to the eleventh transistor T11 being turned off and the twelfth transistor T12 being turned on, the output terminal OUT outputs the low-level voltage transmitted by the first reference voltage terminal VGL.

In the stage after P5, as shown in Figure 3, the input terminal IN continues to maintain a low level voltage, the first node N1 maintains a low level, and the second transistor T2 is always on. Therefore, the voltage of the second node N2 depends on the first clock The output level of the terminal CK, that is, when the first clock terminal CK outputs a high-level signal, the potential of the second node N2 is high. As shown in FIG. 3, the waveforms of the first clock signal received by the first clock terminal CK and the second clock signal received by the second clock terminal CB are substantially opposite, that is, when the low level signal of the first clock terminal CK, the second clock terminal CB outputs a high-level signal; and when the second clock terminal CB outputs a low-level signal, the first clock terminal CK outputs a high-level signal. In this way, when the second clock terminal CB outputs a low level, the first clock terminal CK outputs a high level, that is, the second node N2 is at a high potential, so the sixth transistor T6 and the seventh transistor T7 cannot be turned on at the same time. In this way, it is ensured that the points N1 and N3 will not be charged into the high voltage of the second reference voltage terminal VGH.

According to the above description, the role of the second transistor T2 is to control the turn-on and turn-off of the transistor T6 to ensure that the first node N1 and the third node N3 remain low in the stage after P5, and are protected from the transmission of the second reference voltage terminal VGH The effect of high voltage.

In addition, in the stage after P5, according to the above analysis, the input pulse of the input terminal IN remains valid, that is, the low level, so that the fifth transistor T5 remains on; the first node N1 and the third node N3 are at an effective potential, namely Low potential to ensure that the twelfth transistor T12 is turned on, and the output terminal OUT outputs a low level voltage. Therefore, when the second clock signal output by the second clock terminal CB changes from a high level to a low level signal (that is, when it is valid), due to the step-down effect of the capacitor (similar to the bootstrap effect), the second capacitor C2 will The potential of the third node N3 is further pulled down, so that the twelfth transistor T12 is turned on more fully and the output capability is enhanced. At this time, if the first capacitor C1 and the fifth transistor T5 are removed from the circuit structure of FIG. 2, the voltage of the third node N3 is pulled down, and the potential of the first node N1 is higher than that of the third node N3. The voltage on a node N1 will charge the first node N1 through T12 (although T12 may be cut off due to the decrease in the potential of the third node N3, this cutoff is not completely disconnected, because the voltage at point N4 is higher than N1, there may still be A small amount of leakage current flows through T12), causing fluctuations in the gate voltage of the twelfth transistor T12, affecting the stability of the output waveform of the circuit.

It is precisely because of the presence of the first capacitor C1 in the first control circuit 120 that when the second clock signal output by the second clock terminal CB changes from a high level to a low level signal (that is, when it is valid), the first capacitor C1 will (With the second capacitor C2 pulling down the potential of the point N3) synchronously pulling down the potential of the first node N1. At this time, since N1 and N3 are pulled down synchronously, the potential is the same, which completely avoids the leakage current flowing through T4, that is, T4 is completely cut off (equivalent to completely disconnected), that is, the first node N1 will not charge the third node N3. The stability of the potential of the third node N3 is ensured, thereby ensuring the stability of the output waveform of the shift register circuit, and improving the driving quality of the circuit.

FIG. 4 schematically shows the circuit structure of another example circuit 400 of the shift register circuit 100 shown in FIG. 1. As shown in FIG. 4, the structure of another example circuit 400 of the shift register circuit 100 is basically the same as the structure of the example circuit 200 shown in FIG. 2, except that in the another example circuit 400 shown in FIG. The three control circuit 140 also includes a thirteenth transistor T13 and a fourth capacitor C4, wherein the fourth capacitor C4 is connected between the sixth node N6 and the seventh node N7, and the gate of the thirteenth transistor T13 is connected to the first reference The first electrode of the voltage terminal VGL is connected to the second node N2, and the second electrode thereof is connected to the seventh node N7.

In some embodiments according to the present disclosure, similar to the functions of the first capacitor C1 and the second capacitor C2, the presence of the fourth capacitor C4 may be advantageous because when the potential at the seventh node N7 is low and the second clock When the second clock signal at terminal CB becomes valid (that is, from high level to low level) (for example, the P2 stage shown in FIG. 3), the eighth transistor T8 and the ninth transistor T9 are turned on, and you can use Due to the effect of the fourth capacitor C4, the potential of the seventh node N7 is pulled lower to enhance the driving capability of the eighth transistor T8, so that it can be turned on or turned on more fully. In addition, the purpose of adding a transistor T13 between N2 and N7 is to connect the seventh node N7 to the second node when necessary (for example, when the potential of the seventh node N7 is pulled down by the fourth capacitor C4 (lower than the potential of N2)). The two nodes N2 are isolated or disconnected, so as to prevent the decrease of the potential of the seventh node N7 from affecting the second node N2, maintain the potential of the N2 point and reduce the jump, thereby ensuring the stability of the second transistor T2.

Specifically, in the P2 phase shown in FIG. 3, the second clock signal output by the second clock terminal CB changes from high to low, the second node N2 is at a low potential, and the thirteenth transistor T13 responds to the first reference voltage terminal VGL The seventh node N7 is turned on at a low voltage, and the eighth transistor T8 and the ninth transistor T9 are turned on, so the fourth capacitor C4 pulls the seventh node N7 to a lower potential by the action of the capacitor. In order to enhance the driving ability of the eighth transistor T8; at this time, due to the decrease in the potential of the seventh node N7 (lower than the potential at the point N2), the thirteenth transistor T13 is turned off to a certain extent to reduce the change from the second node N2 to the seventh node N2. The leakage current flowing through the node N7 enables the second node N2 to maintain a relatively stable potential and reduce jumps to ensure the stability of the second transistor T2.

FIG. 5 schematically shows a block diagram of a gate driving circuit 500 based on the shift register circuit of FIG. 2. As shown in FIG. 5, the gate driver 500 includes N cascaded shift register circuits SR(1), SR(2),..., SR(N-1) and SR(N), each of which shifts The bit register circuit may take the form of the shift register circuit 200 as described above with respect to FIG. 2. N can be an integer greater than or equal to 2. In the gate driver 500, except for the N-th shift register circuit SR(N), the output terminal OUT of each shift register circuit is connected to the input terminal IN of the next adjacent shift register circuit.

The N shift register circuits SR(1), SR(2),..., SR(N-1) and SR(N) in the gate driver 500 can be respectively connected to the N gate lines G[1], G[2],..., G[N-1] and G[N]. Each of the shift register circuits may also be connected to a first reference voltage line vgl configured to transmit a first reference voltage, a second reference voltage line vgh configured to transmit a second reference voltage, and a second reference voltage line vgh configured to transmit a first clock. Signal and the second clock signal of the first clock line clka and the second clock line clkb. In particular, the shift register circuits SR(1), SR(2),..., SR(N-1) and SR(N) in the first clock terminal CK of the 2k-1th shift register circuit and The second clock terminal CB of the 2kth shift register circuit is connected to the first clock line clka, and the shift register circuits SR(1), SR(2),..., SR(N-1) and SR(N The second clock terminal CB of the 2k-1th shift register circuit and the first clock terminal CK of the 2kth shift register circuit in) are connected to the second clock line clkb, where k is a positive integer and 2k≦N. It will be understood that the first and second clock signals CK and CB are supplied to the shift register circuits SR(1), SR(2),..., SR(N-1) and SR(N ), so that each of the shift register circuits operates with the same (but "time-shifted") timing to sequentially generate output signals as gate turn-on pulses.

FIG. 6 schematically shows a block diagram of a display device 600 according to some embodiments of the present disclosure. 6, the display device 600 includes a display panel 610, a timing controller 620, a gate driver 630, a data driver 640, and a voltage generator 650. The gate driver 630 may take the form of the gate driving circuit 500 shown above in relation to FIG. 5, and the first clock line clka, the second clock line clkb, the first reference voltage line vgl, and the second clock line shown in FIG. The reference voltage line vgh is omitted in FIG. 6 for convenience of illustration.

The display panel 610 is connected to a plurality of gate lines GL extending in a first direction D1 and a plurality of data lines DL extending in a second direction D2 crossing (eg, substantially perpendicular) to the first direction D1. The display panel 610 includes a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and a corresponding one of the data lines DL. The display panel 610 may be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, or any other suitable type of display panel.

The timing controller 620 controls the operation of the display panel 610, the gate driver 630, the data driver 640, and the voltage generator 650. The timing controller 620 receives input image data RGBD and an input control signal CONT from an external device (for example, a host). The input image data RGBD may include a plurality of input pixel data for a plurality of pixels. Each input pixel data may include red gray data R, green gray data G, and blue gray data B for a corresponding one of a plurality of pixels. The input control signal CONT may include a main clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and so on. The timing controller 620 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT. The implementation of the timing controller 620 is known in the art. The timing controller 620 may be implemented in many ways (such as, for example, using dedicated hardware) to perform various functions discussed herein. A "processor" is an example of a timing controller 620 that employs one or more microprocessors, which can be programmed using software (such as microcode) to perform various functions discussed herein. The timing controller 620 may be implemented with or without a processor, and may also be implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions. Examples of the timing controller 620 include, but are not limited to, conventional microprocessors, application specific integrated circuits (ASIC), and field programmable gate arrays (FPGA).

The gate driver 630 receives the first control signal CONT1 from the timing controller 620. The first control signal CONT1 may include first and second clock signals that are transmitted via the first and second clock lines clka and clkb shown in FIG. 5 and have opposite phases. The gate driver 630 generates a plurality of gate driving signals for output to the gate line GL based on the first control signal CONT1. The gate driver 630 may sequentially apply a plurality of gate driving signals to the gate line GL.

The data driver 640 receives the second control signal CONT2 from the timing controller 620 and outputs image data RGBD'. The data driver 640 generates a plurality of data voltages based on the second control signal CONT2 and the output image data RGBD'. The data driver 640 may apply the generated plurality of data voltages to the data line DL.

The voltage generator 650 supplies power to the display panel 610, the timing controller 620, the gate driver 630, the data driver 640, and potentially other components. Specifically, the voltage generator 650 is configured to supply the first reference voltage and the second reference voltage respectively transmitted via the first reference voltage line vgl and the second reference voltage line vgh shown in FIG. 5 under the control of the timing controller 620. Reference voltage. The configuration of the voltage generator 650 may be known in the art.

In some embodiments according to the present disclosure, the gate driver 630 and/or the data driver 640 may be disposed on the display panel 610, or may be connected to the display panel 610 by means of, for example, a tape carrier package (TCP). . For example, the gate driver 630 may be integrated in the display panel 610 as a row drive array (GOA) circuit.

Examples of the display device 600 include, but are not limited to, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.

In some embodiments of the present disclosure, there is also provided a method 700 for driving the shift register circuit 100 according to some embodiments of the present disclosure as shown in FIG. 1. As shown in FIG. 7, the method 700 includes:

At step 710, an input signal is provided to the input terminal IN;

At step 720, the first clock signal and the second clock signal are provided to the first clock terminal CK and the second clock terminal CB, respectively;

At step 730, the first reference voltage is supplied to the first reference voltage terminal VGL and the second reference voltage is supplied to the second reference voltage terminal VGH, wherein the first reference voltage and the second reference voltage are at different potentials; and

At step 740, in response to the input signal, the first clock signal, the second clock signal, the first reference voltage, and the second reference voltage, the shift register circuit 100 performs the following operations: outputting the output signal from the output terminal OUT .

In some embodiments of the above-mentioned driving method according to the present disclosure, the first reference voltage may be at a valid voltage level and the second reference voltage may be at an invalid voltage level, and the operation performed by the shift register circuit 100 may specifically include The control circuit 120 performs the following operation: in response to the third node N3 being at a valid potential, the input signal is valid, and the second clock signal is valid, the first node N1 and the third node N3 are disconnected.

By using the driving method 700 of the shift register circuit 100 according to some embodiments of the present disclosure, it is possible to prevent the leakage current caused by the incomplete cut-off of the transistor in the related art from adversely affecting the potential at the third node N3, thereby ensuring the output circuit 150 The transistor in is fully and stably turned on to ensure the stability of the output waveform and the quality of the output signal.

Although the specific embodiments of the present disclosure have been shown and described, it is obvious to those skilled in the art that several changes and modifications can be made in its broader aspects without departing from the disclosure. Therefore, the appended rights The requirements should include all such changes and modifications within its scope, as if they fall within the true spirit and scope of the present disclosure.

Claims (15)

1. A shift register circuit includes:

   The input circuit is connected to the input terminal, the first clock terminal, the first reference voltage terminal, the first node, and the second node, and is configured to control the connection between the input terminal and the first node in response to the first clock signal from the first clock terminal On-off and on-off between the first reference voltage terminal and the second node, and in response to the potential of the first node, controlling the on-off of the first clock terminal and the second node;

   The first control circuit is connected to the first node, the input terminal, the second clock terminal, the first reference voltage terminal and the third node, and is configured to respond to the input signal from the input terminal and the second clock signal from the second clock terminal, Control the on and off of the first node and the third node;

   The second control circuit is electrically connected to the second node, the second clock terminal, the second reference voltage terminal and the first node, and is configured to control the second reference voltage in response to the potential of the second node and the second clock signal The connection between the terminal and the first node;

   The third control circuit is connected to the first node, the second node, the second reference voltage terminal, the second clock terminal, and the fourth node, and is configured to control the second reference voltage terminal and the fourth node in response to the potential of the first node The on-off of the fourth node, and in response to the potential of the second node and the second clock signal, controlling the on-off of the second clock terminal and the fourth node; and

   The output circuit is connected to the second reference voltage terminal, the third node, the fourth node and the output terminal, and is configured to control the on-off of the first reference voltage terminal and the output terminal in response to the potential of the third node , And in response to the potential of the fourth node, controlling the on-off of the second reference voltage terminal and the output terminal.
2. The shift register circuit according to claim 1, wherein the first control circuit is further configured to enable the first node in response to the third node being at a valid potential, the input signal being valid, and the second clock signal being valid Disconnect from the third node.
3. The shift register circuit according to claim 1, wherein the input circuit comprises:

   A first transistor, the gate of which is connected to the first clock terminal, the first electrode of which is connected to the input terminal, and the second electrode of which is connected to the first node;

   A second transistor whose gate is connected to the first node, its first electrode is connected to the first clock terminal, and its second electrode is connected to the second node; and

   The third transistor has its gate connected to the first clock terminal, its first electrode connected to the first reference voltage terminal, and its second electrode connected to the second node.
4. The shift register circuit according to claim 1, wherein the first control circuit comprises:

   A fourth transistor, its gate is connected to the first reference voltage terminal, its first electrode is connected to the first node, and its second electrode is connected to the third node;

   A fifth transistor, the gate of which is connected to the input terminal, the first electrode of which is connected to the fifth node, and the second electrode of which is connected to the first node;

   A first capacitor connected between the second clock terminal and the fifth node; and

   The second capacitor is connected between the third node and the second clock terminal.
5. The shift register circuit according to claim 1, wherein the second control circuit comprises:

   A sixth transistor, the gate of which is connected to the second node, the first electrode of which is connected to the second reference voltage terminal, and

   The seventh transistor has its gate connected to the second clock terminal, its first electrode connected to the second electrode of the sixth transistor, and its second electrode connected to the first node.
6. The shift register circuit according to claim 1, wherein the third control circuit comprises:

   An eighth transistor, the gate of which is connected to the second node, the first electrode of which is connected to the second clock terminal, and the second electrode of which is connected to the sixth node;

   A ninth transistor, the gate of which is connected to the second clock terminal, the first electrode of which is connected to the sixth node, and the second electrode of which is connected to the fourth node; and

   The tenth transistor has its gate connected to the first node, its first electrode connected to the second reference voltage terminal, and its second electrode connected to the fourth node.
7. The shift register circuit according to claim 1, wherein the output circuit comprises:

   An eleventh transistor, the gate of which is connected to the fourth node, the first electrode of which is connected to the second reference voltage terminal, and the second electrode of which is connected to the output terminal; and

   The twelfth transistor has its gate connected to the third node, its first electrode connected to the first reference voltage terminal, and its second electrode connected to the output terminal.
8. The shift register circuit according to claim 7, wherein the output circuit further comprises:

   The third capacitor is connected between the fourth node and the second reference voltage terminal.
9. The shift register circuit according to claim 6, wherein the third control circuit further comprises:

   A thirteenth transistor, the gate of which is connected to the first reference voltage terminal, the first electrode of which is connected to the second node, and the second electrode of which is connected to the seventh node; and

   The fourth capacitor is connected between the sixth node and the seventh node.
10. The shift register circuit according to claim 1, wherein the input circuit, the output circuit, the first control circuit, the second control circuit, and the third control circuit each include a transistor that is a single gate极 Transistor.
11. 10. The shift register circuit according to claim 10, wherein the transistors are all N-type transistors or all P-type transistors.
12. A gate drive circuit, comprising N cascaded shift register circuits according to any one of claims 1-11, N is an integer greater than or equal to 2, wherein in the N shift register circuits , The output terminal of the m-th shift register circuit is connected to the input terminal of the m+1-th shift register circuit, m is an integer and 1≤m<N,

    Wherein each first reference voltage terminal of the N shift register circuits is connected to a first reference voltage line to receive the first reference voltage,

    Wherein each second reference voltage terminal of the N shift register circuits is connected to a second reference voltage line to receive the second reference voltage,

    The first clock terminal of the 2k-1th shift register circuit and the second clock terminal of the 2kth shift register circuit in the N shift register circuits are connected to the first clock line to receive the first clock Signal, and

    The second clock terminal of the 2k-1th shift register circuit and the first clock terminal of the 2kth shift register circuit in the N shift register circuits are connected to the second clock line to receive the second clock Signal, the first clock signal and the second clock signal have opposite phases, k is a positive integer and 2k≦N.
13. A display device includes:

    The gate driving circuit according to claim 12;

    A timing controller configured to supply the first clock signal and the second clock signal to the first clock line and the second clock line, respectively, the first clock signal and the second clock signal Have opposite phases; and

    A voltage generator connected to the timing controller and configured to supply the first reference voltage and the second reference voltage line to the first reference voltage line and the second reference voltage line under the control of the timing controller The second reference voltage.
14. A method for driving the shift register circuit according to any one of claims 1 to 11, comprising:

    Providing the input signal to the input terminal;

    Providing the first clock signal and the second clock signal to the first clock terminal and the second clock terminal, respectively;

    The first reference voltage and the second reference voltage are respectively supplied to the first reference voltage terminal and the second reference voltage terminal, wherein the first reference voltage and the second reference voltage are at different potentials ;as well as

    In response to the input signal, the first clock signal, the second clock signal, the first reference voltage, and the second reference voltage, the shift register circuit performs the following operations:

    The output signal is output from the output terminal.
15. The method according to claim 14, wherein the first reference voltage is at a valid voltage level and the second reference voltage is at an invalid voltage level, and the operation performed by the shift register circuit further comprises a first control circuit Do the following:

    In response to the third node being at a valid potential, the input signal being valid, and the second clock signal being valid, the first node and the third node are disconnected.

Images