CN113903309B

CN113903309B - Shifting register unit, control method thereof and grid drive circuit

Info

Publication number: CN113903309B
Application number: CN202111251622.8A
Authority: CN
Inventors: 袁粲; 李永谦; 张大成
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-10-26
Filing date: 2021-10-26
Publication date: 2023-04-07
Anticipated expiration: 2041-10-26
Also published as: CN113903309A

Abstract

Provided are a shift register unit, a control method thereof and a gate driving circuit, the shift register unit including: a first input circuit for providing a potential of the power signal terminal to the pull-up node under the control of the first control signal terminal; a first reset circuit for supplying a potential of the power signal terminal to the pull-down node and supplying a potential of the reference signal terminal to the pull-up node under the control of the second control signal terminal; a second input circuit for supplying an input signal terminal potential to the pull-up node under the control of the third control signal terminal and the clock signal terminal; the second reset circuit is used for controlling the potential of the pull-down node under the control of the clock signal end and the input signal end; an output circuit; and a control circuit.

Description

Shifting register unit, control method thereof and grid drive circuit

Technical Field

The present disclosure relates to the field of digital circuit technologies, and in particular, to a shift register unit, a control method thereof, and a gate driving circuit.

Background

In the current OLED display field, a Gate On Array (GOA) circuit and a time sequence design are used to drive a display screen to display. In the related art, two driving modes are mainly used for performing internal compensation, which are a PE (Progressive emission) Progressive sequential driving mode and an SE (singular emission) full-screen Simultaneous driving mode. The PE driving mode is line-by-line reset + compensation + light emitting, the SE mode is full screen reset + compensation, data are written line by line, and finally the full screen simultaneously emits light. In the two driving modes, a plurality of GOAs are often required to generate gate driving signals for resetting, compensating and data writing, and the number of transistors and signal lines of the GOAs is large, and the number of connecting lines and overlines is large, so that the occupied space is large.

Disclosure of Invention

In one aspect, a shift register cell is provided, including but not limited to: a first input circuit, connected to a first control signal terminal, a power supply signal terminal, and a pull-up node of the shift register unit, configured to supply a potential of the power supply signal terminal to the pull-up node under signal control of the first control signal terminal; a first reset circuit connected to a second control signal terminal, the power signal terminal, a reference signal terminal, the pull-up node, and the pull-down node of the shift register unit, and configured to supply a potential of the power signal terminal to the pull-down node and a potential of the reference signal terminal to the pull-up node under control of a signal of the second control signal terminal; a second input circuit connected to an input signal terminal, a third control signal terminal, a clock signal terminal, and the pull-up node, and configured to supply a potential of the input signal terminal to the pull-up node under control of the third control signal terminal and the clock signal terminal; a second reset circuit connected to the clock signal terminal, the input signal terminal, the power signal terminal, and the pull-down node, and configured to control a potential of the pull-down node under control of the clock signal terminal and the input signal terminal; an output circuit connected to the pull-up node, the pull-down node, the power supply signal terminal, the reference signal terminal, and the output signal terminal, and configured to supply a signal of the power supply signal terminal to the output signal terminal under control of a potential of the pull-up node and supply a potential of the reference signal terminal to the output signal terminal under control of a potential of the pull-down node; and a control circuit connected to the pull-up node and the pull-down node, configured to pull down a potential of the pull-down node according to a potential of the pull-up node, and to pull down a potential of the pull-up node according to a potential of the pull-down node.

In an exemplary embodiment of the present disclosure, the second reset circuit is further configured to electrically isolate the power signal terminal from the pull-down node under control of the clock signal terminal and the input signal terminal.

In an exemplary embodiment of the present disclosure, the second input circuit includes: a first transistor, a gate of which is connected to the clock signal terminal, and a first pole of which is connected to the input signal terminal; and a gate of the second transistor is connected to the third control signal terminal, a first pole of the second transistor is connected to a second pole of the first transistor, and a second pole of the second transistor is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, the gate of the first transistor is connected to the first clock signal terminal, and the second input circuit further includes: a third transistor, a gate of which is connected to the pull-up node, and a first pole of which is connected to the second clock signal terminal; a fourth transistor, a gate of which is connected to the third control signal terminal, and a first pole of which is connected to a second pole of the third transistor; and a first end of the first capacitor is connected with the pull-up node, and a second end of the first capacitor is connected with the second pole of the fourth transistor.

In an exemplary embodiment of the present disclosure, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, and the second reset circuit includes: a gate of the fifth transistor is connected to the second clock signal terminal, and a first electrode of the fifth transistor is connected to the power signal terminal; a sixth transistor, a gate of which is connected to the input signal terminal, a first pole of which is connected to the second clock signal terminal, and a second pole of which is connected to the second pole of the fifth transistor; a seventh transistor, a gate of which is connected to the second pole of the fifth transistor, and a first pole of which is connected to the first clock signal terminal; a gate of the eighth transistor is connected to the first clock signal terminal, a first pole of the eighth transistor is connected to the second pole of the seventh transistor, and the second pole of the eighth transistor is connected to the pull-down node; and a first end of the second capacitor is connected with the grid electrode of the seventh transistor, and a second end of the second capacitor is connected with the second pole of the seventh transistor.

In an exemplary embodiment of the present disclosure, the second reset circuit further includes: a ninth transistor, a gate of the ninth transistor is connected to the second control signal terminal, a first pole of the ninth transistor is connected to the power signal terminal, and a second pole of the ninth transistor is connected to the second pole of the fifth transistor.

In an exemplary embodiment of the present disclosure, the output circuit includes: a tenth transistor, a gate of which is connected to the pull-up node, a first pole of which is connected to the power signal terminal, and a second pole of which is connected to the output signal terminal; a gate of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the reference signal terminal, and a second electrode of the eleventh transistor is connected to the output signal terminal; a first end of the third capacitor is connected with the pull-up node, and a second end of the third capacitor is connected with the output signal end; and a first end of the fourth capacitor is connected with the pull-down node, and a second end of the fourth capacitor is connected with the reference signal end.

In an exemplary embodiment of the present disclosure, the first reset circuit includes: a first reset sub-circuit connected to the second control signal terminal, the reference signal terminal and the pull-up node, and configured to supply a potential of the reference signal terminal to the pull-up node under control of a signal of the second control signal terminal; a second reset sub-circuit connected to the second control signal terminal, the power signal terminal, and the pull-down node, and configured to supply a potential of the power signal terminal to the pull-down node under control of a signal of the second control signal terminal.

In an exemplary embodiment of the present disclosure, the first reset sub-circuit includes: a twelfth transistor, a gate of the twelfth transistor is connected to the second control signal terminal, a first pole of the twelfth transistor is connected to the reference signal terminal, and a second pole of the twelfth transistor is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the first reset sub-circuit includes: a thirteenth transistor, a gate of which is connected to the second control signal terminal, and a first pole of which is connected to the reference signal terminal; and a fourteenth transistor, a gate of the fourteenth transistor is connected to the second control signal terminal, a first pole of the fourteenth transistor is connected to a second pole of the thirteenth transistor, and a second pole of the fourteenth transistor is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the second reset sub-circuit includes: a fifteenth transistor, a gate of which is connected to the second control signal terminal, a first pole of which is connected to the power signal terminal, and a second pole of which is connected to the pull-down node.

In an exemplary embodiment of the present disclosure, the first input circuit includes: and a sixteenth transistor, wherein a gate of the sixteenth transistor is connected to the first control signal terminal, a first electrode of the sixteenth transistor is connected to the power signal terminal, and a second electrode of the sixteenth transistor is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the control circuit includes: a first control sub-circuit connected to the pull-up node, the pull-down node, and the reference signal terminal, and configured to supply a potential of the reference signal terminal to the pull-up node under control of a potential of the pull-down node; a second control sub-circuit connected to the pull-up node, the pull-down node, and the reference signal terminal, and configured to supply a potential of the reference signal terminal to the pull-down node under control of a potential of the pull-up node.

In an exemplary embodiment of the present disclosure, the first control sub-circuit includes: a seventeenth transistor, a gate of the seventeenth transistor being connected to the pull-down node, a first pole of the seventeenth transistor being connected to the reference signal terminal, and a second pole of the seventeenth transistor being connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the first control sub-circuit includes: a gate of the eighteenth transistor is connected to the pull-down node, and a first electrode of the eighteenth transistor is connected to the reference signal terminal; a nineteenth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the second pole of the eighteenth transistor, and a second pole of which is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the second control sub-circuit includes a twentieth transistor, a gate of the twentieth transistor is connected to the pull-up node, a first pole of the twentieth transistor is connected to the reference signal terminal, and a second pole of the twentieth transistor is connected to the pull-down node.

In an exemplary embodiment of the present disclosure, the second control sub-circuit includes: a twenty-first transistor, a gate of which is connected to the pull-up node, and a first pole of which is connected to the reference signal terminal; a twenty-second transistor, a gate of the twenty-second transistor being connected to the pull-up node, a first pole of the twenty-second transistor being connected to a second pole of the twenty-first transistor, and a second pole of the twenty-second transistor being connected to the pull-down node.

In an exemplary embodiment of the present disclosure, the first reset sub-circuit of the first reset circuit includes a thirteenth transistor and a fourteenth transistor, the first control sub-circuit of the control circuit includes an eighteenth transistor and a nineteenth transistor, and the shift register unit further includes: a twenty-third transistor, a gate of the twenty-third transistor being connected to the pull-up node, a first pole of the twenty-third transistor being connected to the power reference signal terminal, and a second pole of the twenty-third transistor being connected to the second pole of the thirteenth transistor, the first pole of the fourteenth transistor, the second pole of the eighteenth transistor, and the first pole of the nineteenth transistor.

In an exemplary embodiment of the present disclosure, the shift register unit further includes: and the output circuit is connected to the output signal end of the shift register unit through the load circuit.

A second aspect of the present disclosure provides a gate driving circuit comprising a plurality of cascaded stages of shift register cells as described above.

In an exemplary embodiment of the present disclosure, the first control signal terminal of each shift register unit is connected to receive a first control signal, the second control signal terminal is connected to receive a second control signal, and the third control signal terminal is connected to receive a third control signal; the input signal end of the nth stage shift register unit is connected with the output signal end of the nth-x stage shift register unit, wherein n is an integer greater than 1, and x is an integer greater than or equal to 1; the first clock signal end of the n-x stage shift register unit is connected to receive a first clock signal, and the second clock signal end of the n-x stage shift register unit is connected to receive a second clock signal; the first clock signal end of the nth stage shift register unit is connected to receive the second clock signal, and the second clock signal end of the nth stage shift register unit is connected to receive the first clock signal.

A third aspect of the present disclosure provides a method of controlling a shift register unit as described above, comprising: in the first stage, the first input circuit provides the electric potential of a power supply signal end to a pull-up node under the control of a signal of a first control signal end, the electric potential of the pull-up node enables the output circuit to provide a signal of the power supply signal end to the output signal end and enables the control circuit to pull down the electric potential of the pull-down node, the first reset circuit provides the electric potential of the power supply signal end to the pull-down node and provides the electric potential of a reference signal end to the pull-up node under the control of a signal of a second control signal end, and the electric potential of the pull-down node enables the output circuit to provide a signal of the reference signal end to the output signal end and enables the control circuit to pull down the electric potential of the pull-up node; in the second stage, the second input circuit provides the potential of the input signal end to the pull-up node under the control of the third control signal end and the clock signal end, the potential of the pull-up node enables the output circuit to provide the signal of the power signal end to the output signal end and enables the control circuit to pull down the potential of the pull-down node, the second reset circuit pulls up the potential of the pull-down node under the control of the signals of the clock signal end, the input signal end and the power signal end, and the potential of the pull-down node enables the output circuit to provide the signal of the reference signal end to the output signal end and enables the control circuit to pull down the potential of the pull-up node.

In an exemplary embodiment of the present disclosure, the method further comprises: in a first phase, a second reset circuit electrically isolates the power signal terminal from the pull-down node under the control of the clock signal terminal and the input signal terminal.

Drawings

To more clearly illustrate the technical aspects of the embodiments of the present disclosure, reference will now be made in brief to the accompanying drawings of the embodiments, it being understood that the drawings described below relate only to some embodiments of the disclosure and are not intended as limitations thereon, in which:

FIG. 1 schematically illustrates a schematic block diagram of a shift register cell of one exemplary embodiment of the present disclosure;

FIG. 2 schematically illustrates a circuit diagram of a shift register cell of another exemplary embodiment of the present disclosure;

FIG. 3 schematically illustrates a circuit diagram of a shift register cell of yet another exemplary embodiment of the present disclosure;

fig. 4 schematically illustrates a schematic block diagram of a gate driving circuit of an exemplary embodiment of the present disclosure;

FIG. 5 schematically shows a signal timing diagram of a shift register cell of an exemplary embodiment of the present disclosure;

FIG. 6 schematically illustrates a simulation diagram of signal timing of a shift register cell of one exemplary embodiment of the present disclosure;

fig. 7 schematically illustrates a simulation diagram of signal timing of a gate driving circuit of an exemplary embodiment of the present disclosure;

fig. 8 schematically illustrates a driving effect diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure.

Detailed Description

While the present disclosure will be fully described with reference to the accompanying drawings, which contain preferred embodiments of the disclosure, it should be understood before this description that one of ordinary skill in the art can modify the disclosure described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the foregoing description is a broad disclosure directed to persons of ordinary skill in the art, and that there is no intent to limit the exemplary embodiments described in this disclosure.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form in order to simplify the drawing.

The shift register unit, the control method thereof, and the gate driving circuit according to the embodiments of the present disclosure are described in detail with reference to fig. 1 to 8.

Fig. 1 schematically shows a schematic block diagram of a shift register unit according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the shift register unit of the embodiment of the present disclosure includes a first input circuit 100, a second input circuit 200, a first reset circuit 300, a second reset circuit 400, an output circuit 500, and a control circuit 600.

The first input circuit 100 is connected to the first control signal terminal SC1, the power signal terminal VGH, and the pull-up node Q of the shift register unit. The first input circuit 100 can provide the potential of the power signal terminal VGH to the pull-up node Q under the control of the first control signal terminal SC 1.

The first reset circuit 300 is connected to the second control signal terminal SC2, the power signal terminal VGH, the reference signal terminal VGL, the pull-up node Q, and the pull-down node QB of the shift register unit. The first reset circuit 300 may supply the potential of the power signal terminal VGH to the pull-down node QB and the potential of the reference signal terminal VGL to the pull-up node Q under the control of the signal of the second control signal terminal SC 2.

The second input circuit 200 is connected to the input signal terminal STU, the third control signal terminal SC3, the clock signal terminal CLK, and the pull-up node Q. The second input circuit 200 may supply the potential of the input signal terminal STU to the pull-up node Q under the control of the third control signal terminal SC3 and the clock signal terminal CLK.

The second reset circuit 400 is connected to the clock signal terminal CLK, the input signal terminal STU, the power signal terminal VGH, and the pull-down node QB. The second reset circuit 400 may pull up the potential of the pull-down node QB under the control of the clock signal terminal and the input signal terminal STU.

The output circuit 500 is connected to the pull-up node Q, the pull-down node QB, the power signal terminal VGH, the reference signal terminal VGL, and the output signal terminal OUT. The output circuit 500 may provide the signal of the power supply signal terminal VGH to the output signal terminal OUT under the control of the potential of the pull-up node Q, and provide the potential of the reference signal terminal VGL to the output signal terminal OUT under the control of the potential of the pull-down node QB.

The control circuit 600 connects the pull-up node Q and the pull-down node QB. The control circuit 600 may pull down the potential of the pull-down node QB according to the potential of the pull-up node Q, and pull down the potential of the pull-up node Q according to the potential of the pull-down node QB.

In some embodiments, the second reset circuit 400 may also electrically isolate the power supply signal terminal VGH from the pull-down node QB under the control of the clock signal terminal CLK and the input signal terminal STU.

The embodiment of the present disclosure can generate the gate driving signal for compensation and reset and the gate driving signal for data writing, respectively, by providing two sets of the input circuit and the reset circuit in the shift register unit, and make them not affect each other, so that SE scanning can be realized instead of a plurality of shift register units.

Fig. 2 schematically shows a circuit diagram of a shift register cell of another exemplary embodiment of the present disclosure.

As shown in fig. 2, the shift register unit includes a first input circuit 100, a second input circuit 200, a first reset circuit, a second reset circuit 400, an output circuit 500, and a control circuit 600. The above description of the first input circuit 100, the second input circuit 200, the first reset circuit 300, the second reset circuit 400, the output circuit 500, and the control circuit 600 is also applicable to the present embodiment.

In some embodiments, as shown in fig. 2, the clock signal terminals may include a first clock signal terminal CK and a second clock signal terminal XCK.

The second input circuit 200 may include a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected to the clock signal terminal (in this embodiment, the first clock signal terminal XCK), and the first pole of the first transistor T1 is connected to the input signal terminal STU. The gate of the second transistor T2 is connected to the third control signal terminal SC3, the first pole of the second transistor T2 is connected to the second pole of the first transistor T1, and the second pole of the second transistor T2 is connected to the pull-up node Q.

The second reset circuit 400 may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a second capacitor C2. The gate of the fifth transistor T5 is connected to the second clock signal terminal CK, and the first electrode of the fifth transistor T5 is connected to the power signal terminal VGH. The gate of the sixth transistor T6 is connected to the input signal terminal STU, the first pole of the sixth transistor T6 is connected to the second clock signal terminal CK, and the second pole of the sixth transistor T6 is connected to the second pole of the fifth transistor T5. A gate of the seventh transistor T7 is connected to the second pole of the fifth transistor T5, and a first pole of the seventh transistor T7 is connected to the first clock signal terminal XCK. A gate of the eighth transistor T8 is connected to the first clock signal terminal XCK, a first pole of the eighth transistor T8 is connected to the second pole of the seventh transistor T7, and a second pole of the eighth transistor T8 is connected to the pull-down node QB. A first terminal of the second capacitor C2 is connected to the gate of the seventh transistor T7, and a second terminal of the second capacitor C2 is connected to the second pole of the seventh transistor T7.

In some embodiments, the second reset circuit 400 may further include a ninth transistor T9. A gate of the ninth transistor T9 is connected to the second control signal terminal SC2, a first pole of the ninth transistor T9 is connected to the power supply signal terminal VGH, and a second pole of the ninth transistor is connected to the second pole of the fifth transistor T5.

In some embodiments, the output circuit 500 may include: a tenth transistor T10, an eleventh transistor T11, a third capacitor C3, and a fourth capacitor C4. A gate of the tenth transistor T10 is connected to the pull-up node Q, a first pole of the tenth transistor T10 is connected to the power signal terminal VGH, and a second pole of the tenth transistor T10 is connected to the output signal terminal OUT. A gate of the eleventh transistor T11 is connected to the pull-down node QB, a first pole of the eleventh transistor T11 is connected to the reference signal terminal VGL, and a second pole of the eleventh transistor T11 is connected to the output signal terminal OUT. A first end of the third capacitor C3 is connected to the pull-up node Q, and a second end of the third capacitor C3 is connected to the output signal terminal OUT. A first terminal of the fourth capacitor C4 is connected to the pull-down node QB, and a second terminal of the fourth capacitor C4 is connected to the reference signal terminal VGL.

In some embodiments, as shown in fig. 2, the first reset circuit may include a first reset sub-circuit 310 and a second reset sub-circuit 320.

The first reset sub-circuit 310 is connected to the second control signal terminal SC2, the reference signal terminal VGL, and the pull-up node Q. The first reset sub-circuit 310 may provide the potential of the reference signal terminal VGL to the pull-up node Q under the control of the signal of the second control signal terminal SC 2. In some embodiments, the first reset sub-circuit 310 may include a twelfth transistor T12. A gate of the twelfth transistor T12 is connected to the second control signal terminal SC2, a first pole of the twelfth transistor T12 is connected to the reference signal terminal VGL, and a second pole of the twelfth transistor is connected to the pull-up node Q.

The second reset sub-circuit 320 is connected to the second control signal terminal SC2, the power signal terminal VGH, and the pull-down node QB. The second reset sub-circuit 320 may supply the potential of the power supply signal terminal VGH to the pull-down node QB under the control of the signal of the second control signal terminal SC 2. In some embodiments, the second reset sub-circuit 320 includes a fifteenth transistor T15. A gate of the fifteenth transistor T15 is connected to the second control signal terminal SC2, a first pole of the fifteenth transistor T15 is connected to the power signal terminal VGH, and a second pole of the fifteenth transistor is connected to the pull-down node QB.

In some embodiments, the first input circuit 100 may include a sixteenth transistor T16. A gate of the sixteenth transistor T16 is connected to the first control signal terminal SC1, a first pole of the sixteenth transistor T16 is connected to the power signal terminal VGH, and a second pole of the sixteenth transistor is connected to the pull-up node Q.

In some embodiments, control circuit 600 may include a first control subcircuit 610 and a second control subcircuit 620.

The first control sub-circuit 610 connects the pull-up node Q, the pull-down node QB, and the reference signal terminal VGL. The first control sub-circuit 610 may provide the potential of the reference signal terminal VGL to the pull-up node Q under the control of the potential of the pull-down node QB. In some embodiments, the first control sub-circuit 610 includes a seventeenth transistor T17. A gate of the seventeenth transistor T17 is connected to the pull-down node QB, a first pole of the seventeenth transistor T17 is connected to the reference signal terminal VGL, and a second pole of the seventeenth transistor is connected to the pull-up node Q.

The second control sub-circuit 620 connects the pull-up node Q, the pull-down node QB, and the reference signal terminal VGL. The second control sub-circuit 620 may supply the potential of the reference signal terminal VGL to the pull-down node QB under the control of the potential of the pull-up node Q. In some embodiments, the second control sub-circuit comprises a twentieth transistor T20. The gate of the twentieth transistor T20 is connected to the pull-down node Q, the first pole of the twentieth transistor T20 is connected to the reference signal terminal VGL, and the second pole of the twentieth transistor is connected to the pull-down node QB.

Fig. 3 schematically shows a circuit diagram of a shift register cell of yet another exemplary embodiment of the present disclosure.

As shown in fig. 3, the shift register unit includes a first input circuit 100, a second input circuit 200', a first reset circuit, a second reset circuit 400, an output circuit 500, and a control circuit 600', similar to fig. 2. The first input circuit 100 and the second reset circuit 400 and the output circuit 500 may be respectively the same as the first input circuit 100, the second reset circuit 400 and the output circuit 500, and are not described herein again. For the sake of brevity, the following description will mainly describe the differences in detail.

As shown in fig. 3, the second input circuit 200' includes a third transistor T3, a fourth transistor T4, and a first capacitor C1 in addition to the first transistor T1 and the second transistor T2.

A gate of the first transistor T1 is connected to the first clock signal terminal XCK, and a first electrode of the first transistor T1 is connected to the input signal terminal STU. The gate of the second transistor T2 is connected to the third control signal terminal SC3, the first pole of the second transistor T2 is connected to the second pole of the first transistor T1, and the second pole of the second transistor T2 is connected to the pull-up node Q. The gate of the third transistor T3 is connected to the pull-up node Q, and the first pole of the third transistor is connected to the second clock signal terminal. A gate of the fourth transistor T4 is connected to the third control signal terminal SC3, and a first pole of the fourth transistor T4 is connected to a second pole of the third transistor T3. A first terminal of the first capacitor C1 is connected to the pull-up node Q, and a second terminal of the first capacitor C1 is connected to the second pole of the fourth transistor T4.

As shown in fig. 3, the first reset circuit includes a first reset sub-circuit 310' and a second reset sub-circuit 320. Unlike the first reset sub-circuit 310 of fig. 2, the first reset sub-circuit 310' includes a thirteenth transistor T13 and a fourteenth transistor T14. A gate of the thirteenth transistor T13 is connected to the second control signal terminal SC2, and a first pole of the thirteenth transistor T13 is connected to the reference signal terminal VGL. A gate of the fourteenth transistor T14 is connected to the second control signal terminal SC2, a first pole of the fourteenth transistor T is connected to the second pole of the thirteenth transistor T13, and a second pole of the fourteenth transistor T14 is connected to the pull-up node Q. The second reset sub-circuit 320 may be the same as the second reset sub-circuit 320 described above with reference to fig. 2 and will not be described again here.

The control circuit 600' includes a first control sub-circuit 610' and a second control sub-circuit 620'. Unlike the first control sub-circuit 610 of fig. 2, the first control sub-circuit 610' includes an eighteenth transistor T18 and a nineteenth transistor T19. A gate of the eighteenth transistor T18 is connected to the pull-down node QB, and a first pole of the eighteenth transistor is connected to the reference signal terminal VGL. A gate of the nineteenth transistor T19 is connected to the pull-down node QB, a first pole of the nineteenth transistor T19 is connected to the second pole of the eighteenth transistor, and a second pole of the nineteenth transistor is connected to the pull-up node Q. Unlike the second control sub-circuit 620 of fig. 2, the second control sub-circuit 620' includes a twenty-first transistor T21 and a twenty-second transistor T22. The gate of the twenty-first transistor T21 is connected to the pull-up node Q, and the first pole of the twenty-first transistor is connected to the reference signal terminal VGL. The gate of the twentieth transistor T22 is connected to the pull-down node Q, the first pole of the twentieth transistor is connected to the second pole of the twenty-first transistor, and the second pole of the twentieth transistor is connected to the pull-down node QB.

In fig. 3, the second pole of the thirteenth transistor T13, the first pole of the fourteenth transistor T14, the second pole of the eighteenth transistor T18, and the first pole of the nineteenth transistor T19 are connected to the node off. In some embodiments, the shift register unit may further include a twenty-third transistor T23. The gate of the twentieth transistor T23 is connected to the pull-up node Q, the first pole of the twentieth transistor T23 is connected to the power supply signal terminal VGH, and the second pole of the twentieth transistor T23 is connected to the node off. When the pull-up node Q is at a high level, the twenty-third transistor T23 is turned on, thereby supplying a high level of the power signal terminal VGH to the node off. In this case, both the first pole and the second pole of the fourteenth transistor T14 are at a high level, so that the fourteenth transistor T14 can be prevented from leaking electricity. Similarly, the first pole and the second pole of the nineteenth transistor T19 are also both high level, so that the nineteenth transistor T19 can be prevented from leaking current.

In some embodiments, the shift register cell further comprises a load circuit 700. The output circuit 500 is connected to the output signal terminal OUT of the shift register unit through the load circuit 700. As shown in fig. 3, the load circuit 700 may include a plurality of load units, each of which includes a resistor R and a capacitor C. In a load unit, a first end of a resistor R is used as an input end of the load unit, a second end of the resistor R is used as an output end of the load unit, a first end of a capacitor C is connected with the second end of the resistor R, and a second end of the capacitor C is grounded. The output end of each stage of load unit is connected with the input end of the next stage of load unit, so that the series connection of the load units is realized, wherein the input end of the first stage of load unit, the second pole of the tenth transistor and the second pole of the eleventh transistor are connected to a node G, and the output end of the last stage of load unit is used as an output signal end OUT of the whole shift register unit.

Embodiments of the present disclosure also provide a gate driving circuit including a plurality of cascaded shift register units as described above. The gate driving circuit will be described in detail with reference to fig. 4.

Fig. 4 schematically illustrates a schematic block diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure.

As shown in fig. 4, the gate driving circuit includes a plurality of cascaded shift register units GOA _1, GOA _2, … (hereinafter, referred to as shift register unit GOA).

The first control signal terminal SC1 of each shift register unit GOA is connected to receive the first control signal SC1, the second control signal terminal SC2 is connected to receive the second control signal SC2, and the third control signal terminal SC3 is connected to receive the third control signal SC3.

An input signal terminal STU of the nth stage shift register unit is connected with an output signal terminal OUT of the nth-x stage shift register unit, wherein n is an integer larger than 1, and x is an integer larger than or equal to 1. For example, as shown in fig. 4, x =1, the input signal terminal STU of the 1 ST stage shift register unit GOA _1 is connected to receive the start signal ST, the input signal terminal STU of the 2 nd stage shift register unit GOA _2 is connected to the output signal terminal OUT of the 1 ST stage shift register unit GOA _1, the input signal terminal STU of the 3 rd stage shift register unit GOA _3 is connected to the output signal terminal OUT of the 2 nd stage shift register unit GOA _2, and so on.

The first clock signal terminal XCK of the n-x stage shift register unit is connected to receive the first clock signal XCk, and the second clock signal terminal CK of the n-x stage shift register unit is connected to receive the second clock signal CK. The first clock signal terminal XCK of the nth stage shift register unit is connected to receive the second clock signal Ck, and the second clock signal terminal Ck of the nth stage shift register unit is connected to receive the first clock signal XCk. For example, as shown in fig. 4, when x =1, the first clock signal terminal XCK of the 1 st stage shift register unit GOA _1 is connected to receive the first clock signal XCk, and the second clock signal terminal CK of the 1 st stage shift register unit GOA _1 is connected to receive the second clock signal CK. The first clock signal terminal XCK of the level 2 shift register unit GOA _2 is connected to receive the second clock signal Ck, and the second clock signal terminal Ck of the level 2 shift register unit GOA _2 is connected to receive the first clock signal XCk. The first clock signal terminal XCK of the 3 rd stage shift register unit GOA _3 is connected to receive the first clock signal XCk, the second clock signal terminal CK of the 3 rd stage shift register unit GOA _3 is connected to receive the second clock signal CK, and so on.

In the embodiment of the present disclosure, the power signal terminal VGH of each shift register unit GOA is connected to receive the power signal VGH, and the reference signal terminal VGL of each shift register unit GOA is connected to receive the reference signal VGL.

Although the gate driving circuit of the embodiment of the present disclosure is described above with x =1 as an example, the embodiment of the present disclosure is not limited thereto. In some embodiments, x may be set to other values as needed, in which case the signal waveform at the clock signal end and/or the number of the clock signal ends may be adaptively adjusted to achieve the same or similar functions as the gate driving circuit described above, and will not be described herein again.

Embodiments of the present disclosure also provide a control method of the shift register unit described above. The method is applicable to the shift register unit of any of the embodiments described above. The method includes a first stage and a second stage.

In the first stage, the first input circuit provides the electric potential of the power signal end to the pull-up node under the control of the signal of the first control signal end, the electric potential of the pull-up node enables the output circuit to provide the signal of the power signal end to the output signal end and enables the control circuit to pull down the electric potential of the pull-down node, the first reset circuit provides the electric potential of the power signal end to the pull-down node and provides the electric potential of the reference signal end to the pull-up node under the control of the signal of the second control signal end, and the electric potential of the pull-down node enables the output circuit to provide the signal of the reference signal end to the output signal end and enables the control circuit to pull down the electric potential of the pull-up node. The shift register cell generates gate driving signals for compensation and reset in a first phase, also referred to as compensation and reset phase.

In the second stage, the second input circuit provides the potential of the input signal end to the pull-up node under the control of the third control signal end and the clock signal end, the potential of the pull-up node enables the output circuit to provide the signal of the power signal end to the output signal end and enables the control circuit to pull down the potential of the pull-down node, the second reset circuit pulls up the potential of the pull-down node under the control of the signals of the clock signal end, the input signal end and the power signal end, and the potential of the pull-down node enables the output circuit to provide the signal of the reference signal end to the output signal end and enables the control circuit to pull down the potential of the pull-up node Q. The shift register unit generates a gate driving signal for data writing in a second phase, which is also referred to as a data writing phase.

In some embodiments, the second reset circuit may further electrically isolate the power supply signal terminal from the pull-down node under control of the clock signal terminal and the input signal terminal in the first stage.

A control method of the shift register unit according to the embodiment of the present disclosure is described in detail below with reference to fig. 5 and 6.

Fig. 5 schematically shows a signal timing diagram of a shift register unit according to an exemplary embodiment of the present disclosure. Fig. 6 schematically shows a simulation diagram of signal timing of a shift register cell of an exemplary embodiment of the present disclosure. The signal timing of fig. 5 and 6 will be described in detail below in conjunction with the shift register circuit of fig. 3.

As shown in fig. 5, the first clock signal, the second clock signal, the first control signal, the second control signal and the third control signal are applied to the first clock signal terminal XCK, the second clock signal terminal CK, the first control signal terminal SC1, the second control signal terminal SC2 and the third control signal terminal SC3 of the shift register unit, respectively, the power signal and the reference signal are applied to the power signal terminal VGH and the reference signal terminal VGL of the shift register unit, respectively, and the input signal is applied to the input signal terminal STU of the shift register unit. The signals at the first clock signal terminal XCK, the second clock signal terminal CK, the first control signal terminal SC1, the second control signal terminal SC2, and the third control signal terminal SC3 may be ac signals, for example, the signals at the first clock signal terminal XCK and the second clock signal terminal CK are periodic signals and are opposite in phase, and the signals at the first control signal terminal SCl, the second control signal terminal SC2, the third control signal terminal SC3, and the input signal terminal STU are pulse signals. The signals at the power signal terminal VGH and the reference signal terminal VGL may be dc signals, for example, the power signal terminal VGH is at a constant high level, and the reference signal terminal VGL is at a constant low level.

The first stage includes period (1) to period (5).

In the period (1), as shown in fig. 5, the first control signal terminal SC1 is at a high level, the second control signal terminal SC2 and the third control signal terminal SC3 are at a low level, the input signal terminal STU is at a high level, the second clock signal terminal CK is at a low level, and the first clock signal terminal XCK is at a high level. The high level of the first control signal terminal SC1 turns on the sixteenth transistor T16 to charge the pull-up node Q to a high level. The tenth transistor T10 is turned on by the high level of the pull-up node Q, and the high level of the power signal terminal VGH is supplied to the node G, thereby outputting the high level at the output signal terminal OUT. The high level of the input signal terminal STU turns on the sixth transistor T6, so that the M point is pulled to the low level of the second clock signal terminal CK. The low level of the point M causes the seventh transistor T7 to be turned off. At this time, although the eighth transistor T8 is turned on by the high level of the first clock signal terminal XCK, the seventh transistor T7 is turned off, so that the power signal terminal VGH is electrically isolated from the pull-down node QB, thereby preventing the low level of the pull-down node QB from being affected. The high level of the pull-up node Q also turns on the twenty first and twenty second transistors T21 and T22, thereby pulling the pull-down node QB point to a low level. The low level of the pull-down node QB turns off the eleventh transistor T11 so as not to affect the high level of the output signal terminal OUT. Because of the voltage division of the resistors, the voltage rise of the output signal terminal OUT is slower than that of the pull-up node Q point, so that the output signal terminal OUT and the pull-up node Q point generate bootstrap in the charging process, the potential of the pull-up node Q point is higher than that of the power supply signal terminal VGH, and the lossless output of the output signal terminal OUT is further ensured.

In the period (2), the second clock signal terminal CK becomes the high level, the first clock signal terminal XCK becomes the low level, and the input signal terminal STU maintains the high level. The second clock signal terminal CK becomes a high level to turn on the fifth transistor T5, and the high level of the input signal terminal STU turns on the sixth transistor T6, thereby bringing the point M to a high level. The seventh transistor T7 is turned on by the high level of the point M, the eighth transistor T8 is turned off by the low level of the first clock signal terminal XCK, and the power signal terminal VGH can be electrically isolated from the pull-down node QB, so that the pull-down node QB is maintained at the low level. The presence of the first capacitor C1 keeps the pull-up node Q point at a high level, and the output signal terminal OUT continues to output a high level.

In the period (3), the second clock signal terminal CK becomes the low level, the first clock signal terminal XCK becomes the high level, and the input signal terminal STU maintains the high level. The high level of the input signal terminal STU turns on the sixth transistor T6, thereby pulling down the M point to the low level of the second clock signal terminal CK. The fifth transistor T5 is turned off by the low level of the second clock signal terminal CK, the seventh transistor T7 is turned off by the low level of the M-point, and the eighth transistor T8 is turned on by the high level of the first clock signal terminal XCK. This allows the high level of the power signal terminal VGH to remain electrically isolated from the pull-down node QB, so that the pull-down node QB can keep at a low level. The first capacitor C1 keeps the pull-up node Q at a high level, so that the output signal terminal OUT continuously outputs a high level.

In the period (4), the operations of the period (2) and the period (3) are repeated, the pull-up node Q continues to be at the high level, and the pull-down node QB continues to be at the low level, thereby causing the output signal terminal OUT to continuously output the high level.

In the period (5), the second control signal terminal SC2 is at the high level, and the input signal terminal STU becomes the low level. The high level of the second control signal terminal SC2 turns on the fifteenth transistor T15, thereby supplying the high level of the power supply signal terminal VGH to the pull-down node QB. The high level of the pull-down node QB turns on the eighteenth and nineteenth transistors T18 and T19, thereby discharging the pull-up node Q point to the low level of the reference signal terminal VGL. The low level of the pull-up node Q turns off the twenty first and twenty second transistors T21 and T22. The tenth transistor T10 is also turned off by the low level of the pull-up node Q, and the eleventh transistor T11 is turned on by the high level of the pull-down node QB, so that the node G is pulled down to the low level of the reference signal terminal VGL, and the output signal terminal OUT is pulled down to the low level.

After the operations from the time period (1) to the time period (5) are performed, the full screen reset and compensation time period is finished, and it can be seen from the function that the full screen reset and compensation time is adjustable through the second control signal terminal SC2, and through the arrangement of the thirteenth transistor T13, the fourteenth transistor T14, the eighteenth transistor T18, the nineteenth transistor T19 and the seventh transistor T7, the anti-creeping design is realized. The high potential of the pull-up node Q point needs to be kept for a long time from the time period (1) to the time period (5), and the leakage of the pull-up node Q can be prevented through the leakage-proof design, so that the condition that the output of the circuit is abnormal due to unstable voltage of the pull-up node Q can be relieved.

The second phase may include period (6) through period (R).

In the period (6), the second clock signal terminal CK and the third control signal terminal SC3 are at a high level, and the first clock signal terminal XCK and the input signal terminal STU are at a low level. The high level of the third control signal terminal SC3 turns on the second transistor T2. At this time, since the first clock signal terminal XCK is at a low level, the first transistor T1 is turned off, and the pull-up node Q remains at a low level. The high level of the second clock signal terminal CK turns on the fifth transistor T5, thereby supplying the high level of the power signal terminal VGH to the point M, thereby turning on the seventh transistor T7. Although the seventh transistor T7 is turned on, the eighth transistor T8 is turned off by the low level of the first clock signal terminal XCK, and thus the pull-down node QB is maintained at the high level. The high level of the pull-down node QB turns on the twenty-first and twenty-second transistors T21 and T22, thereby maintaining the pull-up node Q at a low level. The eleventh transistor T11 is turned on by the high level of the pull-down node QB, and the tenth transistor T10 is turned off by the low level of the pull-up node Q, so that the output signal terminal OUT continues to be at the low level.

In the period (7), the second clock signal terminal CK is at a low level, the first clock signal terminal XCK is at a high level, and the third control signal terminal SC3 and the input signal terminal STU are at a high level. The high levels of the third control signal terminal SC3 and the first clock signal terminal XCK turn on the first and second transistors T1 and T2, thereby charging the pull-up node Q to a high level. The high level of the pull-up node Q turns on the tenth transistor T10, thereby causing the output signal terminal OUT to output a high level. The high level of the pull-up node Q also discharges the pull-down node QB to a low level through the twenty-first transistor T21 and the twenty-second transistor T22, and the output signal terminal OUT outputs a high level, which is a gate precharge stage. In this process, the low levels of the input signal terminal STU and the second clock signal terminal CK turn off both the fifth transistor T5 and the sixth transistor T6, thereby discharging the M-point to a low level. The seventh transistor T7 is turned off by the low level of the point M, and the eighth transistor T8 is turned on by the high level of the first clock signal terminal XCK so as not to affect the voltage level of the pull-down node QB.

In the period (8), the second clock terminal CK is at a high level, the first clock terminal XCK is at a low level, and the third control signal terminal SC3 maintains at a high level. Since both the third control signal terminal SC3 and the pull-up node Q are at a high level, the third transistor T3 and the fourth transistor T4 are in an on state, thereby supplying the high level of the second clock signal terminal CK to the node a. At this time, due to the bootstrap effect of the first capacitor C1, the potential of the pull-up node Q is further raised, and due to the bootstrap effect of the third capacitor C3, the potential of the node G is further raised, and the output signal terminal OUT generates lossless output.

In the period (9), the second clock terminal CK is at a low level, the first clock terminal XCK is at a high level, and the input signal terminal STU is at a low level. The presence of the second capacitor C2 makes the point M still high, so that the seventh transistor T7 and the eighth transistor T8 are turned on, and the pull-down node QB is charged to the high level of the first clock terminal XCK. The high level of the pull-down node QB turns on the eighteenth and nineteenth transistors T18 and T19, and the pull-up node Q point is pulled down to a low level through the eighteenth and nineteenth transistors T18 and T19. Since the pull-up node Q is at a low level and the pull-down node Q is at a high level, the tenth transistor T10 is turned off, the eleventh transistor T11 is turned on, and the output signal terminal OUT is discharged to a low level.

In period (r), the second clock terminal CK is received at a high level and the first clock terminal XCK is received at a low level. The eighth transistor T8 is turned off, so that the pull-down node QB is maintained at a high level, the pull-up node Q is maintained at a low level, and the output signal terminal OUT continues to be maintained at a low level.

Then, the operation of period (9) and the operation in the area in the cavity are repeated, and the output signal terminal OUT is continuously maintained in the low level state.

As shown in fig. 6, in the first phase, i.e. the reset and compensation phase, in response to the first control signal terminal SCl being at a high level, the shift register unit generates an output signal at a continuously high level and outputs the output signal at the output signal terminal OUT; in response to the high level of the second control signal terminal SC2, the first reset circuit of the shift register unit resets the pull-down node QB to the high level and resets the pull-up node Q to the low level, thereby changing the output signal of the output signal terminal OUT to the low level. In this way, the shift register unit generates gate driving signals for compensation and reset in the first stage.

In the second phase, i.e., the data writing phase, the high level of the third control signal terminal SC3, the shift register unit pulls up the pull-up node Q to the high level based on the input signal of the input signal terminal STU, thereby generating the output signal of the high level at the output signal terminal OUT. In response to the first arrival of the high level of the first clock signal XCK and the low level of the second clock signal CK, the second reset circuit of the shift register unit resets the pull-down node QB to the high level, and the control circuit pulls down the pull-up node Q to the low level, thereby generating an output signal of the low level at the output signal terminal OUT. In this way, the shift register unit generates a gate driving signal for data writing in the second stage. It can be seen that the waveform of the gate driving signal generated in the second stage is different from the waveform of the gate driving signal generated in the first stage.

Fig. 7 schematically shows a simulation diagram of signal timing of a gate driving circuit of an exemplary embodiment of the present disclosure. The timing chart is applicable to the gate driver circuit of any of the embodiments described above.

The signal timing of fig. 7 will be described in detail with reference to the gate driving circuit of fig. 4. For convenience of description, only the output signals OUT <1>, OUT <2>, OUT <3>, OUT <28>, OUT <29>, OUT <30>, OUT <52>, OUT <53> and OUT <54> of the first to third shift registers, the 28 to 30 shift registers and the 52 to 54 shift registers are shown in fig. 7.

As shown in fig. 7, in the first stage, the shift registers of the respective stages perform the operation of the first stage as described above under the control of the first control signal and the second control signal. For example, the first stage of the shift register unit GOA1 generates the output signal OUT <1> by using the signal timing of the first stage as shown in fig. 5. Since the input signal terminal STU of the next-stage shift register unit GOA _2 is connected to the output signal terminal OUT of the next-stage shift register unit GOA _1 and the clock signals of the two clock signal terminals are in anti-phase with the shift register unit GOA _1, the output signal OUT <1> of the previous-stage output signal terminal OUT is used as the input signal of the next-stage input signal terminal STU, and the second-stage output signal OUT <2> having the same waveform as the first-stage output signal OUT <1> is generated. By analogy, each stage of shift register unit generates synchronous output signals in the first stage. As shown in the first stage of fig. 7, the outputs OUT <1>, OUT <2>, OUT <3> … … OUT <28>, OUT <29>, OUT <30> … … OUT <52>, OUT <53>, OUT <54> continue high for the same period.

In the second stage, the shift registers of the respective stages perform the second-stage operation as described above under the control of the first control signal and the second control signal. For example, the first stage of shift register unit GOA _1 generates the output signal OUT <1> with the signal timing of the first stage as shown in fig. 5. Since the input signal terminal STU of the next-stage shift register unit GOA _2 is connected to the output signal terminal OUT of the next-stage shift register unit GOA _1 and the clock signals of the two clock signal terminals are in anti-phase with the shift register unit GOA _1, the output signal OUT <1> of the previous-stage output signal terminal OUT is used as the input signal of the next-stage input signal terminal STU, and the second-stage output signal OUT <2> shifted with respect to the first-stage output signal OUT <1> is generated. By analogy, each stage of shift register unit generates output signals which are sequentially shifted in the first stage. As shown in the second stage of FIG. 7, the outputs OUT <1>, OUT <2>, OUT <3> … … OUT <28>, OUT <29>, OUT <30> … … OUT <52>, OUT <53>, OUT <54> are sequentially shifted pulse signals.

As shown in fig. 8, each frame includes a reset compensation phase, a data writing phase, and a light emitting phase. In the reset compensation stage, output signals of all stages of shift registers in the gate driving circuit are all high level and are kept for a period of time at the high level, so that the functions of reset and compensation are completed. After the reset compensation stage is finished, a data writing stage is started, each cascaded shift register generates output signals shifted in sequence, and therefore pixels of the display area are scanned step by step so that data writing can be conducted on the pixels. And entering a light-emitting stage after data writing, and driving the pixels of the display area to emit light so as to finish the display of one frame.

According to the embodiment of the disclosure, by reducing the number of the shift register units, one shift register unit is adopted, functions of reset compensation and data writing can be realized, the number of the shift register units is reduced, the product frame can be effectively reduced, the number of signal lines can be reduced by adopting one shift register unit, the structure is simplified, and the product yield is effectively improved.

It will be appreciated by those skilled in the art that the embodiments described above are exemplary and can be modified by those skilled in the art, and that the structures described in the various embodiments can be freely combined without conflict in structure or principle.

Having described preferred embodiments of the present disclosure in detail, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and the disclosure is not limited to the exemplary embodiments set forth herein.

Claims

1. A shift register cell comprising:

a first input circuit, connected to a first control signal terminal, a power supply signal terminal, and a pull-up node of the shift register unit, configured to supply a potential of the power supply signal terminal to the pull-up node under signal control of the first control signal terminal;

a first reset circuit, connected to a second control signal terminal, the power signal terminal, a reference signal terminal, the pull-up node, and a pull-down node of the shift register unit, and configured to provide a potential of the power signal terminal to the pull-down node and a potential of the reference signal terminal to the pull-up node under the control of a signal of the second control signal terminal;

a second input circuit connected to an input signal terminal, a third control signal terminal, a clock signal terminal, and the pull-up node, and configured to supply a potential of the input signal terminal to the pull-up node under control of the third control signal terminal and the clock signal terminal;

a second reset circuit connected to the clock signal terminal, the input signal terminal, the power signal terminal, and the pull-down node, configured to control a potential of the pull-down node under control of the clock signal terminal and the input signal terminal, and to electrically isolate the power signal terminal from the pull-down node under control of the clock signal terminal and the input signal terminal;

an output circuit connected to the pull-up node, the pull-down node, the power supply signal terminal, the reference signal terminal, and an output signal terminal, and configured to supply a signal of the power supply signal terminal to the output signal terminal under control of a potential of the pull-up node and supply a potential of the reference signal terminal to the output signal terminal under control of a potential of the pull-down node; and

a control circuit connected to the pull-up node and the pull-down node, configured to pull down a potential of the pull-down node according to a potential of the pull-up node, and pull down a potential of the pull-up node according to a potential of the pull-down node;

the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, and the second reset circuit includes:

a gate of the fifth transistor is connected to the second clock signal terminal, and a first electrode of the fifth transistor is connected to the power signal terminal;

a sixth transistor, a gate of which is connected to the input signal terminal, a first pole of which is connected to the second clock signal terminal, and a second pole of which is connected to the second pole of the fifth transistor;

a seventh transistor, a gate of which is connected to the second pole of the fifth transistor, and a first pole of which is connected to the first clock signal terminal;

a gate of the eighth transistor is connected to the first clock signal terminal, a first pole of the eighth transistor is connected to the second pole of the seventh transistor, and the second pole of the eighth transistor is connected to the pull-down node;

and a first end of the second capacitor is connected with the grid electrode of the seventh transistor, and a second end of the second capacitor is connected with the second pole of the seventh transistor.

2. The shift register cell of claim 1, wherein the second input circuit comprises:

a first transistor, a gate of which is connected to the clock signal terminal, and a first pole of which is connected to the input signal terminal;

and a gate of the second transistor is connected to the third control signal terminal, a first pole of the second transistor is connected to a second pole of the first transistor, and a second pole of the second transistor is connected to the pull-up node.

3. The shift register unit according to claim 2, wherein the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, the gate of the first transistor is connected to the first clock signal terminal, the second input circuit further comprises:

a third transistor, a gate of which is connected to the pull-up node, and a first pole of which is connected to the second clock signal terminal;

a fourth transistor, a gate of which is connected to the third control signal terminal, and a first pole of which is connected to a second pole of the third transistor;

and a first end of the first capacitor is connected with the pull-up node, and a second end of the first capacitor is connected with the second pole of the fourth transistor.

4. The shift register cell of claim 1, wherein the second reset circuit further comprises: a ninth transistor, a gate of the ninth transistor is connected to the second control signal terminal, a first pole of the ninth transistor is connected to the power signal terminal, and a second pole of the ninth transistor is connected to the second pole of the fifth transistor.

5. The shift register cell of claim 3, wherein the output circuit comprises:

a tenth transistor, a gate of which is connected to the pull-up node, a first pole of which is connected to the power signal terminal, and a second pole of which is connected to the output signal terminal;

an eleventh transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the reference signal terminal, and a second pole of which is connected to the output signal terminal;

a first end of the third capacitor is connected with the pull-up node, and a second end of the third capacitor is connected with the output signal end;

and a first end of the fourth capacitor is connected with the pull-down node, and a second end of the fourth capacitor is connected with the reference signal end.

6. The shift register cell of claim 1, wherein the first reset circuit comprises:

a first reset sub-circuit, connected to the second control signal terminal, the reference signal terminal and the pull-up node, configured to provide a potential of the reference signal terminal to the pull-up node under the control of a signal of the second control signal terminal;

a second reset sub-circuit connected to the second control signal terminal, the power signal terminal, and the pull-down node, and configured to supply a potential of the power signal terminal to the pull-down node under control of a signal of the second control signal terminal.

7. The shift register cell of claim 6, wherein the first reset subcircuit comprises:

a twelfth transistor, a gate of the twelfth transistor is connected to the second control signal terminal, a first pole of the twelfth transistor is connected to the reference signal terminal, and a second pole of the twelfth transistor is connected to the pull-up node.

8. The shift register cell of claim 6, the first reset subcircuit comprising:

a thirteenth transistor, a gate of which is connected to the second control signal terminal, and a first pole of which is connected to the reference signal terminal; and

a fourteenth transistor, a gate of the fourteenth transistor is connected to the second control signal terminal, a first pole of the fourteenth transistor is connected to a second pole of the thirteenth transistor, and a second pole of the fourteenth transistor is connected to the pull-up node.

9. The shift register cell of claim 6, wherein the second reset subcircuit comprises:

a fifteenth transistor, a gate of which is connected to the second control signal terminal, a first pole of which is connected to the power signal terminal, and a second pole of which is connected to the pull-down node.

10. The shift register cell of claim 1, wherein the first input circuit comprises:

and a sixteenth transistor, wherein a gate of the sixteenth transistor is connected to the first control signal terminal, a first electrode of the sixteenth transistor is connected to the power signal terminal, and a second electrode of the sixteenth transistor is connected to the pull-up node.

11. The shift register cell of claim 1, wherein the control circuit comprises:

a first control sub-circuit connected to the pull-up node, the pull-down node, and the reference signal terminal, and configured to supply a potential of the reference signal terminal to the pull-up node under control of a potential of the pull-down node;

a second control sub-circuit connected to the pull-up node, the pull-down node, and the reference signal terminal, and configured to supply a potential of the reference signal terminal to the pull-down node under control of a potential of the pull-up node.

12. The shift register cell of claim 11, wherein the first control subcircuit comprises:

a seventeenth transistor, a gate of the seventeenth transistor being connected to the pull-down node, a first pole of the seventeenth transistor being connected to the reference signal terminal, and a second pole of the seventeenth transistor being connected to the pull-up node.

13. The shift register cell of claim 11, wherein the first control sub-circuit comprises:

a gate of the eighteenth transistor is connected to the pull-down node, and a first electrode of the eighteenth transistor is connected to the reference signal terminal;

a nineteenth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the second pole of the eighteenth transistor, and a second pole of which is connected to the pull-up node.

14. The shift register cell of claim 11, wherein the second control subcircuit includes a twentieth transistor, a gate of the twentieth transistor being connected to the pull-up node, a first pole of the twentieth transistor being connected to the reference signal terminal, a second pole of the twentieth transistor being connected to the pull-down node.

15. The shift register cell of claim 11, wherein the second control sub-circuit comprises:

a twenty-first transistor, wherein a gate of the twenty-first transistor is connected to the pull-up node, and a first pole of the twenty-first transistor is connected to the reference signal terminal;

a twenty-second transistor, a gate of the twenty-second transistor being connected to the pull-up node, a first pole of the twenty-second transistor being connected to a second pole of the twenty-first transistor, a second pole of the twenty-second transistor being connected to the pull-down node.

16. The shift register cell of any one of claims 1-15, wherein the first reset sub-circuit of the first reset circuit comprises a thirteenth transistor and a fourteenth transistor, the first control sub-circuit of the control circuit comprises an eighteenth transistor and a nineteenth transistor, the shift register cell further comprising:

a twenty-third transistor, a gate of the twenty-third transistor being connected to the pull-up node, a first pole of the twenty-third transistor being connected to the power supply signal terminal, and a second pole of the twenty-third transistor being connected to the second pole of the thirteenth transistor, the first pole of the fourteenth transistor, the second pole of the eighteenth transistor, and the first pole of the nineteenth transistor.

17. The shift register cell of any one of claims 1 to 15, further comprising: and the output circuit is connected to the output signal end of the shift register unit through the load circuit.

18. A gate drive circuit comprising a plurality of cascaded stages of shift register cells as claimed in any one of claims 1 to 17.

19. The gate drive circuit of claim 18, wherein,

the first control signal end of each shift register unit is connected to receive a first control signal, the second control signal end is connected to receive a second control signal, and the third control signal end is connected to receive a third control signal;

the input signal end of the nth stage shift register unit is connected with the output signal end of the nth-x stage shift register unit, wherein n is an integer greater than 1, and x is an integer greater than or equal to 1;

the first clock signal end of the n-x stage shift register unit is connected to receive a first clock signal, and the second clock signal end of the n-x stage shift register unit is connected to receive a second clock signal;

the first clock signal end of the nth stage shift register unit is connected to receive the second clock signal, and the second clock signal end of the nth stage shift register unit is connected to receive the first clock signal.

20. A method of controlling a shift register cell as claimed in any one of claims 1 to 17, comprising:

in the first stage, the first input circuit provides the potential of a power signal end to a pull-up node under the control of a signal of a first control signal end, the potential of the pull-up node enables the output circuit to provide a signal of the power signal end to the output signal end and enables the control circuit to pull down the potential of the pull-down node, the first reset circuit provides the potential of the power signal end to the pull-down node and provides the potential of a reference signal end to the pull-up node under the control of a signal of a second control signal end, and the potential of the pull-down node enables the output circuit to provide a signal of the reference signal end to the output signal end and enables the control circuit to pull down the potential of the pull-up node;

in the second stage, the second input circuit provides the potential of the input signal end to the pull-up node under the control of the third control signal end and the clock signal end, the potential of the pull-up node enables the output circuit to provide the signal of the power signal end to the output signal end and enables the control circuit to pull down the potential of the pull-down node, the second reset circuit pulls up the potential of the pull-down node under the control of the signals of the clock signal end, the input signal end and the power signal end, and the potential of the pull-down node enables the output circuit to provide the signal of the reference signal end to the output signal end and enables the control circuit to pull down the potential of the pull-up node.

21. The method of claim 20, further comprising: in a first phase, the second reset circuit electrically isolates the power signal terminal from the pull-down node under the control of the clock signal terminal and the input signal terminal.