CN110140433B - 电子模块以及电子模块的制造方法 - Google Patents
电子模块以及电子模块的制造方法 Download PDFInfo
- Publication number
- CN110140433B CN110140433B CN201780077608.6A CN201780077608A CN110140433B CN 110140433 B CN110140433 B CN 110140433B CN 201780077608 A CN201780077608 A CN 201780077608A CN 110140433 B CN110140433 B CN 110140433B
- Authority
- CN
- China
- Prior art keywords
- sealing resin
- substrate
- main surface
- electronic component
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K5/00—Casings, cabinets or drawers for electric apparatus
- H05K5/06—Hermetically-sealed casings
- H05K5/065—Hermetically-sealed casings sealed by encapsulation, e.g. waterproof resin forming an integral casing, injection moulding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K5/00—Casings, cabinets or drawers for electric apparatus
- H05K5/02—Details
- H05K5/0247—Electrical details of casings, e.g. terminals, passages for cables or wiring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/002—Casings with localised screening
- H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81439—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83862—Heat curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09936—Marks, inscriptions, etc. for information
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10545—Related components mounted on both sides of the PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10719—Land grid array [LGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1316—Moulded encapsulation of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1327—Moulding over PCB locally or completely
Abstract
提供具备辨识性高的印字并抑制翘曲的产生的电子模块,具备具有第一主面(1A)以及第二主面(1B)的基板(1)、安装于第一主面(1A)的第一电子部件(5、6)、安装于第二主面(1B)的第二电子部件(8、9)、第一密封树脂(14A)以及第二密封树脂(14B),贯通基板(1)和第一密封树脂(14A)形成贯通孔(4、24),在贯通孔(4、24)的内部安装有第三电子部件(10),在贯通孔(4、24)与第三电子部件(10)之间填充第二密封树脂(14B)且第二密封树脂(14B)形成为从第一密封树脂(14A)的表面露出,沿基板(1)的法线方向透视的情况下,第二密封树脂(14B)包围第三电子部件(10),第一密封树脂和第二密封树脂由不同种类的树脂构成。
Description
技术领域
本发明涉及电子模块。
背景技术
在专利文献1(日本专利第5454681号公报)中公开了一种为了安装高度高的电子部件而在基板设置贯通孔,并在该贯通孔内配置高度高的电子部件的电子模块。
图10表示专利文献1公开的电子模块(模块基板)1000。
电子模块1000具备基板(芯基板)101。在基板101中贯通上侧主面和下侧主面形成有贯通孔(cavity)102。
在基板101的上侧主面以及下侧主面分别安装有电子部件103。
另外,电子模块1000具备高度高(厚度大)的电子部件104。在底面形成有多个电极,并使用那些电极将电子部件104安装于中继基板(小片基板)105。而且,通过将中继基板105安装于基板的上侧主面的贯通孔102周边部分,从而将电子部件104配置在贯通孔102的内部。
电子模块1000具备密封树脂(树脂层)106。密封树脂106形成在基板101的上侧主面和下侧主面这两方。另外,密封树脂106也被填充到贯通孔102的内壁和电子部件104的缝隙中。密封树脂106由一种树脂形成。即,在基板101的上侧主面、基板101的下侧主面以及贯通孔102的内部,密封树脂106由一种单一的树脂形成。
此外,在电子模块1000中,将中继基板105安装于基板的上侧主面的贯通孔102部分,并使高度高的电子部件104从基板101的下侧主面突出地配置。然而,对此加以变更,也可以将中继基板105安装于基板的下侧主面的贯通孔102部分,并使高度高的电子部件104从基板101的上侧主面突出地配置。特别是在基板101的上侧主面的密封树脂106的厚度尺寸大于基板101的下侧主面的密封树脂106的厚度尺寸的情况下,将中继基板105安装于基板的下侧主面的贯通孔102部分,并使高度高的电子部件104从基板101的上侧主面突出地配置更能够有助于使电子部件104采用高度更高(厚度较大)的电子部件。
专利文献1:日本专利第5454681号公报
在对电子模块1000加以变更,将中继基板105安装于基板101的下侧主面的贯通孔102部分,并使高度高的电子部件104从基板101的上侧主面突出地配置的情况下,存在以下所说明那样的问题。
即,在使高度高的电子部件104从基板101的上侧主面突出地配置的情况下,电子模块1000被施加热,所以有时在形成在基板101的上侧主面上的密封树脂106的顶面产生凹凸。即,在使高度高的电子部件104从基板101的上侧主面突出地配置的情况下,电子部件104的周围的密封树脂106的厚度尺寸被也加到填充至贯通孔102的内部的树脂的厚度尺寸,从而与其它部分(未形成贯通孔102的部分)的厚度尺寸相比非常大。因此,若在利用回流焊安装电子模块1000时等被施加热,则贯通孔102的正上方的密封树脂106的顶面与其它部分相比,较大地膨胀并隆起,有时在顶面产生凹凸。即,存在由于被施加热而在形成于基板101的上侧主面的密封树脂106的顶面产生凹凸的情况。
而且,假如在贯通孔102的正上方的密封树脂106的顶面对产品编号、生产日、生产批次、方向性等信息进行印字的情况下,印字会被破坏,有可能无法读取印字。
发明内容
本发明的电子模块是为了解决上述的以往课题而完成的,作为其手段,本发明的模块具备:基板,具有第一主面以及第二主面;至少一个第一电子部件,被安装于第一主面;至少一个第二电子部件,被安装于第二主面;第一密封树脂,在第一主面覆盖第一电子部件而形成;以及第二密封树脂,在第二主面覆盖第二电子部件而形成,贯通基板和第一密封树脂形成至少一个贯通孔,在贯通孔的内部安装有第三电子部件,在贯通孔的内壁与第三电子部件之间填充第二密封树脂,并且第二密封树脂形成为从第一密封树脂的表面露出,沿基板的法线方向上透视的情况下,第二密封树脂包围第三电子部件,第一密封树脂和第二密封树脂由不同种类的树脂构成。
此外,第一密封树脂和第二密封树脂由不同种类的树脂构成是指例如构成两者的树脂的、组成、固化时的收缩率、固化度、线膨胀系数、杨氏模量、颜色、有无含有填料、填料的含有率、填料的大小、玻璃化温度等中至少一个不同。
优选,对除了局部露出的第二密封树脂的表面以外的第一密封树脂的表面实施印字。其原因在于即使完成的电子模块被施加例如由回流焊所引起的热而在包含局部露出的第二密封树脂的表面的第一密封树脂的表面产生凹凸,也只要事先除去局部露出的第二密封树脂的表面来实施印字,就不会因凹凸导致损害印字的辨识性。即,由于被施加所造成的凹凸相对于第一密封树脂的表面以局部露出的第二密封树脂的表面为中心而产生,所以只要事先除去局部露出的第二密封树脂的表面来实施印字,就不会因凹凸导致损害印字的辨识性。
优选构成第一密封树脂的树脂和构成第二密封树脂的树脂的线膨胀系数不同。该情况下,通过调整构成第一密封树脂的树脂和构成第二密封树脂的树脂的线膨胀系数,能够抑制被施加热时的翘曲的产生。
另外,优选构成第一密封树脂的树脂和构成第二密封树脂的树脂的杨氏模量不同。此时,通过调整构成第一密封树脂的树脂和构成第二密封树脂的树脂的杨氏模量,能够抑制被施加热时的翘曲的产生。
优选在未形成贯通孔的部分中,第一密封树脂的厚度尺寸大于第二密封树脂的厚度尺寸。此时,可以使安装于贯通孔的内部的电子部件的高度尺寸增大。
另外,本发明的电子模块的制造方法依次具备如下的工序:准备基板的工序,基板具有第一主面以及第二主面且贯通第一主面与第二主面之间形成有至少一个贯通孔;将第二电子部件安装于基板的第二主面,并且使第三电子部件从基板的第一主面局部突出地安装于基板的贯通孔的内部的工序;在基板的第二主面、形成在贯通孔与第三电子部件之间的空隙的内部以及从基板的第一主面局部突出的第三电子部件的周围形成第二密封树脂,以便覆盖第二电子部件以及第三电子部件的工序;在基板的第一主面安装第一电子部件的工序;以及在基板的第一主面形成第一密封树脂,以便覆盖第一电子部件且包围第二密封树脂的工序,其中该第二密封树脂在基板的第一主面上形成在第三电子部件的周围,第一密封树脂和第二密封树脂由不同的种类的树脂构成,第二密封树脂从第一密封树脂的表面局部露出。
另外,本发明的另一个电子模块的制造方法依次具备如下的工序:准备具有第一主面以及第二主面的基板的工序;在基板的第一主面安装第一电子部件的工序;在基板的第一主面形成第一密封树脂,以便覆盖第一电子部件的工序;形成贯通基板以及第一密封树脂的至少一个贯通孔的工序;在基板的第二主面安装第二电子部件,并在基板的贯通孔的内部安装第三电子部件的工序;以及在基板的第二主面和贯通孔的内部形成第二密封树脂,以便覆盖第二电子部件以及第三电子部件的工序,第一密封树脂和第二密封树脂由不同种类的树脂构成,第二密封树脂从第一密封树脂的表面局部露出。根据该制法方法,能够容易地制作本发明的电子模块。
优选在上述的本发明的电子模块的制造方法中,还具备在第一密封树脂的表面的除了第二密封树脂露出的部分以外的部分形成印字的工序。此时,能够对电子模块的品种、产品编号、生产日、生产批次、方向性等信息进行印字。此外,优选形成印字的工序通过照射激光来进行。此时,能够容易地进行印字。
在本发明的电子模块中,由于第一密封树脂和第二密封树脂由不同种类的树脂构成,第二密封树脂从第一密封树脂的表面局部露出,所以能够容易地识别形成于基板的贯通孔的位置。贯通孔的正上方的电子模块的顶面在被施加热的情况下容易产生凹凸,但只要事先除去该部分来形成印字,则即使产生凹凸也不会损害印字的辨识性。
另外,对于本发明的电子模块而言,由于第一密封树脂和第二密封树脂由不同种类的树脂构成,所以通过调整构成两者的树脂的、固化时的收缩率、固化度、线膨胀系数、杨氏模量等,能够抑制在使第一密封树脂、第二密封树脂固化时、由回流焊等施加热时产生翘曲这一情况。
根据本发明的电子模块的制法方法,能够容易地制作本发明的电子模块。
附图说明
图1是表示第一实施方式所涉及的电子模块100的剖视图。
图2的(A)~(D)分别是表示在电子模块100的制造方法1中所实施的工序的剖视图。
图3的(E)~(G)是图2(D)的后续,分别是表示在电子模块100的制造方法1中所实施的工序的剖视图。
图4的(H)~(J)是图3(G)的后续,分别是表示在电子模块100的制造方法1中所实施的工序的剖视图。
图5的(A)~(C)分别是表示在电子模块100的制造方法2中所实施的工序的剖视图。
图6的(D)~(F)的图5(C)的后续,分别是表示在电子模块100的制造方法2中所实施的工序的剖视图。
图7的(G)、(H)是图6(F)的后续,分别是表示在电子模块100的制造方法2中所实施的工序的剖视图。
图8是表示第二实施方式所涉及的电子模块200的剖视图。
图9是表示第三实施方式所涉及的电子模块300的剖视图。
图10是表示专利文献1所公开的电子模块1000的剖视图。
具体实施方式
以下,与附图一起对用于实现本发明的方式进行说明。
此外,各实施方式例示地示出本发明的实施方式,本发明不限定于实施方式的内容。另外,也能够组合不同的实施方式所记载的内容来实施,该情况下的实施内容也包含于本发明。另外,附图用于帮助说明书的理解,有时示意性地被描绘出。存在所描绘的构成要素或构成要素之间的尺寸的比率与说明书所记载的它们的尺寸的比率不一致的情况。另外,说明书所记载的构成要素有在附图中被省略的情况、省略个数来描绘的情况等。
[第一实施方式]
图1表示第一实施方式所涉及的电子模块100。其中,图1是电子模块100的剖视图。
电子模块100具备基板1。基板1的材质是任意的,例如能够使用使用了PCB(PolyChlorinated Biphenyl;多氯联苯)等的树脂基板、使用了LTCC(Low Temperature Co-fired Ceramics;低温共烧陶瓷)等的陶瓷基板。另外,基板1的构造也是任意的,可以是多层基板,也可以是单层基板。
基板1具有第一主面1A(上侧主面)和第二主面1B(下侧主面)。
在第一主面1A形成有电路布线图案2,在第二主面1B形成有电路布线图案3。电路布线图案2、3例如由银、铜等金属构成。
在基板1中,贯通第一主面1A和第二主面1B之间形成有将电路布线图案2、3的规定位置彼此连接的导通孔导体(未图示)。
在基板1中,贯通第一主面1A和第二主面1B之间形成有贯通孔4。贯通孔4用于安装(收容)后述的第三电子部件所涉及的电子部件10。贯通孔4比电子部件10大100μm~1000μm左右地形成,以便在形成后述的第二密封树脂14B时提高树脂的流动性。
电子模块100具备电子部件5、6作为安装于基板1的第一主面1A上的第一电子部件。电子部件5是在两端形成有电极的片状部件。电子部件6是在底面形成有多个电极的LGA(Land grid array:栅格阵列封装)型部件。电子部件5、6的电极通过焊料7与电路布线图案2连接。但是,代替焊料7,电子部件6的电极也可以通过凸起(金凸起、焊料凸起等)与电路布线图案2连接,其中,该电子部件6是LGA型部件。
电子模块100具备电子部件8、9作为安装于基板1的第二主面1B上的第二电子部件。电子部件8是在两端形成有电极的片状部件。电子部件9是底面形成有多个电极的LGA型部件。电子部件8、9的电极通过焊料7与电路布线图案3连接。但是,代替焊料7,电子部件9的电极也可以通过凸起(金凸起焊料凸起等)与电路布线图案3连接,其中,该电子部件9是LGA型部件。
电子模块100具备电子部件10作为安装于贯通孔4的内部的第三电子部件。电子部件10是底面形成有多个电极的LGA型部件。使用在一个主面(图中的上侧主面)形成有电路布线图案12的中继基板11,将电子部件10安装于贯通孔4的内部。具体而言,电子部件10的电极通过焊料7与形成在中继基板11上的电路布线图案12连接。而且,形成在中继基板11上的另一电路布线图案12通过焊料7与形成在基板1的第二主面1B(下侧主面)上的电路布线图案3连接。
此外,使电子部件10的电极与形成在中继基板11上的电路布线图案12连接的焊料7优选是高熔点焊料。或者,也可以使用热固化性的导电性糊剂来代替焊料7。另一方面,使形成在中继基板11上的另一电路布线图案12与电路布线图案3连接的焊料7优选是低熔点焊料。即,由于使电子部件10的电极与形成在中继基板11上的电路布线图案12连接之后,再使形成在中继基板11上的另一电路布线图案12与电路布线图案3连接,所以如果不使焊料满足上述的关系,则当使形成在中继基板11上的另一电路布线图案12与电路布线图案3连接时,电子部件10的电极有可能从中继基板11的电路布线图案12脱离。
在贯通孔4的内壁与安装于贯通孔4的内部的电子部件(第三电子部件)10之间形成有间隙13。
在电子模块100中,在基板1的第一主面1A形成有第一密封树脂14A。第一密封树脂14A覆盖电子部件(第一电子部件)5、6来进行保护。第一密封树脂14A例如由环氧树脂、聚酰亚胺树脂形成。第一密封树脂14A中形成有贯通孔24,该贯通孔24与基板1的贯通孔4连接且到达第一密封树脂14A的表面(顶面)。
在电子模块100中,在基板1的第二主面1B形成有第二密封树脂14B。第二密封树脂14B覆盖电子部件(第二电子部件)8、9来进行保护。另外,第二密封树脂14B被填充到贯通孔4与电子部件(第三电子部件)10之间的间隙13,还被填充到形成在第一密封树脂14A中的贯通孔24与电子部件10之间的间隙13,并从第一密封树脂14A的表面(顶面)露出。其结果为,沿基板1的法线方向透视的情况下,第二密封树脂14B包围(覆盖)电子部件10来进行保护。第二密封树脂14B也例如由环氧树脂聚酰亚胺树脂形成。
在第二密封树脂14B的底面形成有多个连接端子15。连接端子15例如由银、铜等金属构成。虽然未进行图示,但形成在基板1上的电路布线图案3的规定位置和连接端子15根据需要通过贯通第二密封树脂14B形成的导通孔导体而连接。
虽然未进行图示,但在除了局部露出的第二密封树脂14B以外的、第一密封树脂14A的表面上,通过数字、符号、文字等对电子模块100的品种、产品编号、生产日、生产批次、方向性等信息进行印字。印字例如通过激光照射而形成,第一密封树脂14A的表面被雕刻到规定的深度。
可以根据需要而在电子模块100的顶面和四个侧面形成屏蔽膜。此时,能够通过屏蔽膜抑制噪声从外部侵入到电子模块100的内部这一情况,还能够抑制电子模块100使噪声放射到外部这一情况。此外,优选屏蔽膜与具备接地电位的连接端子15连接。
在电子模块100中,第一密封树脂14A和第二密封树脂14B由不同种类的树脂构成。其中,由不同种类的树脂构成是指例如构成两者的树脂的组成、固化时的收缩率、固化度、线膨胀系数、杨氏模量、颜色、有无含有填料、填料的含有率、填料的大小等中的至少一个不同。
在电子模块100中,由于构成第一密封树脂14A的树脂和构成第二密封树脂14B的树脂由不同种类的树脂构成,所以可以抑制翘曲的产生。
例如,假设在由同一种类的树脂形成第一密封树脂14A和第二密封树脂14B的情况下,则在使第一密封树脂14A、第二密封树脂14B固化时、为了通过回流焊安装已完成的电子模块而进行加热时等,包括基板1整体有时产生翘曲。该翘曲是由于如下的情况而产生的,即,第一密封树脂14A的厚度尺寸和第二密封树脂14B的厚度尺寸不均匀、第一密封树脂14A覆盖的电子部件(第一电子部件)5、6的总体积和第二密封树脂14B覆盖的电子部件(第二电子部件)8、9的总体积不均匀等。通过产生翘曲,从而基板1的第一主面1A侧或者第二主面1B侧任意一侧收缩,另一侧膨胀。
当在使第一密封树脂14A、第二密封树脂14B固化时产生翘曲的情况下,通过调整构成第一密封树脂14A的树脂以及构成第二密封树脂14B的树脂的、固化时的收缩率,能够抑制翘曲的产生。更具体而言,假设在由构成第一密封树脂14A的树脂构成第一密封树脂14A以及第二密封树脂14B两方的情况下,或者,由构成第二密封树脂14B的树脂构成第一密封树脂14A以及第二密封树脂14B两方的情况下,则在使第一密封树脂14A以及第二密封树脂14B固化时,基板1的第一主面1A侧或者第二主面1B侧的任意一侧收缩,另一侧膨胀,产生翘曲的情况下,如果对构成形成在进行收缩的一侧的第一密封树脂14A或者第二密封树脂14B的树脂使用固化时的收缩率小的树脂,对构成形成在进行膨胀的一侧的第一密封树脂14A或者第二密封树脂14B的树脂使用固化时的收缩率大的树脂,则能够抑制使第一密封树脂14A和第二密封树脂14B固化时的翘曲的产生。
或者,在使第一密封树脂14A、第二密封树脂14B固化时产生翘曲的情况下,通过调整构成第一密封树脂14A的树脂以及构成第二密封树脂14B的树脂的固化度,能够抑制翘曲的产生。更具体而言,假设由构成第一密封树脂14A的树脂构成第一密封树脂14A以及第二密封树脂14B两方的情况下,或者,由构成第二密封树脂14B的树脂构成第一密封树脂14A以及第二密封树脂14B两方的情况下,则在使第一密封树脂14A以及第二密封树脂14B固化时,基板1的第一主面1A侧或者第二主面1B侧的任意一侧收缩,另一侧膨胀,产生翘曲的情况下,如果对构成形成在进行收缩的一侧的第一密封树脂14A或者第二密封树脂14B的树脂使用固化度低的树脂,对构成形成在进行膨胀的一侧的第一密封树脂14A或者第二密封树脂14B的树脂使用固化度高的树脂,则能够抑制使第一密封树脂14A和第二密封树脂14B固化时的翘曲的产生。
另外,在为了通过回流焊安装已完成的电子模块而进行加热时等产生翘曲的情况下,通过调整构成第一密封树脂14A的树脂以及构成第二密封树脂14B的树脂的线膨胀系数,能够抑制翘曲的产生。更具体而言,假设由构成第一密封树脂14A的树脂构成第一密封树脂14A以及第二密封树脂14B两方的情况下,或者,由构成第二密封树脂14B的树脂构成第一密封树脂14A以及第二密封树脂14B两方的情况下,则在该电子模块完成后被施加热时,基板1的第一主面1A侧或者第二主面1B侧的任意一侧收缩,另一侧膨胀而产生翘曲的情况下,如果对构成形成在进行收缩的一侧的第一密封树脂14A或者第二密封树脂14B的树脂使用线膨胀系数大的树脂,对构成形成在进行膨胀的一侧的第一密封树脂14A或者第二密封树脂14B的树脂使用线膨胀系数小的树脂,则能够抑制被施加热时的翘曲的产生。
或者,在为了通过回流焊安装已完成的电子模块而进行加热时等产生翘曲的情况下,通过调整构成第一密封树脂14A的树脂以及构成第二密封树脂14B的树脂的杨氏模量,能够抑制翘曲的产生。更具体而言,假设由构成第一密封树脂14A的树脂构成第一密封树脂14A以及第二密封树脂14B两方的情况下,或者,由构成第二密封树脂14B的树脂构成第一密封树脂14A以及第二密封树脂14B两方的情况下,则在该电子模块完成后被施加热时,基板的第一主面侧或者第二主面侧的任意一侧收缩,另一侧膨胀而产生翘曲的情况下,如果对构成形成在进行收缩的一侧的第一密封树脂14A或者第二密封树脂14B的树脂使用杨氏模量小的树脂,对构成形成在进行膨胀的一侧的第一密封树脂14A或者第二密封树脂14B的树脂使用杨氏模量大的树脂,则能够抑制被施加热时的翘曲的产生。
另外,在电子模块100中,由于构成第一密封树脂14A的树脂和构成第二密封树脂14B的树脂由不同种类的树脂构成,所以能够从顶面侧确认形成在基板1中的贯通孔4的位置。即,在电子模块100的顶面中,由于树脂的种类不同,所以在第一密封树脂14A与从第一密封树脂14A局部露出的第二密封树脂14B之间形成界面,能够确认形成在基板1中的贯通孔4的大致位置。
电子模块100的贯通孔4的正上方的顶面若在回流焊等时被施加热则容易产生凹凸,但在电子模块100中,能够对从第一密封树脂14A局部露出的第二密封树脂14B做标记而预先从顶面侧确认形成在基板1的贯通孔4的位置,所以能够将该部分除外来形成印字,只要事先那样操作,则即使在顶面产生凹凸,也不会损害印字的辨识性。
另外,虽然高度高的电子部件(第三电子部件)10的顶面大多位于从第一密封树脂14A局部露出的第二密封树脂14B其正下方,但在电子模块100中,由于能够将该部分除外来形成印字,所以即使在通过激光照射进行印字的情况下,电子部件10也不太可能通过激光照射损伤(熔融等)。
由以上的结构构成的第一实施方式所涉及的电子模块100能够例如通过以下说明的两个制造方法容易地制作。此外,在实际的制造工序中,通过使用母基板,并在中途进行单片化,由此一并制作多个电子模块100,但在以下,为了便于说明,对制作一个电子模块100的情况进行说明。
<电子模块100的制造方法1>
首先,如图2(A)所示,预先准备基板1,在该基板中,在第一主面1A形成电路布线图案2,在第二主面1B形成电路布线图案3,贯通两主面间形成将电路布线图案2、3的规定位置彼此连接的导通孔导体(未图示)。此外,在基板1是由LTCC等构成的陶瓷基板的情况下,在制作基板1时,例如利用如下说明的方法同时在基板1中形成贯通孔4。
在作为陶瓷基板的基板1为多层基板的情况下,通过在层叠前的各陶瓷生片形成掏空孔,将形成有掏空孔的多个陶瓷生片层叠来制作未烧制基板,并对该未烧制基板进行烧制,由此能够在烧制后的基板1形成贯通孔4。或者,通过将多个陶瓷生片层叠来制作未烧制基板,对该未烧制基板实施激光照射、利用加工机等进行的切削加工来形成贯通孔4后,对该未烧制基板进行烧制,由此能够在烧制后的基板1形成贯通孔4。另外,在作为陶瓷基板的基板1为单层基板的情况下,通过准备未烧制基板,对该未烧制基板实施激光照射、利用加工机等进行的切削加工来形成贯通孔4后,对该未烧制基板进行烧制,由此能够在烧制后的基板1形成贯通孔4。
另一方面,在基板1为由PCB等构成的树脂基板的情况下,如图2(B)所示,在基板1形成贯通孔4。具体而言,通过激光的照射、利用加工机等进行的切削,在基板1形成贯通孔4。作为激光,能够使用UV激光、CO2激光等。根据需要,在形成贯通孔4后,进行基板1的清洗。清洗可以干式清洗、湿式清洗的任何一个。在湿式清洗的情况下,能够进行超声波清洗。
与基板1的准备并行地准备电子部件(第三电子部件)10和中继基板11。预先在中继基板11的上侧主面形成电路布线图案12。而且,如图2(C)所示,通过焊料7使形成在电子部件10的底面的电极与中继基板11的规定的电路布线图案12连接。此外,对使电子部件10的电极与形成在中继基板11上的电路布线图案12连接的焊料7使用高熔点焊料。或者,也可以代替高熔点焊料而使用热固化性的导电性糊剂。
接下来,如图2(D)所示,通过焊料7将安装有电子部件(第二电子部件)8、9和电子部件10的中继基板11安装于形成在基板1的第二主面1B上的电路布线图案3。此外,对这些安装所使用的焊料7使用低熔点焊料。其结果为,电子部件10被安装于贯通孔4的内部。而且,在贯通孔4的内壁与电子部件10之间形成间隙13。另外,电子部件10从基板1的第一主面1A局部露出。
接下来,如图3(E)所示,从基板1的第一主面1A局部露出的电子部件10被盖状的成形用夹具51覆盖。成形用夹具51具有比电子部件10大的内尺寸。
接下来,如图3(F)所示,向基板1的第二主面1B上、基板1的贯通孔4的内部以及配置在基板1的第一主面的成形用夹具51的内部供给液状的树脂并使之固化,从而对第二密封树脂14B进行成形。其结果为,第二电子部件所涉及的电子部件8、9被第二密封树脂14B覆盖。另外,第三电子部件所涉及的电子部件10被第二密封树脂14B覆盖(包围)。此外,在本实施方式中,使用液状树脂对第二密封树脂14B进行了成形,但也可以代替该方法而采用传递成形、压缩成形等。在传递成形中,将安装有电子部件8、9以及与中继基板11连接的电子部件10的基板1收容在金属模(未图示)内,从树脂注入孔向金属模内注入树脂并使之固化来进行成形。在压缩成形中,在金属模内(未图示)中同时收容安装有电子部件8、9以及与中继基板11连接的电子部件10的基板1和秤量出的树脂的两方,并进行加压、固化来进行成形。
接下来,如图3(G)所示,从第二密封树脂14B除去成形用夹具51。
接下来,如图4(H)所示,通过焊料7将电子部件(第一电子部件)5、6安装于形成在基板1的第一主面1A的电路布线图案2。
接下来,如图4(I)所示,在基板1的第一主面1A上对第一密封树脂14A进行成形。其结果为,第一电子部件所涉及的电子部件5、6被第一密封树脂14A覆盖。此外,对第一密封树脂14A的成形能够采用利用液状树脂的成形、传递成形、压缩成形、利用片材树脂的成形等。此外,在利用片材树脂的成形中,在安装于基板1的第一主面1A的电子部件5、6上叠加半熔融状态的树脂片,并进行加压、固化来进行成形。
接下来,如图4(J)所示,在第二密封树脂14B的底面通过溅射等形成连接端子15。另外,对除了局部露出的第二密封树脂14B以外的第一密封树脂14A的表面照射激光来对表示品种、产品编号、生产日、生产批次、方向性等信息的数字、符号、文字等进行印字,由此完成电子模块100。此外,也可以根据需要,在顶面和四个侧面通过薄膜技术形成屏蔽膜。
<电子模块100的制造方法2>
首先,如图5(A)所示,预先准备基板1,在该基板1中,在第一主面1A形成电路布线图案2,在第二主面1B形成电路布线图案3,贯通两主面间形成将电路布线图案2、3的规定位置彼此连接的导通孔导体(未图示)。此外,在基板1中,在该时刻未形成贯通孔4。
与基板1的准备并行地准备电子部件(第三电子部件)10和中继基板11。然后,如图5(B)所示,通过焊料7使形成在电子部件10的底面的电极与中继基板11的规定的电路布线图案12连接。此外,对使电子部件10的电极与形成在中继基板11上的电路布线图案12连接的焊料7使用高熔点焊料。
接下来,如图5(C)所示,通过焊料7将电子部件(第一电子部件)5、6安装于形成在基板1的第一主面1A的电路布线图案2。
接下来,如图6(D)所示,在基板1的第一主面1A上对第一密封树脂14A进行成形。其结果为,第一电子部件所涉及的电子部件5、6被第一密封树脂14A覆盖。此外,第一密封树脂14A的成形能够采用利用液状树脂的成形、传递成形、压缩成形、利用片材树脂的成形等。
接下来,如图6(E)所示,贯通基板1以及第一密封树脂14A在基板1形成贯通孔4,在第一密封树脂14A形成贯通孔24。贯通孔4、24通过激光的照射、利用加工机进行的切削而形成。
接下来,如图6(F)所示,通过焊料7将安装有电子部件(第二电子部件)8、9和电子部件10的中继基板11安装于形成在基板1的第二主面1B的电路布线图案3。其中,对这些安装所使用的焊料7使用低熔点焊料。其结果为,将电子部件10配置于贯通孔4、24的内部。
接下来,如图7(G)所示,向基板1的第二主面1B上和基板1的贯通孔4、24的内部供给树脂并使之固化,由此对第二密封树脂14B进行成形。其结果为,第二电子部件所涉及的电子部件8、9被第二密封树脂14B覆盖。另外,第三电子部件所涉及的电子部件10被第二密封树脂14B覆盖(包围)。此外,第二密封树脂14B的成形能够采用利用液状树脂的成形、传递成形、压缩成形等。
接下来,如图7(H)所示,在第二密封树脂14B的底面通过溅射等形成连接端子15。另外,对除了局部露出的第二密封树脂14B以外的第一密封树脂14A的表面照射激光来打压表示品种、产品编号、生产日、生产批次、方向性等信息的数字、符号、文字等,由此完成电子模块100。此外,也可以根据需要,在顶面和四个侧面通过薄膜技术形成屏蔽膜。
[第二实施方式]
图8表示第二实施方式所涉及的电子模块200。但是,图8是电子模块200的剖视图。
电子模块200对第一实施方式所涉及的电子模块100追加了构成。具体而言,在电子模块200中,在电子模块100的顶面和四个侧面形成屏蔽膜16。
屏蔽膜16虽然没有图示,但形成为由Ti、Ni、Cr、SUS或者Ti、Ni、Cr、SUS的合金构成的紧贴层、由Cu、Al、Ag或者Cu、Al、Ag的合金构成的导电层、由Ti、Ni、Cr或者Ti、Ni、Cr的合金构成的耐腐蚀层这3层结构。此外,优选屏蔽膜16与具备接地电位的连接端子15连接。
屏蔽膜16能够使用薄膜技术而形成。此外,通常,屏蔽膜16在对除了局部露出的第二密封树脂14B以外的第一密封树脂14A的表面进行印字后形成。但是,也可以事先掌握从第一密封树脂14A露出的第二密封树脂14B的位置,形成屏蔽膜16后,对除了第二密封树脂14B露出的部分以外的第一密封树脂14A上的屏蔽膜16上照射激光来形成印字。
电子模块200通过屏蔽膜16抑制噪声从外部向内部的侵入。另外,电子模块200通过屏蔽膜16抑制噪声向外部的放射。
[第三实施方式]
图9表示第三实施方式所涉及的电子模块300。其中,图9是电子模块300的剖视图。
电子模块300对第一实施方式所涉及的电子模块100加以变更。具体而言,在电子模块100中,作为安装于贯通孔4的内部的第三电子部件,使用底面形成有多个电极的LGA型部件的电子部件10,但在电子模块300中,代替电子部件10而使用两侧面形成有电极的电子部件30。具体而言,如图9所示,通过焊料7使电子部件30的电极与L字型的金属端子31连接,通过其它的焊料7使各金属端子31与形成在基板1的第二主面1B的电路布线图案3连接。此外,优选对使连接金属端子31与电子部件30的电极连接的焊料7使用高熔点焊料,对使金属端子31与电路布线图案3连接的焊料7使用低熔点焊料。
这样,安装于贯通孔4的内部的第三电子部件可以是侧面形成有电极的电子部件30。
以上,对第一实施方式~第三实施方式所涉及的电子模块100~300进行了说明。然而,本发明并不限于上述的内容,能够按照发明的主旨进行各种变更。
例如,在上述实施方式中,在基板设置一个贯通孔,在该贯通孔的内部配置电子部件,但也可以在基板设置多个贯通孔,在多个贯通孔每个的内部配置电子部件。
另外,在上述实施方式中,在一个贯通孔的内部配置一个电子部件,但也可以例如从基板的下侧和上侧分别配置电子部件,在一个贯通孔配置两个电子部件。
并且,由电子模块构成的电子电路是任意的,能够构成各种电子电路。
附图标记的说明
1…基板
1A…第一主面
1B…第二主面
2…电路布线图案(形成在第一主面1A的电路布线图案)
3…电路布线图案(形成在第二主面1B的电路布线图案)
4…贯通孔(形成在基板1的贯通孔)
5、6…电子部件(第一电子部件)
7…焊料
8、9…电子部件(第二电子部件)
10,30…电子部件(第三电子部件)
11…中继基板
12…电路布线图案(形成在11的电路布线图案)
13…间隙
14A…第一密封树脂
14B…第二密封树脂
15…连接端子
16…屏蔽膜
24…贯通孔(形成在第一密封树脂14A的贯通孔)
31…金属端子
51…成形用夹具
100、200、300…电子模块
Claims (11)
1.一种电子模块,具备:基板,具有第一主面以及第二主面;至少一个第一电子部件,被安装于上述第一主面;至少一个第二电子部件,被安装于上述第二主面;第一密封树脂,在上述第一主面覆盖上述第一电子部件而形成;以及第二密封树脂,在上述第二主面覆盖上述第二电子部件而形成,其中,
贯通上述基板和上述第一密封树脂形成至少一个贯通孔,
在上述贯通孔的内部安装有第三电子部件,
在上述贯通孔的内壁与上述第三电子部件之间填充上述第二密封树脂,并且上述第二密封树脂形成为从上述第一密封树脂的表面露出,
沿上述基板的法线方向透视的情况下,上述第二密封树脂包围上述第三电子部件,
上述第一密封树脂和上述第二密封树脂由不同种类的树脂构成。
2.根据权利要求1所述的电子模块,其中,
对除了局部露出的上述第二密封树脂的表面以外的上述第一密封树脂的表面实施印字。
3.根据权利要求1所述的电子模块,其中,
构成上述第一密封树脂的树脂和构成上述第二密封树脂的树脂的线膨胀系数不同。
4.根据权利要求2所述的电子模块,其中,
构成上述第一密封树脂的树脂和构成上述第二密封树脂的树脂的线膨胀系数不同。
5.根据权利要求1~4中的任意一项所述的电子模块,其中,
构成上述第一密封树脂的树脂和构成上述第二密封树脂的树脂的杨氏模量不同。
6.根据权利要求1~4中的任意一项所述的电子模块,其中,
在未形成上述贯通孔的部分中,上述第一密封树脂的厚度尺寸大于上述第二密封树脂的厚度尺寸。
7.根据权利要求5所述的电子模块,其中,
在未形成上述贯通孔的部分中,上述第一密封树脂的厚度尺寸大于上述第二密封树脂的厚度尺寸。
8.一种电子模块的制造方法,其中,
依次具备如下的工序:
准备基板的工序,上述基板具有第一主面以及第二主面且贯通上述第一主面与上述第二主面之间形成有至少一个贯通孔;
将第二电子部件安装于上述基板的上述第二主面,并且使第三电子部件从上述基板的上述第一主面局部突出地安装于上述基板的上述贯通孔的内部的工序;
在上述基板的上述第二主面、形成在上述贯通孔与上述第三电子部件之间的空隙的内部以及从上述基板的上述第一主面局部突出的上述第三电子部件的周围形成第二密封树脂,以便覆盖上述第二电子部件以及上述第三电子部件的工序;
在上述基板的上述第一主面安装第一电子部件的工序;以及
在上述基板的上述第一主面形成第一密封树脂以便覆盖上述第一电子部件且包围上述第二密封树脂的工序,上述第二密封树脂在上述基板的上述第一主面上形成在上述第三电子部件的周围,
上述第一密封树脂和上述第二密封树脂由不同种类的树脂构成,
上述第二密封树脂从上述第一密封树脂的表面局部露出。
9.一种电子模块的制造方法,其中,
依次具备如下的工序:
准备具有第一主面以及第二主面的基板的工序;
在上述基板的上述第一主面安装第一电子部件的工序;
在上述基板的上述第一主面形成第一密封树脂以便覆盖上述第一电子部件的工序;
形成贯通上述基板以及上述第一密封树脂的至少一个贯通孔的工序;
在上述基板的第二主面安装第二电子部件,并在上述基板的上述贯通孔的内部安装第三电子部件的工序;以及
在上述基板的上述第二主面和上述贯通孔的内部形成第二密封树脂以便覆盖上述第二电子部件以及上述第三电子部件的工序,
上述第一密封树脂和上述第二密封树脂由不同的种类的树脂构成,
上述第二密封树脂从上述第一密封树脂的表面局部露出。
10.根据权利要求8或者9所述的电子模块的制造方法,其中,
还具备在上述第一密封树脂的表面的除了上述第二密封树脂露出的部分以外的部分形成印字的工序。
11.根据权利要求10所述的电子模块的制造方法,其中,
通过激光的照射进行形成上述印字的工序。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016-243794 | 2016-12-15 | ||
JP2016243794 | 2016-12-15 | ||
PCT/JP2017/043780 WO2018110383A1 (ja) | 2016-12-15 | 2017-12-06 | 電子モジュールおよび電子モジュールの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110140433A CN110140433A (zh) | 2019-08-16 |
CN110140433B true CN110140433B (zh) | 2021-10-12 |
Family
ID=62558526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780077608.6A Active CN110140433B (zh) | 2016-12-15 | 2017-12-06 | 电子模块以及电子模块的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10660227B2 (zh) |
JP (1) | JP6677318B2 (zh) |
CN (1) | CN110140433B (zh) |
WO (1) | WO2018110383A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102524812B1 (ko) * | 2018-11-06 | 2023-04-24 | 삼성전자주식회사 | 반도체 패키지 |
WO2020202972A1 (ja) * | 2019-03-29 | 2020-10-08 | 太陽誘電株式会社 | モジュールおよびその製造方法 |
US11139268B2 (en) * | 2019-08-06 | 2021-10-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method of manufacturing the same |
WO2024057475A1 (ja) * | 2022-09-15 | 2024-03-21 | 株式会社Fuji | 樹脂積層体形成装置、および樹脂積層体形成方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101055858A (zh) * | 2006-04-10 | 2007-10-17 | 联华电子股份有限公司 | 半导体封装结构 |
CN101552254A (zh) * | 2008-04-04 | 2009-10-07 | 恩益禧电子股份有限公司 | 多层布线基板、半导体封装以及制造半导体封装的方法 |
JP2011119619A (ja) * | 2009-12-07 | 2011-06-16 | Renesas Electronics Corp | 半導体パッケージ |
WO2012165111A1 (ja) * | 2011-05-31 | 2012-12-06 | 株式会社村田製作所 | 多層基板の製造方法および多層基板 |
CN102907188A (zh) * | 2010-05-26 | 2013-01-30 | 株式会社村田制作所 | 模块基板及其制造方法 |
CN104701280A (zh) * | 2013-12-05 | 2015-06-10 | 株式会社村田制作所 | 元器件内置模块 |
CN104701189A (zh) * | 2014-12-29 | 2015-06-10 | 华进半导体封装先导技术研发中心有限公司 | 三层封装基板的制作方法及三层封装基板 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4587772B2 (ja) * | 2004-10-22 | 2010-11-24 | イビデン株式会社 | 多層プリント配線板 |
US7919849B2 (en) * | 2007-04-04 | 2011-04-05 | Ibiden Co., Ltd. | Package substrate and device for optical communication |
JPWO2009037833A1 (ja) * | 2007-09-21 | 2011-01-06 | パナソニック株式会社 | 立体プリント配線板およびその製造方法ならびに電子部品モジュール |
US8963016B2 (en) * | 2008-10-31 | 2015-02-24 | Taiyo Yuden Co., Ltd. | Printed wiring board and method for manufacturing same |
JP5892388B2 (ja) | 2011-01-12 | 2016-03-23 | 株式会社村田製作所 | 樹脂封止型モジュール |
JP5614566B2 (ja) * | 2011-06-03 | 2014-10-29 | 株式会社村田製作所 | 多層基板の製造方法および多層基板 |
CN104380848B (zh) * | 2012-07-05 | 2019-07-23 | 株式会社村田制作所 | 部件内置基板 |
WO2014188624A1 (ja) * | 2013-05-22 | 2014-11-27 | 株式会社カネカ | 放熱構造体 |
KR20150053579A (ko) * | 2013-11-08 | 2015-05-18 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
JP2015195263A (ja) * | 2014-03-31 | 2015-11-05 | マイクロン テクノロジー, インク. | 半導体装置及びその製造方法 |
JP6373219B2 (ja) * | 2015-03-31 | 2018-08-15 | 太陽誘電株式会社 | 部品内蔵基板および半導体モジュール |
JP2018157089A (ja) * | 2017-03-17 | 2018-10-04 | イビデン株式会社 | プリント配線板およびその製造方法 |
-
2017
- 2017-12-06 JP JP2018556608A patent/JP6677318B2/ja active Active
- 2017-12-06 CN CN201780077608.6A patent/CN110140433B/zh active Active
- 2017-12-06 WO PCT/JP2017/043780 patent/WO2018110383A1/ja active Application Filing
-
2019
- 2019-05-31 US US16/428,162 patent/US10660227B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101055858A (zh) * | 2006-04-10 | 2007-10-17 | 联华电子股份有限公司 | 半导体封装结构 |
CN101552254A (zh) * | 2008-04-04 | 2009-10-07 | 恩益禧电子股份有限公司 | 多层布线基板、半导体封装以及制造半导体封装的方法 |
JP2011119619A (ja) * | 2009-12-07 | 2011-06-16 | Renesas Electronics Corp | 半導体パッケージ |
CN102907188A (zh) * | 2010-05-26 | 2013-01-30 | 株式会社村田制作所 | 模块基板及其制造方法 |
WO2012165111A1 (ja) * | 2011-05-31 | 2012-12-06 | 株式会社村田製作所 | 多層基板の製造方法および多層基板 |
CN104701280A (zh) * | 2013-12-05 | 2015-06-10 | 株式会社村田制作所 | 元器件内置模块 |
CN104701189A (zh) * | 2014-12-29 | 2015-06-10 | 华进半导体封装先导技术研发中心有限公司 | 三层封装基板的制作方法及三层封装基板 |
Non-Patent Citations (1)
Title |
---|
LED封装用超支化聚酯改性环氧树脂的研究;曾庆鹏等;《中国塑料》;20131226(第12期);全文 * |
Also Published As
Publication number | Publication date |
---|---|
JPWO2018110383A1 (ja) | 2019-10-24 |
CN110140433A (zh) | 2019-08-16 |
WO2018110383A1 (ja) | 2018-06-21 |
JP6677318B2 (ja) | 2020-04-08 |
US10660227B2 (en) | 2020-05-19 |
US20190289737A1 (en) | 2019-09-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110140433B (zh) | 电子模块以及电子模块的制造方法 | |
JP5100081B2 (ja) | 電子部品搭載多層配線基板及びその製造方法 | |
JP6408540B2 (ja) | 無線モジュール及び無線モジュールの製造方法 | |
CN102119588B (zh) | 元器件内置模块的制造方法及元器件内置模块 | |
EP2911484A2 (en) | Printed circuit board and method of fabricating the same | |
CN102548253A (zh) | 多层电路板的制作方法 | |
JP6139653B2 (ja) | 部品内蔵樹脂多層基板 | |
US20090025210A1 (en) | Circuit board structure with concave conductive cylinders and method for fabricating the same | |
JP5708814B2 (ja) | モジュールの製造方法 | |
US20090316329A1 (en) | Chip component and method for producing the same and component built-in module and method for producing the same | |
TWI566355B (zh) | 電子元件封裝結構及製作方法 | |
CN104241231A (zh) | 芯片封装基板及其制作方法 | |
EP3291285A1 (en) | Semiconductor package structure with a polymer gel surrounding solders connecting a chip to a substrate and manufacturing method thereof | |
WO2017119249A1 (ja) | 多層基板及び多層基板の製造方法 | |
CN102136459B (zh) | 封装结构及其制法 | |
JP5539453B2 (ja) | 電子部品搭載多層配線基板及びその製造方法 | |
CN112533381B (zh) | 母板制作方法 | |
JP2015144165A (ja) | 回路モジュール及びその製造方法 | |
KR20170124769A (ko) | 전자 소자 모듈 및 그 제조 방법 | |
JP5250502B2 (ja) | 半導体装置及びその製造方法 | |
KR101080358B1 (ko) | 인쇄회로기판 제조방법 | |
CN109950017B (zh) | 电子部件以及电子部件的制造方法 | |
JP6735793B2 (ja) | 複合基板及びリジッド基板 | |
JP2019125746A (ja) | 電子部品搭載用基板、回路基板および電子部品搭載用基板の製造方法 | |
CN109275340B (zh) | 模块 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |