CN110137144A - 具有平坦化的钝化层的半导体器件及其制造方法 - Google Patents

具有平坦化的钝化层的半导体器件及其制造方法 Download PDF

Info

Publication number
CN110137144A
CN110137144A CN201910066850.4A CN201910066850A CN110137144A CN 110137144 A CN110137144 A CN 110137144A CN 201910066850 A CN201910066850 A CN 201910066850A CN 110137144 A CN110137144 A CN 110137144A
Authority
CN
China
Prior art keywords
passivation layer
semiconductor devices
top surface
active surface
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910066850.4A
Other languages
English (en)
Other versions
CN110137144B (zh
Inventor
金泳龙
白承德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN110137144A publication Critical patent/CN110137144A/zh
Application granted granted Critical
Publication of CN110137144B publication Critical patent/CN110137144B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H01L2224/14519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本公开提供了具有平坦化的钝化层的半导体器件及其制造方法。一种半导体器件包括：半导体基板，被分成焊盘区域和单元区域并具有有源表面和与有源表面相反的非有源表面；多个金属线，在半导体基板的有源表面上；钝化层，在半导体基板的有源表面上；以及多个凸块，在单元区域中。钝化层包括第一钝化层和第二钝化层，该第一钝化层覆盖所述多个金属线并具有沿着所述多个金属线的排布轮廓的非平坦的顶表面，该第二钝化层在第一钝化层的非平坦的顶表面上并具有其上设置所述多个凸块的平坦化的顶表面。

Description

具有平坦化的钝化层的半导体器件及其制造方法
技术领域
本发明构思涉及一种半导体器件以及制造该半导体器件的方法。更具体地，本发明构思涉及具有微凸块(例如热凸块，被设计为促进从半导体器件的一区域的散热)的半导体器件及其制造方法。
背景技术
半导体封装提供集成电路通过其可在电子产品中容易使用的手段。通常，半导体封装具有安装在印刷电路板(PCB)上的半导体芯片以及将半导体芯片电连接到印刷电路板的接合引线或凸块。随着电子产业的发展，对标准化和小型化半导体封装的兴趣增加。此外，正在进行各种研究以提高半导体封装的运行速度。然而，半导体封装的标准化和小型化以及半导体封装的运行速度的提高会在最终封装的芯片(IC)的运行可靠性上引起某些问题。
发明内容
根据本发明构思的一方面，提供一种半导体器件，该半导体器件具有焊盘区域和与焊盘区域分开的至少一个单元区域，并包括：半导体基板，具有有源表面和与有源表面相反的非有源表面；多个金属线的排布，在半导体基板的有源表面上；多个凸块，在所述至少一个单元区域中；第一钝化层，覆盖所述多个金属线并具有非平坦的顶表面，该非平坦的顶表面具有由所述多个金属线的排布规定的轮廓；以及第二钝化层，在第一钝化层的非平坦的顶表面上并具有平坦的顶表面，并且其中凸块设置在第二钝化层的平坦的顶表面上。
根据本发明构思的另一个方面，提供一种半导体器件，该半导体器件具有焊盘区域和与焊盘区域分开的至少一个单元区域，并包括：半导体基板，具有有源表面和与有源表面相反的非有源表面；多个金属线，在半导体基板的有源表面上；多个凸块，在所述至少一个单元区域中；第一钝化层，覆盖所述多个金属线并包括第一绝缘材料；以及第二钝化层，包括第二绝缘材料并具有平坦的顶表面，并且其中第二绝缘材料具有与第一绝缘材料的成分不同的成分，凸块设置在第二钝化层的平坦的顶表面上，并且第一钝化层和第二钝化层具有非平坦的界面。
根据本发明构思的另一个方面，提供一种制造半导体器件的方法，该方法包括：提供半导体基板，该半导体基板分成单元区域和焊盘区域并包括有源表面和与有源表面相反的非有源表面；在半导体基板的有源表面上形成多个金属线；在半导体基板的有源表面上形成第一钝化层，该第一钝化层覆盖金属线并具有沿着金属线的排布轮廓的非平坦的顶表面；在第一钝化层的非平坦的顶表面上形成第二钝化层；化学机械抛光第二钝化层以平坦化第二钝化层的顶表面；以及在单元区域的第二钝化层上形成多个虚设凸块。
根据本发明构思的另一方面，提供一种半导体器件，该半导体器件具有其中提供半导体器件的集成电路的至少一个器件区域以及与所述至少一个器件区域分开并且没有无源和有源电子部件的连接区域，并包括：半导体基板，具有有源表面和与有源表面相反的非有源表面，集成电路的至少部分设置在半导体基板的有源表面处；电介质层，在半导体基板的有源表面上；金属线，设置在器件区域中的电介质层的上表面上；钝化层，设置在电介质层上并且其中埋设金属线，并具有位于金属线之上的平坦的顶表面；通路，在连接区域中的半导体基板中延伸并电连接到集成电路；以及散热凸块，直接设置在器件区域中的集成电路之上的钝化层的平坦顶表面上并与集成电路电隔离。
附图说明
图1A是根据本发明构思的具有半导体器件的半导体封装的示例的截面图。
图1B是根据本发明构思的具有半导体器件的半导体封装的示例的示意图或布局。
图2A是图1A的半导体封装的芯片堆叠的示例的截面图。
图2B是根据本发明构思的半导体器件的示例的平面图。
图2C是根据本发明构思的半导体封装的另一个示例的平面图。
图3A、图3B、图3C、图3D、图3E、图3F和图3G是半导体器件在其制造过程中的截面图，并共同地示出根据本发明构思的制造半导体器件的方法的示例。
图4A、图4B和图4C是半导体器件在其制造过程中的各阶段期间的截面图，并示出根据本发明构思的制造半导体器件的方法的另一示例。
具体实施方式
图1A示出根据本发明构思的半导体封装1000的示例。
参照图1A，半导体封装1000可以是高带宽存储器(HBM)模块，其包括封装基板1600、安装在封装基板1600上的芯片堆叠1100和集成电路芯片1200、以及包封芯片堆叠1100和集成电路芯片1200的外模塑层1400。
半导体封装1000还可以包括提供在封装基板1600上的中介板(interposer)1500。中介板1500可以使芯片堆叠1100和集成电路芯片1200彼此电连接并电连接到封装基板1600。半导体封装1000还可以包括提供在外模塑层1400上的热辐射板1700。热辐射板1700可以将半导体封装1000中产生的热排放到外面。
封装基板1600可以是印刷电路板并可以包括多个外部端子1650。多个连接端子1550可以提供在中介板1500和封装基板1600之间，中介板1500和封装基板1600通过该多个连接端子1550而彼此电连接。
集成电路芯片1200可以包括中央处理单元(CPU)、图形处理单元(GPU)、系统芯片(SoC)等。多个内部端子1250可以提供在集成电路芯片1200和中介板1500之间。集成电路芯片1200可以通过内部端子1250电连接到中介板1500和芯片堆叠1100。
集成电路芯片1200和芯片堆叠1100可以由提供在中介板1500上的内模塑层1300包封。或者，内模塑层1300可以被省略，并且外模塑层1400可以替代地包封集成电路芯片1200和芯片堆叠1100。集成电路芯片1200的顶表面1200s和芯片堆叠1100的顶表面1100s可以位于彼此相同的水平面处或在彼此不同的水平面处。例如，集成电路芯片1200的顶表面1200s和芯片堆叠1100的顶表面1100s可以是共平面的。
图1B示意性地示出根据本发明构思的半导体封装的示例。
参照图1B，可以提供多个芯片堆叠1100。例如，两个芯片堆叠1100可以彼此相邻地设置在集成电路芯片1200的相反两侧的每个上。每个芯片堆叠1100可以包括垂直地堆叠在缓冲器件上的多个半导体器件，并将在下面参照图2A讨论。每个半导体器件可以具有连接区域以及与焊盘区域分开的至少一个器件区域。半导体器件的构成该半导体器件的IC的有源和/或无源电子部件位于器件区域中，而用于将IC连接到外部器件的通路(例如贯穿电极)位于连接区域中。连接区域(在下文称为“焊盘区域”)可以没有构成IC的任何电子部件(有源或无源)。半导体封装1000可以具有在从几Gbps至几十Gbps的范围内的带宽，并可以在实践中用于图形卡、手机、计算机、平板等。在图1B中，CPU和GPU可以被统称为xPU。
图2A详细地示出图1A的半导体封装的芯片堆叠的示例。
参照图2A，芯片堆叠1100可以包括缓冲器件20、垂直地堆叠在缓冲器件20上的多个半导体器件10、以及位于缓冲器件20上并包封半导体器件10的模塑层30。缓冲器件20可以包括逻辑芯片，该逻辑芯片将在缓冲器件20和半导体器件10之间传输的信号分支。缓冲器件20可以提供有多个连接端子25，缓冲器件20通过所述多个连接端子25电连接到图1A的半导体封装1000的中介板1500。
半导体器件10可以是半导体存储芯片。半导体器件10可以包括堆叠在缓冲器件20上的第一半导体存储芯片11、第二半导体存储芯片12、第三半导体存储芯片13和第四半导体存储芯片14。第一半导体存储芯片11至第四半导体存储芯片14中的每个可以具有前表面10sf和后表面10sb。前表面10sf可以对应于芯片的有源表面，后表面10sb可以对应于芯片的非有源表面。第一半导体存储芯片11至第四半导体存储芯片14中的每个可以以这样的方式设置，使得其芯片主体的前表面10sf面对缓冲器件20。
第一半导体存储芯片11至第四半导体存储芯片14可以具有相同的厚度或不同的厚度。例如，第一半导体存储芯片11至第三半导体存储芯片13可以具有相同的第一厚度TH1，第四半导体存储芯片14可以具有大于第一厚度TH1的第二厚度TH2。或者，第一半导体存储芯片11至第四半导体存储芯片14的全部可以具有第一厚度TH1或第二厚度TH2。
第一半导体存储芯片11至第四半导体存储芯片14中的每个可以包括焊盘区域10a和提供有存储单元阵列的单元区域10b。多个贯穿电极160可以提供在第一半导体存储芯片11至第三半导体存储芯片13中的每个的焊盘区域10a中。贯穿电极160可以不提供在第四半导体存储芯片14的焊盘区域10a中。贯穿电极160可以使第一半导体存储芯片11至第四半导体存储芯片14彼此电连接，并且还将第一半导体芯片11电连接到缓冲器件20。贯穿电极160可以电连接到单元区域10b中提供的存储单元(图3A中的102)。
多个电微凸块150和多个虚设微凸块140可以提供在第一半导体存储芯片11至第四半导体存储芯片14中的每个的前表面10sf处。电微凸块150可以直接或间接地联接到贯穿电极160。虚设微凸块140可以与第一半导体存储芯片11至第四半导体存储芯片14的每个和缓冲器件20电隔离。第一半导体存储芯片11至第四半导体存储芯片14中的每个的虚设微凸块140可以为热凸块，该热凸块将相应存储芯片中产生的热排放到存储芯片的外部。
图2B和图2C示出根据本发明构思的半导体器件10的微凸块的布局的各示例。
参照图2B，焊盘区域10a可以沿着第二方向D2跨过半导体器件10的中心纵向地延伸。电微凸块150可以提供在焊盘区域10a中。可以提供多个单元区域10b并且单元区域10b可以沿着第二方向D2设置在焊盘区域10a的相反两侧。此外，每个单元区域10b可以在第一方向D1上相邻于焊盘区域10a的一侧纵向地延伸，第一方向D1与第二方向D2相交，例如垂直于第二方向D2。
虚设微凸块140可以均匀地设置在半导体器件10的由单元区域10b和除了焊盘区域10a之外的所有其它区域构成的区域上。电微凸块150可以具有与虚设微凸块140的密度相同的密度或不同的密度。例如，电微凸块150的密度可以大于虚设微凸块140的密度。
参照图2C，在此示例中，虚设微凸块140主要集中在半导体器件10中产生大部分热量的热点上。例如，虚设微凸块140可以集中在单元区域10b中并可以不存在于单元区域10b之间或周围的区域中。
如图2B或图2C所示，电微凸块150可以在焊盘区域10a中设置在芯片主体的前表面10sf处，并且虚设微凸块140可以在单元区域10b中设置在芯片主体的前表面10sf处。半导体器件10的前表面10sf可以为平坦化的表面。平坦化的前表面10sf可以在执行光刻工艺时防止光从其散射，这可以进而防止虚设微凸块140和电微凸块150形成为不正常的形状。这将在下面参照图3A至图3G进一步讨论。
图3A至图3G示出根据本发明构思的制造半导体器件的方法的示例。在下面的描述中，将集中在图2A所示的半导体器件10的单元区域10b上。下面的描述可以同样地或类似地应用于半导体器件10的焊盘区域10a。
参照图3A，半导体基板100可以在其上提供有存储单元102以及覆盖存储单元102的层间电介质层104。半导体基板100可以为硅晶片、锗晶片、硅锗晶片或化合物晶片，其每个具有有源表面100a以及与有源表面100a相反的非有源表面100b。存储单元102可以通过在半导体基板100的有源表面100a上形成一个或更多个晶体管而形成。层间电介质层104可以通过在半导体基板100上沉积绝缘材料诸如硅氧化物或硅氮化物而形成。
存储单元102可以包括存储部件，诸如电连接到晶体管的电容器。如图2A所示，焊盘区域10a可以在其上提供有电连接到存储单元102的贯穿电极160。贯穿电极160延伸穿过半导体基板100。
参照图3B，层间电介质层104可以在其上提供有下金属线112以及覆盖下金属线112的下金属间电介质层114。下金属线112可以包括铜或铝。下金属间电介质层114可以通过在层间电介质层104上沉积绝缘材料诸如硅氧化物或硅氮化物而形成。
下金属间电介质层114可以在其上提供有上金属线132以及覆盖上金属线132的第一钝化层134(在下文称为钝化层的第一部分或下部分)。可选地，下金属间电介质层114还可以在其上提供有中间金属线122以及覆盖中间金属线122的中间金属间电介质层124。中间金属线122可以包括铜或铝。中间金属间电介质层124可以通过在提供有中间金属线122的下金属间电介质层114上沉积绝缘材料诸如硅氧化物或硅氮化物而形成。
第一钝化层134可以通过在提供有上金属线132的中间金属间电介质层124上沉积绝缘材料诸如硅氧化物、硅氮化物或光敏聚酰亚胺(PSPI)而形成。例如，第一钝化层134可以是硅氮化物层。第一钝化层134可以具有由其中埋设的上金属线132的排布(即形貌)指示的轮廓，从而具有非平坦的顶表面134s。例如，第一钝化层134的顶表面134s可以具有在上金属线132上的凸起以及在上金属线132之间的凹陷，例如可以具有波浪或起伏的上表面。第一钝化层134可以具有在从几μm至几十μm(例如从约1μm至约20μm)的范围内的平均厚度T1。没有对第一钝化层134的顶表面134s执行平坦化工艺。
参照图3C，第二钝化层136(在下文称为钝化层的第二部分或上部分)可以形成在第一钝化层134上。第二钝化层136可以通过在第一钝化层134上沉积绝缘材料诸如硅氧化物、硅氮化物或光敏聚酰亚胺(PSPI)而形成。例如，第二钝化层136可以是硅氧化物层。由于第二钝化层136形成在第一钝化层134上，所以它可以具有非平面的初始顶表面136sa。第二钝化层136可以具有初始平均厚度T2a，范围为几μm至几十μm，例如约1μm至约40μm。
参照图3D，可以对第二钝化层136执行平坦化工艺。例如，可以执行化学机械抛光工艺以平坦化第二钝化层136。第二钝化层136可以于是具有平坦的顶表面136s。
平坦化工艺可以使第二钝化层136具有小于初始平均厚度T2a的平均厚度T2。第二钝化层136的平均厚度T2可以落入从几μm至几十μm的范围内，例如等于或小于约20μm，并且更窄地，从约0.1μm至约5μm。
因此，钝化层138可以形成为具有双层结构，该双层结构包括第一钝化层134和第二钝化层136。第二钝化层136的平坦化的顶表面136s可以提供钝化层138的平坦的顶表面。第一钝化层134的顶表面134s可以在第一钝化层134和第二钝化层136之间提供非平坦的界面。
如以上讨论的，第一钝化层134和第二钝化层136可以由硅氧化物层、硅氮化物层或光敏聚酰亚胺(PSPI)层形成。例如，第一钝化层134可以由具有相对优良的电介质特性和强度的硅氮化物层(例如SiNx)形成，并且第二钝化层136可以由能够通过本质上常规的化学机械抛光而容易地抛光的硅氧化物层(例如SiO2)形成。或者，第一钝化层134和第二钝化层136可以由相同的材料形成，例如硅氮化物层或硅氧化物层。
参照图3E，掩模图案90可以形成在钝化层138上。例如，钝化层138可以涂覆有光致抗蚀剂，然后可以对光致抗蚀剂的涂层(涂覆层)执行光刻工艺，结果掩模图案90具有多个开口92。开口92可以暴露第二钝化层136的平坦化的顶表面136s。由于第二钝化层136具有平坦的顶表面136s，所以在执行光刻工艺时可以减少或防止光的散开的反射。因此，掩模图案90可以形成为具有期望形状的开口92。
参照图3F，金属柱142和盖层144可以形成在每个开口92中。例如，第二钝化层136的平坦化的顶表面136s的暴露部分可以镀覆有金属诸如铜或铝，或者金属可以沉积在开口92中以形成部分地填充开口92的金属柱142。然后，金属柱142可以镀覆有焊料，或者焊料可以沉积在开口92的剩余部分中以形成填充开口92的其余部分的盖层144。当执行镀覆工艺时，包括金属的籽晶层可以进一步形成在开口92中。
参照图3G，可以去除掩模图案90，然后可以执行回流工艺。回流工艺可以使得盖层144具有基本上球形或半球形的形状。结果，半导体器件10可以被制造为在钝化层138上具有多个虚设微凸块140，其每个包括金属柱142和盖层144。
如图2A所示，多个电微凸块150可以形成在半导体器件10的焊盘区域10a上，其电微凸块150电连接到贯穿电极160。电微凸块150可以具有与虚设微凸块140的密度相同或不同的密度。例如，电微凸块150的密度可以大于虚设微凸块140的密度。
如词语“虚设”对于本领域的人员所指示的，虚设微凸块140没有在半导体器件10中或为半导体器件10形成任何电连接。在此示例中，虚设微凸块140用作辐射半导体器件10中产生的热的热沉，该热主要在存储单元102中产生。每个虚设微凸块140可以具有在从几μm至几百μm的范围内的高度H，例如从约5μm至约100μm。
大量的虚设微凸块是所希望的以最大化半导体器件10的热辐射特性。如果第二钝化层136的顶表面136s是非平坦的，则当执行用于形成掩模图案的光刻工艺时，具有与将要形成的虚设微凸块数对应的开口数的掩模图案90会具有由光的散开的反射引起的不希望的形状。这会导致形成不正常形状的虚设微凸块。
另一方面，根据本发明构思的一方面，如以上参照图3E讨论的，第二钝化层136具有平坦化的(即平坦的)顶表面136s。当掩模图案90形成在第二钝化层136的平坦化的顶表面136s上时，掩模图案90可以在执行光刻工艺时不受光的散开的反射的影响。因此，掩模图案90可以具有所希望形状的开口92，并且如图3F和图3G所示，开口92可以促进形成(在其中)被设计为最有效辐射热的规定形状的虚设微凸块140。
图4A至图4C示出根据本发明构思的制造半导体器件的方法的另一个示例。
参照图4A，可以执行与以上参照图3A讨论的工艺类似的工艺以在半导体基板100的具有存储单元102的有源表面100a上形成上金属线132。钝化层134可以形成为具有非平坦的初始顶表面134sa，覆盖上金属线132。钝化层134可以为硅氧化物层、硅氮化物层或光敏聚酰亚胺(PSPI)层。例如，钝化层134可以为具有初始平均厚度T1a的硅氮化物层。初始平均厚度T1a可以落入从几μm至几十μm的范围内，例如从大于1μm至约40μm。
参照图4B，可以平坦化钝化层134。例如，可以执行化学机械抛光工艺以平坦化钝化层134。钝化层134可以于是具有平坦的顶表面134s。平坦化工艺可以使得钝化层134具有小于初始平均厚度T1a的平均厚度T1。平均厚度T1可以落入几μm至几十μm的范围内，例如从大于1μm至约20μm，并且更窄地，从大于1μm至约10μm。
参照图4C，可以执行以上参照图3E和图3F描述的工艺以在钝化层134上形成虚设微凸块140。如以上参照图4B讨论的，在此状态下，钝化层134具有平坦的顶表面134s；因此，虚设微凸块140可以具有没有异常的所规定的(希望的)形状。
根据本发明构思，钝化层的顶表面可以是平坦的。因此，多个虚设微凸块可以采用光刻工艺形成在钝化层的平坦的顶表面上，而在虚设微凸块的形状上没有异常发生。结果，半导体器件可以具有优良的散热和电特性。
本发明构思不应被解释为限于这里描述的示例。相反，这里描述的示例的各种组合、修改和变化落入本发明构思的如权利要求书中阐述的精神和范围内。
本申请要求于2018年2月8日在韩国知识产权局提交的韩国专利申请第10-2018-0015706号的优先权，其全部内容通过引用结合于此。

Claims (25)

1.一种半导体器件，具有焊盘区域以及与所述焊盘区域分开的至少一个单元区域，并包括：
半导体基板，具有有源表面和与所述有源表面相反的非有源表面；
多个金属线的排布，在所述半导体基板的所述有源表面上；
多个凸块，在所述至少一个单元区域中；
第一钝化层，覆盖所述多个金属线并具有非平坦的顶表面，该非平坦的顶表面具有由所述多个金属线的所述排布规定的轮廓；以及
第二钝化层，在所述第一钝化层的所述非平坦的顶表面上并具有平坦的顶表面，
其中所述凸块设置在所述第二钝化层的所述平坦的顶表面上。
2.如权利要求1所述的半导体器件，其中所述第一钝化层和所述第二钝化层由各自的绝缘材料形成，并且所述各自的绝缘材料具有彼此不同的成分。
3.如权利要求2所述的半导体器件，其中所述第一钝化层包括硅氮化物层，并且
所述第二钝化层包括硅氧化物层。
4.如权利要求1所述的半导体器件，其中所述多个凸块包括在所述半导体器件中被电隔离的多个虚设凸块。
5.如权利要求1所述的半导体器件，还包括延伸穿过所述半导体器件的所述焊盘区域中的所述半导体基板的多个贯穿电极，
其中所述多个凸块都不电连接到所述多个贯穿电极中的任一个。
6.如权利要求5所述的半导体器件，还包括在所述半导体器件的所述焊盘区域中的所述第二钝化层上并电连接到所述多个贯穿电极的多个电凸块。
7.如权利要求1所述的半导体器件，其中当在平面图中看时，所述焊盘区域线性地延伸跨过所述半导体基板的中心，并且
所述至少一个单元区域包括在所述焊盘区域的相反两侧的多个单元区域。
8.一种半导体器件，具有焊盘区域以及与所述焊盘区域分开的至少一个单元区域，并包括：
半导体基板，具有有源表面和与所述有源表面相反的非有源表面；
多个金属线，在所述半导体基板的所述有源表面上；
多个凸块，在所述至少一个单元区域中；
第一钝化层，覆盖所述多个金属线并包括第一绝缘材料；以及
第二钝化层，包括第二绝缘材料并具有平坦的顶表面，所述第二绝缘材料具有与所述第一绝缘材料的成分不同的成分，
其中所述凸块设置在所述第二钝化层的所述平坦的顶表面上，并且
所述第一钝化层和所述第二钝化层具有非平坦的界面。
9.如权利要求8所述的半导体器件，其中所述第一钝化层的所述第一绝缘材料包括硅氮化物，并且
所述第二钝化层的所述第二绝缘材料包括硅氧化物。
10.如权利要求8所述的半导体器件，还包括在所述半导体器件的所述单元区域中的存储单元以及延伸穿过所述半导体器件的所述焊盘区域中的所述半导体基板的多个贯穿电极。
11.如权利要求10所述的半导体器件，还包括多个电凸块，该多个电凸块在所述第二钝化层上、位于所述半导体器件的所述焊盘区域中并电连接到所述多个贯穿电极。
12.如权利要求8所述的半导体器件，其中所述凸块是与所述半导体器件的所述单元区域中的电路电隔离的热凸块。
13.如权利要求8所述的半导体器件，其中所述多个凸块直接设置在所述第二钝化层的所述平坦的顶表面上。
14.如权利要求8所述的半导体器件，其中所述多个凸块中的每个包括：
金属柱，在所述第二钝化层的所述平坦的顶表面上；和
盖层，覆盖所述金属柱。
15.如权利要求8所述的半导体器件，
其中，在所述多个金属线上，所述界面是朝向所述多个凸块凸起的，并且
其中，在所述多个金属线之间，所述界面是朝向所述半导体基板凹入的。
16.一种制造半导体器件的方法，所述方法包括：
提供半导体基板，所述半导体基板被分成单元区域和焊盘区域并包括有源表面和与所述有源表面相反的非有源表面；
在所述半导体基板的所述有源表面上形成多个金属线；
在所述半导体基板的所述有源表面上形成第一钝化层，所述第一钝化层覆盖所述金属线并具有沿着所述金属线的排布轮廓的非平坦的顶表面；
在所述第一钝化层的所述非平坦的顶表面上形成第二钝化层；
化学机械抛光所述第二钝化层以平坦化所述第二钝化层的顶表面；以及
在所述单元区域的所述第二钝化层上形成多个虚设凸块。
17.如权利要求16所述的方法，其中所述第一钝化层和所述第二钝化层由彼此不同的绝缘材料形成。
18.如权利要求17所述的方法，其中
形成所述第一钝化层包括沉积硅氮化物层，并且
形成所述第二钝化层包括沉积硅氧化物层。
19.如权利要求16所述的方法，其中形成所述第二钝化层包括在所述第一钝化层上沉积与所述第一钝化层的绝缘材料不同的绝缘材料以形成绝缘层，所述绝缘层具有沿着所述第一钝化层的所述非平坦的顶表面的轮廓的非平坦的顶表面。
20.如权利要求16所述的方法，其中形成所述多个虚设凸块包括在所述单元区域的所述第二钝化层的所述平坦化的顶表面上形成多个热凸块，所述多个热凸块不电连接到所述单元区域也不电连接到所述多个金属线。
21.如权利要求20所述的方法，其中形成所述多个热凸块包括：
在所述第二钝化层上形成掩模图案，所述掩模图案具有暴露所述第二钝化层的所述平坦化的顶表面的多个开口；
在所述多个开口的每个中顺序地镀覆金属柱和盖层；
去除所述掩模图案；以及
回流所述盖层。
22.如权利要求16所述的方法，其中所述半导体基板还包括在所述焊盘区域上并穿过所述半导体基板的多个贯穿电极。
23.如权利要求22所述的方法，还包括在所述焊盘区域的所述第二钝化层上形成多个电凸块，
其中所述多个电凸块电连接到所述多个贯穿电极。
24.一种半导体器件，具有至少一个器件区域以及连接区域，所述半导体器件的集成电路提供在所述至少一个器件区域中，所述连接区域与所述至少一个器件区域分开并且没有无源和有源电子部件，该半导体器件包括：
半导体基板，具有有源表面和与所述有源表面相反的非有源表面，所述集成电路的至少部分设置在所述半导体基板的所述有源表面处；
电介质层，在所述半导体基板的所述有源表面上；
多个金属线，设置在所述器件区域中的所述电介质层的上表面上；
钝化层，设置在所述电介质层上并且其中埋设所述多个金属线，所述钝化层具有位于所述多个金属线之上的平坦的顶表面；
通路，在所述连接区域中的所述半导体基板中延伸并电连接到所述集成电路；
散热凸块，直接设置在所述器件区域中的所述集成电路之上的所述钝化层的所述平坦的顶表面上并与所述集成电路电隔离。
25.如权利要求24所述的半导体器件，其中所述钝化层具有其中埋设所述多个金属线的下部分和具有其上设置所述散热凸块的所述平坦的顶表面的上部分，并且
所述钝化层的所述下部分具有非平坦的、起伏的顶表面，该非平坦的、起伏的顶表面具有由所述多个金属线的形貌所规定的轮廓。
CN201910066850.4A 2018-02-08 2019-01-24 具有平坦化的钝化层的半导体器件及其制造方法 Active CN110137144B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2018-0015706 2018-02-08
KR1020180015706A KR102495582B1 (ko) 2018-02-08 2018-02-08 평탄화된 보호막을 갖는 반도체 소자 및 그 제조방법

Publications (2)

Publication Number Publication Date
CN110137144A true CN110137144A (zh) 2019-08-16
CN110137144B CN110137144B (zh) 2024-06-04

Family

ID=67476150

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910066850.4A Active CN110137144B (zh) 2018-02-08 2019-01-24 具有平坦化的钝化层的半导体器件及其制造方法

Country Status (3)

Country Link
US (2) US10847447B2 (zh)
KR (1) KR102495582B1 (zh)
CN (1) CN110137144B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112530879A (zh) * 2019-08-29 2021-03-19 美光科技公司 微电子装置和微电子装置制造
CN113471188A (zh) * 2020-03-30 2021-10-01 南亚科技股份有限公司 半导体封装及其制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102500170B1 (ko) * 2018-01-03 2023-02-16 삼성전자주식회사 금속 범프를 갖는 반도체 소자 및 그 제조방법
US20200402958A1 (en) * 2019-06-20 2020-12-24 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and methods of manufacturing the same
CN112768422B (zh) * 2019-11-06 2024-03-22 欣兴电子股份有限公司 芯片封装结构及其制作方法
US11189338B1 (en) * 2020-03-27 2021-11-30 Xilinx, Inc. Multi-rank high bandwidth memory (HBM) memory
KR20220054118A (ko) 2020-10-23 2022-05-02 삼성전자주식회사 적층 칩 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010028923A1 (en) * 1997-10-09 2001-10-11 Leonard Forbes Methods of forming an insulating material proximate a substrate, and methods of forming an insulating material between components of an integrated circuit
CN101075595A (zh) * 2006-05-15 2007-11-21 中芯国际集成电路制造(上海)有限公司 半导体晶片焊料凸块结构及其制造方法
CN105428337A (zh) * 2014-09-11 2016-03-23 三星电子株式会社 半导体封装及其制造方法
US20160118326A1 (en) * 2014-10-23 2016-04-28 Samsung Electronics Co., Ltd. Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04147651A (ja) * 1990-04-02 1992-05-21 Toshiba Corp 半導体装置およびその製造方法
JP3241772B2 (ja) 1991-11-14 2001-12-25 株式会社日立製作所 半導体装置の製造方法
US6245594B1 (en) 1997-08-05 2001-06-12 Micron Technology, Inc. Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly
US6724084B1 (en) 1999-02-08 2004-04-20 Rohm Co., Ltd. Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device
JP3446826B2 (ja) 2000-04-06 2003-09-16 沖電気工業株式会社 半導体装置及びその製造方法
US20060051274A1 (en) 2004-08-23 2006-03-09 Wright Allen B Removal of carbon dioxide from air
US8125052B2 (en) * 2007-05-14 2012-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure with improved cracking protection
JP2012532459A (ja) * 2009-07-02 2012-12-13 フリップチップ インターナショナル エルエルシー 垂直ピラー相互接続方法及び構造体
KR20130035619A (ko) 2011-09-30 2013-04-09 삼성전자주식회사 반도체 소자의 연결 범프 형성 방법
US9978656B2 (en) 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
KR20130096990A (ko) 2012-02-23 2013-09-02 삼성전자주식회사 반도체 장치
US9646894B2 (en) * 2013-03-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
KR20150038842A (ko) 2013-10-01 2015-04-09 삼성디스플레이 주식회사 구동 칩, 이를 구비한 표시 장치 및 구동 칩 제조 방법
KR101566593B1 (ko) 2013-12-11 2015-11-05 주식회사 동부하이텍 반도체 패키지
US10163856B2 (en) * 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
KR102454892B1 (ko) 2015-12-09 2022-10-14 삼성전자주식회사 반도체 칩, 이를 포함하는 반도체 패키지, 및 반도체 칩의 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010028923A1 (en) * 1997-10-09 2001-10-11 Leonard Forbes Methods of forming an insulating material proximate a substrate, and methods of forming an insulating material between components of an integrated circuit
CN101075595A (zh) * 2006-05-15 2007-11-21 中芯国际集成电路制造(上海)有限公司 半导体晶片焊料凸块结构及其制造方法
CN105428337A (zh) * 2014-09-11 2016-03-23 三星电子株式会社 半导体封装及其制造方法
US20160118326A1 (en) * 2014-10-23 2016-04-28 Samsung Electronics Co., Ltd. Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112530879A (zh) * 2019-08-29 2021-03-19 美光科技公司 微电子装置和微电子装置制造
CN112530879B (zh) * 2019-08-29 2022-04-29 美光科技公司 微电子装置和微电子装置制造
US11769738B2 (en) 2019-08-29 2023-09-26 Micron Technology, Inc. Apparatuses exhibiting enhanced stress resistance and planarity, and related microelectronic devices and memory devices
CN113471188A (zh) * 2020-03-30 2021-10-01 南亚科技股份有限公司 半导体封装及其制造方法
CN113471188B (zh) * 2020-03-30 2024-04-05 南亚科技股份有限公司 半导体封装及其制造方法

Also Published As

Publication number Publication date
CN110137144B (zh) 2024-06-04
US11488894B2 (en) 2022-11-01
US20190244878A1 (en) 2019-08-08
KR20190096131A (ko) 2019-08-19
US20210028092A1 (en) 2021-01-28
US10847447B2 (en) 2020-11-24
KR102495582B1 (ko) 2023-02-06

Similar Documents

Publication Publication Date Title
CN110137144A (zh) 具有平坦化的钝化层的半导体器件及其制造方法
US11996366B2 (en) Semiconductor package including interposer
US10665571B2 (en) Semiconductor package
US20230112056A1 (en) Semiconductor packages
CN107851615B (zh) 独立3d堆叠
US9613881B2 (en) Semiconductor device having improved heat-dissipation characteristics
CN104253115A (zh) 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制
KR20040088584A (ko) 와이어 본드 패드를 가진 반도체 소자 및 그 제조 방법
KR20150049622A (ko) 패키지 온 패키지 장치
TWI763198B (zh) 製造半導體封裝的方法以及半導體封裝
US11862571B2 (en) Semiconductor package
US20210005527A1 (en) Stacked semiconductor package having heat dissipation structure
KR20220134721A (ko) 반도체 패키지
US20170141041A1 (en) Semiconductor package assembly
US20230092410A1 (en) Semiconductor package and method of manufacturing the same
CN115708200A (zh) 半导体封装件
US9721928B1 (en) Integrated circuit package having two substrates
TWI576976B (zh) 無核心層封裝結構
KR20220077762A (ko) 방열층을 포함한 반도체 패키지
US20230105942A1 (en) Semiconductor package and method of fabricating the same
TWI790054B (zh) 天線整合式封裝結構
US11469184B2 (en) Semiconductor device and manufacturing method of the same
TW201919186A (zh) 無銲墊外扇晶粒堆疊結構及其製作方法
KR20150140977A (ko) 반도체 패키지 장치 및 그 제조방법
TW202306092A (zh) 半導體封裝

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant