CN110120391A - A kind of high robust ESD device for ESD protection - Google Patents
A kind of high robust ESD device for ESD protection Download PDFInfo
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- CN110120391A CN110120391A CN201910353954.3A CN201910353954A CN110120391A CN 110120391 A CN110120391 A CN 110120391A CN 201910353954 A CN201910353954 A CN 201910353954A CN 110120391 A CN110120391 A CN 110120391A
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- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000024241 parasitism Effects 0.000 abstract description 22
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- 101000590281 Homo sapiens 26S proteasome non-ATPase regulatory subunit 14 Proteins 0.000 description 7
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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Abstract
The invention belongs to electronic technology fields, and in particular to Electro-static Driven Comb (ESD) protects the design of device, a kind of high robust ESD device structure for ESD protection is specifically provided, to improve the robustness of GGNMOS.In the existing GGNMOS structure basis of the present invention, N number of the first conduction type heavily doped region A is used in second of conduction type well region1With N number of second of conduction type heavily doped region B1Device current path of releasing from the parasitic path npn1 of script and the parasitism path the npn2 path Liang Zhong is become the parasitic path npn1, the parasitism path npn2 and three kinds of the path SCR path by adjacent and spaced design；Since electric current is released the increase in path, so that ESD device of the present invention can be realized higher robustness compared to traditional GGNMOS device；Meanwhile high robust ESD device of the present invention and chip area needed for common GGNMOS device are completely the same, i.e., the present invention realizes higher robustness in the case where identical chip area.
Description
Technical field
The invention belongs to electronic technology fields, and in particular to Electro-static Driven Comb (ESD:Electro-Static discharge)
Protect the design of device, espespecially a kind of high robust ESD device.
Background technique
Static discharge (Electro-Static discharge, abbreviation ESD) phenomenon refers to the object with different potentials
The charge transfer phenomenon occurred when close to each other or contact；In discharge process, since discharge time is extremely short, very big electricity can be generated
Stream；For integrated circuit, internal components can be damaged or even be burnt to this high current, lead to chip failure.Static discharge is existing
The links used are transported as possibly being present at chip production, therefore ESD protection measure is for the reliability of chip
It is very important.
Since grounded-grid NMOS device (Gate-Grounded NMOSFET abbreviation GGNMOS) is most simultaneous with CMOS technology
Hold, design is simple, and with the development of technique, and ESD performance can also move to new process and be unlikely to produce ESD performance
Raw big degeneration, so GGNMOS is most common ESD protection device in current circuit.Traditional GGNMOS (Gate-
Grounded NMOSFET) device architecture as shown in Figure 1, when to the GGNMOS device PAD1 apply a positive pulse, PAD2
When ground connection, the p-n junction first between N-shaped heavily doped region 113 and p-substrate 110 is reverse-biased, when reversed bias voltage is greater than N+/P substrate knot
Avalanche breakdown voltage when, the p-n junction occur avalanche breakdown, generate a large amount of electron-hole pair；The electronics of generation is through N-shaped weight
Doped region 113 reaches PAD1, meanwhile, the hole that snowslide generates reaches PAD2 through p-substrate 110, p-type heavily doped region 111, in p
Pressure drop is generated on the resistance substrate of type substrate 110, eventually leads to the p-n junction being made of p-substrate 110 and N-shaped heavily doped region 112
Forward conduction, parasitic npn pipe is opened and ESD electric current of releasing in GGNMOS.
In practical applications, in order to save chip area, the mode for generalling use interdigital distribution carrys out design layout structure.Often
GGNMOS (Gate-Grounded NMOSFET) element layout structure of use is as shown in Figure 2；Fig. 3 is AA ' line section in Fig. 2
Figure.The structure is made of M GGNMOS pipe, and wherein GGNMOS pipe 100 is by N-shaped heavy doping source region 132, N-shaped heavy doping drain region 133
It is constituted with the N-shaped multi-crystal silicon area 150 on thin oxide layer, GGNMOS pipe 200 is by N-shaped heavy doping source region 134, N-shaped heavy doping drain region
133 and thin oxide layer on N-shaped multi-crystal silicon area 151 constitute, GGNMOS pipe 300 by N-shaped heavy doping source region 134, N-shaped heavy doping leak
N-shaped multi-crystal silicon area 152 in area 135 and thin oxide layer is constituted, and GGNMOS pipe M00 is leaked by N-shaped heavy doping source region, N-shaped heavy doping
N-shaped multi-crystal silicon area in area and thin oxide layer is constituted.P-type heavily doped region 111, p-type heavily doped region 131, on M thin oxide layer
N-shaped multi-crystal silicon area 150,151,152 ..., M/2+1 N-shaped heavy doping source region 132,134 ... are connected, the yin as device
Pole；N-shaped heavily doped region 121, M/2 N-shaped heavy doping drain region 133,135 ... are connected, the anode as device.
When the PAD1 of GGNMOS device applies a positive pulse and PAD2 is grounded, by taking GGNMOS pipe 100 as an example, n first
P-n junction between type heavy doping drain region 133 and p-type well region 130 is reverse-biased, when the snowslide that reversed bias voltage is greater than N+/P-well knot is hit
When wearing voltage, which occurs avalanche breakdown, generates a large amount of electron-hole pair；The electronics of generation is through N-shaped heavy doping drain region
133 reach PAD1, and hole reaches PAD2 through p-type well region 130, p-type heavily doped region 131, produces in the well resistance of p-type well region 130
Raw pressure drop eventually leads to the p-n junction forward conduction being made of p-type well region 130 and N-shaped heavy doping source region 132, parasitism in GGNMOS
Npn1 pipe open, thus first parasitism npn1 path current path of releasing generates；Similarly, by N-shaped weight in GGNMOS pipe 200
Second parasitism path npn1 that doped drain 133, p-type well region 130 and N-shaped heavy doping source region 134 are constituted, GGNMOS pipe 300
In the third parasitism path npn1 that is made of N-shaped heavy doping drain region 135, p-type well region 130 and N-shaped heavy doping source region 134,
The path m-th parasitism npn1 being made of in GGNMOS pipe M00 N-shaped heavy doping drain region, p-type well region 130 and N-shaped heavy doping source region
Be not always the case unlatching.Later, due to p-n junction (the i.e. collector-base of npn2 of N-shaped well region 120 and the composition of p-type well region 130
Knot) it is reverse-biased, and p-n junction (i.e. the base-emitter junction of npn2) positively biased that p-type well region 130 and N-shaped heavy doping source region 132 are constituted,
Parasitic npn2 pipe is opened, and first parasitism npn2 electric current path of releasing generates；Similarly, N-shaped heavily doped region 121, N-shaped deep-well region
120, second parasitism path npn2 that p-type well region 130 and N-shaped heavy doping source region 134 are constituted, N-shaped heavily doped region 121, N-shaped trap
The M/2+1 parasitism path npn2 that area 120, p-type well region 130 and N-shaped heavy doping source region are constituted also is so to open.Therefore exist
When esd event arrives, which releases ESD electric current jointly there are two types of path.
However, the ESD robustness of GGNMOS is relatively low, it means that for given ESD target, based on GGNMOS's
ESD protection scheme needs to consume more chip areas；Thus, for the ESD protection under advanced technologies, how to improve GGNMOS
The robustness of device is an important research direction of ESD device optimization.
Summary of the invention
It is an object of the invention to provide a kind of high robust ESD device structure for ESD protection regarding to the issue above,
The device architecture divides N-shaped weight in existing GGNMOS structure basis, by being inserted into multiple p-type heavily doped regions in N-shaped well region
Doped region, so that it is logical to form parasitic silicon controlled rectifier (SCR) (Silicon-Controlled-Rectifier, abbreviation SCR) electric current
Road substantially increases the ESD robustness of GGNMOS under identical chip area.
To achieve the above object, The technical solution adopted by the invention is as follows:
A kind of high robust ESD device structure for ESD protection, comprising:
The first conduction type silicon substrate, interior the first the conduction type weight being arranged of the first described conduction type silicon substrate
Doped region A1；
Second of the conduction type well region formed on the silicon substrate, the interior N being arranged of second of conduction type well region
A the first conduction type heavily doped region A2With N number of second of conduction type heavily doped region B1, described two conduction types it is heavily doped
Miscellaneous area is adjacent and is spaced apart；
The first the conduction type well region formed on second of conduction type well region, the first described conductive type of trap
The first the conduction type heavily doped region A being arranged in area3, M/2+1 second of conduction type heavy doping source region and M/2 second
Kind conduction type heavy doping drain region；The M/2+1 second of conduction type heavy doping source regions and M/2 second of conduction types
Heavy doping drain region is spaced apart, and between second of conduction type heavy doping drain region and second of conduction type heavy doping source region
It is respectively provided with thin oxide layer area on silicon face, second of conductivity type polysilicon area is all covered in each thin oxide layer area；
The first conduction type heavily doped region A1, the first conduction type heavily doped region A3, second of conduction type
Multi-crystal silicon area, M/2+1 second of conduction type heavy doping source regions homogeneously connect, the cathode as device；It is described it is N number of the first lead
Electric type heavily doped region A2, N number of second of conduction type heavily doped region B1, second of the conduction type heavy doping drain region M/2 it is homogeneous
Even, the anode as device；
N is positive integer, and M is even number.
The beneficial effects of the present invention are:
The present invention provides a kind of high robust ESD device structure for ESD protection, in second of conduction type well region
Using N number of the first conduction type heavily doped region A1With N number of second of conduction type heavily doped region B1It is adjacent and spaced set
Device current path of releasing from the parasitic path npn1 of script and the parasitism path the npn2 path Liang Zhong is become the parasitic road npn1 by meter
Diameter, the parasitism path npn2 and three kinds of the path SCR path；Since electric current is released the increase in path, so that ESD device of the present invention is compared
It can be realized higher robustness in traditional GGNMOS device；Meanwhile high robust ESD device of the present invention and common GGNMOS
Chip area needed for device is completely the same, i.e., the present invention realizes higher robustness in the case where identical chip area.
Detailed description of the invention
Fig. 1 is traditional GGNMOS device architecture schematic diagram.
Fig. 2 is the domain of common GGNMOS device architecture.
Fig. 3 is AA ' line profile in Fig. 2.
Fig. 4 is a kind of domain of high robust ESD device structure in the embodiment of the present invention.
Fig. 5 be the embodiment of the present invention in along Fig. 4 the sectional view of AA ' line and connection mode schematic diagram.
Fig. 6 be the embodiment of the present invention in along Fig. 4 the sectional view of BB ' line and connection mode schematic diagram.
Specific embodiment
The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments.
Embodiment 1
The present embodiment provides a kind of high robust ESD device structure for ESD protection, domain structure as shown in figure 4,
The device architecture includes:
P-type silicon substrate 110 inside sets cricoid p-type heavily doped region 111；
A N-shaped well region 120 is formed in the P-type silicon substrate and is enclosed in cricoid p-type heavily doped region 111, institute
State and set N number of N-shaped heavily doped region and N number of p-type heavily doped region in N-shaped well region 120, the heavily doped region of two kinds of conduction types it is adjacent and
Every distribution, cyclic annular heavily doped region is collectively constituted；
A p-type well region 130 is formed on the N-shaped well region 120 and is surrounded in the N-shaped well region 120 cyclic annular heavy doping
In area；A cricoid p-type heavily doped region 131, the heavy doping source region of M/2+1 N-shaped are respectively equipped in the p-type well region 130
132,134 ..., the heavy doping drain region 133,135 ... of M/2 N-shaped；The heavy doping source region and M/2 of the M/2+1 N-shaped
The heavy doping drain region of N-shaped is spaced apart and is enclosed in cricoid p-type heavily doped region 131；The heavy doping source region and n of N-shaped
Thin oxide layer area 140,141,142 ..., thin oxide layer Qu Shangjun are provided on silicon face between the heavy doping drain region of type
It is covered with N-shaped multi-crystal silicon area 150,151,152 ...；
The cross-sectional view of above-mentioned ESD device structure is as shown in Figure 5 and Figure 6；Wherein, Fig. 5 be Fig. 4 in AA ' line sectional view and
Connection mode, Fig. 6 are the sectional view and connection mode of BB ' line in Fig. 4；It is more specific:
P-type silicon substrate 110 inside sets p-type heavily doped region 111；
N-shaped well region 120 is formed on the substrate, effect is to be separated by the GGNMOS device above it with p-type silicon substrate
From setting N-shaped heavily doped region 122 and N-shaped heavily doped region 123 (as shown in Figure 5) and p-type heavily doped region in the N-shaped well region
124 and p-type heavily doped region 125 (as shown in Figure 6), p-type heavily doped region and N-shaped heavily doped region is adjacent and interval is to form segmentation；
Between the p-type heavily doped region 111 and N-shaped heavily doped region 122,123 (p-type heavily doped region 124,125), N-shaped weight
Doped region 122,123 (p-type heavily doped region 124,125) and p-type heavily doped region 131, p-type heavily doped region 131 and N-shaped heavily doped region
Shallow trench isolation (Shallow Trench Isolation, abbreviation STI) is equipped between 132, such as shadow region in Fig. 5, Fig. 6
It is shown；
The heavy doping of the heavily doped region 122, heavily doped region 123, heavily doped region 124, heavily doped region 125, M/2 N-shaped
Drain region 133,135 ... is connected with PAD1, the anode as this high robust ESD device；The heavily doped region 111, heavy doping
Area 131, the heavy doping source region 132 of M/2+1 N-shaped, 134 ..., N-shaped multi-crystal silicon area on M thin oxide layer 150,151,
152 ... are connected with PAD2, the cathode as this high robust ESD device.
N is positive integer, and M is even number.
The working principle of above-mentioned high robust ESD device are as follows:
Due to the segmentation of N-shaped heavily doped region in N-shaped trap, the electric current of high robust ESD device of the present invention releases path by original
This parasitic path npn1 and the parasitism path the npn2 path Liang Zhong becomes the parasitic path npn1, the parasitism path npn2 and the path SCR
Three kinds of paths；When the PAD1 to the high robust ESD device applies a positive pulse and PAD2 is grounded, managed with GGNMOS
For 100, the p-n junction first between N-shaped heavy doping drain region 133 and p-type well region 130 is reverse-biased, when reversed bias voltage is greater than N+/P-
When the avalanche breakdown voltage of well knot, which occurs avalanche breakdown, generates a large amount of electron-hole pair；The electronics of generation passes through
N-shaped heavy doping drain region 133 reaches PAD1, and hole reaches PAD2 through p-type well region 130, p-type heavily doped region 131, in p-type well region 130
Well resistance on generate pressure drop, eventually lead to the p-n junction forward conduction being made of p-type well region 130 and N-shaped heavy doping source region 132,
Parasitic npn1 pipe is opened in GGNMOS, thus first parasitism npn1 path current path of releasing generates；Similarly, GGNMOS is managed
Second parasitism path npn1 being made of in 200 N-shaped heavy doping drain region 133, p-type well region 130 and N-shaped heavy doping source region 134,
The third being made of in GGNMOS pipe 300 N-shaped heavy doping drain region 135, p-type well region 130 and N-shaped heavy doping source region 134 is parasitic
The path npn1, the m-th being made of in GGNMOS pipe M00 N-shaped heavy doping drain region, p-type well region and N-shaped heavy doping source region are parasitic
The path npn1 is not always the case unlatching.Later, due to p-n junction (the i.e. current collection of npn2 of N-shaped well region 120 and the composition of p-type well region 130
Pole-base junction) it is reverse-biased, and p-n junction (the i.e. base-emitter of npn2 that p-type well region 130 and N-shaped heavy doping source region 132 are constituted
Knot) positively biased, parasitic npn2 pipe opens, and first parasitism npn2 electric current path of releasing generates；Similarly, N-shaped heavily doped region 122, N-shaped
Second parasitism path npn2 that deep-well region 120, p-type well region 130 and N-shaped heavy doping source region 134 are constituted, N-shaped heavily doped region
123, the M/2+1 parasitism path npn2 that N-shaped well region 120, p-type well region 130 and N-shaped heavy doping source region are constituted also is so to open
It opens.Finally, the P+/DNW of p-type heavily doped region 124 and N-shaped well region 120 ties forward conduction, by p-type heavily doped region 124, N-shaped well region
120, pnp pipe conducting in the parasitic SCR that p-type well region 130, N-shaped heavy doping source region 132 are constituted, then first parasitism path SCR is led
It is logical, it generates ESD and releases access；Similarly, p-type heavily doped region 124, N-shaped well region 120, p-type well region 130, N-shaped heavy doping source region 134
The second parasitism path SCR constituted, p-type heavily doped region 125, N-shaped well region 120, p-type well region 130, N-shaped heavy doping source region structure
At the M/2+1 parasitism path SCR be also so to open.Since electric current is released the increase in path, ESD device of the present invention is compared
Higher robustness can be realized in traditional GGNMOS device.Simultaneously as high robust ESD device of the invention is only original
GGNMOS device N-shaped well region N-shaped heavily doped region on the basis of insertion p-type heavily doped region be split, therefore ESD device of the present invention
Chip area needed for part and common GGNMOS device is completely the same.
The above description is merely a specific embodiment, any feature disclosed in this specification, except non-specifically
Narration, can be replaced by other alternative features that are equivalent or have similar purpose；Disclosed all features or all sides
Method or in the process the step of, other than mutually exclusive feature and/or step, can be combined in any way.
Claims (1)
1. a kind of high robust ESD device structure for ESD protection, which is characterized in that the device architecture includes:
The first conduction type silicon substrate (110), interior the first conduction type being arranged of the first described conduction type silicon substrate
Heavily doped region A1(111)；
Second of the conduction type well region (120) formed on the silicon substrate, the interior N being arranged of second of conduction type well region
A the first conduction type heavily doped region A2(124,125) and N number of second of conduction type heavily doped region B1(122,123), it is described
The heavily doped region of two kinds of conduction types is adjacent and is spaced apart；
The first the conduction type well region (130) formed on second of conduction type well region, the first described conduction type
The first the conduction type heavily doped region A being arranged in well region3(131), M/2+1 second of conduction type heavy doping source regions
(132,134......) and M/2 second of conduction type heavy doping drain regions (133,135......)；The M/2+1 second
Kind conduction type heavy doping source region is spaced apart with M/2 second of conduction type heavy doping drain regions, and second of conduction type
Be respectively provided on silicon face between heavy doping drain region and second of conduction type heavy doping source region thin oxide layer area (140,141,
142......), second of conductivity type polysilicon area (150,151,152......) are all covered in each thin oxide layer area；
The first conduction type heavily doped region A1, the first conduction type heavily doped region A3, second of conduction type polycrystalline
Silicon area, M/2+1 second of conduction type heavy doping source regions homogeneously connect, the cathode as device；The first described N number of conductive-type
Type heavily doped region A2, N number of second of conduction type heavily doped region B1, second of the conduction type heavy doping drain region M/2 be connected,
Anode as device.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030189230A1 (en) * | 2001-12-26 | 2003-10-09 | Kei-Kang Hung | Semiconductor device with substrate-triggered esd protection |
| US20040070900A1 (en) * | 2002-10-11 | 2004-04-15 | Industrial Technology Research Institute | Electrostatic discharge protection device for mixed voltage interface |
| CN104183593A (en) * | 2013-05-22 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure |
| CN106298764A (en) * | 2015-05-19 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and electronic installation |
-
2019
- 2019-04-29 CN CN201910353954.3A patent/CN110120391B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030189230A1 (en) * | 2001-12-26 | 2003-10-09 | Kei-Kang Hung | Semiconductor device with substrate-triggered esd protection |
| US20040070900A1 (en) * | 2002-10-11 | 2004-04-15 | Industrial Technology Research Institute | Electrostatic discharge protection device for mixed voltage interface |
| CN104183593A (en) * | 2013-05-22 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure |
| CN106298764A (en) * | 2015-05-19 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and electronic installation |
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