US20030189230A1 - Semiconductor device with substrate-triggered esd protection - Google Patents
Semiconductor device with substrate-triggered esd protection Download PDFInfo
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- US20030189230A1 US20030189230A1 US10/117,147 US11714702A US2003189230A1 US 20030189230 A1 US20030189230 A1 US 20030189230A1 US 11714702 A US11714702 A US 11714702A US 2003189230 A1 US2003189230 A1 US 2003189230A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 76
- 230000001960 triggered effect Effects 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 230000003071 parasitic effect Effects 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 abstract description 6
- 238000003491 array Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Definitions
- the invention relates to a semiconductor device and, more particularly, to a semiconductor device with substrate-triggered electrostatic discharge (ESD) protection.
- ESD electrostatic discharge
- the electrostatic protection is one of the important issues of the integrated circuits. Since the electrostatic charge is accompanied with a relatively high voltage (may be several thousands volts), those skilled in the art may utilize an electrostatic discharge (ESD) protection circuit to protect the semiconductor device, thereby preventing the semiconductor device from being damaged by the electrostatic charge.
- ESD electrostatic discharge
- a conventional semiconductor device 1 with ESD protection includes a guard ring 11 and a MOS (Metal-Oxide-Semiconductor) transistor array 12 .
- the MOS transistor array 12 has a plurality of MOS transistors, each of which is composed of a source 121 , a drain 122 and a gate 123 .
- the circuit layout of the gate 123 is of a finger-type.
- a plurality of N + diffusion areas and a plurality of P + diffusion areas are formed on a substrate 20 .
- the N + diffusion areas 21 and 22 serve as the source 121 and the drain 122 shown in FIG. 1A, respectively.
- the P + diffusion area 23 serves as the guard ring 11 shown in FIG. 1A.
- the N + diffusion areas 21 and 22 and the substrate 20 form a parasitic bipolar junction transistor (parasitic BJT) 24 .
- parasitic BJT parasitic bipolar junction transistor
- the junction between the base and the emitter of the parasitic BJT 24 is forward biased by the ESD pulse, such as of a human-body mode (HBM), in order to trigger the parasitic BJT 24 into an active region.
- HBM human-body mode
- the finger-type NMOS transistors as described above cannot be uniformly triggered as expected, but only a part of the fingers are activated. The result is that the semiconductor device 1 is easily subjected to ESD damage. Therefore, even if there are more MOS fingers forming the parasitic BJT in the semiconductor device 1 to discharge the electrostatic charge, the ESD robustness of the semiconductor device 1 is still very low. In other words, since the turn-on speeds of the fingers are different from one another, the turn-on uniformity is not good. Thus, the ESD protection level of the semiconductor device does not come up to expectation.
- a conventional semiconductor device 3 with substrate-triggered ESD technique includes a guard ring 31 and a MOS transistor array 32 .
- the MOS transistor array 32 has a plurality of MOS transistors 321 , a plurality of fingers 322 constituted by the gates of the MOS transistors 321 , and a plurality of substrate-triggered areas 323 between the fingers 322 . As shown in FIG.
- the semiconductor device 3 is different from the aforementioned semiconductor device 1 in having a plurality of P + diffusion areas 41 and a plurality of isolation portions 42 .
- Each of the isolation portions 42 can be a shallow trench isolation (STI) portion for separating the P + diffusion areas 41 from the N + diffusion areas.
- STI shallow trench isolation
- each finger can be efficiently improved by forming a substrate-triggered area between two adjacent fingers.
- three substrate-triggered areas 323 (as shown in FIG. 2A) have to be provided for four fingers 322 , these substrate-triggered areas may increase the area of the circuit layout.
- the number of the MOS transistors in the MOS transistor array greatly decreases due to the provision of the substrate-triggered area. The manufacturing cost of the semiconductor device is thus increased.
- a semiconductor device with substrate-triggered ESD protection in accordance with one aspect of the invention includes a guard ring, a first MOS transistor array, a second MOS transistor array and a substrate-triggered portion.
- the first MOS transistor array, the second MOS transistor array and the substrate-triggered portion are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array.
- the substrate-triggered portion can bias a base of at least one parasitic BJT in the first MOS transistor array and a base of at least one parasitic BJT in the second MOS transistor array.
- an isolation portion is further formed among the guard ring, the first MOS transistor array, the second MOS transistor array and the substrate-triggered portion.
- the semiconductor device with substrate-triggered ESD protection further includes a first N-well and a second N-well.
- the first N-well and the second N-well are formed between the first MOS transistor array and the second MOS transistor array, and located at two sides of the substrate-triggered portion, respectively.
- the substrate-triggered portion is formed between two MOS transistor arrays, but not formed between two fingers in one MOS transistor array. As a result, it can be used for improving the ESD protection ability of the semiconductor device without greatly increasing the area of the circuit layout with this design.
- FIG. 1A is a schematic illustration showing a circuit layout of a conventional semiconductor device with ESD protection
- FIG. 1B is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line AA′ in FIG. 1A;
- FIG. 2A is a schematic illustration showing a circuit layout of another conventional semiconductor device with substrate-triggered ESD protection
- FIG. 2B is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line BB′ in FIG. 2A;
- FIG. 3A is a schematic illustration showing a circuit layout of a semiconductor device with substrate-triggered ESD protection design in accordance with a preferred embodiment of the invention
- FIG. 3B is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line CC′ in FIG. 3A;
- FIG. 3C is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line DD′ in FIG. 3A;
- FIG. 3D is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line EE′ in FIG. 3A;
- FIG. 4 is a schematic illustration showing a circuit layout of a semiconductor device with substrate-triggered ESD protection design in accordance with another preferred embodiment of the invention.
- FIG. 5 is a schematic illustration showing a circuit layout of a semiconductor device with substrate-triggered ESD protection design in accordance with another preferred embodiment of the invention.
- a semiconductor device 5 with substrate-triggered ESD protection technique in accordance with a preferred embodiment of the invention includes a guard ring 51 , a first MOS transistor array 52 , a second MOS transistor array 53 , a substrate-triggered portion 54 and an isolation portion 55 .
- the first MOS transistor array 52 , the second MOS transistor array 53 , the substrate-triggered portion 54 and the isolation portion 55 are formed in a region surrounded by the guard ring 51 .
- the substrate-triggered portion 54 is located between the first MOS transistor array 52 and the second MOS transistor array 53 .
- the isolation portion 55 is formed among the guard ring 51 , the first MOS transistor array 52 , the second MOS transistor array 53 and the substrate-triggered portion 54 so as to separate these regions.
- the guard ring 51 is formed on a P + diffusion area 61 of a substrate 60 .
- the first MOS transistor array 52 , the second MOS transistor array 53 , the substrate-triggered portion 54 and the isolation portion 55 can be an N + diffusion area 62 , an N + diffusion area 63 , a P + diffusion area 64 and a shallow trench isolation (STI) portion 65 formed on the substrate 60 , respectively.
- STI shallow trench isolation
- the first MOS transistor array 52 and the second MOS transistor array 53 include a first parasitic BJT 521 (as shown in FIG. 3C) and a second parasitic BJT 531 (as shown in FIG. 3D), respectively.
- the trigger current I trig can flow through the P + diffusion area 64 to the P + diffusion area 61 serving as the guard ring 51 , so as to produce a voltage drop.
- the voltage drop is the product of the trigger current I trig and the substrate resistor R sub and is capable of forward-biasing the base-emitter junctions of the parasitic BJTs 521 and 531 into active states, so as to enable the parasitic BJTs to discharge the electrostatic charge.
- the MOS transistors in the first MOS transistor array 52 and the second MOS transistor array 53 can be NMOS transistors or PMOS transistors.
- first parasitic BJT 521 and the second parasitic BJT 531 shown in FIGS. 3C and 3D are merely schematic illustrations.
- the direction from the collector to the emitter of the parasitic BJTs i.e., the direction from the source to the drain of each MOS transistor
- the direction of the trigger current Itig flowing through the substrate-triggered portion 54 to the P + diffusion area 61 is parallel to a line CC′ (as shown in FIG. 3A).
- first parasitic BJT 521 can be widely referred to all parasitic BJTs in the first MOS transistor array 52
- second parasitic BJT 531 can be widely referred to all parasitic BJTs in the second MOS transistor array 53 .
- a semiconductor device 7 with substrate-triggered ESD protection design in accordance with another preferred embodiment of the invention further includes a first N-well 56 and a second N-well 57 .
- the first N-well 56 and the second N-well 57 are formed between the first MOS transistor array 52 and the second MOS transistor array 53 , and are located at two sides of the substrate-triggered portion 54 , respectively. Since the first N-well 56 and the second N-well 57 are N diffusion areas that are deeply diffused into the substrate, and the substrate-triggered portion 54 is a P + diffusion area, when the ESD event occurs, the trigger current flows from the substrate-triggered portion 54 to the substrate.
- the trigger current components toward the first N-well 56 and the second N-well 57 decrease. Consequently, the trigger current components toward the first MOS transistor array 52 and the second MOS transistor array 53 correspondingly increase. In this case, since the trigger current can efficiently bias the bases of the parasitic BJTs in the first MOS transistor array 52 and the second MOS transistor array 53 , the ESD protection ability of the semiconductor device 7 can be efficiently improved without greatly increasing the circuit layout area.
- the semiconductor device 5 and 7 mentioned above might include three (or more than three) MOS transistor arrays, two (or more than two) substrate-triggered portions and N-wells formed in a region surrounded by the guard ring 51 .
- a semiconductor device 8 with substrate-triggered ESD protection design in accordance with another preferred embodiment of the invention includes a guard ring 81 , three MOS transistor arrays 82 , two substrate-triggered portions 83 , an isolation portion 84 and four N-wells 85 .
- the N-wells are formed at both sides of the substrate-triggered portions 83 .
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Abstract
Description
- 1. Field of the Invention
- The invention relates to a semiconductor device and, more particularly, to a semiconductor device with substrate-triggered electrostatic discharge (ESD) protection.
- 2. Description of the Related Art
- The electrostatic protection is one of the important issues of the integrated circuits. Since the electrostatic charge is accompanied with a relatively high voltage (may be several thousands volts), those skilled in the art may utilize an electrostatic discharge (ESD) protection circuit to protect the semiconductor device, thereby preventing the semiconductor device from being damaged by the electrostatic charge.
- Referring to FIG. 1A, a
conventional semiconductor device 1 with ESD protection includes aguard ring 11 and a MOS (Metal-Oxide-Semiconductor)transistor array 12. TheMOS transistor array 12 has a plurality of MOS transistors, each of which is composed of asource 121, adrain 122 and agate 123. The circuit layout of thegate 123 is of a finger-type. As shown in FIG. 1B, a plurality of N+ diffusion areas and a plurality of P+ diffusion areas are formed on asubstrate 20. The N+ diffusion areas 21 and 22 serve as thesource 121 and thedrain 122 shown in FIG. 1A, respectively. The P+ diffusion area 23 serves as theguard ring 11 shown in FIG. 1A. The N+ diffusion areas 21 and 22 and thesubstrate 20 form a parasitic bipolar junction transistor (parasitic BJT) 24. Thus, the junction between the base and the emitter of theparasitic BJT 24 is forward biased by the ESD pulse, such as of a human-body mode (HBM), in order to trigger theparasitic BJT 24 into an active region. Thus, theMOS transistor array 12 can be protected. - However, the finger-type NMOS transistors as described above cannot be uniformly triggered as expected, but only a part of the fingers are activated. The result is that the
semiconductor device 1 is easily subjected to ESD damage. Therefore, even if there are more MOS fingers forming the parasitic BJT in thesemiconductor device 1 to discharge the electrostatic charge, the ESD robustness of thesemiconductor device 1 is still very low. In other words, since the turn-on speeds of the fingers are different from one another, the turn-on uniformity is not good. Thus, the ESD protection level of the semiconductor device does not come up to expectation. - In order to overcome the aforementioned problem, those skilled in the art may improve the turn-on uniformity of each finger by various circuit tricks. One of the most commonly used methods is to use a substrate-triggered ESD protection circuit for improving the turn-on uniformity of the MOS fingers. Referring to FIG. 2A, a
conventional semiconductor device 3 with substrate-triggered ESD technique includes aguard ring 31 and aMOS transistor array 32. TheMOS transistor array 32 has a plurality ofMOS transistors 321, a plurality offingers 322 constituted by the gates of theMOS transistors 321, and a plurality of substrate-triggeredareas 323 between thefingers 322. As shown in FIG. 2B, a plurality of N+ diffusion areas and a plurality of P+ diffusion areas are formed on asubstrate 40. Since the diffusion areas are similar to those of theaforementioned semiconductor device 1, detailed description thereof is omitted. Thesemiconductor device 3 is different from theaforementioned semiconductor device 1 in having a plurality of P+ diffusion areas 41 and a plurality of isolation portions 42. Each of the isolation portions 42 can be a shallow trench isolation (STI) portion for separating the P+ diffusion areas 41 from the N+ diffusion areas. Thus, when the ESD event occurs, the trigger current Itrig flows through the P+ diffusion areas 41 to thesubstrate 40, and then the bases ofparasitic BJTs parasitic BJTs - To sum up, the turn-on uniformity of each finger can be efficiently improved by forming a substrate-triggered area between two adjacent fingers. However, since three substrate-triggered areas323 (as shown in FIG. 2A) have to be provided for four
fingers 322, these substrate-triggered areas may increase the area of the circuit layout. In other words, in each MOS transistor array, there is a large area not formed with MOS transistors. Therefore, the number of the MOS transistors in the MOS transistor array greatly decreases due to the provision of the substrate-triggered area. The manufacturing cost of the semiconductor device is thus increased. - As above, it is an important subject matter to provide the substrate-triggered area so as to improve the ESD protection ability of the semiconductor device without greatly increasing the area of the circuit layout.
- In view of the aforementioned problem, it is an important object of the invention to provide a semiconductor device with substrate-triggered ESD protection technique and having a substrate-triggered area capable of improving the ESD protection ability without greatly increasing the area of the circuit layout.
- To achieve this object, a semiconductor device with substrate-triggered ESD protection in accordance with one aspect of the invention includes a guard ring, a first MOS transistor array, a second MOS transistor array and a substrate-triggered portion. In the invention, the first MOS transistor array, the second MOS transistor array and the substrate-triggered portion are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. Thus, the substrate-triggered portion can bias a base of at least one parasitic BJT in the first MOS transistor array and a base of at least one parasitic BJT in the second MOS transistor array. As stated above, an isolation portion is further formed among the guard ring, the first MOS transistor array, the second MOS transistor array and the substrate-triggered portion.
- In addition, in another aspect of the invention, the semiconductor device with substrate-triggered ESD protection further includes a first N-well and a second N-well. The first N-well and the second N-well are formed between the first MOS transistor array and the second MOS transistor array, and located at two sides of the substrate-triggered portion, respectively.
- To sum up, in the semiconductor device with substrate-triggered ESD protection design in accordance with the invention, the substrate-triggered portion is formed between two MOS transistor arrays, but not formed between two fingers in one MOS transistor array. As a result, it can be used for improving the ESD protection ability of the semiconductor device without greatly increasing the area of the circuit layout with this design.
- The above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following detailed descriptions and accompanying drawings, wherein:
- FIG. 1A is a schematic illustration showing a circuit layout of a conventional semiconductor device with ESD protection;
- FIG. 1B is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line AA′ in FIG. 1A;
- FIG. 2A is a schematic illustration showing a circuit layout of another conventional semiconductor device with substrate-triggered ESD protection;
- FIG. 2B is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line BB′ in FIG. 2A;
- FIG. 3A is a schematic illustration showing a circuit layout of a semiconductor device with substrate-triggered ESD protection design in accordance with a preferred embodiment of the invention;
- FIG. 3B is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line CC′ in FIG. 3A;
- FIG. 3C is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line DD′ in FIG. 3A;
- FIG. 3D is a schematic illustration showing a cross-sectional view of the semiconductor device taken along a line EE′ in FIG. 3A;
- FIG. 4 is a schematic illustration showing a circuit layout of a semiconductor device with substrate-triggered ESD protection design in accordance with another preferred embodiment of the invention; and
- FIG. 5 is a schematic illustration showing a circuit layout of a semiconductor device with substrate-triggered ESD protection design in accordance with another preferred embodiment of the invention.
- The semiconductor device with substrate-triggered ESD protection technique in accordance with preferred embodiments of the invention will be described with reference to the accompanying drawings, wherein the same reference numbers denote the same elements.
- Referring to FIG. 3A, a semiconductor device5 with substrate-triggered ESD protection technique in accordance with a preferred embodiment of the invention includes a
guard ring 51, a firstMOS transistor array 52, a secondMOS transistor array 53, a substrate-triggeredportion 54 and anisolation portion 55. - In this embodiment, the first
MOS transistor array 52, the secondMOS transistor array 53, the substrate-triggeredportion 54 and theisolation portion 55 are formed in a region surrounded by theguard ring 51. The substrate-triggeredportion 54 is located between the firstMOS transistor array 52 and the secondMOS transistor array 53. In addition, theisolation portion 55 is formed among theguard ring 51, the firstMOS transistor array 52, the secondMOS transistor array 53 and the substrate-triggeredportion 54 so as to separate these regions. - As shown in FIG. 3B, the
guard ring 51 is formed on a P+ diffusion area 61 of asubstrate 60. In addition, the firstMOS transistor array 52, the secondMOS transistor array 53, the substrate-triggeredportion 54 and theisolation portion 55 can be an N+ diffusion area 62, an N+ diffusion area 63, a P+ diffusion area 64 and a shallow trench isolation (STI)portion 65 formed on thesubstrate 60, respectively. It is obvious from FIG. 3B that the shallowtrench isolation portion 65 isolates the N+ diffusion area 62, the N+ diffusion area 63 and the P+ diffusion area 64 from one another. - As stated above, the first
MOS transistor array 52 and the secondMOS transistor array 53 include a first parasitic BJT 521 (as shown in FIG. 3C) and a second parasitic BJT 531 (as shown in FIG. 3D), respectively. When the ESD event occurs, the trigger current Itrig can flow through the P+ diffusion area 64 to the P+ diffusion area 61 serving as theguard ring 51, so as to produce a voltage drop. The voltage drop is the product of the trigger current Itrig and the substrate resistor Rsub and is capable of forward-biasing the base-emitter junctions of theparasitic BJTs MOS transistor array 52 and the secondMOS transistor array 53 can be NMOS transistors or PMOS transistors. - It should be noted that the first
parasitic BJT 521 and the secondparasitic BJT 531 shown in FIGS. 3C and 3D are merely schematic illustrations. In this embodiment, the direction from the collector to the emitter of the parasitic BJTs (i.e., the direction from the source to the drain of each MOS transistor) is parallel to lines DD′ and EE′ (as shown in FIG. 3A). On the other hand, the direction of the trigger current Itig flowing through the substrate-triggeredportion 54 to the P+ diffusion area 61 is parallel to a line CC′ (as shown in FIG. 3A). In addition, the firstparasitic BJT 521 can be widely referred to all parasitic BJTs in the firstMOS transistor array 52, while the secondparasitic BJT 531 can be widely referred to all parasitic BJTs in the secondMOS transistor array 53. - Referring to FIG. 4, a
semiconductor device 7 with substrate-triggered ESD protection design in accordance with another preferred embodiment of the invention further includes a first N-well 56 and a second N-well 57. In this embodiment, the first N-well 56 and the second N-well 57 are formed between the firstMOS transistor array 52 and the secondMOS transistor array 53, and are located at two sides of the substrate-triggeredportion 54, respectively. Since the first N-well 56 and the second N-well 57 are N diffusion areas that are deeply diffused into the substrate, and the substrate-triggeredportion 54 is a P+ diffusion area, when the ESD event occurs, the trigger current flows from the substrate-triggeredportion 54 to the substrate. At this time, due to the blocking effects of the first N-well 56 and the second N-well 57, the trigger current components toward the first N-well 56 and the second N-well 57 decrease. Consequently, the trigger current components toward the firstMOS transistor array 52 and the secondMOS transistor array 53 correspondingly increase. In this case, since the trigger current can efficiently bias the bases of the parasitic BJTs in the firstMOS transistor array 52 and the secondMOS transistor array 53, the ESD protection ability of thesemiconductor device 7 can be efficiently improved without greatly increasing the circuit layout area. - It should be noted that the
semiconductor device 5 and 7 mentioned above might include three (or more than three) MOS transistor arrays, two (or more than two) substrate-triggered portions and N-wells formed in a region surrounded by theguard ring 51. As shown in FIG. 5, for example, asemiconductor device 8 with substrate-triggered ESD protection design in accordance with another preferred embodiment of the invention includes aguard ring 81, threeMOS transistor arrays 82, two substrate-triggeredportions 83, anisolation portion 84 and four N-wells 85. The N-wells are formed at both sides of the substrate-triggeredportions 83. These elements of thesemiconductor device 8 are as described hereinbefore. People who skilled in the art should know that the amount of MOS transistor arrays, substrate-triggered portions and N-wells could be designed depending on the requirement of producers. - While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.
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TW090132428A TW519748B (en) | 2001-12-26 | 2001-12-26 | Semiconductor device with substrate-triggered ESD protection |
US10/117,147 US6639283B1 (en) | 2001-12-26 | 2002-04-04 | Semiconductor device with substrate-triggered ESD protection |
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2001
- 2001-12-26 TW TW090132428A patent/TW519748B/en not_active IP Right Cessation
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2002
- 2002-04-04 US US10/117,147 patent/US6639283B1/en not_active Expired - Lifetime
Cited By (14)
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US7323752B2 (en) * | 2004-09-30 | 2008-01-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuit with floating diffusion regions |
US20060065933A1 (en) * | 2004-09-30 | 2006-03-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuit with floating diffusion regions |
US20150001679A1 (en) * | 2009-03-11 | 2015-01-01 | Renesas Electronics Corporation | Esd protection element |
US9177949B2 (en) * | 2009-03-11 | 2015-11-03 | Renesas Electronics Corporation | ESD protection element |
WO2011031349A1 (en) * | 2009-09-08 | 2011-03-17 | Xilinx, Inc. | Shared electrostatic discharge protection for integrated circuit output drivers |
US8218277B2 (en) * | 2009-09-08 | 2012-07-10 | Xilinx, Inc. | Shared electrostatic discharge protection for integrated circuit output drivers |
JP2013504201A (en) * | 2009-09-08 | 2013-02-04 | ザイリンクス インコーポレイテッド | Shared electrostatic discharge protection for integrated circuit output drivers |
KR101330383B1 (en) | 2009-09-08 | 2013-11-15 | 자일링크스 인코포레이티드 | Shared electrostatic discharge protection for integrated circuit output drivers |
CN102484112B (en) * | 2009-09-08 | 2014-12-17 | 吉林克斯公司 | Shared electrostatic discharge protection for integrated circuit output drivers |
CN102484112A (en) * | 2009-09-08 | 2012-05-30 | 吉林克斯公司 | Shared electrostatic discharge protection for integrated circuit output drivers |
US20110058290A1 (en) * | 2009-09-08 | 2011-03-10 | Xilinx, Inc. | Shared electrostatic discharge protection for integrated circuit output drivers |
EP3163618A1 (en) * | 2015-10-27 | 2017-05-03 | Nexperia B.V. | Electrostatic discharge protection device |
US10262988B2 (en) | 2015-10-27 | 2019-04-16 | Nexperia B.V. | Electrostatic discharge protection device |
CN110120391A (en) * | 2019-04-29 | 2019-08-13 | 电子科技大学 | A kind of high robust ESD device for ESD protection |
Also Published As
Publication number | Publication date |
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TW519748B (en) | 2003-02-01 |
US6639283B1 (en) | 2003-10-28 |
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