CN110120391B - High-robustness ESD device for ESD protection - Google Patents

High-robustness ESD device for ESD protection Download PDF

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CN110120391B
CN110120391B CN201910353954.3A CN201910353954A CN110120391B CN 110120391 B CN110120391 B CN 110120391B CN 201910353954 A CN201910353954 A CN 201910353954A CN 110120391 B CN110120391 B CN 110120391B
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heavily doped
type
region
esd
path
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CN110120391A (en
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刘志伟
王琰
杜飞波
刘继芝
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

The invention belongs to the technical field of electronics, particularly relates to design of an electrostatic discharge (ESD) protection device, and particularly provides a high-robustness ESD device structure for ESD protection, which is used for improving the robustness of GGNMOS. Based on the existing GGNMOS structure, the invention uses the second conduction typeN first conductive type heavily doped regions A are adopted in the well region1And N heavily doped regions B of the second conductivity type1The adjacent and spaced design changes the device current leakage path from the original parasitic npn1 path and parasitic npn2 path into the parasitic npn1 path, parasitic npn2 path and SCR path; due to the increase of the current discharge path, compared with the traditional GGNMOS device, the ESD device can realize higher robustness; meanwhile, the layout area required by the high-robustness ESD device is completely consistent with that of a common GGNMOS device, namely the high-robustness ESD device realizes higher robustness under the condition of the same layout area.

Description

High-robustness ESD device for ESD protection
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to a design of an Electro-Static discharge (ESD) protection device, in particular to a high-robustness ESD device.
Background
An electrostatic discharge (ESD) phenomenon refers to a charge transfer phenomenon that occurs when objects having different electric potentials come close to or contact each other; in the discharging process, because the discharging time is extremely short, a large current can be generated; for integrated circuits, such large currents can damage or even burn internal devices, resulting in chip failure. The electrostatic discharge phenomenon may occur in various stages of chip production, transportation and use, and thus ESD protection measures are very important for the reliability of the chip.
Because a Grounded-Gate NMOS device (GGNMOS for short) is most compatible with CMOS process, the design is simple, and with the development of the process, the ESD performance can be translated to a new process without causing large degradation of the ESD performance, so the GGNMOS is the most commonly used ESD protection device in the current circuit. A conventional GGNMOS (Gate-group NMOSFET) device structure is shown in FIG. 1, when a positive pulse is applied to a PAD1 of the GGNMOS device and a PAD2 is Grounded, a P-N junction between an N-type heavily doped region 113 and a P-type substrate 110 is reversely biased, and when the reverse bias voltage is greater than the avalanche breakdown voltage of an N +/P substrate junction, the P-N junction is subjected to avalanche breakdown to generate a large number of electron-hole pairs; the generated electrons reach the PAD1 through the heavily doped n-type region 113, and simultaneously, the avalanche generated holes reach the PAD2 through the p-type substrate 110 and the heavily doped p-type region 111, so that a voltage drop is generated on the substrate resistance of the p-type substrate 110, and finally, the p-n junction formed by the p-type substrate 110 and the heavily doped n-type region 112 is conducted in the forward direction, and the parasitic npn tube in the GGNMOS is turned on and discharges ESD current.
In practical applications, in order to save chip area, a layout structure is usually designed in an interdigital distribution manner. A layout structure of a commonly used GGNMOS (Gate-group NMOSFET) device is shown in fig. 2; FIG. 3 is a cross-sectional view taken along line AA' of FIG. 2. The structure is composed of M GGNMOS tubes, wherein the GGNMOS tube 100 is composed of an n-type heavily doped source region 132, an n-type heavily doped drain region 133 and an n-type polysilicon region 150 on a thin oxide layer, the GGNMOS tube 200 is composed of an n-type heavily doped source region 134, an n-type heavily doped drain region 133 and an n-type polysilicon region 151 on the thin oxide layer, the GGNMOS tube 300 is composed of an n-type heavily doped source region 134, an n-type heavily doped drain region 135 and an n-type polysilicon region 152 on the thin oxide layer, and the GGNMOS tube M00 is composed of an n-type heavily doped source region, an n-type heavily doped drain region and an n-type polysilicon region on the thin oxide. The p-type heavily doped region 111, the p-type heavily doped region 131, the n-type polycrystalline silicon regions 150, 151 and 152 … … on the M thin oxide layers, and the M/2+1 n-type heavily doped source regions 132 and 134 … … are connected and used as the cathode of the device; the heavily doped n-type region 121 and the M/2 heavily doped n- type drain regions 133 and 135 … … are connected to serve as an anode of the device.
When a positive pulse is applied to the PAD1 of the GGNMOS device and the PAD2 is grounded, taking the GGNMOS tube 100 as an example, firstly, a P-N junction between an N-type heavily doped drain region 133 and a P-type well region 130 is reversely biased, and when the reverse bias voltage is greater than the avalanche breakdown voltage of an N +/P-well junction, the P-N junction is subjected to avalanche breakdown to generate a large number of electron-hole pairs; the generated electrons reach the PAD1 through the n-type heavily doped drain region 133, the holes reach the PAD2 through the p-type well region 130 and the p-type heavily doped region 131, a voltage drop is generated on the well resistor of the p-type well region 130, and finally, a p-n junction formed by the p-type well region 130 and the n-type heavily doped source region 132 is conducted in the forward direction, an npn1 tube parasitic in the GGNMOS is turned on, and a first parasitic npn1 path current discharge path is generated; similarly, the second parasitic npn1 path formed by the heavily doped n-type drain region 133, the p-type well 130 and the heavily doped n-type source region 134 in the GGNMOS transistor 200, the third parasitic npn1 path formed by the heavily doped n-type drain region 135, the p-type well 130 and the heavily doped n-type source region 134 in the GGNMOS transistor 300, and the mth parasitic npn1 path formed by the heavily doped n-type drain region, the p-type well 130 and the heavily doped n-type source region in the GGNMOS transistor M00 are all turned on. Then, since the p-n junction formed by the n-type well region 120 and the p-type well region 130 (i.e., the collector-base junction of npn 2) is reverse biased and the p-n junction formed by the p-type well region 130 and the heavily doped n-type source region 132 (i.e., the base-emitter junction of npn 2) is forward biased, the parasitic npn2 transistor is turned on and a first parasitic npn2 current bleeding path is generated; similarly, the second parasitic npn2 path formed by the heavily doped n-type region 121, the heavily doped n-type deep well region 120, the p-type well region 130, and the heavily doped n-type source region 134, and the (M/2 + 1) th parasitic npn2 path formed by the heavily doped n-type region 121, the heavily doped n-type well region 120, the p-type well region 130, and the heavily doped n-type source region are also turned on. Therefore, when an ESD event occurs, the GGNMOS device has two paths which discharge ESD current together.
However, the ESD robustness of GGNMOS is relatively low, which means that a GGNMOS-based ESD protection scheme needs to consume more chip area for a given ESD target; therefore, for the ESD protection under advanced technology, how to improve the robustness of the GGNMOS device is an important research direction for ESD device optimization.
Disclosure of Invention
The invention aims to provide a high-robustness ESD device structure for ESD protection, on the basis of the existing GGNMOS structure, the device structure divides an n-type heavily doped region by inserting a plurality of p-type heavily doped regions into an n-type well region, so that a parasitic Silicon-Controlled-Rectifier (SCR) current path is formed, and the ESD robustness of the GGNMOS is greatly improved under the same layout area.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a highly robust ESD device structure for ESD protection, comprising:
a first conductive type silicon substrate, a first conductive type heavily doped region A arranged in the first conductive type silicon substrate1；
Formed on the silicon substrateThe second conductive type well region, N first conductive type heavily doped regions a arranged in the second conductive type well region2And N heavily doped regions B of the second conductivity type1The heavily doped regions of the two conductivity types are adjacent and distributed at intervals;
a first conductivity type well region formed on the second conductivity type well region, and a first conductivity type heavily doped region A arranged in the first conductivity type well region3M/2+1 second conductivity type heavily doped source regions and M/2 second conductivity type heavily doped drain regions; the M/2+1 second-conductivity-type heavily-doped source regions and the M/2 second-conductivity-type heavily-doped drain regions are distributed at intervals, thin oxide regions are arranged on the silicon surface between the second-conductivity-type heavily-doped drain regions and the second-conductivity-type heavily-doped source regions, and each thin oxide region is covered with a second-conductivity-type polycrystalline silicon region;
the first conductive type heavily doped region A1A heavily doped region A of the first conductivity type3The second conductive type polysilicon region and the M/2+1 second conductive type heavily doped source regions are connected and used as the cathode of the device; the N first conductive type heavily doped regions A2N heavily doped regions B of the second conductivity type1The M/2 second conduction type heavily doped drain regions are connected and used as the anode of the device;
n is a positive integer and M is an even number.
The invention has the beneficial effects that:
the invention provides a high-robustness ESD device structure for ESD protection, wherein N first conductivity type heavily doped regions A are adopted in a second conductivity type well region1And N heavily doped regions B of the second conductivity type1The adjacent and spaced design changes the device current leakage path from the original parasitic npn1 path and parasitic npn2 path into the parasitic npn1 path, parasitic npn2 path and SCR path; due to the increase of the current discharge path, compared with the traditional GGNMOS device, the ESD device can realize higher robustness; meanwhile, the ESD device with high robustness and the common GGNMOS device of the inventionThe layout areas required by the elements are completely consistent, namely, the invention realizes higher robustness under the condition of the same layout area.
Drawings
Fig. 1 is a schematic structural diagram of a conventional GGNMOS device.
Fig. 2 is a layout of a conventional GGNMOS device structure.
FIG. 3 is a cross-sectional view taken along line AA' of FIG. 2.
Fig. 4 is a layout of a highly robust ESD device structure according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view taken along line AA' of FIG. 4 and a connection method according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view taken along line BB' in FIG. 4 and a schematic diagram of a connection method in an embodiment of the present invention.
Detailed description of the preferred embodiments
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Example 1
The present embodiment provides a highly robust ESD device structure for ESD protection, whose layout structure is shown in fig. 4, where the device structure includes:
a P-type silicon substrate 110 with an annular P-type heavily doped region 111 therein;
an N-type well region 120 is formed on the P-type silicon substrate and is surrounded in the annular P-type heavily doped region 111, N N-type heavily doped regions and N P-type heavily doped regions are arranged in the N-type well region 120, the heavily doped regions of the two conduction types are adjacent and distributed at intervals to form the annular heavily doped region together;
a p-type well region 130 is formed over the n-type well region 120 and is surrounded by the ring-shaped heavily doped region in the n-type well region 120; an annular p-type heavily doped region 131, M/2+1 n-type heavily doped source regions 132 and 134 … …, and M/2 n-type heavily doped drain regions 133 and 135 … … are respectively arranged in the p-type well region 130; the M/2+1 n-type heavily doped source regions and the M/2 n-type heavily doped drain regions are distributed at intervals and are all surrounded in the annular p-type heavily doped region 131; thin oxide regions 140, 141 and 142 … … are arranged on the silicon surface between the n-type heavily doped source region and the n-type heavily doped drain region, and the thin oxide regions are covered with n- type polysilicon regions 150, 151 and 152 … …;
cross-sectional views of the ESD device structure are shown in fig. 5 and 6; wherein, FIG. 5 is a cross-sectional view and a connection manner of the line AA 'in FIG. 4, and FIG. 6 is a cross-sectional view and a connection manner of the line BB' in FIG. 4; more specifically:
a p-type silicon substrate 110 with a p-type heavily doped region 111 therein;
an n-type well region 120 is formed on the substrate and is used for isolating the GGNMOS device above the substrate from the p-type silicon substrate, an n-type heavily doped region 122 and an n-type heavily doped region 123 (shown in figure 5), a p-type heavily doped region 124 and a p-type heavily doped region 125 (shown in figure 6) are arranged in the n-type well region, and the p-type heavily doped region and the n-type heavily doped region are adjacent and spaced to form division;
shallow Trench Isolation (STI for short) is arranged between the p-type heavily doped region 111 and the n-type heavily doped regions 122 and 123 (p-type heavily doped regions 124 and 125), between the n-type heavily doped regions 122 and 123 (p-type heavily doped regions 124 and 125) and the p-type heavily doped region 131, and between the p-type heavily doped region 131 and the n-type heavily doped region 132, as shown by the shaded regions in fig. 5 and 6;
the heavily doped region 122, the heavily doped region 123, the heavily doped region 124, the heavily doped region 125, and the M/2 n-type heavily doped drain regions 133 and 135 … … are connected with the PAD1 and used as an anode of the high-robustness ESD device; the heavily doped region 111, the heavily doped region 131, the M/2+1 n-type heavily doped source regions 132 and 134 … …, and the n- type polysilicon regions 150, 151 and 152 … … on the M thin oxide layers are connected with the PAD2 and serve as a cathode of the high-robustness ESD device.
N is a positive integer and M is an even number.
The working principle of the high-robustness ESD device is as follows:
due to the division of an n-type heavily doped region in an n-type well, the current discharge path of the high-robustness ESD device is changed into three paths, namely a parasitic npn1 path, a parasitic npn2 path and an SCR path, from the original two paths, namely a parasitic npn1 path and a parasitic npn2 path; when a positive pulse is applied to the PAD1 of the high-robustness ESD device and the PAD2 is grounded, taking the GGNMOS tube 100 as an example, firstly, a P-N junction between the N-type heavily doped drain region 133 and the P-type well region 130 is reversely biased, and when the reverse bias voltage is greater than the avalanche breakdown voltage of an N +/P-well junction, the P-N junction is subjected to avalanche breakdown to generate a large number of electron-hole pairs; the generated electrons reach the PAD1 through the n-type heavily doped drain region 133, the holes reach the PAD2 through the p-type well region 130 and the p-type heavily doped region 131, a voltage drop is generated on the well resistor of the p-type well region 130, and finally, a p-n junction formed by the p-type well region 130 and the n-type heavily doped source region 132 is conducted in the forward direction, an npn1 tube parasitic in the GGNMOS is turned on, and a first parasitic npn1 path current discharge path is generated; similarly, the second parasitic npn1 path formed by the heavily doped n-type drain region 133, the p-type well region 130, and the heavily doped n-type source region 134 in the GGNMOS 200, the third parasitic npn1 path formed by the heavily doped n-type drain region 135, the p-type well region 130, and the heavily doped n-type source region 134 in the GGNMOS 300, and the mth parasitic npn1 path formed by the heavily doped n-type drain region, the p-type well region, and the heavily doped n-type source region in the GGNMOS M00 are all turned on. Then, since the p-n junction formed by the n-type well region 120 and the p-type well region 130 (i.e., the collector-base junction of npn 2) is reverse biased and the p-n junction formed by the p-type well region 130 and the heavily doped n-type source region 132 (i.e., the base-emitter junction of npn 2) is forward biased, the parasitic npn2 transistor is turned on and a first parasitic npn2 current bleeding path is generated; similarly, the second parasitic npn2 path formed by the heavily doped n-type region 122, the deep n-type well region 120, the p-type well region 130, and the heavily doped n-type source region 134, and the (M/2 + 1) th parasitic npn2 path formed by the heavily doped n-type region 123, the n-type well region 120, the p-type well region 130, and the heavily doped n-type source region are also turned on. Finally, the P +/DNW junction of the P-type heavily doped region 124 and the n-type well region 120 is conducted in the forward direction, and a pnp transistor in a parasitic SCR formed by the P-type heavily doped region 124, the n-type well region 120, the P-type well region 130 and the n-type heavily doped source region 132 is conducted, so that the first parasitic SCR path is conducted, and an ESD discharge path is generated; similarly, the second parasitic SCR path formed by the p-type heavily doped region 124, the n-type well region 120, the p-type well region 130, and the n-type heavily doped source region 134, and the (M/2 + 1) th parasitic SCR path formed by the p-type heavily doped region 125, the n-type well region 120, the p-type well region 130, and the n-type heavily doped source region are also turned on. Compared with the traditional GGNMOS device, the ESD device can realize higher robustness due to the increase of the current discharge path. Meanwhile, the high-robustness ESD device is divided by inserting the p-type heavily doped region on the basis of the n-type heavily doped region of the n-type well region of the original GGNMOS device, so that the layout area required by the ESD device is completely consistent with that required by a common GGNMOS device.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.

Claims (1)

1. A highly robust ESD device structure for ESD protection, the device structure comprising:
a first conductivity type silicon substrate (110) provided with a first conductivity type heavily doped region A1（111）；
A second conductivity type well region (120) formed on the silicon substrate, and N first conductivity type heavily doped regions A arranged in the second conductivity type well region2(124, 125) and N heavily doped regions B of the second conductivity type1(122, 123), the first conduction type heavily doped region A2And a second conductive type heavily doped region B1Are distributed adjacently and at intervals;
a first conductivity type well region (130) formed over the second conductivity type well region, and a heavily doped first conductivity type region A disposed within the first conductivity type well region3(131) M/2+1 heavily doped source regions (132, 134.) of a second conductivity type and M/2 heavily doped drain regions (133, 135.); the M/2+1 heavily doped source regions of the second conductivity type and the M/2 heavily doped drain regions of the second conductivity type are distributed at intervals, thin oxide regions (140, 141, 142) are arranged on the silicon surface between the heavily doped drain regions of the second conductivity type and the heavily doped source regions of the second conductivity type, and each thin oxide region is covered with a polysilicon region (150, 151, 152) of the second conductivity type......）；
The first conductive type heavily doped region A1A heavily doped region A of the first conductivity type3The second conductive type polysilicon region and the M/2+1 second conductive type heavily doped source regions are connected and used as the cathode of the device; the N first conductive type heavily doped regions A2N heavily doped regions B of the second conductivity type1And the M/2 second conductivity type heavily doped drain regions are connected and used as the anode of the device.
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TW519748B (en) * 2001-12-26 2003-02-01 Faraday Tech Corp Semiconductor device with substrate-triggered ESD protection
US7394630B2 (en) * 2002-10-11 2008-07-01 Ming-Dou Ker Electrostatic discharge protection device for mixed voltage interface
CN104183593B (en) * 2013-05-22 2017-08-25 中芯国际集成电路制造(上海)有限公司 ESD-protection structure
CN106298764B (en) * 2015-05-19 2019-06-28 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and electronic device

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