CN110246837B - Double-diode ESD protection circuit - Google Patents
Double-diode ESD protection circuit Download PDFInfo
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- CN110246837B CN110246837B CN201910500481.5A CN201910500481A CN110246837B CN 110246837 B CN110246837 B CN 110246837B CN 201910500481 A CN201910500481 A CN 201910500481A CN 110246837 B CN110246837 B CN 110246837B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
Abstract
The invention provides a double-diode ESD protection circuit which comprises a high-end diode, a low-end diode, an ESD main path and a parasitic PNP triode. The high-end diode anode, the low-end diode cathode and the parasitic PNP triode emitter are connected with a circuit to be protected IO, the high-end diode cathode, the ESD main path anode and the parasitic PNP triode base are connected with a circuit to be protected VDD, and the low-end diode anode, the ESD main path cathode and the parasitic PNP triode collector are connected with a circuit to be protected GND. According to the invention, the ESD current of IO to GND is released through the parasitic PNP triode, namely, an ESD current release path of IO to GND is added, and compared with a double-diode ESD protection circuit with the same area, the failure current of the circuit is effectively improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuits and semiconductors, and relates to a double-diode ESD protection circuit which can be used for ESD protection of a chip level and a system level in an integrated circuit.
Technical Field
With the continuous advance of the scientific and technological revolution, the semiconductor technology and the integrated circuit technology have made great progress, so that the chip area is continuously reduced, and the operation speed is continuously improved. However, the high integration and high operating speed make integrated circuits and electronic devices more susceptible to ESD damage. Thus, ESD is an important component of integrated circuit reliability. ESD protection of integrated circuits is mainly implemented using ESD protection circuits. In the industry, the failure current is an important indicator of the ESD protection circuit. The ESD protection circuit is divided into two types, and generally, an ESD protection module is connected between an IO circuit and a GND circuit to be protected to release an ESD current when the operation speed or frequency of the circuit to be protected is low. The circuit is simple in design, but the ESD protection module occupies a large amount of chip area due to large size, has large parasitic capacitance and leakage current, and is not suitable for ESD protection of circuits with high speed or frequency. High frequency or high speed integrated circuits require ESD protection circuits with smaller circuit areas and lower parasitic capacitances and leakage currents. The double-diode ESD protection circuit is also widely used in the industry due to its small occupied area, low parasitic capacitance and leakage current. The basic structure of the double-diode ESD protection circuit is shown in FIG. 1, and comprises a high-side diode, a low-side diode and an ESD main path. The high-end diode is used for releasing ESD current of a circuit to be protected IO to VDD, the low-end diode is used for releasing ESD current of a circuit to be protected GND to IO, the ESD main path is used for releasing ESD current of the circuit to be protected VDD to GND, the ESD current from the circuit to be protected IO to GND is released to VDD from IO through the high-end diode, and then is released to GND from VDD through the ESD main path. The double-diode ESD protection circuit releases ESD current by forward conduction of the diode, so that the double-diode ESD protection circuit has smaller circuit area, parasitic capacitance and leakage current, and is widely applied to ESD protection of radio frequency, high-speed and digital circuits.
The double-diode ESD protection circuit is well-focused by researchers at home and abroad due to the characteristics of low leakage current, low parasitic capacitance and the like. To increase the failure current of a dual diode ESD protection circuit, designers typically increase the circuit area or design ESD main paths with higher failure currents. In addition, there are other methods proposed by the researchers in recent years, for example, in the paper entitled "Low-C ESD Protection Design with Dual Resistor-trigger SCRs in CMOS Technology" published by Chun-Yu Lin et al in "IEEE Transactions on devices and Materials Reliability" in 2018, a Low parasitic capacitance Dual diode Protection circuit is proposed, which has a structure shown in fig. 2, and uses the series connection of a Resistor and two high-side diodes to replace the high-side diodes of the basic circuit, and uses the series connection of a Resistor and two Low-side diodes to replace the Low-side diodes of the basic circuit, thereby further reducing the parasitic capacitance of the circuit. However, the failure current of the circuit is not effectively increased for the same circuit area. Meanwhile, because a high-end diode, a low-end diode and two resistors are added, the starting voltage of the circuit is improved, and the circuit is not suitable for ESD protection of a low-voltage circuit.
Disclosure of Invention
The invention aims to provide a double-diode ESD protection circuit aiming at the defects of the prior art, and the double-diode ESD protection circuit is used for solving the technical problem of low failure current in the prior art.
In order to achieve the purpose, the invention adopts the technical scheme that:
a double-diode ESD protection circuit comprises a high-end diode, a low-end diode and an ESD main path, wherein the anode of the high-end diode and the cathode of the low-end diode are connected with a circuit IO to be protected, the cathode of the high-end diode and the anode of the ESD main path are connected with a circuit VDD to be protected, the anode of the low-end diode and the cathode of the ESD main path are connected with a circuit GND to be protected, the high-end diode is used for releasing ESD current of the circuit IO to be protected to the VDD, and the low-end diode is used for releasing ESD current of the circuit GND to the IO to be protected; the ESD main path is used for releasing ESD current of a circuit VDD to be protected to GND; the circuit further comprises a parasitic PNP triode, wherein an emitting electrode of the parasitic PNP triode is connected with the circuit to be protected IO, a base electrode of the parasitic PNP triode is connected with the circuit to be protected VDD, and a collector electrode of the parasitic PNP triode is connected with the circuit to be protected GND.
In the double-diode ESD protection circuit, the high-side diode is an N-well P + diode.
In the double-diode ESD protection circuit, the parasitic PNP triode has the emitter adopting a P + structure, the base adopting an N-well structure and the collector adopting a P-substrate structure, and the starting voltage BV of the parasitic PNP triodeCEOThe reverse breakdown voltage of the N trap and the P substrate and the current amplification factor of the parasitic PNP triode are used for determining, and the calculation formula is as follows:
wherein, BVCBOIs parasitic PNP triode collector-base reverse breakdown voltage, i.e. reverse breakdown voltage between N well and P substrate, beta is parasitic PNP triode current amplification factor, N is constant determined by semiconductor material for manufacturing circuit, BVCBOAnd β are calculated as:
wherein E iscritCritical electric field for avalanche breakdown, NDFor semiconductor doping concentration, i.e. N-well and P-substrate concentration, WEAnd NERespectively, the width and concentration of the emitter, i.e. the width and concentration of P +, WBAnd NBRespectively representing the width and concentration of the base, i.e. the distance of P + to the P substrate and the concentration of the N-well, ni being the intrinsic semiconductor concentration.
In the above-mentioned double-diode ESD protection circuit, the on-resistance of the parasitic PNP transistor is determined by its current amplification factor β and the collector width, i.e., the distance from the N-well to the P-substrate electrode.
Compared with the prior art, the invention has the following advantages:
1. according to the parasitic PNP triode adopted by the invention, the emitter electrode is connected with the circuit IO to be protected, the base electrode is connected with the circuit VDD to be protected, the collector electrode is connected with the circuit GND to be protected, and ESD current between the IO and the GND can be released from the emitter electrode and the base electrode of the parasitic PNP triode to the collector electrode, namely, an ESD current release path from the IO to the GND is increased.
2. The invention can effectively reduce the starting voltage and the conducting resistance of the parasitic PNP triode by adjusting the widths of the emitter, the base and the collector of the parasitic PNP triode and the concentrations of the N trap and the P substrate.
3. The parasitic PNP triode is added on the structure of the basic double-diode ESD protection circuit, and compared with the prior art that a high-end diode, a low-end diode and a resistor are added, the structure of the double-diode ESD protection circuit is simpler on the premise that the low leakage current and the small occupied area of the protection circuit are ensured.
Drawings
FIG. 1 is a schematic diagram of a basic structure of a conventional double-diode ESD protection circuit;
FIG. 2 is a schematic diagram of a prior art structure;
FIG. 3 is a schematic structural view of the present invention;
fig. 4 is a schematic structural diagram of a parasitic PNP triode employed in the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments.
Referring to fig. 3, the present invention includes a high side diode, a low side diode, an ESD main path, and a parasitic PNP transistor. The high-end diode anode, the low-end diode cathode and the parasitic PNP triode emitter are connected with a circuit to be protected IO, the high-end diode cathode, the ESD main path anode and the parasitic PNP triode base are connected with a circuit to be protected VDD, and the low-end diode anode, the ESD main path cathode and the parasitic PNP triode collector are connected with a circuit to be protected GND.
The high-side diode may be a deep N-well P + diode, an N-type isolation diode, an N-well diode, etc., and since the N-well diode is simple to manufacture and is most common in semiconductor manufacturing processes, the N-well P + diode is used in this embodiment.
The low-side diode can be a P-substrate diode, an N-type isolation diode and a P-well N + diode, and the P-substrate diode is adopted in the embodiment.
The ESD main path may adopt a GGNMOS, RGNMOS, or SCR structure, and the SCR structure is adopted in this embodiment.
The parasitic PNP triode can adopt a P + emitter, a deep N well, an N buried layer or an N well and the like as the base, and can adopt a P well or a P substrate and the like as the collector. In summary, referring to fig. 4, the parasitic PNP transistor of the present embodiment adopts a structure in which the emitter is P +, the base is N-well, and the collector is P-substrate. Because the parasitic PNP triode can directly adopt the N trap and the P + of the high-end diode as the base electrode and the emitter electrode, other semiconductor layers are not added in the circuit. The prior art adds a high-side diode, a low-side diode and two resistors, at least one N well and semiconductor layers for manufacturing the resistors. Therefore, compared with the prior art, the structure of the invention is simpler.
Parasitic PNP triode turn-on voltage BVCEOThe reverse breakdown voltage of the N trap and the P substrate and the current amplification factor of the parasitic PNP triode are used for determining, and the calculation formula is as follows:
wherein, BVCBOThe parasitic PNP triode current amplification factor is the collector-base reverse breakdown voltage of the parasitic PNP triode, namely the reverse breakdown voltage between the N trap and the P substrate, beta is the parasitic PNP triode current amplification factor, and N is a constant determined by a semiconductor material for manufacturing the circuit. Therefore, BV can be reducedCBOAnd increasing beta decreasing BVCEO。BVCBOAnd β are calculated as:
wherein E iscritCritical electric field for avalanche breakdown, NDFor semiconductor doping concentration, i.e. N-well and P-substrate concentration, WEAnd NERespectively, the width and concentration of the emitter, WBAnd NBRespectively representing the width and the concentration of a base electrode, and ni is the concentration of an intrinsic semiconductor; the width and the concentration of the emitter are the width and the concentration of P +; the base width and the concentration are respectively the distance from P + to the P substrate and the concentration of the N trap. Thus, BV can be reduced by increasing the concentration of the N-well or P-substrateCBOTo thereby reduce BVCEO(ii) a Also by reducing WBOr increase WEIncrease beta, thereby reducing BVCEO. In summary, the parasitic PNP triode can be adjusted by adjusting the concentration of the N well and the P substrate and the width of the emitter and the base of the parasitic PNP triodeThe starting voltage of the pole tube can be applied to the ESD protection of a high-voltage circuit and can also be applied to the ESD protection of a low-voltage circuit. In addition, the on-resistance of the parasitic PNP transistor is determined by its current amplification factor β and the collector width, i.e., the distance from the N-well to the P-substrate electrode. The on-resistance of the parasitic PNP transistor can be reduced by increasing β or decreasing the distance from the N-well to the P-substrate electrode.
The protection principle of the invention is as follows: when an ESD event occurs, the ESD current of the circuit to be protected IO to VDD is released through the high-end diode, the ESD current of the circuit to be protected VDD to GND is released through the ESD main path, the ESD current of the circuit to be protected GND to IO is released through the low-end diode, and the ESD current of the circuit to be protected IO to GND is released through the high-end diode and the ESD main path. Further, the voltage generated by the ESD event causes the voltage between IO and GND to reach the turn-on voltage BV of the parasitic PNP transistorCEOTherefore, the ESD current of the IO pair GND can be released from the emitter and the base of the parasitic PNP triode to the collector, namely, an ESD current release path of the IO pair GND is added, and compared with a double-diode ESD protection circuit with the same area, the failure current of the circuit is effectively improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the innovative concept of the present invention, but these changes are all within the scope of the present invention.
Claims (4)
1. A double-diode ESD protection circuit comprises a high-end diode, a low-end diode and an ESD main path, wherein the anode of the high-end diode and the cathode of the low-end diode are connected with a circuit IO to be protected, the cathode of the high-end diode and the anode of the ESD main path are connected with a circuit VDD to be protected, the anode of the low-end diode and the cathode of the ESD main path are connected with a circuit GND to be protected, the high-end diode is used for releasing ESD current of the circuit IO to be protected to the VDD, and the low-end diode is used for releasing ESD current of the circuit GND to the IO to be protected; the ESD main path is used for releasing ESD current of a circuit VDD to be protected to GND; the method is characterized in that: the circuit further comprises a parasitic PNP triode, wherein an emitting electrode of the parasitic PNP triode is connected with the circuit to be protected IO, a base electrode of the parasitic PNP triode is connected with the circuit to be protected VDD, and a collector electrode of the parasitic PNP triode is connected with the circuit to be protected GND.
2. The dual-diode ESD protection circuit of claim 1, wherein the high-side diode is an N-well P + diode.
3. The dual-diode ESD protection circuit of claim 1, wherein the parasitic PNP transistor has an emitter with P + structure, a base with N-well structure, and a collector with P-substrate structure, and has a turn-on voltage BVCEOThe reverse breakdown voltage of the N trap and the P substrate and the current amplification factor of the parasitic PNP triode are used for determining, and the calculation formula is as follows:
wherein, BVCBOIs parasitic PNP triode collector-base reverse breakdown voltage, i.e. reverse breakdown voltage between N well and P substrate, beta is parasitic PNP triode current amplification factor, N is constant determined by semiconductor material for manufacturing circuit, BVCBOAnd β are calculated as:
wherein E iscritCritical electric field for avalanche breakdown, NDFor semiconductor doping concentration, i.e. N-well and P-substrate concentration, WEAnd NERespectively represents the width and concentration of P +, WBDenotes the distance of P + to the P substrate, NBDenotes the concentration of the N-well, ni being an intrinsic halfThe concentration of the conductor.
4. The dual-diode ESD protection circuit of claim 3, wherein the parasitic PNP transistor has an on-resistance determined by its current amplification β and a collector width, i.e., a distance from the N-well to the P-substrate electrode.
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| CN201910500481.5A CN110246837B (en) | 2019-06-11 | 2019-06-11 | Double-diode ESD protection circuit |
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| CN201910500481.5A CN110246837B (en) | 2019-06-11 | 2019-06-11 | Double-diode ESD protection circuit |
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| CN111696982B (en) * | 2020-06-09 | 2023-10-03 | 深圳能芯半导体有限公司 | Substrate separation N-type power tube ESD circuit and setting method |
| CN116864503A (en) * | 2023-07-19 | 2023-10-10 | 上海帝迪集成电路设计有限公司 | ESD self-protection high-voltage isolation ring |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022030A (en) * | 2011-09-27 | 2013-04-03 | 半导体元件工业有限责任公司 | Semiconductor device |
| CN103427407A (en) * | 2012-05-21 | 2013-12-04 | 南亚科技股份有限公司 | Electrostatic discharge protection circuit |
| JP2015103605A (en) * | 2013-11-22 | 2015-06-04 | 株式会社メガチップス | ESD protection circuit |
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| US8184415B2 (en) * | 2007-02-12 | 2012-05-22 | Nxp B.V. | ESD-protection device, a semiconductor device and integrated system in a package comprising such a device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022030A (en) * | 2011-09-27 | 2013-04-03 | 半导体元件工业有限责任公司 | Semiconductor device |
| CN103427407A (en) * | 2012-05-21 | 2013-12-04 | 南亚科技股份有限公司 | Electrostatic discharge protection circuit |
| JP2015103605A (en) * | 2013-11-22 | 2015-06-04 | 株式会社メガチップス | ESD protection circuit |
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