CN110069030A - A kind of unmanned aerial vehicle (UAV) control core buckle - Google Patents

A kind of unmanned aerial vehicle (UAV) control core buckle Download PDF

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Publication number
CN110069030A
CN110069030A CN201910304904.6A CN201910304904A CN110069030A CN 110069030 A CN110069030 A CN 110069030A CN 201910304904 A CN201910304904 A CN 201910304904A CN 110069030 A CN110069030 A CN 110069030A
Authority
CN
China
Prior art keywords
xazu5ev
1sfvc784q
uav
aerial vehicle
unmanned aerial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910304904.6A
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Chinese (zh)
Inventor
潘斌
周靖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hunan Inevitable Network Technology Co Ltd
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Hunan Inevitable Network Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Priority to CN201910304904.6A priority Critical patent/CN110069030A/en
Publication of CN110069030A publication Critical patent/CN110069030A/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423Input/output
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/20Pc systems
    • G05B2219/24Pc safety
    • G05B2219/24215Scada supervisory control and data acquisition

Abstract

The invention discloses a kind of unmanned aerial vehicle (UAV) control core buckles, it include: the core processor of model XAZU5EV-1SFVC784Q, the I/O pin of the XAZU5EV-1SFVC784Q connects USB3.0, Gen3 × 4 PCIe, PCIe 2 × 4, USB2.0 PHYs, Gigabit Ethernet PHYs, high speed interface, LVDS I/O port, the I/O pin of the XAZU5EV-1SFVC784Q connects FX10-168 connector, the FX10-168 connector connects 8 pairs of MGT differential signals, core buckle veneer configuration includes: the DDR4 of 8GB+2GB, the EMMC fla of 64GB The QSPI flash of sh, 512Mb, wherein the EMMC flash of the QSPI flash and 64GB of 64MB are connected to the DDR4 SDRAM of DDR4 SDRAM and PLProgrammable the Logic programmable logic of Processing System processing system, when specifically used, the buckle is buckled on bottom plate, the buckle input power 5-12V.It is to solve the problems such as expansion I/O interface is not few, complete using function, design buckle area is larger.

Description

A kind of unmanned aerial vehicle (UAV) control core buckle
Technical field
The present invention relates to unmanned aerial vehicle (UAV) control technical field, in particular to a kind of unmanned aerial vehicle (UAV) control core buckle.
Background technique
Referred to as " unmanned plane ", english abbreviation is " UAV " to UAV, is using radio robot and to provide for oneself The not manned aircraft of presetting apparatus manipulation, or fully or intermittently automatically operated by car-mounted computer.With section The application field of the development of skill, unmanned plane is more and more extensive, for example is used as reconnaissance plane, target drone, takes photo by plane, disaster relief etc..But It is that unmanned aerial vehicle (UAV) control hardware structure in the prior art also has the disadvantage that the I/O interface of 1. extensions is few, is unable to satisfy increasingly More application interface demands;2. it is not complete enough using function, it is unable to satisfy the demand of user's multifunctional use;3. designing buckle face Product is larger, cannot achieve in small space and works;4. design is incomplete, subsequent upgrade is inconvenient, may bring production cost The problems such as high and wasting of resources.
Summary of the invention
For above-mentioned deficiency in the prior art, the present invention provides a kind of unmanned aerial vehicle (UAV) control core buckles, with solution The problems such as certainly expansion I/O interface is not few, complete using function, design buckle area is larger.
In order to achieve the above object of the invention, the technical solution adopted by the present invention are as follows:
A kind of unmanned aerial vehicle (UAV) control core buckle, comprising: the core processor of model XAZU5EV-1SFVC784Q, it is described XAZU5EV-1SFVC784Q I/O pin connection USB3.0, PCIe Gen3 × 4, PCIe 2 × 4, USB2.0 PHYs, The I/O pin of Gigabit Ethernet PHYs, high speed interface, LVDS I/O port, the XAZU5EV-1SFVC784Q connects FX10-168 connector is connect, the FX10-168 connector connects 8 pairs of MGT differential signals, and core buckle veneer configuration includes: The QSPI flash of EMMC flash of DDR4,64GB of 8GB+2GB, 512Mb, wherein the QSPI flash and 64GB of 64MB EMMC flash be connected to the DDR4 SDRAM and PLProgrammable of Processing System processing system When specifically used, which is buckled on bottom plate by the DDR4 SDRAM of Logic programmable logic, the described buckle input power 5-12V。
Further, the XAZU5EV-1SFVC784Q QSPI flash can start out of plate, can also be from EMMC Flash or external SD card starting.
Further, which has 6 user lamps, and two of them user lamp connects Processing System Processing system, 1 user lamp connection Processing System processing system and PLProgrammable Logic can The coupling part of programmed logic, 3 user lamps are connected to PLProgrammable Logic programmable logic.
Further, EMMC flash uses MTFC64GAKAEYF-4M IT, memory space 64GB, EMMC Flash signal Line is connected to the PS MIO pin of XAZU5EV-1SFVC784Q.
Further, 0.85V, 0.9V, 1.2V, 1.8V, 2.5V, 3.3V, 0.6V voltage are produced in the buckle, 1.8V, 2.5V, 3.3V can supply bottom plate by FX10A-168S-SV connector, and XAZU5EV-1SFVC784Q electrifying timing sequence is on veneer 0.85V, 0.9V, 1.8V, 1.2V, 1.8V_bank, 1.8V_bank be available to XAZU5EV-1SFVC784Q bank500 and The voltage of bank502.
Further, the quantity of the DDR4 SDRAM is two, and a channel connects XAZU5EV-1SFVC784Q's Processing System processing system, a channel meet the PLProgrammable in XAZU5EV-1SFVC784Q Logic programmable logic, the DDR4 SDRAM use MT40A1G16KNR-075, and a DDR4 SDRAM is 16 data Position, 2GB memory space, another DDR4 SDRAM is 64 data bit, 8GB memory space.
Further, the XAZU5EV-1SFVC784Q leads ends connection is for FPGA starting of oscillation, the single-ended crystalline substance of 33.33MHz Vibration, FPGA bank64 connection 100MHz LVDS crystal oscillator, as PL DDR4 reference clock, FPGA PS GTR connection 100MHz LVDS crystal oscillator, bank505 connection 27MHz difference crystal oscillator, USB2.0 PHY chip USB3320C connection 24MHz crystal oscillator, network core Piece KSZ9031 connection 25MHz crystal oscillator.
Further, QSPI Flash uses MT25QU512ABB8E12-0SIT, capacity 512Mbit, QSPI Flash letter The PS MIO pin and FX10A-168S-SV connector of number line connection XAZU5EV-1SFVC784Q.
Further, the quantity of 2.0 PHY chip of USB is 2, and two are all connected to PS, and USB PHY0 can match It is set to host and is also configurable to equipment use, USB PHY1 can only be used as host, and 2.0 PHY chip of USB uses USB3320C。
Further, the buckle is equipped with 2 10/100/1000Mbit network PHY chips, and 1 is connected to by RGMII The part PS, 1 is connected to the part PL by RGMII.10/100/1000Mbit network PHY chip uses KSZ9031RNXIC.
The invention has the benefit that
1. versatility is extremely strong, unmanned plane can be used not only for, moreover it can be used to unmanned vehicle direction;2. this buckle size is small, it is applicable in very much In the small situation of working space;3. this buckle is multiple functional, the demand in common work can satisfy completely;4. PS+PL pin Distribution;5. the end PS DDR forms 8G by four particles and stores;6. scalability is good, stability is good.
Detailed description of the invention
Fig. 1 is the structural diagram of the present invention;
Fig. 2 is the structural schematic diagram of FX10-168 connector of the present invention.
Specific embodiment
In order that the present invention can be more clearly and readily understood, following will be combined with the drawings in the embodiments of the present invention, Technical scheme in the embodiment of the invention is clearly and completely described.
As shown in Figure 1, 2, a kind of unmanned aerial vehicle (UAV) control core buckle, comprising: the core of model XAZU5EV-1SFVC784Q Heart processor, the XAZU5EV-1SFVC784Q I/O pin connection USB3.0, PCIe Gen3 × 4, PCIe 2 × 4, USB2.0 PHYs, Gigabit Ethernet PHYs, high speed interface, LVDS I/O port, the XAZU5EV- The I/O pin of 1SFVC784Q connects FX10-168 connector, and the FX10-168 connector connects 8 pairs of MGT differential signals, should The configuration of core buckle veneer includes: the QSPI flash of EMMC flash of DDR4,64GB of 8GB+2GB, 512Mb, wherein The EMMC flash of the QSPI flash and 64GB of 64MB are connected to the DDR4 of Processing System processing system The buckle when specifically used, is buckled in bottom by the DDR4 SDRAM of SDRAM and PLProgrammable Logic programmable logic On plate, the buckle input power 5-12V.
The XAZU5EV-1SFVC784Q QSPI flash can start out of plate, can also be from EMMC flash or outer The starting of portion's SD card.The buckle has 6 user lamps, and two of them user lamp connects Processing System processing System, 1 user lamp connection Processing System processing system and PLProgrammable Logic are programmable The coupling part of logic, 3 user lamps are connected to PLProgrammable Logic programmable logic.EMMC flash is adopted With MTFC64GAKAEYF-4M IT, memory space 64GB, EMMC Flash signal wire is connected to XAZU5EV-1SFVC784Q's PS MIO pin.Produce 0.85V, 0.9V, 1.2V, 1.8V, 2.5V, 3.3V, 0.6V voltage in the buckle, 1.8V, 2.5V, 3.3V can supply bottom plate by FX10A-168S-SV connector, on veneer XAZU5EV-1SFVC784Q electrifying timing sequence be 0.85V, 0.9V, 1.8V, 1.2V, 1.8V_bank, 1.8V_bank are available to XAZU5EV-1SFVC784Q bank500 and bank502 Voltage.The quantity of the DDR4 SDRAM is two, and a channel meets the Processing in XAZU5EV-1SFVC784Q System processing system, a channel connect to may be programmed in the PLProgrammable Logic of XAZU5EV-1SFVC784Q and patrol Volume, it is 16 data bit, 2GB memory space that the DDR4 SDRAM, which uses MT40A1G16KNR-075, a DDR4 SDRAM, Another DDR4 SDRAM is 64 data bit, 8GB memory space.The XAZU5EV-1SFVC784Q leads ends connection is used for FPGA starting of oscillation, 33.33MHz single-end crystal oscillator, FPGA bank64 connection 100MHz LVDS crystal oscillator, as PL DDR4 reference when Clock, FPGA PS GTR connection 100MHz LVDS crystal oscillator, bank505 connection 27MHz difference crystal oscillator, USB2.0 PHY chip USB3320C connection 24MHz crystal oscillator, network chip KSZ9031 connection 25MHz crystal oscillator.QSPI Flash is used MT25QU512ABB8E12-0SIT, capacity 512Mbit, QSPI Flash signal wire connect the PS of XAZU5EV-1SFVC784Q MIO pin and FX10A-168S-SV connector.The quantity of 2.0 PHY chip of USB is 2, and two are all connected to PS, USB PHY0 is configurable to host and is also configurable to equipment use, and USB PHY1 can only be used as host, USB 2.0 PHY chip uses USB3320C.The buckle is equipped with 2 10/100/1000Mbit network PHY chips, and 1 is connected by RGMII It is connected to the part PS, 1 is connected to the part PL by RGMII.10/100/1000Mbit network PHY chip uses KSZ9031RNXIC.After buckle, which is connected to bottom plate, to be powered on, crystal oscillator starting of oscillation, buckle is started to work.
The present invention is applied not only to unmanned plane, and unmanned vehicle can also be used, and is a general core control panel, and other clients can be with Core board is designed without oneself, directly purchases general core board, and Service control program, each user are developed based on core board Application scenarios are different, it is desirable that control application is also different, has general-purpose platform, unmanned plane, unmanned vehicle Related product client can To save the project development time, it is absorbed in respective Service control software development
The above description is only a preferred embodiment of the patent of the present invention, is not intended to limit the invention patent, all in the present invention Made any modifications, equivalent replacements, and improvements etc., should be included in the guarantor of the invention patent within the spirit and principle of patent Within the scope of shield.

Claims (10)

1. a kind of unmanned aerial vehicle (UAV) control core buckle characterized by comprising the core of model XAZU5EV-1SFVC784Q Processor, the XAZU5EV-1SFVC784Q I/O pin connection USB3.0, PCIe Gen3 × 4, PCIe 2 × 4, USB2.0 PHYs, Gigabit Ethernet PHYs, high speed interface, LVDS I/O port, the XAZU5EV- The I/O pin of 1SFVC784Q connects FX10-168 connector, and the FX10-168 connector connects 8 pairs of MGT differential signals, should The configuration of core buckle veneer includes: the QSPI flash of EMMC flash of DDR4,64GB of 8GB+2GB, 512Mb, wherein The EMMC flash of the QSPI flash and 64GB of 64MB are connected to the DDR4 of Processing System processing system The buckle when specifically used, is buckled in bottom by the DDR4 SDRAM of SDRAM and PLProgrammable Logic programmable logic On plate, the buckle input power 5-12V.
2. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: the XAZU5EV- 1SFVC784Q QSPI flash can start out of plate, can also be from EMMC flash or external SD card starting.
3. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: the buckle has 6 users Indicator light, two of them user lamp connect Processing System processing system, 1 user lamp connection The coupling part of Processing System processing system and PLProgrammable Logic programmable logic, 3 users Indicator light is connected to PLProgrammable Logic programmable logic.
4. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: EMMC flash is used MTFC64GAKAEYF-4M IT, memory space 64GB, EMMC Flash signal wire are connected to the PS of XAZU5EV-1SFVC784Q MIO pin.
5. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: produced in the buckle 0.85V, 0.9V, 1.2V, 1.8V, 2.5V, 3.3V, 0.6V voltage, 1.8V, 2.5V, 3.3V can be connected by FX10A-168S-SV Device supply bottom plate is connect, XAZU5EV-1SFVC784Q electrifying timing sequence is 0.85V, 0.9V, 1.8V, 1.2V, 1.8V_bank on veneer, 1.8V_bank is available to the voltage of XAZU5EV-1SFVC784Q bank500 and bank502.
6. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: the DDR4 SDRAM's Quantity is two, and a channel connects the Processing System processing system in XAZU5EV-1SFVC784Q, a channel The PLProgrammable Logic programmable logic in XAZU5EV-1SFVC784Q is connect, the DDR4 SDRAM is used MT40A1G16KNR-075, a DDR4 SDRAM are 16 data bit, 2GB memory space, another DDR4 SDRAM is 64 Position data bit, 8GB memory space.
7. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: the XAZU5EV- The connection of 1SFVC784Q leads ends is for FPGA starting of oscillation, the single-end crystal oscillator of 33.33MHz, FPGA bank64 connection 100MHz LVDS Crystal oscillator, as PL DDR4 reference clock, FPGA PS GTR connection 100MHz LVDS crystal oscillator, bank505 connection 27MHz difference Crystal oscillator, USB2.0 PHY chip USB3320C connection 24MHz crystal oscillator, network chip KSZ9031 connection 25MHz crystal oscillator.
8. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: QSPI Flash is used MT25QU512ABB8E12-0SIT, capacity 512Mbit, QSPI Flash signal wire connect the PS of XAZU5EV-1SFVC784Q MIO pin and FX10A-168S-SV connector.
9. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: 2.0 PHY of USB The quantity of chip is 2, and two are all connected to PS, and USB PHY0 is configurable to host and is also configurable to equipment use, USB PHY1 can only be used as host, and 2.0 PHY chip of USB uses USB3320C.
10. a kind of unmanned aerial vehicle (UAV) control core buckle according to claim 1, it is characterised in that: the buckle is equipped with 2 10/100/1000Mbit network PHY chip, 1 is connected to the part PS by RGMII, and 1 is connected to the portion PL by RGMII Point, 10/100/1000Mbit network PHY chip adopts KSZ9031RNXIC.
CN201910304904.6A 2019-04-16 2019-04-16 A kind of unmanned aerial vehicle (UAV) control core buckle Pending CN110069030A (en)

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CN201910304904.6A CN110069030A (en) 2019-04-16 2019-04-16 A kind of unmanned aerial vehicle (UAV) control core buckle

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113093781A (en) * 2021-04-12 2021-07-09 广东汇天航空航天科技有限公司 Manned aircraft, data interface module and transmission method of flight control data

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Publication number Priority date Publication date Assignee Title
CN103870429A (en) * 2014-04-03 2014-06-18 清华大学 High-speed-signal processing board based on embedded GPU
CN107064960A (en) * 2017-03-28 2017-08-18 上海双微导航技术有限公司 A kind of GNSS satellite receiver baseband hardware platform circuit structure based on SOC frameworks
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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