CN219552900U

CN219552900U - BMC card and computer equipment

Info

Publication number: CN219552900U
Application number: CN202320253819.3U
Authority: CN
Inventors: 符兴建
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2023-02-10
Filing date: 2023-02-10
Publication date: 2023-08-18
Anticipated expiration: 2033-02-10

Abstract

The embodiment of the utility model provides a BMC card and computer equipment, and relates to the technical field of computers, wherein the BMC card comprises a circuit board and a processor; the processor is electrically connected with the circuit board; the processor is arranged on the circuit board and is electrically connected with the circuit board; the first surface of the circuit board is provided with a first golden finger, the second surface of the circuit board is provided with a second golden finger, and the first surface and the second surface are two surfaces opposite to each other. The pins in the first golden finger are electrically connected with the PCIE interface of the processor, and the adjacent pins at the edge part in the second golden finger are used for being electrically connected with a power supply. The PCIE pins and the power supply pins are distributed at the appointed positions, so that applicability of the BMC card on the same type of server platform can be guaranteed, use flexibility of the BMC card can be improved, and cost of remote management and control of the server is reduced.

Description

BMC card and computer equipment

Technical Field

The present utility model relates to the field of computer technologies, and in particular, to a BMC card and a computer device.

Background

In the computer industry, remote monitoring and operation of servers has become a more common functional configuration. One common way to implement this remote management function is to provide the server with a BMC (Baseboard Management Controller ) module, which is a small operating system independent of the server system, and has a standard RJ45 portal to the outside, and a firmware system with independent IP. Server clusters can typically use BMC instructions for large-scale unattended operations, including remote management, monitoring, installation, restarting, etc. of servers.

However, the existing BMC modules on the market are often designed for customizing a certain server, which is difficult to use on other servers built based on the same processor platform, and the application range of a single BMC module is limited, which results in the rise of hardware cost during the remote management operation of the server.

Disclosure of Invention

In view of the above problems, a BMC card and a computer device that overcome or at least partially solve the above problems are provided to solve the problem that the application range of a single BMC module is limited, resulting in an increase in hardware cost when a server remotely manages operations.

In order to solve the problems, in one aspect, the utility model discloses a BMC card, which comprises a circuit board and a processor;

the processor is arranged on the circuit board and is electrically connected with the circuit board;

the first surface of the circuit board is provided with a first golden finger, the second surface of the circuit board is provided with a second golden finger, and the first surface and the second surface are two surfaces opposite to each other;

and a plurality of pins in the first golden finger are electrically connected with the PCIE interface of the processor, and a plurality of adjacent pins at the edge part in the second golden finger are used for being electrically connected with a power supply.

Optionally, the first gold finger includes N pins sequentially arranged according to odd numbers, the second gold finger includes N pins sequentially arranged according to even numbers, and a direction of increasing the pin numbers in the first gold finger is the same as a direction of increasing the pin numbers of the second gold finger; wherein N is a natural number greater than 1.

Optionally, the remaining pins in the first golden finger and/or the second golden finger are respectively connected with a USB interface, a VGA interface, an LPC interface and an I of the processor ² And at least one interface of the C interface, the UART interface, the Ethernet interface, the PWM interface and the GPIO interface is electrically connected.

Optionally, the BMC card further comprises a reset chip and a delay circuit;

one signal input pin of the reset chip is electrically connected with one pin of the first golden finger or the second golden finger and is used for receiving a trigger signal from the outside of the BMC card;

the delay circuit is connected between the signal output pin of the reset chip and the signal input pin of the processor, and the signal output pin of the reset chip is also electrically connected with the other pin of the first golden finger or the second golden finger, and is used for transmitting response signals to the delay circuit and the outside of the BMC card.

Optionally, the BMC card further comprises a monitoring chip;

the monitoring chip is welded on the circuit board and is electrically connected with the circuit board, and the monitoring chip is electrically connected with the other signal input pin of the reset chip and is used for sending a trigger signal in the BMC card to the reset chip.

Optionally, the BMC card further includes at least one memory granule and at least one FLASH memory;

and the memory particles and the FLASH memory are electrically connected with the processor.

Optionally, the number of the FLASH memories is two;

the two FLASH memories are respectively and independently electrically connected with the processor through a group of SPI buses; or, one FLASH memory is electrically connected with the processor through two groups of SPI buses at the same time, wherein one group of SPI buses is also used for electrically connecting the other FLASH memory and the processor.

Optionally, the BMC card further includes a memory card socket;

the memory card holder is electrically connected with the processor and is used for inserting a memory card.

Optionally, the BMC card further includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip is electrically connected between a pin in the first gold finger or the second gold finger and a pin of the processor.

Optionally, the processor is detachably electrically connected to the circuit board.

On the other hand, the utility model also discloses computer equipment, which comprises any BMC card.

The embodiment of the utility model has the following advantages:

in the BMC card provided by the utility model, the pins in the first golden finger on the first surface of the circuit board are electrically connected with the PCIE interface of the processor, and the adjacent pins at the edge part in the second golden finger on the second surface of the circuit board are used for being electrically connected with a power supply.

Drawings

FIG. 1 is a simplified schematic diagram of a BMC card of the present utility model;

FIG. 2 is a schematic diagram of the pin distribution of the BMC card of the present utility model;

FIG. 3 is a simplified schematic diagram of another BMC card of the present utility model.

Detailed Description

In order that the above-recited objects, features and advantages of the present utility model will become more readily apparent, a more particular description of the utility model will be rendered by reference to the appended drawings and appended detailed description.

Referring to fig. 1, an embodiment of the present utility model provides a BMC card, which includes a circuit board 10 and a processor 11;

the processor 11 is disposed on the circuit board 10 and is electrically connected to the circuit board 10;

a first golden finger 101 is arranged on a first surface of the circuit board 10, a second golden finger 102 is arranged on a second surface of the circuit board, and the first surface and the second surface are two surfaces opposite to each other;

the pins in the first golden finger 101 are electrically connected with the PCIE interface of the processor 11, and the adjacent pins at the edge part in the second golden finger 102 are electrically connected with a power supply.

Specifically, as shown in fig. 1, in the BMC card of the embodiment of the present utility model, the processor 11 may be soldered to the circuit board 10 for electrical connection, or may be detachably mounted and fixed on the circuit board 10 through a processor base for electrical connection. Fig. 2 also shows a schematic diagram of the pin distribution of two surface gold fingers on the circuit board 10 according to the embodiment of the present utility model, and it can be seen that, in fig. 2, the left side of the circuit board 10 is a first surface provided with a first gold finger 101, and the right side of the circuit board 10 is a second surface provided with a second gold finger 102.

On the circuit board 10 illustrated in fig. 1, considering the common points of the server platforms of the same type, according to the pin arrangement definition of the BMC slots on the motherboard used by the server platforms, the pins of the BMC card correspondingly designed and defined together with the pin arrangement definition, part of the pins of the first golden finger 101 are electrically connected with the PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus) interface of the processor 11, so as to meet the high-speed transmission requirement of command data required by remote control between the BMC card and the server motherboard. And reserving a plurality of continuous pins at the edge part of the second golden finger 102 on the other side as power supply pins for being electrically connected with a power supply on the server main board, wherein the power supply can be determined according to the suitability of specific use conditions and is required by the basic work of the BMC card. The power supply may be, for example, a 3.3V power supply on a server motherboard. The concentrated arrangement of the power pins at the edge of the second gold finger 102 also helps to avoid interference of the power pins with other signal pins caused by the spaced-apart central penetration of the power pins.

In the BMC card provided by the utility model, the pins in the first golden finger on the first surface of the circuit board are electrically connected with the PCIE interface of the processor, and the adjacent pins at the edge part in the second golden finger on the second surface of the circuit board are used for being electrically connected with the power supply.

Optionally, referring to fig. 2, the first gold finger 101 includes N pins sequentially arranged according to an odd number, the second gold finger 102 includes N pins sequentially arranged according to an even number, and a direction in which the pin number in the first gold finger 101 is incremented is the same as a direction in which the pin number of the second gold finger 102 is incremented. Wherein N is a natural number greater than 1.

Specifically, in one embodiment, the number of pins in the first gold finger 101 of the BMC card in the embodiment of the present utility model may be the same as the number of pins in the second gold finger 102, and may be 2N in total, and numbering is performed from 1 to 2N, where N pins with sequentially increasing odd numbers may be set in the first gold finger 101, and N pins with sequentially increasing even numbers may be set in the second gold finger 102. This same pin count design may reuse the area of the surface of the circuit board 10 to design pins for more signal transmission.

Optionally, in the BMC card of the embodiment of the present utility model, the structure of the BMC card may be designed with reference to the specifications of a DDR4 (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory, fourth generation Double-rate synchronous dynamic random access memory) sodim (Small Outline Dual In-line Memory Module, small-sized dual in-line memory module) so as to match with the DDR4 sodim slot, thereby improving the standardization degree of the BMC card to further reduce the development cost.

Optionally, the dimensions of the circuit board 10 match those of the socket on the server motherboard. Illustratively, the circuit board 10 may be 69.6mm by 44.8mm in size and 1.2mm in thickness.

In addition, when the pin number of the slot on the server motherboard is 260, the pin number of the BMC card can be designed to be 260 in a matching way. As shown in fig. 2, the first gold finger 101 is 130 pins with odd numbers, the second gold finger 102 is 130 pins with even numbers, the odd numbers of the pins in the first gold finger 101 are sequentially increased from 1 to 259, and the even numbers of the pins in the second gold finger 102 are sequentially increased from 2 to 260 along the direction from top to bottom.

The 189 # pin, the 191 # pin, the 195 # pin and the 197 # pin in the first golden finger 101 are electrically connected with the PCIE interface of the processor 11, and the 242 # pin to the 260 # pin in the second golden finger 102 on the other surface are reserved as power supply pins for being electrically connected with a 3.3V power supply.

In addition, it should be noted that, the designated pin serial numbers are merely to indicate the positions of the pins corresponding to the signal functions in the gold finger area, and those skilled in the art can design the pins with the same functions at the same positions and use other numbers without performing any inventive work.

Optionally, in an embodiment, in addition to the above connection, the remaining pins of the first gold finger 101 and/or the second gold finger 102 may be connected to pins with corresponding functions of the processor 11 according to the requirement of the usage function. Illustratively, the remaining pins of the first golden finger 101 and/or the second golden finger 102 are connected with a USB (Universal Serial Bus ) interface, a VGA (Video Graphics Array, video graphics array) interface, an LPC (Low Pin Count) interface, an I ² At least one interface selected from the group consisting of a C (Inter-Integrated Circuit, serial bus) interface, UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter) interface, ethernet interface, PWM (Pulse Width Modulation ) interface, and GPIO (General Purpose Input Output, universal input output) interface is electrically connected.

For example, the above USB interface is connected to pins in the golden finger, the BMC card may be used as a slave device mounted on a server motherboard, and the server motherboard may pass through a USB protocolAnd accessing the data on one side of the BMC card, wherein the BMC card can also transmit the data to the server main board through a USB protocol. Because the VGA interface is an interface related to the display function, after the VGA interface is connected with the pins in the golden finger, the management control of the display equipment connected to one side of the server can be realized by utilizing the remote control function of the BMC card. The LPC interface is a new interface formulated to replace the slower ISA (Instruction Set Architecture ) bus, so that the LPC interface is compatible with the hardware conventionally communicating using the ISA protocol and has a higher rate. I ² The C interface can be used for the BMC card to collect the analog quantities such as the temperature of the processor and the rotating speed of the fan from one side of the server main board so as to carry out remote control after the BMC card analyzes. The UART interface can realize full duplex transmission and receiving, and can be used for two-way communication with the server main board, namely, the BMC card and the server main board can simultaneously transmit and receive data. The ethernet interface may specifically be a GMAC (Gigabyte Media Access Control, gigabit network media access control) interface for implementing high-speed network communication of the BMC card. The PWM interface can be used for controlling devices such as fans connected to one side of the server main board according to the instruction of the BMC card. In addition, a plurality of remaining pins can be connected with the GPIO interface of the processor 11 to perform more data transmission, so as to meet the requirements of more remote control functions, and it is required to be explained that the data transmitted through the GPIO interface is executed according to a protocol complied with by the corresponding function, which is not repeated here.

Referring to the following table, examples of signal definitions for partially numbered pins in embodiments of the present utility model are given:

the above table omits the representation of part of the pin numbers and their signal definitions, which means that the pins omitted from the representation can be designed for connection based on actual functions, for example, they can be suspended or set as the ground pin GND, which is not limited in the embodiment of the present utility model.

As an example of the above table, pins 96, 98, 100, 102, 104, and 106 in the second gold finger 102 may be electrically connected to the GPIO interface of the processor 11, pins 147, 149, 159, 163, and 167 in the first gold finger 101 may be electrically connected to the VGA interface of the processor 11, and pins 171, 173, 177, and 179 in the first gold finger 101 may be electrically connected to the USB interface of the processor 11, and pins 122, 124 in the second gold finger 102 may be electrically connected to the UART interface of the processor 11. Pins 180, 182, 186, 188, 190, 192, 196, 198, 202, 204, 205, 206, 207, 208, 211, 212, 213, 214, 215, 217, 221, 223, 227, 229, 231, 233, 237, 239 and 243 of the second gold finger 102 may be electrically connected to the GMAC interface of the processor 11. In connection with the above table example, it is readily understood that each numbered pin is electrically connected to each signal line in the corresponding functional interface. The connection of more pins to the processor interface is not illustrated here.

Optionally, referring to fig. 3, the BMC card further includes a reset chip 12 and a delay circuit 13;

a signal input pin of the reset chip 12 is electrically connected with one pin of the first gold finger 101 or the second gold finger 102, and is used for receiving a trigger signal from the outside of the BMC card;

the delay circuit 13 is connected between the signal output pin of the reset chip 12 and the signal input pin of the processor 10, and the signal output pin of the reset chip 12 is further electrically connected to the other pin of the first gold finger 101 or the second gold finger 102, so as to transmit a response signal to the delay circuit 13 and the BMC card.

Specifically, in one implementation, as illustrated in fig. 3, the BMC card of the embodiment of the present utility model may further include a reset chip 12 and a delay circuit 13. One signal input pin of the reset chip 12 is electrically connected with one pin of the first gold finger 101 or the second gold finger 102, and the pin is used as a pin for triggering the reset chip 12 to generate a reset signal. After the BMC card is connected with the slot on the server motherboard, the pin can receive a trigger signal sent by the server motherboard outside the BMC card. After the reset chip 12 receives the trigger signal, a response signal may be generated, where the response signal is divided into two paths, one path of response signal is transmitted to the other one of the first golden finger 101 or the second golden finger 102 through the signal output pin, and the other one of the response signal is used as a signal feedback pin on the BMC card, and the other path of response signal may be transmitted to the server motherboard in a feedback manner, so as to inform the server that the BMC card will enter a reset state, and meanwhile, the other path of response signal enters the delay circuit 13, delays and waits for a preset period of time, and then sends the other path of response signal to the processor 10 to execute a reset function. In the preset time, the server side can have enough preparation time to disconnect the communication between the server main board and the BMC card from the software layer, so that the system stability can be improved. For example, any two idle pins electrically connected to the GPIO interface of the processor 11 in the 96 pin, the 98 pin, the 100 pin, the 102 pin, the 104 pin and the 106 pin of the second gold finger 102 may be used, and accordingly, the reset chip 12 and the delay circuit 13 may be connected between the GPIO interface of the processor 11 and the corresponding pins.

Optionally, referring to fig. 3, the BMC card further includes a monitor chip 14; the monitoring chip 14 is soldered on the circuit board 10 and electrically connected to the circuit board 10, and the monitoring chip 14 is electrically connected to another signal input pin of the reset chip 12, and is configured to send a trigger signal inside the BMC card to the reset chip 12.

Specifically, in one implementation manner, as shown in fig. 3, the BMC card of the embodiment of the present utility model may further include a monitoring chip 14, where the monitoring chip 14 may monitor the BMC card itself, and send a trigger signal inside the BMC card to the reset chip 12 according to the working state of the BMC card. It will be appreciated that a chip with built-in watchdog circuit may be used as the monitor chip 14 to automatically reset periodically.

Optionally, referring to fig. 3, the BMC card further includes at least one memory granule 15 and at least one FLASH memory 16;

the memory granule 15 and the FLASH memory 16 are electrically connected to the processor 10.

Specifically, in one implementation, as illustrated in fig. 3, the BMC card of the embodiment of the present utility model may further include at least one memory granule 15 and at least one FLASH memory 16. It can be understood that the above-mentioned BMC card is also a system independent of the server system, and the system can use the storage space inside the processor 10, and also can connect the memory granule 15 and the FLASH memory 16 at the periphery, so as to achieve the improvement of the remote control function of the BMC card and ensure the stability.

It is understood that the memory granule 15 may be DDR3 (Double-Data-Rate Third Generation Synchronous Dynamic Random Access Memory, third generation Double-rate synchronous dynamic random access memory), DDR4 (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory, fourth generation Double-rate synchronous dynamic random access memory) or the latest memory product supported by the processor 10. FLASH memory 16 may also be selected from the latest storage products supported by processor 10 for storing program code or for direct use as a hard disk.

Optionally, referring to fig. 3, the FLASH memories 16 are two;

each of the two FLASH memories 16 is electrically connected to the processor 10 independently by a set of SPI (Serial Peripheral Interface ) buses; or, one of the FLASH memories 16 is electrically connected to the processor 10 through two sets of SPI buses at the same time, wherein one set of SPI buses is also used to electrically connect the other FLASH memory 16 to the processor 10.

Specifically, in one embodiment, as illustrated in fig. 3, when the number of FLASH memories 16 is two, the two FLASH memories 16 are redundant backups, so that data security can be improved. Alternatively, the two FLASH memories 16 may be electrically connected to the processor 10 independently through a set of SPI buses, and the processor 10 reads data from the FLASH memories 16 through the two sets of SPI buses, respectively. One FLASH memory 16 may be electrically connected to the processor 10 through two sets of SPI buses at the same time, and the remaining set of SPI buses may be connected between the other FLASH memory 16 and the processor 10, thereby improving data access efficiency.

Optionally, referring to fig. 3, the BMC card further includes a memory card holder 17;

the memory card holder 17 is electrically connected to the processor 10, and the memory card holder 17 is used for inserting a memory card.

Specifically, in one implementation, as shown in fig. 3, the BMC card of the embodiment of the present utility model further includes a memory card holder 17, where the memory card holder 17 may be a holder according to a type of a memory card used, for example, when the memory card used is an SD card, the memory card holder 17 is a holder of an SD card size, and when the memory card used is a Micro SD card, the memory card holder 17 is a holder of a Micro SD card size. Therefore, the transmission and transfer of data on the BMC card and other devices are facilitated while the storage space is expanded.

Optionally, referring to fig. 3, the BMC card further includes an analog-to-digital conversion chip 18, and the analog-to-digital conversion chip 18 is electrically connected between a pin of the first gold finger 101 or the second gold finger 102 and a pin of the processor 10.

Concretely, an implementationIn this way, as shown in fig. 3, the foregoing BMC card may further include an analog-to-digital conversion chip 18, where the analog-to-digital conversion chip 18 is electrically connected between the pins of the first gold finger 101 or the second gold finger 102 and the pins of the processor 10, and the analog-to-digital conversion chip 18 may convert the analog signal from the server motherboard into a digital signal recognizable by the BMC card. For example, after the analog signals such as the temperature of the processor, the fan speed, etc. on the server are transmitted to the analog-to-digital conversion chip 18 through the pins of the first or second golden finger 101 or 102, the analog-to-digital conversion chip 18 can convert the analog signals into I-compliant signals ² Digital signals of the C (Inter-Integrated Circuit, serial bus) protocol and pass I on the processor 10 ² The C interface is transmitted to the processor 10 for analysis and processing, and the BMC card is used for remotely monitoring the working state of the server.

Optionally, the processor 10 is detachably electrically connected to the circuit board 10.

In particular, in one embodiment, when the processor 10 is connected to the base for detachably and electrically connecting the processor 10 and the circuit board 10, the convenience of upgrading the processor 10 is also facilitated, the processor 10 does not need to be detached from the circuit board 10, or the BMC card is replaced entirely, and the upgrading cost is lower.

The utility model also discloses a computer device, which comprises any BMC card.

It can be understood that the computer device of the embodiment of the present utility model may include a server used by a data center and any of the foregoing BMC cards, and the remote management function of the server may be implemented by plugging the BMC card into a slot of a server motherboard. Of course, based on the foregoing design concept, for similar servers of the same platform, the BMC card has better compatibility and can be widely used.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The foregoing has outlined rather broadly the more detailed description of the utility model in order that the detailed description of the principles and embodiments of the utility model may be better understood, and in order that the present utility model may be better understood; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present utility model, the present description should not be construed as limiting the present utility model in view of the above.

Claims

1. The BMC card is characterized by comprising a circuit board and a processor;

2. The BMC card of claim 1, wherein the first gold finger comprises N pins arranged in sequence according to an odd number, the second gold finger comprises N pins arranged in sequence according to an even number, and a direction in which the pin number in the first gold finger increases is the same as a direction in which the pin number of the second gold finger increases, wherein N is a natural number greater than 1.

3. The BMC card of claim 1, wherein remaining pins in the first golden finger and/or the second golden finger are further respectively connected with a USB interface, a VGA interface, an LPC interface, an I of the processor ² And at least one interface of the C interface, the UART interface, the Ethernet interface, the PWM interface and the GPIO interface is electrically connected.

4. The BMC card of claim 1, further comprising a reset chip and a delay circuit;

5. The BMC card of claim 4, further comprising a monitor chip;

6. The BMC card of claim 1, further comprising at least one memory granule and at least one FLASH memory;

7. The BMC card of claim 6, wherein the FLASH memory is two;

8. The BMC card of any of claims 1 to 7, wherein the BMC card further comprises a memory card socket;

9. The BMC card of any of claims 1-7, further comprising an analog to digital conversion chip electrically connected between a pin in the first gold finger or the second gold finger and a pin of the processor.

10. The BMC card of any of claims 1 to 7, wherein the processor is removably electrically connected to the circuit board.

11. A computer device comprising the BMC card of any of claims 1 to 10.