CN108959158A - A kind of processor plate based on Whitley platform - Google Patents
A kind of processor plate based on Whitley platform Download PDFInfo
- Publication number
- CN108959158A CN108959158A CN201810717608.4A CN201810717608A CN108959158A CN 108959158 A CN108959158 A CN 108959158A CN 201810717608 A CN201810717608 A CN 201810717608A CN 108959158 A CN108959158 A CN 108959158A
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- cpu
- signal
- processor plate
- processor
- pcie
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
Abstract
This application discloses a kind of processor plate based on Whitley platform, which mainly includes being interconnected between CPU0 and CPU1 two CPU, two CPU by UPI signal, and two CPU pass through UPI signal respectively and connect with System Backplane；CPU0 is interconnected by the DMI signal of X4 and the UPLINK PCIE signal of X8 via System Backplane and PCH；The PCIE signal that two CPU pass through X16 respectively is connect via System Backplane with I O board；Two CPU are also interconnected by the PCIE signal of X16 and hard disk backboard respectively；CPU0 is by the OCP3.0 connector of the PCIE signal connection management plate of X16, and management board is for outband management and in-band management；The PCIE signal that CPU0 also passes through X8 is connect with RAID card.The modularization that can be realized processor design by the processor plate in the application is conducive to adapt to flexible project demands, reduces research and development cost, saves time of product development.
Description
Technical field
This application involves server system design fields, more particularly to a kind of processing based on Whitley platform
Device plate.
Background technique
With the development of computer technology, Intel is proposed new server platform Whitley, Whitley platform and needs
The upgrading of CPU architecture, the upgrading in terms of the upgrading of CPU architecture generally includes memory and in terms of IO.With in Whitley platform
How the upgrading of CPU architecture rationally designs the structure of processor main board, to promote the memory of server in server system
Ability and I/O transfer ability are a major issues.
In current processor main board structure, computing module, PCH (Platform are generally included in a processor main board
Controller Hub, platform courses), CPLD (patrol by Complex Programmable Logic Device, complex programmable
Volume device), multiple moulds such as BMC (Baseboard Management Controller, basic management controller) and network
Block.According to specific project demands, is designed by the structure to entire processor main board, makes coordinate operation between modules,
The multiple functions such as stable transmission, the monitoring of data operation, each component to realize signal.
However, in current processor main board structure, since computing module, PCH, CPLD, BMC and network etc. is multiple
Block combiner designs in one piece of processor main board, when project demands change, needs to change entire processor main board
Design, in particular it is required that reappraising the SI (Signal Integrity, signal integrity) of signal in plate, power supply and hard
The schemes such as part design, investment man power and material re-start principle diagram design, PCB (Printed Circuit Board, printing
Circuit board) design, material procurement and board re-pack the processes such as validation test.Therefore, the commonality ratio of processor main board at present
It is poor, it is not easy to the upgrading of server system and the update of product.
Summary of the invention
This application provides a kind of processor plates based on Whitley platform, to solve processor master in the prior art
The problem of plate commonality difference.
In order to solve the above-mentioned technical problem, the embodiment of the present application discloses following technical solution:
A kind of processor plate based on Whitley platform, be applied to server in, the processor plate include: CPU0 and
It is interconnected between CPU1 two CPU, two CPU by UPI signal, and two CPU pass through UPI signal respectively and System Backplane connects
It connects；
CPU0 passes through the DMI signal of X4 and UPLINK PCIE (the peripheral component of X8
Interconnect express, high speed serialization computer expansion bus standard) signal interconnects via System Backplane and PCH；
The PCIE signal that two CPU pass through X16 respectively is connect via System Backplane with I O board；
Two CPU are also interconnected by the PCIE signal of X16 and hard disk backboard respectively；
OCP (Open Compute Project, the open meter that the CPU0 passes through the PCIE signal connection management plate of X16
Calculation project) 3.0 connectors, the management board is for outband management and in-band management；
The PCIE signal that the CPU0 also passes through X8 is connect with RAID card.
Optionally, PCIE signal terminal connected to it matches.
Optionally, the PCIE signal connecting with the I O board meets 4.0 standard of PCIE.
Optionally, the server includes two-way server or four road servers based on Whitley platform.
Optionally, when the server is the two-way server based on Whitley platform, include in the server
One processor plate.
Optionally, when the server is the two-way server based on Whitley platform, CPU0 and CPU1 share three groups
The PCIE signal and hard disk backboard of X16 interconnects.
Optionally, when the server is the four road server based on Whitley platform, include in the server
Two processor plates pass through System Backplane between two processor plates and connect.
Optionally, when the server is the four road server based on Whitley platform, four CPU share six groups of X16
PCIE signal and hard disk backboard interconnect.
Optionally, each CPU maximum supports 16 DIMM (Dual-Inline- in 8 channels in the processor plate
Memory-Modules, dual inline memory module, a kind of memory bar).
Optionally, the memory slot in each CPU is SMT memory slot.
The technical solution that embodiments herein provides can include the following benefits:
The application provides a kind of processor plate based on Whitley platform, the processor plate can be used for two-way server and
In four road servers.The processor plate mainly includes two CPU, is interconnected between two CPU by UPI signal, and two CPU points
Not Tong Guo UPI signal connect with System Backplane.The processor plate passes through PCIE signal and DMI signal respectively and external board is mutual
Connection also by the OCP3.0 connector of PCIE signal connection management plate, therefore is inserted into different OCP cards, to realize and be
The flexible configuration of system network.The PCIE signal that CPU0 in the processor also passes through X8 is connect with RAID card, is connected by RAID card
Hard disk is connect to realize store function.The application is by computing module from the processor main board of the multiple functions of modules of original synthesis
It separates, the special processor plate based on Whitley platform is set, realize the modularization of processor design, and at this
The signal connection device of setting and other boards on device plate is managed, so that the processor plate is mainly responsible for computing function, when project needs
It asks when changing, processor plate accordingly can be upgraded in time, and can be flexible by the processor plate and other boards
Combination, therefore, current processor plate commonality is stronger, is conducive to the upgrading of server system and the update of product.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The application can be limited.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without creative efforts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of the processor plate based on Whitley platform provided by the embodiment of the present application.
Specific embodiment
In order to make those skilled in the art better understand the technical solutions in the application, below in conjunction with the application reality
The attached drawing in example is applied, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described implementation
Example is merely a part but not all of the embodiments of the present application.Based on the embodiment in the application, this field is common
The application protection all should belong in technical staff's every other embodiment obtained without making creative work
Range.
The application in order to better understand explains in detail presently filed embodiment with reference to the accompanying drawing.
Referring to Fig. 1, Fig. 1 is a kind of structure of the processor plate based on Whitley platform provided by the embodiment of the present application
Schematic diagram.As shown in Figure 1, processor plate provided by the present embodiment mainly includes two CPU:CPU0 and CPU1, wherein CPU0
For host CPU, interconnected between two CPU by UPI signal, and two CPU pass through UPI signal respectively and connect with System Backplane.This
SYS BP in embodiment in System Backplane, that is, Fig. 1 is not provided with any chip on System Backplane, for realizing in server system
Signal connection between each board.
With continued reference to Fig. 1 it is found that CPU0 is carried on the back by the DMI signal of X4 and the UPLINK PCIE signal of X8 via system
Plate and PCH are interconnected.The PCIE signal that two CPU pass through X16 respectively is connect via System Backplane with I O board；Two CPU also distinguish
It is interconnected by the PCIE signal and hard disk backboard of X16, HDD (Hard Disk Drive, hard disk drive) BP in Fig. 1 is hard
Disk backboard is provided with hard disk connector, the power regulator VR of hard disk, logic control chip etc. on hard disk backboard, for connecting
Hard disk.
CPU0 is by the OCP3.0 connector of the PCIE signal connection management plate of X16, and management board is for outband management and band
Interior management, the management board in the present embodiment is for the management to all IO in entire server system, including BMC, CPLD etc..This
CUP0 passes through the OCP3.0 connector of the PCIE signal connection management plate of X16 in embodiment, by being inserted into OCP3.0 connector
Different OCP cards can be realized the flexible configuration of grid, that is, is arranged by this connection relationship of CPU0, can make
Processor plate is connected to network interface card, to pass through network and external realization information exchange.
The PCIE signal that CPU0 also passes through X8 in the present embodiment is connect with RAID card, can be realized by RAID connection hard disk
The store function of processor plate.Moreover, passing through the connection of CPU0 and RAID card, it is wired to hard disk backboard using RAID card, it can
It realizes that NVME hard disk and SAS hard disk are compatible, is conducive to the commonality for improving processor plate and the flexibility of configuration.
In conclusion the processor plate can realize the interconnection with external board by PCIE signal and DMI signal.Its
In, to ensure that processor plate and external high-speed communication interconnect, PCIE signal terminal connected to it matches, that is, PCIE
The levels of the standard of signal are determined by the terminal that it is connected.
Specifically, the PCIE signal connecting with I O board meets 4.0 standard of PCIE, and two CPU pass through the PCIE of X16 respectively
Signal is connected to I O board via System Backplane, which follows the principle of PCIE4.0, can make the slot position maximum rate branch of I O board
Hold the signal of PCIE4.0, while can also the standards such as backward compatible PCIE3.0/2.0/1.0.With the PCIE of hard disk backboard interconnection
Signal is 3.0 signal of PCIE, and the PCIE signal for the X16 connecting with OCP3.0 connector is PCIE4.0 signal, is connected with RAID card
The PCIE signal of the X8 connect is 3.0 signal of PCIE.
Processor plate in the application can be used for two-way server or four road servers based on Whitley platform.Work as place
It include a processor plate in two-way server, it may be assumed that the processor device of two-way server when managing device plate applied to two-way server
Include two CPU:CPU0 and CPU1 on plate, is interconnected between two CPU by UPI signal.When processor plate takes applied to four tunnels
When business device, includes upper and lower two processor plates in four road servers, pass through System Backplane between two processor plates and connect.At this time
Totally 4 CPU:CPU0, CPU1, CPU2 and CPU3, every two CPU constitute one group and every two CPU and are set in four road servers
On one processor plate.It is connected between two groups of CPU by System Backplane, it is mutual by UPI signal between two CPU in every group
Connection.
When processor plate is applied in two-way server, CPU0 and CPU1 share the PCIE signal and hard disk of three groups of X16
Backboard interconnection, the signal of each PCIe 3.0*16 can connect 4 NVMe hard disks, therefore, in two-way server, pass through this Shen
Please in processor plate, 12 NVMe hard disks can be connected, that is, 12 NVMe hard disks can be being supported in 2U height.Work as processing
When device plate is applied in four road servers, four CPU share the PCIE signal of six groups of X16 and hard disk backboard interconnects, and take on four tunnels
It is engaged in device, by the way that two processor plates are arranged, 24 NVMe hard disks can be connected, that is, can support 24 NVMe in 4U height
Hard disk.This structure design of processor plate, can make full use of the characteristic distributions of PCIE inside CPU, significantly in the present embodiment
The track lengths for reducing PCIE signal, are conducive to the quality of promotion signal.
Each CPU maximum supports 16 DIMM in 8 channels in processor plate in the present embodiment, can by memory speed from
2933MT/s is promoted to 3200MT/s, compared to the memory rate that previous generation platform Purley platform is able to ascend 30%.
To realize that the structure of 16 DIMM in 8 channels designs, the present embodiment situation constant in the plate width of processor plate
Under, the spacing of spacing and memory slot to CPU between memory slot is all reduced.The spacing and memory slot of memory slot arrive
The distance of CPU is arranged, as long as can meet the cabling specification of Intel memory, and can accommodate 16 DIMM in 8 channels i.e.
It can.Such as: the spacing between memory slot is reduced to 310mil from 370mil, and the minimum spacing of memory slot to CPU subtracts from 880mil
As low as 580mil.
Further, the CPU in the present embodiment processor plate, memory slot are SMT memory slot, memory slot, that is, Memory linkage
Device.That is, the memory slot in the present embodiment in CPU is made of SMT technique, the matter of signal transmission can be greatly promoted
Amount.
In conclusion the processor plate based on Whitley platform in the application, constitutes individually processing by two CPU
Device module separates computing module from the processor main board of the multiple functions of modules of original synthesis, realizes that processor is set
The modularization of meter, so that the processor plate is mainly responsible for computing function.And processor plate is realized by PCIE signal and DMI signal
It is interconnected with external board, processor plate and external network is also realized by the OCP3.0 connector of PCIE signal connection management plate
Connection.This modular structure design, when project demands change, in time can accordingly rise processor plate
Grade, and can be by the processor plate and other board flexible combinations, therefore, current processor plate commonality is stronger, is conducive to
The upgrading of server system and the update of product.And this modular structure design, due to can flexible adaptation it is different
Project demands advantageously reduce research and development cost, save time of product development.
The above is only the specific embodiment of the application, is made skilled artisans appreciate that or realizing this Shen
Please.Various modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of processor plate based on Whitley platform is applied in server, which is characterized in that the processor plate packet
It includes: being interconnected between CPU0 and CPU1 two CPU, two CPU by UPI signal, and two CPU pass through UPI signal respectively and are
Backboard of uniting connects；
CPU0 is interconnected by the DMI signal of X4 and the UPLINK PCIE signal of X8 via System Backplane and PCH；
The PCIE signal that two CPU pass through X16 respectively is connect via System Backplane with I O board；
Two CPU are also interconnected by the PCIE signal of X16 and hard disk backboard respectively；
The CPU0 is by the OCP3.0 connector of the PCIE signal connection management plate of X16, and the management board is for outband management
And in-band management；
The PCIE signal that the CPU0 also passes through X8 is connect with RAID card.
2. a kind of processor plate based on Whitley platform according to claim 1, which is characterized in that the PCIE letter
Number terminal connected to it matches.
3. a kind of processor plate based on Whitley platform according to claim 2, which is characterized in that with the I O board
The PCIE signal of connection meets 4.0 standard of PCIE.
4. a kind of processor plate based on Whitley platform according to claim 1, which is characterized in that the server
Including two-way server or four road servers based on Whitley platform.
5. a kind of processor plate based on Whitley platform according to claim 4, which is characterized in that when the service
It include the processor plate in the server when device is the two-way server based on Whitley platform.
6. a kind of processor plate based on Whitley platform according to claim 5, which is characterized in that when the service
When device is two-way server based on Whitley platform, CPU0 and CPU1 share three groups of X16 PCIE signal and hard disk backboard it is mutual
Connection.
7. a kind of processor plate based on Whitley platform according to claim 4, which is characterized in that when the service
It include that there are two the processor plates when device is the four road server based on Whitley platform, in the server, described in two
It is connected between processor plate by System Backplane.
8. a kind of processor plate based on Whitley platform according to claim 7, which is characterized in that when the service
When device is the four road server based on Whitley platform, four CPU share the PCIE signal of six groups of X16 and hard disk backboard interconnects.
9. any a kind of processor plate based on Whitley platform in -8 according to claim 1, which is characterized in that institute
State 16 DIMM that each CPU maximum in processor plate supports 8 channels.
10. a kind of processor plate based on Whitley platform according to claim 9, which is characterized in that in each CPU
Memory slot be SMT memory slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810717608.4A CN108959158A (en) | 2018-07-03 | 2018-07-03 | A kind of processor plate based on Whitley platform |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810717608.4A CN108959158A (en) | 2018-07-03 | 2018-07-03 | A kind of processor plate based on Whitley platform |
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| CN108959158A true CN108959158A (en) | 2018-12-07 |
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| CN201810717608.4A Pending CN108959158A (en) | 2018-07-03 | 2018-07-03 | A kind of processor plate based on Whitley platform |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10489341B1 (en) * | 2018-06-25 | 2019-11-26 | Quanta Computer Inc. | Flexible interconnect port connection |
| CN111090967A (en) * | 2019-11-29 | 2020-05-01 | 苏州浪潮智能科技有限公司 | PCB layout structure, PCB layout method, PCB wiring method and server mainboard |
| CN112765067A (en) * | 2020-12-31 | 2021-05-07 | 西安易朴通讯技术有限公司 | Hard disk backboard and mainboard assembling structure |
| RU211039U1 (en) * | 2021-07-01 | 2022-05-18 | Общество С Ограниченной Ответственностью "Эмзиор" | SERVER PLATFORM PERFORMED WITH THE POSSIBILITY OF DETECTING CONNECTION/DISCONNECTION OF NETWORK CARDS AND/OR SOLID STATE DRIVES AND IMPLEMENTED WITH NETWORK APPLIANCE FUNCTIONS |
| CN115904849A (en) * | 2023-01-09 | 2023-04-04 | 苏州浪潮智能科技有限公司 | PCIE link signal test method, system, computer equipment and medium |
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Application publication date: 20181207 |