CN108959158A - A kind of processor plate based on Whitley platform - Google Patents

Abstract

The application discloses a processor board based on the Whitley platform. The processor board mainly includes two CPUs, CPU0 and CPU1. The two CPUs are interconnected through UPI signals, and the two CPUs are respectively connected to the system backplane through UPI signals. ; CPU0 is connected to the PCH through the system backplane through the DMI signal of X4 and the UPLINK PCIE signal of X8; the two CPUs are respectively connected to the IO board through the PCIE signal of X16 through the system backplane; the two CPUs are also connected to the IO board through the PCIE signal of X16 Hard disk backplane interconnection; CPU0 is connected to the OCP3.0 connector of the management board through the PCIE signal of X16, and the management board is used for out-of-band management and in-band management; CPU0 is also connected to the RAID card through the PCIE signal of X8. The processor board in this application can realize the modularization of processor design, which is conducive to adapting to flexible project requirements, reducing research and development costs, and saving product development time.

Description

A Processor Board Based on Whitley Platform

technical field

The present application relates to the technical field of server system design, in particular to a processor board based on Whitley platform.

Background technique

With the development of computer technology, Intel has launched a new server platform, Whitley. The Whitley platform requires an upgrade of the CPU architecture. The upgrade of the CPU architecture usually includes the upgrade of memory and IO. With the upgrade of the CPU architecture in the Whitley platform, how to reasonably design the structure of the processor motherboard in the server system to improve the memory capacity and IO transmission capacity of the server is an important issue.

In the current processor motherboard structure, a processor motherboard usually includes a computing module, PCH (PlatformController Hub, platform control), CPLD (Complex Programmable Logic Device, complex programmable logic device), BMC (Baseboard Management Controller, basic management control device) and network and other modules. According to the specific project requirements, through the structural design of the entire processor motherboard, the various modules can be coordinated to operate, so as to realize the stable transmission of signals, data calculation, monitoring of various components and other functions.

However, in the current structure of the processor board, since multiple modules such as the computing module, PCH, CPLD, BMC, and network are combined and designed in one processor board, when the project requirements change, the design of the entire processor board needs to be changed , Specifically, it is necessary to re-evaluate the SI (Signal Integrity, signal integrity) of the signal on the board, power supply and hardware design, and invest manpower and material resources to re-design the schematic diagram and PCB (Printed Circuit Board, printed circuit board) design , material procurement and board card board verification test and other processes. Therefore, at present, the commonality of the mainboard of the processor is relatively poor, which is inconvenient for upgrading of the server system and updating of products.

Contents of the invention

The present application provides a processor board based on the Whitley platform to solve the problem of poor commonality of processor boards in the prior art.

In order to solve the above technical problems, the embodiment of the present application discloses the following technical solutions:

A processor board based on the Whitley platform is used in servers. The processor board includes two CPUs, CPU0 and CPU1. The two CPUs are interconnected through UPI signals, and the two CPUs communicate with the system back through UPI signals respectively. board connection;

CPU0 is interconnected with PCH through the system backplane through the DMI signal of X4 and the UPLINK PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) signal of X8;

The two CPUs are respectively connected to the IO board through the system backplane through the PCIE signal of X16;

The two CPUs are also interconnected with the hard disk backplane through the PCIE signal of X16;

The CPU0 is connected to the OCP (Open Compute Project, Open Compute Project) 3.0 connector of the management board through the PCIE signal of X16, and the management board is used for out-of-band management and in-band management;

The CPU0 is also connected to the RAID card through the PCIE signal of X8.

Optionally, the PCIE signal matches the terminal it is connected to.

Optionally, the PCIE signal connected to the IO board conforms to the PCIE 4.0 standard.

Optionally, the server includes a two-way server or a four-way server based on the Whitley platform.

Optionally, when the server is a two-socket server based on the Whitley platform, the server includes one processor board.

Optionally, when the server is a two-way server based on the Whitley platform, CPU0 and CPU1 have three sets of X16 PCIE signals interconnected with the hard disk backplane.

Optionally, when the server is a four-socket server based on the Whitley platform, the server includes two processor boards, and the two processor boards are connected through a system backplane.

Optionally, when the server is a four-way server based on the Whitley platform, the four CPUs have a total of six groups of X16 PCIE signals interconnected with the hard disk backplane.

Optionally, each CPU in the processor board supports a maximum of 16 DIMMs (Dual-Inline-Memory-Modules, Dual-Inline-Memory-Modules, a memory module) with 8 channels.

Optionally, the memory slots in each CPU are SMT memory slots.

The technical solutions provided by the embodiments of the present application may include the following beneficial effects:

The present application provides a processor board based on the Whitley platform, which can be used in two-way servers and four-way servers. The processor board mainly includes two CPUs, the two CPUs are interconnected through UPI signals, and the two CPUs are respectively connected to the system backplane through UPI signals. The processor board is connected to external boards through PCIE signals and DMI signals, and is also connected to the OCP3.0 connector of the management board through PCIE signals, so different OCP cards can be inserted to realize flexible configuration of the system network. The CPU0 in the processor is also connected to the RAID card through the PCIE signal of the X8, and is connected to the hard disk through the RAID card to realize the storage function. In this application, the computing module is separated from the original processor main board that integrates multiple module functions, and a special processor board based on the Whitley platform is set to realize the modularization of the processor design. The signal connection device of other boards makes the processor board mainly responsible for computing functions. When the project requirements change, the processor board can be upgraded in time, and the processor board can be flexibly combined with other boards. Therefore, , the current processor board has a strong commonality, which is conducive to the upgrade of the server system and the update of the product.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, In other words, other drawings can also be obtained from these drawings on the premise of not paying creative work.

FIG. 1 is a schematic structural diagram of a processor board based on a Whitley platform provided by an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described The embodiments are only some of the embodiments of the present application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

In order to better understand the present application, the implementation manner of the present application will be explained in detail below in conjunction with the accompanying drawings.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a processor board based on a Whitley platform provided by an embodiment of the present application. It can be seen from Fig. 1 that the processor board provided in this embodiment mainly includes two CPUs: CPU0 and CPU1, wherein CPU0 is the main CPU, and the two CPUs are interconnected through UPI signals, and the two CPUs communicate with the system through UPI signals respectively. backplane connection. In this embodiment, the system backplane is the SYS BP in FIG. 1 , and no chip is arranged on the system backplane, which is used to realize the signal connection between various boards in the server system.

Continuing to refer to FIG. 1, it can be seen that CPU0 is interconnected with the PCH through the system backplane through the DMI signal of X4 and the UPLINK PCIE signal of X8. The two CPUs are respectively connected to the IO board through the system backplane through the PCIE signal of X16; the two CPUs are also connected to the hard disk backplane through the PCIE signal of X16, and the HDD (Hard Disk Drive, hard disk drive) BP in Figure 1 is the hard disk The backplane, the hard disk backplane is provided with a hard disk connector, a power regulator VR of the hard disk, a logic control chip, etc., for connecting the hard disk.

CPU0 is connected to the OCP3.0 connector of the management board through the PCIE signal of X16. The management board is used for out-of-band management and in-band management. The management board in this embodiment is used for the management of all IOs in the entire server system, including BMC, CPLD, etc. In this embodiment, CPU0 is connected to the OCP3.0 connector of the management board through the PCIE signal of X16, and the flexible configuration of the system network can be realized by inserting different OCP cards into the OCP3.0 connector, that is, through the connection relationship setting of CPU0 , enabling the processor board to be connected to the network card, thereby realizing information exchange with the outside through the network.

In this embodiment, CPU0 is also connected to the RAID card through the PCIE signal of X8, and the storage function of the processor board can be realized by connecting the hard disk through the RAID. Moreover, through the connection between CPU0 and the RAID card, the RAID card is used to connect to the hard disk backplane, so that the NVME hard disk and the SAS hard disk can be compatible, which is conducive to improving the commonality of the processor board and the flexibility of configuration.

In summary, the processor board can be interconnected with external boards through PCIE signals and DMI signals. Among them, in order to ensure the high-speed communication interconnection between the processor board and the outside, the PCIE signal matches the terminal to which it is connected, that is, the standard level of the PCIE signal is determined by the terminal to which it is connected.

Specifically, the PCIE signal connected to the IO board conforms to the PCIE 4.0 standard, and the two CPUs are respectively connected to the IO board through the PCIE signal of X16 via the system backplane. The maximum rate supports PCIE4.0 signals, and it is also backward compatible with PCIE3.0/2.0/1.0 and other standards. The PCIE signal interconnected with the hard disk backplane is a PCIE 3.0 signal, the PCIE signal of the X16 connected to the OCP3.0 connector is a PCIE4.0 signal, and the PCIE signal of the X8 connected to the RAID card is a PCIE 3.0 signal.

The processor board in this application can be used in a two-socket server or a four-socket server based on the Whitley platform. When the processor board is applied to a two-way server, one processor board is included in the two-way server, that is, the processor board of the two-way server includes two CPUs: CPU0 and CPU1, and the two CPUs are interconnected through UPI signals . When the processor board is applied to a four-way server, the four-way server includes two processor boards, one upper and the lower, and the two processor boards are connected through a system backplane. At this time, the four-way server has four CPUs in total: CPU0, CPU1, CPU2, and CPU3. Every two CPUs form a group and every two CPUs are arranged on a processor board. The two groups of CPUs are connected through the system backplane, and the two CPUs in each group are interconnected through UPI signals.

When the processor board is used in a two-way server, CPU0 and CPU1 have three sets of X16 PCIE signals connected to the hard disk backplane, and each PCIe 3.0*16 signal can be connected to four NVMe hard disks. Therefore, in a two-way server , through the processor board in this application, 12 NVMe hard disks can be connected, that is, 12 NVMe hard disks can be supported within a 2U height. When the processor board is used in a four-way server, the four CPUs have a total of six sets of X16 PCIE signals connected to the hard disk backplane. In a four-way server, by setting two processor boards, 24 NVMe hard drives can be connected. That is, it can support 24 NVMe hard drives within 4U height. The structural design of the processor board in this embodiment can make full use of the distribution characteristics of PCIE inside the CPU, greatly reduce the routing length of PCIE signals, and help improve the quality of signals.

In this embodiment, each CPU in the processor board supports a maximum of 16 DIMMs with 8 channels, which can increase the memory rate from 2933MT/s to 3200MT/s, which can increase the storage rate by 30% compared with the previous generation platform Purley platform .

In order to realize the structural design of 16 DIMMs with 8 channels, in this embodiment, the distance between the memory slots and the distance between the memory slot and the CPU are both reduced while the board width of the processor board remains unchanged. The distance between the memory slots and the distance from the memory slot to the CPU can be set as long as it meets the wiring specification of Intel memory and can accommodate 16 DIMMs with 8 channels. For example: the distance between the memory slots is reduced from 370mil to 310mil, and the minimum distance between the memory slot and the CPU is reduced from 880mil to 580mil.

Further, the memory slot of the CPU in the processor board of this embodiment is an SMT memory slot, and the memory slot is a memory connector. That is to say, in this embodiment, the memory slot in the CPU is made by SMT technology, which can greatly improve the quality of signal transmission.

In summary, the processor board based on the Whitley platform in this application forms a separate processor module through two CPUs, and separates the computing module from the original processor board that integrates multiple module functions to realize the processor The modularity of the design makes this processor board mainly responsible for computing functions. The interconnection between the processor board and the external board is realized through the PCIE signal and the DMI signal, and the OCP3.0 connector of the management board is connected through the PCIE signal to realize the connection between the processor board and the external network. This modular structure design can upgrade the processor board in time when the project requirements change, and can flexibly combine the processor board with other boards. Therefore, the current processor board has strong commonality. , which is conducive to server system upgrades and product updates. Moreover, this modular structure design, because it can flexibly adapt to different project requirements, is conducive to reducing research and development costs and saving product development time.

The above descriptions are only specific implementation manners of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A processor board based on Whitley platform, applied in server, it is characterized in that, described processor board comprises: CPU0 and CPU1 two CPUs, interconnect by UPI signal between two CPUs, and two CPUs respectively Connect to the system backplane through UPI signal; CPU0 is interconnected with PCH through the system backplane through the DMI signal of X4 and the UPLINK PCIE signal of X8; The two CPUs are respectively connected to the IO board through the system backplane through the PCIE signal of X16; The two CPUs are also interconnected with the hard disk backplane through the PCIE signal of X16; The CPU0 is connected to the OCP3.0 connector of the management board through the PCIE signal of X16, and the management board is used for out-of-band management and in-band management; The CPU0 is also connected to the RAID card through the PCIE signal of X8. 2. a kind of processor board based on Whitley platform according to claim 1, is characterized in that, the terminal that described PCIE signal is connected with it matches. 3. a kind of processor board based on Whitley platform according to claim 2, is characterized in that, the PCIE signal that is connected with described IO board complies with PCIE 4.0 standard. 4 . The processor board based on the Whitley platform according to claim 1 , wherein the server comprises a two-way server or a four-way server based on the Whitley platform. 5 . The processor board based on the Whitley platform according to claim 4 , wherein when the server is a two-way server based on the Whitley platform, one processor board is included in the server. 6. a kind of processor board based on Whitley platform according to claim 5, it is characterized in that, when described server is two-way server based on Whitley platform, CPU0 and CPU1 have the PCIE signal and hard disk back of three groups of X16 altogether board interconnection. 7. A kind of processor board based on Whitley platform according to claim 4, it is characterized in that, when described server is based on the four-way server of Whitley platform, two described processor boards are included in the described server , the two processor boards are connected through a system backplane. 8. a kind of processor board based on Whitley platform according to claim 7, it is characterized in that, when described server is based on the four-way server of Whitley platform, four CPUs have the PCIE signal of six groups of X16 and hard disk back board interconnection. 9. The processor board based on the Whitley platform according to any one of claims 1-8, wherein each CPU in the processor board supports a maximum of 16 DIMMs with 8 channels. 10. The processor board based on Whitley platform according to claim 9, wherein the memory slot in each CPU is an SMT memory slot.