CN107247677B - Conversion device and electronic equipment - Google Patents
Conversion device and electronic equipment Download PDFInfo
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- CN107247677B CN107247677B CN201710376380.2A CN201710376380A CN107247677B CN 107247677 B CN107247677 B CN 107247677B CN 201710376380 A CN201710376380 A CN 201710376380A CN 107247677 B CN107247677 B CN 107247677B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/409—Mechanical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
Abstract
The present disclosure provides a conversion apparatus. The present disclosure also provides an electronic device including the conversion apparatus. The conversion device is used for converting a peripheral component interconnect standard PCI slot into a mezzanine local area network ML2 slot on a mainboard, and comprises the following components: the first interface comprises at least one first pin matched with the PCI slot; a second interface comprising at least one second pin that is the same as a pin in the ML2 socket; and the conversion unit is used for electrically connecting the first interface and the second interface and correspondingly converting the signal from the first interface into a signal matched with the second interface.
Description
Technical Field
The present disclosure relates to a conversion apparatus and an electronic device.
Background
The slot widely used on the server for connecting the external equipment is a Peripheral Component Interconnect (PCI) slot which can be connected with equipment with a PCI interface. However, the devices with interfaces of the mezzanine local area network ML2 on the mainboard are present in the market, and have higher signal interference resistance and stability than the PCI interface devices. Devices for the ML2 interface need to connect with the ML2 slot. Currently, only a few servers have ML2 slots themselves, and for servers without ML2 slots, the ML2 interface devices will not be used.
Disclosure of Invention
One aspect of the present disclosure provides a conversion apparatus for converting peripheral component interconnect standard PCI slots to mezzanine local area network ML2 slots on a motherboard. The conversion device comprises a first interface, a second interface and a conversion unit. The first interface comprises at least one first pin matched with the PCI slot. A second interface comprising at least one second pin identical to a pin in the ML2 socket. And the conversion unit is used for electrically connecting the first interface and the second interface and correspondingly converting the signal from the first interface into a signal matched with the second interface.
Optionally, the conversion unit includes a connection subunit, and connects the second pin with one or more corresponding first pins according to a signal transmitted by the second pin.
Optionally, the conversion unit further includes a reserved subunit, and for a second pin of the first interface, which does not have a corresponding first pin, the second pin is connected to an idle pin in the first interface.
Optionally, the connection subunit includes a signal transmission module, and connects each of the first group of second pins with the first pin, which has the same signal as the signal transmitted by the first group of second pins, in a one-to-one correspondence manner.
Optionally, the connection subunit includes a signal conversion module, and connects each of the second pins in the second group with one or more first pins that transmit different signals but have corresponding relationships with the second pins.
Optionally, the signal conversion module includes a signal processing sub-module and a transmission sub-module. And the signal processing submodule is used for processing the signals transmitted by the corresponding one or more first pins aiming at least one second pin in the second group of second pins to obtain the same signals transmitted by the at least one second pin. And the transmission submodule is used for transmitting the signals processed by the signal processing submodule to the at least one second pin.
Optionally, when the at least one second pin transmits a voltage signal, the signal processing sub-module processes the signal transmitted by the corresponding one or more first pins to obtain a signal with the same magnitude as the voltage signal. Optionally, when the at least one second pin transmits a clock signal, the signal processing sub-module processes a signal transmitted by the corresponding one or more first pins to obtain a signal with the same period as the clock signal. Optionally, the signal processing sub-module converts a signal transmitted by at least one first pin into a signal transmitted by a second pin with a different number from the at least one first pin.
Another aspect of the present disclosure provides an electronic device including the conversion apparatus as described above.
Drawings
For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 schematically illustrates an external view of a typical PCI slot and an ML2 slot;
FIG. 2 schematically illustrates a block diagram of a conversion apparatus according to an embodiment of the disclosure;
FIG. 3 schematically illustrates a block diagram of a conversion apparatus according to another embodiment of the present disclosure;
fig. 4 schematically shows a block diagram of a connection subunit in a conversion arrangement according to an embodiment of the present disclosure;
FIG. 5 schematically illustrates a block diagram of a conversion apparatus according to yet another embodiment of the present disclosure; and
fig. 6 schematically shows a block diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The words "a", "an" and "the" and the like as used herein are also intended to include the meanings of "a plurality" and "the" unless the context clearly dictates otherwise. Furthermore, the terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.
Some block diagrams are shown in the figures. It will be understood that some blocks of the block diagrams, or combinations thereof, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the instructions, which execute via the processor, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.
Accordingly, the techniques of this disclosure may be implemented in hardware and/or software (including firmware, microcode, etc.). In addition, the techniques of this disclosure may take the form of a computer program product on a computer-readable medium having instructions stored thereon for use by or in connection with an instruction execution system. In the context of this disclosure, a computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the instructions. For example, the computer readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Specific examples of the computer readable medium include: magnetic storage devices, such as magnetic tape or Hard Disk Drives (HDDs); optical storage devices, such as compact disks (CD-ROMs); a memory, such as a Random Access Memory (RAM) or a flash memory; and/or wired/wireless communication links.
Embodiments of the present disclosure provide a conversion apparatus and an electronic device having the same. The conversion device is used for converting the peripheral component interconnect standard PCI slots into the ML2 slots of the interlayer local area network on the mainboard. The conversion device specifically comprises a first interface, a second interface and a conversion unit. The first interface comprises at least one first pin matched with the PCI slot. The second interface includes at least one second pin that is identical to a pin in the ML2 socket. The conversion unit is used for electrically connecting the first interface and the second interface and correspondingly converting the signals from the first interface into signals matched with the second interface.
PCI in this disclosure is an abbreviation for Peripheral Component Interconnect, known in Chinese as the Peripheral Component Interconnect standard. PCI slots are slots that are widely used on current motherboards to connect to external devices.
ML2 is an abbreviation for Mezzanine Lan on Motherboard v2 in this disclosure, known in Chinese as Mezzanine LAN on Motherboard. The ML2 slot is also applied to the mainboard, and can be connected with an external device with an ML2 interface.
FIG. 1 schematically illustrates an external view of a typical PCI slot and an ML2 slot.
As shown in FIG. 1, both PCI slots and ML2 slot have pinjacks for connecting to interfaces having corresponding electronic devices. Corresponding pins are disposed within the pin receptacles.
As can be seen from fig. 1, the pin arrangement of the PCI slot and the ML2 slot are different because the protocols for transmitting signals are different.
In making the present invention, the inventors noted that there is some difference in the functionality of both PCI slots and ML2 slots, but there is also a greater similarity between the two.
In particular, the similarity between the PCI slot and the ML2 slot is mainly expressed in that the signals transmitted by all the pins of the PCI slot and the ML2 slot can be basically divided into three categories, namely clock signals, voltage signals and transmission signals. The transmission signal is a signal for transmitting a signal in the main board to an external device. Based on this similarity, clock signals, voltage signals, and transport signals from corresponding pins in the PCI slot may be coupled to corresponding pins of the ML2 slot, thereby enabling conversion of most of the signals from the PCI slot to signals matching the ML2 slot.
The distinction between PCI slots and ML2 slots is mainly made in the following two aspects.
In the first aspect, the pin arrangement of the two is different. The pin wiring in the PCI slot is formed by centralizing high-level pins and centralizing low-level pin wiring; and the pin wiring of high and low level in the ML2 slot is in a cross arrangement mode, and the mode can improve the anti-interference capability of signal transmission by utilizing the stability of transmission signals.
In a second aspect, a portion of the pins in the ML2 slot that carry signals are connected to a Baseboard Management Controller (BMC), which is not present in a PCI slot. The pin wiring of the ML2 slot can be connected with the BMC, so that the device connected with the ML2 slot has an NCSI (network Controller baseband interface) function, wherein the NCSI function is used for monitoring the network connection state.
Since there are no pins in the PCI slot to connect to the BMC, the converted ML2 slot from the PCI slot may lack NCSI functionality.
However, the NCSI function is only an attached BMC function, and the ML2 slot without the NCSI function does not affect the use of the ML2 interface connected with the device in most cases.
In addition, the function of the missing NCSI can be completed by the active setting of the mainboard. Specifically, the pins of the ML2 slot connected to the BMC may be connected to the idle pins of the PCI slot, and the idle pins may be connected to the corresponding locations of the BMC accordingly, wherein the idle pins are not connected to any signal source if they are not actively configured. In this way, the ML2 slot converted from the PCI slot is provided with NCSI functionality.
The conversion device provided by each embodiment of the present disclosure is based on the above idea, and is used to convert a peripheral component interconnect standard PCI slot into a mezzanine local area network ML2 slot on a motherboard, thereby extending the usage scenario of a device with an ML2 interface.
Fig. 2 schematically shows a block diagram of a conversion apparatus according to an embodiment of the present disclosure.
As shown in fig. 2, the conversion apparatus 200 according to the embodiment of the present disclosure includes a first interface 210, a second interface 220, and a conversion unit 230.
The first interface 210 includes at least one first pin that mates with a PCI slot.
The first interface 210 is configured to be connected to a PCI slot, such that at least one first pin of the first interface 210 is electrically connected to a corresponding pin of the PCI slot, so that signals transmitted by the pins of the PCI slot are correspondingly transmitted to the first interface 210.
A second interface 220 comprising at least one second pin identical to a pin in the ML2 socket.
At least one second pin in the second interface 220 is the same as a pin in the ML2 slot, so that a device having an ML2 interface can be connected to the second interface 220 to transmit signals transmitted by the second pin in the second interface 220 to the device.
The conversion unit 230 electrically connects the first interface 210 and the second interface 220, and is configured to correspondingly convert the signal from the first interface into a signal matched with the second interface.
According to the conversion apparatus 200 of the embodiment of the present disclosure, when the first interface 210 is connected to the PCI slot and the device having the ML2 interface is connected to the second interface, the signal transmitted by the corresponding pin in the PCI slot may be first transmitted to the first interface 210, then correspondingly transmitted to the second interface 220 through the conversion unit 230, and finally transmitted to the device having the ML2 interface, so that the device having the ML2 interface can operate.
In this way, the conversion apparatus 200 according to the embodiment of the present disclosure correspondingly converts the signal in the PCI slot into a signal matching the ML2 slot.
The conversion device 200 according to the embodiment of the disclosure enables a device with an ML2 interface to use a PCI slot widely used in a current motherboard, thereby extending the usage scenario of the device with an ML2 interface.
Fig. 3 schematically shows a block diagram of a conversion apparatus 300 according to another embodiment of the present disclosure.
The conversion apparatus 300 is one of the specific embodiments of the conversion apparatus 200 according to the embodiment of the present disclosure.
As shown in fig. 3, the conversion apparatus 300 includes a first interface 210, a second interface 220, and a conversion unit 230. Wherein the conversion unit 230 comprises a connection subunit 330.
Specifically, the connection subunit 330 connects the second pin of the second interface 220 to one or more corresponding first pins of the first interface 210 according to the signal transmitted by the second pin.
Fig. 4 schematically shows a block diagram of a connection subunit 330 in a conversion apparatus 300 according to an embodiment of the present disclosure.
As shown in fig. 4, the connection subunit 330 may include a signal transmission module 331 according to an embodiment of the present disclosure.
According to the embodiment of the disclosure, the signal transmission module 331 is configured to connect each of the first group of second pins with the first pin that has the same signal transmitted by the first group of second pins in a one-to-one correspondence manner.
According to the embodiment of the present disclosure, each of the first group of second pins has a first pin in the first interface 210 to transmit the same signal. The signal transmission module 331 connects each pin of the first group of second pins with the corresponding first pin according to the signal transmitted by the first group of second pins, thereby implementing the corresponding transmission of the signal from the first pin of the first interface 210 to the corresponding second pin of the second interface 220.
For example, when a signal transmitted by a certain pin in the first group of second pins in the second interface 220 is a voltage signal, if there is a first pin transmitting the same voltage signal in the first interface 210, the second pin is directly connected to the first pin.
Alternatively, when a signal transmitted by a certain pin of the first group of second pins in the second interface 220 is a clock signal with a specific period, if there is a first pin transmitting the same clock signal with the specific period in the first interface 210, the first pin is directly connected to the second pin.
Or, when the signals transmitted by a certain pin in the first group of second pins in the second interface 220 and a certain first pin in the first interface 210 both come from the same signal source, the second pin is directly connected to the first pin.
Similar situations are not sufficient, and are not described in detail here.
According to the embodiment of the present disclosure, the connection subunit 330 may implement transmission of signals from the first pin in the first interface 210 to the first group of second pins in the second interface 220 with a corresponding relationship, so as to facilitate wiring layout.
According to an embodiment of the present disclosure, the connection subunit 330 may also include a signal conversion module 332 for connecting each pin of the second group of second pins with one or more first pins that transmit different signals but have corresponding relationships therewith.
According to the embodiment of the present disclosure, for each pin in the second group of second pins, although there is not one first pin identical to the signal transmitted thereto in the first interface 210, there are one or more first pins that can convert the transmitted signal accordingly. By processing and converting the signals transmitted by the one or more first pins, the signals transmitted by each of the second pins in the second group can be correspondingly obtained. In this case, each of the second group of second pins may be correspondingly connected to the one or more first pins.
According to the embodiment of the present disclosure, the connection subunit 330 may also connect one or more first pins of the first interface 210 and the second interface 220, which may perform signal conversion, with each pin of the second group of second pins, thereby greatly expanding the capability of transmitting signals from the first interface 210 to the second interface 220, so that signals in the PCI slot may be correspondingly transmitted to the ML2 slot as much as possible. In this way, on the one hand, waste and loss of signaling in the PCI slot is avoided, and on the other hand, the integrity of the ML2 slot functionality provided by the second interface 220 is improved.
According to an embodiment of the present disclosure, the signal conversion module 332 may include a signal processing sub-module 3321 and a signal transmission sub-module 3322.
The signal processing sub-module 3321 is configured to, for at least one second pin in the second group of second pins, process a signal transmitted by the corresponding one or more first pins to obtain a same signal as the signal transmitted by the at least one second pin.
The transmission sub-module 3322 is configured to transmit the signal processed by the signal processing sub-module 3321 to the at least one second pin.
Specifically, for example, when at least one second pin transmits a voltage signal, the signal processing sub-module 3321 may process the signal transmitted by the corresponding one or more first pins to obtain a signal having the same magnitude as the voltage signal.
For example, when at least one second pin transmits a voltage signal of 3.3V, the first interface 210 does not have a first pin transmitting a voltage signal of 3.3V, but the first interface 210 has a first pin transmitting a voltage signal of 12V.
At this time, the signal processing sub-module 3321 may attenuate the 12V voltage transmitted by the first pin to convert the voltage into a 3.3V voltage signal. Then the transmission sub-module 3322 transmits the processed 3.3V signal voltage to the at least one second pin.
Alternatively, when the at least one second pin transmits a clock signal and the first interface 210 does not transmit a first pin having the same period as the clock signal, the signal processing sub-module 3321 may process the clock signal transmitted by the corresponding one or more first pins to obtain a signal having the same period as the clock signal. Then, the signal transmission sub-module 3322 transmits the processed clock signal to the at least one second pin.
According to an embodiment of the present disclosure, the signal processing sub-module 3321 may also convert a signal transmitted by at least one first pin into a signal transmitted by a second pin having a different number of pins from the at least one first pin.
For the second group of second pins in the second interface 220, there may be one first pin capable of signal conversion in the first interface 210, or there may be a plurality of first pins capable of signal combination conversion for transmitted signals.
For example, when at least one second pin transmits a 12V voltage signal, and two first pins in the first interface 210 transmit 5V and 7V voltage signals, respectively, at this time, the signal processing sub-module 3321 may combine the two first pins transmitting 5V and 7V voltage signals, respectively, to obtain a 12V voltage signal.
In addition, there may also be a case where multiple pins in the second group of second pins in the second interface 220 correspond to the same first pin in the first interface 210.
For example, for a certain clock signal, there may be only one first pin in the first interface 210, whereas in the second interface 220 there may be two second pins needed to introduce the clock signal. At this time, the signal processing submodule 3321 may split the clock signal transmitted by the first pin into two paths of clock signals identical to the two paths of clock signals, and then the two paths of clock signals are transmitted to two pins of the second group of second pins by the signal transmission submodule 3322.
According to the embodiment of the present disclosure, when the signal processing sub-module 3321 processes the signal transmitted by the first pin, a signal amplifier and the like may be added to enhance the function of the processed signal and improve the signal strength and the like.
According to the embodiment of the present disclosure, the converting apparatus 300 connects the second pin and one or more corresponding first pins according to the signal transmitted by the second interface 220 through the connection subunit 330 in the converting unit 230, so as to convert the signal from the first interface 210 into a signal matched with the second interface 220.
Specifically, the connection subunit 330 connects, through the signal transmission module 331, each of the first group of second pins with the first pin, which has the same signal transmitted by the first group of second pins, in a one-to-one correspondence manner. And/or the signal conversion module 332 connects each of the second pins of the second group with one or more first pins that transmit different signals but have corresponding relationships with the second pins.
In this way, the conversion apparatus 300 correspondingly converts and/or transmits the signal introduced in the first interface 210 according to the signal transmitted by the second pin in the second interface 220, thereby achieving the corresponding conversion of the signal transmitted in the PCI slot into the signal matched with the ML2 slot.
Fig. 5 schematically shows a block diagram of a conversion apparatus 500 according to yet another embodiment of the present disclosure.
According to an embodiment of the present disclosure, the conversion apparatus 500 is another of the specific embodiments of the conversion apparatus 200.
As shown in fig. 5, the conversion apparatus 500 includes a first interface 210, a second interface 220, and a conversion unit 230. Wherein the conversion unit 230 comprises a reservation subunit 530 in addition to the connection subunit 330.
According to the embodiment of the present disclosure, for a second pin of the first interface 210 without a corresponding first pin, the reservation subunit 530 connects the second pin of the second interface 220 with an idle pin of the first interface 210.
Specifically, for example, for the second pin of the second interface 220 used for transmitting signals from the BMC, there is no corresponding first pin of the first interface 210.
At this time, the second pin is connected to the idle pin in the first interface 210, so that if a user or a manufacturer actively connects the idle pin in the PCI slot to a corresponding position on the BMC according to the connection relationship between the second pin and the BMC, the second interface 220 has the NCSI function.
Alternatively, by connecting the second pin to an idle pin in the first interface 210, even without any modification to the PCI slot, the functions other than NCSI can still be performed for the device with ML2 interface connected to the second interface 220.
According to the embodiment of the present disclosure, while the conversion apparatus 500 can convert the signal transmitted in the PCI slot into the signal matched with the ML2 slot, it is possible to add further NCSI function to the second interface 220, and it provides conditions for the user to obtain the complete ML2 slot function from the widely used PCI slot.
Fig. 6 schematically shows a block diagram of an electronic device according to an embodiment of the disclosure.
As shown in fig. 6, an electronic device 600 according to an embodiment of the present disclosure includes the conversion apparatus 200. The conversion device 200 is used for converting the PCI slots into ML2 slots on the mainboard.
The conversion apparatus 200 includes a first interface 210, a second interface 220, and a conversion unit 230.
The first interface 210 includes at least one first pin that mates with a PCI slot.
The first interface 210 is configured to be connected to a PCI slot, such that at least one first pin of the first interface 210 is electrically connected to a corresponding pin of the PCI slot, so that signals transmitted by the pins of the PCI slot are correspondingly transmitted to the first interface 210.
A second interface 220 comprising at least one second pin identical to a pin in the ML2 socket.
At least one second pin in the second interface 220 is the same as a pin in the ML2 slot, so that a device having an ML2 interface can be connected to the second interface 220 to transmit signals transmitted by the second pin in the second interface 220 to the device.
The conversion unit 230 electrically connects the first interface 210 and the second interface 220, and is configured to correspondingly convert the signal from the first interface into a signal matched with the second interface.
In the electronic device 600 according to the embodiment of the disclosure, when the first interface 210 of the conversion apparatus 200 is connected to the PCI slot and the second interface 220 is connected to the device having the ML2 interface, the signals transmitted by the corresponding pins in the PCI slot may be first transmitted to the first interface 210, then correspondingly transmitted to the second interface 220 through the conversion unit 230, and finally transmitted to the device having the ML2 interface, so that the device having the ML2 interface can operate.
In this way, the electronic device 600 according to the embodiment of the present disclosure may externally connect a device having an ML2 interface through the conversion apparatus 200.
According to an embodiment of the present disclosure, the conversion apparatus 200 in the electronic device 600 may be the conversion apparatus 300.
Specifically, the conversion apparatus 300 includes a first interface 210, a second interface 220, and a conversion unit 230. Wherein the conversion unit 230 comprises a connection subunit 330.
The connection subunit 330 is configured to connect the second pin of the second interface 220 to one or more corresponding first pins of the first interface 210 according to a signal transmitted by the second pin.
According to an embodiment of the present disclosure, the connection subunit 330 may include a signal transmission module 331, configured to connect each of the first group of second pins with the same first pin as the signal transmitted by the first group of second pins in a one-to-one correspondence manner.
According to an embodiment of the present disclosure, the connection subunit 330 may also include a signal conversion module 332 for connecting each pin of the second group of second pins with one or more first pins that transmit different signals but have corresponding relationships therewith.
Specifically, the signal conversion module 332 may include a signal processing sub-module 3321 and a signal transmission sub-module 3322.
The signal processing sub-module 3321 is configured to, for at least one second pin in the second group of second pins, process a signal transmitted by the corresponding one or more first pins to obtain a same signal as the signal transmitted by the at least one second pin.
The transmission sub-module 3322 is configured to transmit the signal processed by the signal processing sub-module 3321 to the at least one second pin.
According to an embodiment of the present disclosure, the conversion apparatus 200 in the electronic device 600 may also be the conversion apparatus 500. The conversion apparatus 500 includes a first interface 210, a second interface 220, and a conversion unit 230. Wherein the conversion unit 230 comprises a reservation subunit 530 in addition to the connection subunit 330.
According to the embodiment of the present disclosure, for a second pin of the first interface 210 without a corresponding first pin, the reservation subunit 530 connects the second pin of the second interface 220 with an idle pin of the first interface 210.
Specifically, for example, for the second pin of the second interface 220 used to transmit signals from the BMC, there is no corresponding first pin of the first interface 210.
At this time, the second pin is connected to the idle pin in the first interface 210, so that if the electronic device 600 is configured, that is, the idle pin in the PCI slot is connected to a corresponding position on the BMC according to the connection relationship between the second pin and the BMC, the second interface 220 also has the NCSI function.
Alternatively, by connecting the second pin to an idle pin in the first interface 210, even without any modification to the PCI slot, the functions other than NCSI can still be performed for the device with ML2 interface connected to the second interface 220.
According to the embodiment of the disclosure, while the conversion device 500 in the electronic device 600 can convert the signal transmitted in the PCI slot into the signal matched with the ML2 slot, it is possible to add further NCSI function to the second interface 220 in the electronic device 600, and it is provided that the electronic device 600 obtains the complete function of the ML2 slot from the PCI slot.
Methods, apparatus, units and/or modules according to embodiments of the present disclosure may be implemented using hardware or firmware, for example Field Programmable Gate Arrays (FPGAs), Programmable Logic Arrays (PLAs), systems on a chip, systems on a substrate, systems on a package, Application Specific Integrated Circuits (ASICs), or in any other reasonable manner for integrating or packaging circuits, or in any suitable combination of software, hardware and firmware implementations. The system may include a storage device to implement the storage described above. When implemented in these manners, the software, hardware, and/or firmware used is programmed or designed to perform the corresponding above-described methods, steps, and/or functions according to the present disclosure. One skilled in the art can implement one or more of these systems and modules, or one or more portions thereof, using different implementations as appropriate to the actual needs. Such implementations are within the scope of the present disclosure.
Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.
While the disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined not only by the appended claims, but also by equivalents thereof.
Claims (10)
1. A translation mechanism for translating peripheral component interconnect standard PCI slots to mezzanine local area network ML2 slots on a motherboard, comprising:
the first interface comprises a plurality of first pins matched with the PCI slot, wherein high-level pins in the first pins are collectively arranged together, and low-level pins are collectively arranged together;
a second interface including a plurality of second pins identical to pins in the ML2 socket, wherein high and low pins in the plurality of second pins are arranged crosswise;
the conversion unit is used for electrically connecting the first interface and the second interface, correspondingly converting the signal from the first interface into a signal matched with the second interface, and comprises: connecting a first pin for transmitting one of a clock signal, a voltage signal and a transmission signal in a first interface to a corresponding second pin in a second interface; and connecting a second pin connected with the baseboard management controller in the second interface with an idle pin in the plurality of first pins of the first interface.
2. The conversion apparatus of claim 1, wherein the conversion unit comprises:
and the connecting subunit is used for connecting the second pin with one or more corresponding first pins according to the signal transmitted by the second pin.
3. The conversion apparatus of claim 2, wherein the conversion unit further comprises:
and the reserved subunit is used for connecting the second pin with the idle pin in the first interface for the second pin of which the first pin corresponding to the second pin does not exist in the first interface.
4. The conversion apparatus of claim 2, wherein the connection subunit comprises:
and the signal transmission module is used for correspondingly connecting each pin in the first group of second pins with the first pins which have the same signals transmitted by the first group of second pins one to one.
5. The conversion apparatus of claim 2, wherein the connection subunit comprises:
and the signal conversion module is used for connecting each pin in the second group of second pins with one or more first pins which transmit different signals with corresponding relations.
6. The conversion apparatus of claim 5, wherein the signal conversion module comprises:
the signal processing submodule is used for processing signals transmitted by one or more corresponding first pins aiming at least one second pin in the second group of second pins to obtain the same signals transmitted by the at least one second pin;
and the transmission submodule is used for transmitting the signals processed by the signal processing submodule to the at least one second pin.
7. The conversion device of claim 6, wherein when the at least one second pin transmits a voltage signal, the signal processing submodule processes the signal transmitted by the corresponding one or more first pins to obtain a signal with the same magnitude as the voltage signal.
8. The conversion device of claim 6, wherein when the at least one second pin transmits a clock signal, the signal processing submodule processes the signal transmitted by the corresponding one or more first pins to obtain a signal with the same period as the clock signal.
9. The conversion apparatus according to claim 6, wherein the signal processing sub-module converts a signal transmitted from at least one first pin into a signal transmitted from a second pin having a different number of pins from the at least one first pin.
10. An electronic device comprising the conversion apparatus as claimed in any one of claims 1 to 9.
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