CN110061052A - 高正向阻断电压门极灵敏触发单向可控硅芯片和制造方法 - Google Patents

高正向阻断电压门极灵敏触发单向可控硅芯片和制造方法 Download PDF

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CN110061052A
CN110061052A CN201910360828.0A CN201910360828A CN110061052A CN 110061052 A CN110061052 A CN 110061052A CN 201910360828 A CN201910360828 A CN 201910360828A CN 110061052 A CN110061052 A CN 110061052A
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俞荣荣
王成森
朱法扬
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JIANGSU JIEJIE MICROELECTRONICS CO Ltd
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Abstract

本发明公开了一种高正向阻断电压门极灵敏触发单向可控硅芯片,包括阳极电极A、背面P型短基区、P型对通隔离环、门极电极G、N‑型长基区、正面P型短基区、N+型发射区、阴极电极K、隔离钝化槽和设置在正面的氧化膜。制造方法:生长氧化层、光刻对通隔离环、离子注入铝、对通隔离环扩散、双面P型短基区扩散、正面光刻发射区、N+发射区磷扩散、光刻隔离钝化槽及腐蚀、Sipos+Gpp钝化保护、光刻引线、双面蒸发电极、双面光刻反刻、真空合金、芯片测试、划片分离。本发明满足VDRM>2200V,实现极高的正向阻断电压。

Description

高正向阻断电压门极灵敏触发单向可控硅芯片和制造方法
技术领域
本发明涉及半导体芯片技术领域,尤其涉及一种高正向阻断电压门极灵敏触发单向可控硅芯片和制造方法。
背景技术
目前市场上的门极灵敏触发型单向晶闸管芯片,门极电极在隔离钝化槽的内侧,由P型杂质组成。阳极电极在芯片的背面,阴极电极在芯片正面,由N+杂质构成。这种芯片结构的正向阻断电压是由图示1的N-P结承受的,由于结的终端与沟槽形成负角,一般VDRM在600-1100V之间。在某些特殊行业应用时,需要VDRM>2200V,这种结构就无法实现。目前已知的全球各大晶闸管产品供应商,无法提供此类产品。
发明内容
为解决上述缺陷,本发明提供一种高正向阻断电压门极灵敏触发型单向芯片和制造方法。
本发明的技术方案是:一种高正向阻断电压门极灵敏触发单向可控硅芯片,包括阳极电极A、背面P型短基区、P型对通隔离环、门极电极G、N-型长基区、正面P型短基区、N+型发射区、阴极电极K、隔离钝化槽和设置在正面的氧化膜,所述正面P型短基区设置在N-型长基区正面,且和N+型发射区连接成一体,所述N-型长基区与正面P型短基区之间形成正向电压PN结,所述门极电极G设置在正面P型短基区顶面,所述阴极电极K设置在N+型发射区顶面;所述背面P型短基区设置在N-型长基区背面,所述N-型长基区与背面P型短基区之间形成反向电压PN结,所述背面P型短基区顶面设有阳极电极A;所述正面P型短基区通过P型对通隔离环与背面P型短基区相连,所述背面P型短基区四周设有环状的隔离钝化槽。
进一步地,所述隔离钝化槽的厚度为115-125um。
高正向阻断电压门极灵敏触发单向可控硅芯片的制造方法,包括以下步骤:
(1)生长氧化层:取厚度315±5um、电阻率为50-60Ω的区熔单晶双磨硅片,进行酸腐、碱腐后,化学清洗,甩干后在1150℃--1200℃的温度下氧化3-5h,氧化膜的厚度控制在10000-13000A之间;
(2)光刻对通隔离环:在硅片两面分别涂覆光刻胶、曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的对通隔离环窗口的氧化膜腐蚀掉,去残胶、清洗、甩干;
(3)离子注入铝:离子注入机铝源通过高压加速后,注入硅片表面;
(4)对通隔离环扩散:扩散温度1250℃--1280℃,扩散时间为60-80h,通入氮气和氧气进行保护,氮气流量5.8-6.2L/min,氧气流量0.4-0.6L/min;升温速率为3-5℃/min,降温速率为1-3℃/min;
(5)双面P型短基区扩散:双面注入硼;双面注入铝;然后在LPCVD炉生长Poly保护膜,进行铝再扩散;铝再扩的温度为1260-1270℃,扩散时间为11-13h,通入氮气和氧气保护,流量同隔离环扩散;降温至1180℃时,进行湿氧氧化,湿氧的气体流量为2.3-2.7L/min,湿氧时间为3.5-4.5h,然后降温(降温速率为1-3℃/min)至650℃出炉;
(6)正面光刻发射区:在硅片两面涂覆光刻胶,正面采用发射版对准曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的N+型发射区窗口的氧化膜腐蚀掉,背面则曝光,保护氧化层,免被腐蚀;
(7)N+发射区磷扩散:采用POCL3为扩散源,对发射窗口进行磷掺杂,分予扩散再分布两步完成;予扩散温度1050℃-1150℃,予扩时间85-95min,源温15-20℃;磷再扩温度为1180℃-1220℃,扩散时间为4-5.5h,发射区磷扩散结深在22-28um;
(8)光刻隔离钝化槽及腐蚀:正面涂覆光刻胶、曝光、保护;背面涂覆光刻胶、对版曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的隔离钝化槽窗口的氧化层腐蚀掉,然后再用硅腐蚀液,腐蚀出深度为115-125um的隔离钝化槽;
(9)钝化保护:在腐蚀出的隔离钝化槽内用LPCVD生长一层Sipos保护膜,厚度为9000-11000A,然后填充玻璃粉,烧结成玻璃,再用LPCVD法生长一层LTO膜覆盖硅片表面,厚度为3000-6000A;
(10)光刻引线:在硅片两面分别涂覆光刻胶,分别对准曝光、显影、坚膜,利用BOE腐蚀液与Sipos腐蚀液逐层腐蚀LTO-Sipos-SiO2,使需进行引线的部分显露出来;
(11)双面蒸发电极:利用电子束蒸发后;正面蒸发铝,厚度在5-7um;背面蒸发钛-镍-银,厚度为1400-5000-5000A,反刻后正面形成门极电极G和阴极电极K,背面形成阳极电极A;
(12)真空合金、芯片测试、划片分离。
进一步地,所述步骤(3)中注入铝时的注入的能量为130-150KeV,注入剂量为2.5E15—4E15/cm 2
进一步地,所述步骤(5)中注入硼时的注入的能量为60-100KeV,注入剂量为1.5E15-3E15/cm 2
进一步地,所述步骤(5)中注入铝时的注入的能量为100-150KeV,注入剂量为3E14-5E14/cm 2
本发明的有益效果:通过对结构的优化,使灵敏触发型单向晶闸管的正向电压PN结端与背面P型短基区四周的环状的隔离钝化槽形成正角击穿,原始单晶厚度为 315±5um,可以满足VDRM>2200V,实现极高的正向阻断电压。
附图说明
图1是背景技术中晶闸管芯片的纵向剖视结构示意图。
图2是本发明的纵向剖视结构示意图。
图3是本发明的俯视结构示意图。
图4是本发明的仰视结构示意图。
其中:1、门极电极G,2、阴极电极K,3、隔离钝化槽,4、阳极电极A,5、正面P型短基区,6、N-型长基区,7、背面P型短基区,8、P型对通隔离环,9、N+型发射区,10、氧化膜,11、反向电压PN结,12、正向电压PN结。
具体实施方式
下面结合附图对本发明做进一步详述,下面描述中的仅仅是本发明中记载的附图,对本领域的普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图,获得其它的附图。
如图2-图4所示,高正向阻断电压门极灵敏触发单向可控硅芯片,包括阳极电极A4、背面P型短基区7、P型对通隔离环8、门极电极G1、N-型长基区6、正面P型短基区5、N+型发射区9、阴极电极K2、隔离钝化槽3和设置在正面的氧化膜10,正面P型短基区5设置在N-型长基区6正面,且和N+型发射区9连接成一体,N-型长基区6与正面P型短基区5之间形成正向电压PN结12,门极电极G1设置在正面P型短基区5顶面,阴极电极K2设置在N+型发射区9顶面;背面P型短基区7设置在N-型长基区6背面,N-型长基区6与背面P型短基区7之间形成反向电压PN结11,背面P型短基区7顶面设有阳极电极A4;正面P型短基区5通过P型对通隔离环8与背面P型短基区7相连,背面P型短基区7四周设有环状的隔离钝化槽3。
进一步地,隔离钝化槽3的厚度为115-125um。
高正向阻断电压门极灵敏触发单向可控硅芯片的制造方法,包括以下步骤:
(1)生长氧化层:取厚度315±5um、电阻率为50-60Ω的区熔单晶双磨硅片,进行酸腐、碱腐后,化学清洗,甩干后在1150℃--1200℃的温度下氧化3-5h,氧化膜的厚度控制在10000-13000A之间;
(2)光刻对通隔离环:在硅片两面分别涂覆光刻胶、曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的对通隔离环窗口的氧化膜腐蚀掉,去残胶、清洗、甩干;
(3)离子注入铝:离子注入机铝源通过高压加速后,注入硅片表面;
(4)对通隔离环扩散:扩散温度1250℃--1280℃,扩散时间为60-80h,通入氮气和氧气进行保护,氮气流量5.8-6.2L/min,氧气流量0.4-0.6L/min;升温速率为3-5℃/min,降温速率为1-3℃/min;
(5)双面P型短基区扩散:双面注入硼;双面注入铝;然后在LPCVD炉生长Poly保护膜,进行铝再扩散;铝再扩的温度为1260-1270℃,扩散时间为11-13h,通入氮气和氧气保护,流量同隔离环扩散;降温至1180℃时,进行湿氧氧化,湿氧的气体流量为2.3-2.7L/min,湿氧时间为3.5-4.5h,然后降温(降温速率为1-3℃/min)至650℃出炉;
(6)正面光刻发射区:在硅片两面涂覆光刻胶,正面采用发射版对准曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的N+型发射区窗口的氧化膜腐蚀掉,背面则曝光,保护氧化层,免被腐蚀;
(7)N+发射区磷扩散:采用POCL3为扩散源,对发射窗口进行磷掺杂,分予扩散再分布两步完成;予扩散温度1050℃-1150℃,予扩时间85-95min,源温15-20℃;磷再扩温度为1180℃-1220℃,扩散时间为4-5.5h,发射区磷扩散结深在22-28um;
(8)光刻隔离钝化槽及腐蚀:正面涂覆光刻胶、曝光、保护;背面涂覆光刻胶、对版曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的隔离钝化槽窗口的氧化层腐蚀掉,然后再用硅腐蚀液,腐蚀出深度为115-125um的隔离钝化槽;
(9)钝化保护:在腐蚀出的隔离钝化槽内用LPCVD生长一层Sipos保护膜,厚度为9000-11000A,然后填充玻璃粉,烧结成玻璃,再用LPCVD法生长一层LTO膜覆盖硅片表面,厚度为3000-6000A;
(10)光刻引线:在硅片两面分别涂覆光刻胶,分别对准曝光、显影、坚膜,利用BOE腐蚀液与Sipos腐蚀液逐层腐蚀LTO-Sipos-SiO2,使需进行引线的部分显露出来;
(11)双面蒸发电极:利用电子束蒸发后;正面蒸发铝,厚度在5-7um;背面蒸发钛-镍-银,厚度为1400-5000-5000A,反刻后正面形成门极电极G和阴极电极K,背面形成阳极电极A;
(12)真空合金、芯片测试、划片分离。
进一步地,步骤(3)中注入铝时的注入的能量为130-150KeV,注入剂量为2.5E15—4E15/cm 2
进一步地,步骤(5)中注入硼时的注入的能量为60-100KeV,注入剂量为1.5 E15-3E15/cm 2
进一步地,步骤(5)中注入铝时的注入的能量为100-150KeV,注入剂量为3 E14-5E14/cm 2
本发明通过对结构的优化,使灵敏触发型单向晶闸管的正向电压PN结端与背面P型短基区四周的环状的隔离钝化槽形成正角击穿,原始单晶厚度为 315±5um,可以满足VDRM>2200V,实现极高的正向阻断电压。

Claims (6)

1.高正向阻断电压门极灵敏触发单向可控硅芯片,包括阳极电极A、背面P型短基区、P型对通隔离环、门极电极G、N-型长基区、正面P型短基区、N+型发射区、阴极电极K、隔离钝化槽和设置在正面的氧化膜,其特征在于:所述正面P型短基区设置在N-型长基区正面,且和N+型发射区连接成一体,所述N-型长基区与正面P型短基区之间形成正向电压PN结,所述门极电极G设置在正面P型短基区顶面,所述阴极电极K设置在N+型发射区顶面;所述背面P型短基区设置在N-型长基区背面,所述N-型长基区与背面P型短基区之间形成反向电压PN结,所述背面P型短基区顶面设有阳极电极A;所述正面P型短基区通过P型对通隔离环与背面P型短基区相连,所述背面P型短基区四周设有环状的隔离钝化槽。
2.根据权利要求1所述的高正向阻断电压门极灵敏触发单向可控硅芯片,其特征在于:所述隔离钝化槽的厚度为115-125um。
3.高正向阻断电压门极灵敏触发单向可控硅芯片的制造方法,其特征在于,包括以下步骤:
(1)生长氧化层:取厚度310-320um、电阻率为50-60Ω的区熔单晶双磨硅片,进行酸腐、碱腐后,化学清洗,甩干后在1150℃--1200℃的温度下氧化3-5h,氧化膜的厚度控制在10000-13000A之间;
(2)光刻对通隔离环:在硅片两面分别涂覆光刻胶、曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的对通隔离环窗口的氧化膜腐蚀掉,去残胶、清洗、甩干;
(3)离子注入铝:离子注入机铝源通过高压加速后,注入硅片表面;
(4)对通隔离环扩散:扩散温度1250℃--1280℃,扩散时间为60-80h,通入氮气和氧气进行保护,氮气流量5.8-6.2L/min,氧气流量0.4-0.6L/min;升温速率为3-5℃/min,降温速率为1-3℃/min;
(5)双面P型短基区扩散:双面注入硼;双面注入铝;然后在LPCVD炉生长Poly保护膜,进行铝再扩散;铝再扩的温度为1260-1270℃,扩散时间为11-13h,通入氮气和氧气保护,流量同隔离环扩散;降温至1180℃时,进行湿氧氧化,湿氧的气体流量为2.3-2.7L/min,湿氧时间为3.5-4.5h,然后降温(降温速率为1-3℃/min)至650℃出炉;
(6)正面光刻发射区:在硅片两面涂覆光刻胶,正面采用发射版对准曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的N+型发射区窗口的氧化膜腐蚀掉,背面则曝光,保护氧化层,免被腐蚀;
(7)N+发射区磷扩散:采用POCL3为扩散源,对发射窗口进行磷掺杂,分予扩散再分布两步完成;予扩散温度1050℃-1150℃,予扩时间85-95min,源温15-20℃;磷再扩温度为1180℃-1220℃,扩散时间为4-5.5h,发射区磷扩散结深在22-28um;
(8)光刻隔离钝化槽及腐蚀:正面涂覆光刻胶、曝光、保护;背面涂覆光刻胶、对版曝光、显影、坚膜,利用BOE腐蚀液将显影后裸露出来的隔离钝化槽窗口的氧化层腐蚀掉,然后再用硅腐蚀液,腐蚀出深度为115-125um的隔离钝化槽;
(9)钝化保护:在腐蚀出的隔离钝化槽内用LPCVD生长一层Sipos保护膜,厚度为9000-11000A,然后填充玻璃粉,烧结成玻璃,再用LPCVD法生长一层LTO膜覆盖硅片表面,厚度为3000-6000A;
(10)光刻引线:在硅片两面分别涂覆光刻胶,分别对准曝光、显影、坚膜,利用BOE腐蚀液与Sipos腐蚀液逐层腐蚀LTO-Sipos-SiO2,使需进行引线的部分显露出来;
(11)双面蒸发电极:利用电子束蒸发后;正面蒸发铝,厚度在5-7um;背面蒸发钛-镍-银,厚度为1400-5000-5000A,反刻后正面形成门极电极G和阴极电极K,背面形成阳极电极A;
(12)真空合金、芯片测试、划片分离。
4.根据权利要求3所述的高正向阻断电压门极灵敏触发单向可控硅芯片的制造方法,其特征在于:所述步骤(3)中注入铝时的注入的能量为130-150KeV,注入剂量为2.5E15—4E15/cm 2
5.根据权利要求3所述的高正向阻断电压门极灵敏触发单向可控硅芯片的制造方法,其特征在于:所述步骤(5)中注入硼时的注入的能量为60-100KeV,注入剂量为1.5 E15-3E15/cm 2
6.根据权利要求1所述的高正向阻断电压门极灵敏触发单向可控硅芯片的制造方法,其特征在于:所述步骤(5)中注入铝时的注入的能量为100-150KeV,注入剂量为3 E14-5E14/cm 2
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113161238A (zh) * 2021-04-20 2021-07-23 江苏韦达半导体有限公司 高温度特性门极灵敏型触发可控硅芯片的制作工艺

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0031898A1 (de) * 1979-12-18 1981-07-15 Tag Semiconductors Limited, Wilmington Zürich Branch Verfahren zum Erzeugen von dotierten Bereichen zur gegenseitigen elektrischen Isolation einzelner Halbleiterelemente auf einer Siliziumscheibe, sowie nach dem Verfahren hergestellte Halbleiteranordnung
US4484214A (en) * 1980-10-27 1984-11-20 Hitachi, Ltd. pn Junction device with glass moats and a channel stopper region of greater depth than the base pn junction depth
CN101587907A (zh) * 2009-04-29 2009-11-25 启东市捷捷微电子有限公司 低结电容过压保护晶闸管器件芯片及其生产方法
CN101853878A (zh) * 2010-06-03 2010-10-06 西安理工大学 一种pnp-沟槽复合隔离RC-GCT器件及制备方法
CN102244078A (zh) * 2011-07-28 2011-11-16 启东市捷捷微电子有限公司 台面工艺可控硅芯片结构和实施方法
CN104637997A (zh) * 2015-01-28 2015-05-20 电子科技大学 一种双模逆导门极换流晶闸管及其制备方法
CN105590959A (zh) * 2015-12-17 2016-05-18 清华大学 具有双p基区门阴极结构的门极换流晶闸管及其制备方法
CN105633133A (zh) * 2016-03-14 2016-06-01 江苏捷捷微电子股份有限公司 单一负信号触发的双向晶闸管芯片及其制造方法
CN108598180A (zh) * 2018-04-11 2018-09-28 浙江世菱电力电子有限公司 一种整流二极管及其制备方法
CN209708983U (zh) * 2019-04-30 2019-11-29 江苏捷捷微电子股份有限公司 高正向阻断电压门极灵敏触发单向可控硅芯片

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0031898A1 (de) * 1979-12-18 1981-07-15 Tag Semiconductors Limited, Wilmington Zürich Branch Verfahren zum Erzeugen von dotierten Bereichen zur gegenseitigen elektrischen Isolation einzelner Halbleiterelemente auf einer Siliziumscheibe, sowie nach dem Verfahren hergestellte Halbleiteranordnung
US4484214A (en) * 1980-10-27 1984-11-20 Hitachi, Ltd. pn Junction device with glass moats and a channel stopper region of greater depth than the base pn junction depth
CN101587907A (zh) * 2009-04-29 2009-11-25 启东市捷捷微电子有限公司 低结电容过压保护晶闸管器件芯片及其生产方法
CN101853878A (zh) * 2010-06-03 2010-10-06 西安理工大学 一种pnp-沟槽复合隔离RC-GCT器件及制备方法
CN102244078A (zh) * 2011-07-28 2011-11-16 启东市捷捷微电子有限公司 台面工艺可控硅芯片结构和实施方法
CN104637997A (zh) * 2015-01-28 2015-05-20 电子科技大学 一种双模逆导门极换流晶闸管及其制备方法
CN105590959A (zh) * 2015-12-17 2016-05-18 清华大学 具有双p基区门阴极结构的门极换流晶闸管及其制备方法
CN105633133A (zh) * 2016-03-14 2016-06-01 江苏捷捷微电子股份有限公司 单一负信号触发的双向晶闸管芯片及其制造方法
CN108598180A (zh) * 2018-04-11 2018-09-28 浙江世菱电力电子有限公司 一种整流二极管及其制备方法
CN209708983U (zh) * 2019-04-30 2019-11-29 江苏捷捷微电子股份有限公司 高正向阻断电压门极灵敏触发单向可控硅芯片

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113161238A (zh) * 2021-04-20 2021-07-23 江苏韦达半导体有限公司 高温度特性门极灵敏型触发可控硅芯片的制作工艺
CN113161238B (zh) * 2021-04-20 2024-04-09 江苏韦达半导体有限公司 高温度特性门极灵敏型触发可控硅芯片的制作工艺

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