CN110047929B - 具有沟槽栅极的半导体电子器件及其制造方法 - Google Patents

具有沟槽栅极的半导体电子器件及其制造方法 Download PDF

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CN110047929B
CN110047929B CN201910033481.9A CN201910033481A CN110047929B CN 110047929 B CN110047929 B CN 110047929B CN 201910033481 A CN201910033481 A CN 201910033481A CN 110047929 B CN110047929 B CN 110047929B
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semiconductor body
gate
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D·G·帕蒂
M·萨姆比
F·F·R·托亚
S·D·马里亚尼
E·皮兹
G·巴里拉罗
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STMicroelectronics SRL
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Abstract

本公开涉及具有沟槽栅极的半导体电子器件及其制造方法。一种垂直导电半导体电子器件，包括：半导体本体；在半导体本体中的体区；在体区中的源极端子；与源极区域空间相对的漏极端子；以及穿过体区和源极区域延伸深入半导体本体的沟槽栅极。沟槽栅极包括掩埋在半导体本体中的多孔氧化硅的电介质区域，以及延伸在多孔氧化硅的电介质区域和第一侧之间的栅极导电区域。

Description

具有沟槽栅极的半导体电子器件及其制造方法
技术领域
本公开涉及一种具有沟槽栅极的半导体电子器件以及用于制造具有沟槽栅极的半导体电子器件的方法。
背景技术
已知具有掩埋栅极区域或沟槽栅极区域的垂直导电功率金属氧化物半导体场效应晶体管(MOSFET)。
例如，专利文献No.US 2015/0206968描述了一种垂直沟道横向扩散金属氧化物半导体(LDMOS)半导体器件，其中栅极沟槽延伸深入半导体体区中并包括掺杂多晶硅制成的、由电介质区域(例如由氧化硅或氮化硅制成)围绕并与半导体体区电绝缘的导电区域。
电介质区域可以由沉积工艺例如液相沉积(LPD)或者另外由氧化物的热生长而形成。这两个工艺存在一些固有限制。例如，电介质层的沉积可以引起晶体界面应力，这可以危害器件的电操作(例如产生用于电荷载流子的陷阱)，而热生长通常涉及使用用于保护其中热氧化物的生长是不希望或达不到预期目标的表面区域的结构。
发明内容
一个或多个实施例涉及一种用于制造将克服现有技术的缺点的至少一些的具有沟槽栅极的电子器件的方法。
根据本公开，提供了一种半导体电子器件以及一种用于制造半导体电子器件的方法。
为了更好理解本公开，现在纯粹借由非限定性示例的方式、参照附图描述其优选实施例，其中图1-图13在侧面剖视图中说明了根据本公开实施例的用于制造具有沟槽区域的半导体电子器件的制造步骤。
根据本公开，提供了一种功率器件，特别是MOS晶体管，其具有在器件的正面侧上的源极电极，在器件的背面侧上的漏极电极，以及从正面侧朝向背面侧延伸的沟槽栅极。
附图说明
下文中参照图1-图13描述根据本公开的用于制造电子器件的步骤。图1-图13在侧面剖视图中图示了在由相互正交的轴线X、Y和Z所限定的空间坐标系统中的电子器件。
具体实施方式
特别地，本公开描述了用于本公开的感兴趣的制造步骤(也即，关于提供具有内部绝缘区域的沟槽栅极的结构)。在此并未描述或在附图中说明可以是本质上已知类型的电子器件的其他元件(例如边缘区域或其他结构)。
图1说明了包括衬底1的晶片100，特别是由单晶硅制成，具有第一导电类型(在此，N型)和第一掺杂浓度(例如高于1019原子/cm3)。衬底1被界定在沿着轴线Z彼此相对的第一侧1a上和第二侧1b上。
例如通过硅的外延生长，在衬底1上形成结构层或区域2，其具有第一导电类型(N)和低于衬底1的掺杂剂浓度(例如包括在1·1015和5·1016离子/cm3之间)。结构区域2具有沿着Z的厚度，其基于其中电子器件将要工作的电压类型而被选择，并且例如包括近似在1.5μm和100μm之间。
结构区域2由沿方向Z彼此相对的第一侧2a和第二侧2b被界定。结构区域2的第二侧2b与衬底1的第一侧1a重合。
根据一些备选实施例(未示出)，例如外延生长并类似于结构区域2的一个或多个其他结构区域可以形成在衬底1的第一侧1a和结构区域2的第二侧2b之间。
在结构层2的第一侧2a上随后形成掩模多层4，其包括：第一掩模层4a，与第一侧2a接触，例如由经由热氧化生长的、具有在5nm和100nm之间的厚度氧化硅制成；第二掩模层4b，紧接在第一掩模层4a顶部上，例如由具有在10nm和1μm之间厚度的氮化硅制成；以及第三掩模层4c，紧接在第二掩模层4b顶部上，例如由具有在10nm和10μm之间厚度的四乙基原硅酸盐(TEOS)或光致抗蚀剂制成。第一掩模层4a具有在硅的结构层2与氮化硅的第二掩模层4b之间形成界面的功能，以便于防止由氮化硅诱发的机械应力并防止硅表面自身氮化，硅表面自身氮化危害了器件的工作。第二掩模层4b形成用于蚀刻结构层2的后续步骤的硬掩模。第三掩模层4c形成用于蚀刻结构层2的步骤的另一硬掩模。
通过光刻技术，在晶片100的其中将要形成沟槽栅极的区域中移除掩模多层4。随后执行蚀刻，特别是干式蚀刻，例如反应离子蚀刻(RIE)，用于选择性移除通过掩模多层4暴露的结构层2的一部分并且以便于形成由底壁6a和侧壁6b所界定的沟槽6。沟槽6具有深度，从结构层2的第一侧2a开始测量，例如被包括在1和2μm之间。
在顶视平面图中，在平面XY中，沟槽6具有条带形状，具有沿着轴线Y的、范围从几微米至几毫米的主延伸，以及沿着轴线X的包括在0.5μm和1.5μm之间的宽度。可以针对沟槽6设计其他布图，例如一旦再次在平面XY中观看其可以具有圆形的形状，具有包括在0.5μm和1.5μm之间直径，或者一些其他形状，例如通常多边形。
接着(图2)，在沟槽6的底壁6a处形成具有第二导电类型(在此，P+导电类型)的注入区域8，例如通过硼离子注入的步骤。更特别地，执行多个连续注入(例如从一次至三次注入)，每个以相应的注入能量注入，但是具有掺杂剂原子的相同剂量(或在限定范围中选择的各自剂量，例如多于一个数量级)。由此形成注入区域8，其从沟槽6的底壁6a以从底壁6a开始测量的若干微米的深度d1延伸。注入剂量借由示例的方式被包括在5·1014和5·1015原子/cm3之间，并且注入能量借由示例的方式包括在100keV和1000keV之间。
后续的在例如包括在900℃和1150℃之间的高温处，以30秒快速热处理(也已知为RTA或RTP)来激活注入区域8的掺杂剂，并使能其在结构层2中最小扩散，特别是深度。由此形成掺杂区域10(图3)，其具有从底壁6a开始测量的延伸d2，仅稍微大于d1且仅大若干微米。
作为RTA或RTP的备选，能够执行原位蒸气形成(ISSG)类型的氧化工艺，或者再次备选地，在烘炉中的氧化(湿式或干式)。
接着(图4)，将掺杂区域10转换为多孔硅区域12。
通常，多孔硅的结构从形态学的观点看呈现微孔的互联网络。微孔的大小、方向、位置和深度取决于在其形成期间设置的参数，以及其中形成多孔硅的区域的导电类型。
实际上，如已知的，基于其中形成微孔硅区域的密度和掺杂类型，多孔硅的形态不同。在本公开的上下文中，根据之前讨论的实施例，在P型硅的情形中，微孔的平均直径范围在1nm和100nm之间，并且获得的结构分支、高度互联且均匀。当用于形成掺杂区域10的掺杂剂的剂量增大时，微孔的直径以及它们之间的距离增大。本申请人已经注意到，注入剂量影响多孔硅生长速率以及多孔程度(特别地，掺杂剂的剂量越高，以全硅体积为代价，孔洞的体积越大)。
用于硅的阳极蚀刻的系统通常包括具有三个电极的单元，其中一个由单晶硅晶片100表示，其包含水性电解溶液。
晶片100相对于电解溶液位于正(阳极)电势处；晶片100的正面侧(具有沟槽6)被设置为与电解溶液直接接触。电解溶液通常由氟化氢(HF)、去离子水和乙醇构成。使用其他化合物以提高暴露至蚀刻的硅表面的可润性，减少在电化学反应期间在电极处所形成的氢气泡的形成。
将要形成的多孔硅区域12的特性(微孔的大小、方向、多孔率)显著地取决于在蚀刻步骤期间设置的参数，特别是取决于：
–溶液中电解质的成分，以及因此溶液中存在HF的百分比被选择在5％和48％之间；
–阳极化电流的数值，被选择在5mA/cm2和1000mA/cm2之间；
–蚀刻时间，被选择在5秒和500秒之间；
–衬底的电阻率(也即掺杂，如之前已经所述)；以及
–工艺期间溶液的温度，此处在室温下执行。
对于可以在黑暗中阳极化的P型硅区域，立即发生溶解反应。替代地，对于N型硅，利用光的存在。因此能够在注入区域10中选择性形成多孔硅区域。孔洞允许晶体硅的溶解化学反应，这发生在硅与电解溶液之间的界面处。
接着，执行图5的步骤，其中将多孔硅区域12转变为特别是氧化硅的电介质区域14。
多孔硅区域12的多孔特性使其能以极端情形转变为氧化硅(也已知为PSO，多孔氧化硅)。多孔硅实际上在低温下展现高氧化速率，氧化速率远远高于单晶硅。这基本上是由于广大表面暴露于如下工艺所致，该工艺使得在相对短时间内将要获得具有大厚度的多孔氧化硅层。
为此目的，在烘炉中高温执行氧化工艺(例如快速热处理，在1000℃温度，温度以5秒-30秒的间隔斜坡上升，以1分钟-10分钟间隔维持在该温度，并以30秒-60秒的间隔将温度斜坡下降至室温)。该快速热氧化(RTO)工艺将多孔硅区域12转变为低密度氧化硅的电介质区域14。
在此所述的热氧化工艺同样引起在沟槽6的侧壁6b上形成氧化物层，具有沿着轴线X测量的若干纳米的厚度d3。因此，减小了沟槽6的内部净容积。
接下来是(图6)例如经由化学气相沉积(CVD)形成电介质材料层16的步骤，其具有比电介质区域14的密度较高的密度，例如由TEOS(备选地，可以选择硼磷硅酸盐玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)以及玻璃上硅树脂(SOG))制成，直至完全填充了沟槽6。电介质材料层16填充沟槽6并且类似地沉积在晶片100上。
接着(图7)，执行各向异性等离子化学蚀刻以逐渐移除电介质材料层16和第三掩模层4c(两者在该示例中由TEOS制成)，直至在此用作蚀刻停止层的Si3N4的第二掩模层4b。电介质材料层16的一部分16’被保留在沟槽6内、底侧6a上，以完全覆盖并保护电介质区域14。
可选地，以HF进行进一步蚀刻(湿法蚀刻)以完全移除任何可能仍然存在于沟槽6的内壁6b上的氧化物。
随后(图8)，进行两步选择性化学蚀刻以相应移除第二掩模层4b和第一下层掩模层4a，直至暴露结构层2的第一侧2a。
随后接着是(图9)例如由热氧化在沟槽6的侧壁6b上(也即在与沟槽6内暴露的结构层2的界面处)以及在结构层2的第一侧2a上形成栅极氧化物层20的步骤。栅极氧化物层20具有例如包括在10nm和50nm之间的厚度。
接着(图10)，沉积具有第一导电类型(N)以及包括在1017原子/cm3和1019原子/cm3之间掺杂水平的掺杂多晶硅层22，以及(图11)，执行后续蚀刻步骤以用于从晶片100的正面移除掺杂多晶硅层22，除了沟槽6之外。换言之，在此为掺杂多晶硅N的沟槽导电区域24延伸在部分16’上沟槽6中，完全填充了沟槽6。
在未示出的不同实施例中，沟槽导电区域24仅部分填充沟槽6，从而停止在从第一侧2a沿着Z测量的、在100nm与沟槽6深度之间的距离处。
沟槽导电区域24至少部分地形成栅极电极，其由栅极氧化物层20(栅极电介质)与结构层2电绝缘。
接着，参照图12，采用注入掺杂种类并扩散的已知技术形成具有第二导电类型(P)的体区30，以及具有第一导电类型(N)、与沟槽6自对准(在此如之前所述已填充)的一个或多个源极区域32。
晶片100的加工可以随后继续(图13)，沉积前金属化电介质33，蚀刻后者以用于通过光刻打开电接触以便于到达并暴露栅极电极24和源极区域32的相应表面部分，分别沉积接触栅极电极24和源极区域32的一个或多个金属层，以及光刻定义所述金属层36以用于完成源极和栅极电极的形成(图13的剖视图专用于表示栅极金属化结构36)。在晶片背面上(在衬底1的第二侧1b上)进一步沉积使能形成漏极金属化结构38。
详细地，通过注入P型掺杂剂种类形成体区30以便于获得包括近似在1·1017离子/cm3和5·1017离子/cm3之间的掺杂水平。更详细地，在结构区域2中形成体区30，其沿Z方向的深度被包括例如近似在0.5μm和1.0μm之间。
源极区域32在体区30中延伸，面对结构区域2的第一侧2a，沿方向Z的深度被包括例如近似在100nm和150nm之间。源极区域32均具有例如近似1·1020离子/cm3的掺杂水平，并且在顶部平视图中延伸在栅极电极24旁，由电介质20与后者分离。
通过在晶片100上沉积导电材料，特别是金属，诸如铝，形成了栅极和源极金属化结构36。同样，也通过在晶片100的背面上沉积导电材料，特别是金属的步骤形成了漏极金属化结构38，由此完成了漏极端子的形成。
由此形成了垂直导电电子器件(在此，功率MOSFET)40。因此，在使用中，电流可以从源极区域32穿过结构区域2和衬底1垂直地(沿着Z)流动至漏极金属化结构38。
根据本公开的电子器件40借由示例的方式是以下之一：垂直导电功率MOS晶体管，功率绝缘栅极双极晶体管(LGBT)，或MCT(MOS受控晶闸管)。根据需要可以设想其他应用。
通过检查根据本公开所提供的本公开的一些特征，其提供的优点是明显的。
特别地，通过多孔硅的氧化形成电介质区域14是快速且远非昂贵的，并且显著的简化了根据现有技术的制造工艺。
进一步，电介质区域14具有低的介电常数值，这使得能够减小在导电多晶硅区域24(栅极)和结构层2的、在电介质区域14下方延伸的部分之间的寄生电容。
根据本公开的技术方案同样是可靠的，就多孔硅氧化物并未在与结构层2的界面处产生显著应力而言。因此，在其使用期限期间并未注意到工作参数的显著漂移或对于由此制造的电子器件的结构损伤。
最后，根据本公开的工艺是灵活的，就可以在注入区域10的注入和扩散步骤期间调节可以由电介质区域14到达深度而言。
最后，明显的是，可以对在此所述和所示的做出修改和改变，并未由此脱离本公开的范围。
特别地，本公开可以适用于制造与附图中所示不同的电子器件(例如，包括体区和/或源极区域的不同配置)。
上述各个实施例可以组合以提供进一步实施例。可以依照以上详述的说明对实施例做出这些和其他改变。通常，在以下的权利要求中，所使用的术语不应解释为将权利要求限定于说明书和权利要求书中所公开的具体实施例，而是应该解释为包括所有可能实施例以及该权利要求所授权的等价形式的全部范围。因此，权利要求不受公开内容的限制。

Claims (13)

1.一种半导体电子器件，包括：
半导体本体，具有第一导电类型并且具有沿着轴线彼此相对的第一侧和第二侧；
本体区，具有与所述第一导电类型相反的第二导电类型，在所述半导体本体中面对所述第一侧；
源极端子，具有所述第一导电类型，在所述本体区中至少部分地延伸；
漏极端子，具有所述第一导电类型，在所述半导体本体的所述第二侧处延伸；以及
沟槽栅极，其在所述半导体本体中从所述第一侧朝向所述第二侧延伸，穿过所述本体区和源极区域，
所述沟槽栅极包括被掩埋在所述半导体本体中的多孔氧化硅的电介质区域，以及在所述多孔氧化硅的电介质区域与所述第一侧之间延伸的栅极导电区域，
其中栅极电介质在所述栅极导电区域与所述半导体本体之间延伸，
其中所述沟槽栅极进一步包括在所述多孔氧化硅的电介质区域与所述栅极导电区域之间的保护区域，所述保护区域将所述多孔氧化硅的电介质区域与所述栅极导电区域分离，
其中所述保护区域由电介质材料或电绝缘材料制成，所述保护区域具有比所述电介质区域更高的密度。
2.根据权利要求1所述的器件，其中，所述栅极导电区域由掺杂多晶硅制成。
3.根据权利要求1所述的器件，在包括以下项的群组中被选择：垂直导电功率金属氧化物半导体(MOS)晶体管、功率绝缘栅极双极晶体管以及MOS受控晶闸管。
4.一种用于制造半导体电子器件的方法，包括：
在具有第一导电类型的半导体本体的第一侧处形成具有与所述第一导电类型相反的第二导电类型的本体区；
至少部分地在所述本体区中形成具有所述第一导电类型的源极端子；
形成从所述半导体本体的所述第一侧延伸穿过所述本体区和源极区域的沟槽；以及
在所述半导体本体的、与所述第一侧相对的第二侧处形成漏极端子，
在所述沟槽的底侧处以及在所述沟槽的空间延续中，在所述半导体本体中形成多孔硅区域；以及
氧化所述多孔硅区域以形成多孔氧化硅的电介质区域，
所述方法还包括以下步骤：
在多孔氧化硅电介质区域上的所述沟槽中形成保护区域，所述保护区域具有高于所述电介质区域的密度，其中所述保护区域为电介质材料或电绝缘材料；
在所述沟槽的内侧壁上形成栅极电介质；
在所述保护区域上的所述沟槽中形成栅极导电区域，使得所述栅极导电区域由所述保护区域与所述多孔氧化硅的电介质区域分离，并且使得所述栅极电介质在所述栅极导电区域和所述半导体本体之间延伸。
5.根据权利要求4所述的方法，其中，形成所述多孔硅区域包括：
在所述沟槽的底侧处、在所述半导体本体中注入具有所述第二导电类型的掺杂剂种类；
热激活所注入的掺杂剂种类以形成注入区域；以及
执行被设计用于将所述注入区域转变为所述多孔硅区域的电化学反应。
6.根据权利要求5所述的方法，其中，注入所述掺杂剂种类包括采用包括在100keV和1000keV之间的范围内的不同注入能量并且采用包括在5·1014原子/cm3和5·1015原子/cm3之间的相同注入剂量执行多个连续注入。
7.根据权利要求5所述的方法，其中，执行所述电化学反应包括：
将所述半导体本体插入水性电解溶液中，所述水性电解溶液包括百分比在5％和48％之间的氢氟酸；
将所述电解溶液维持在室温；以及
施加具有包括在5mA/cm2和1000mA/cm2之间的值的阳极化电流。
8.根据权利要求5所述的方法，其中，形成所述多孔硅区域进一步包括在900℃和1050℃之间的温度执行热氧化工艺，其中温度以5秒至60秒的间隔斜坡上升，并且以1分钟至10分钟的间隔维持恒定温度。
9.根据权利要求4所述的方法，进一步包括，在所述沟槽的侧壁处形成栅极电介质，所述栅极电介质被配置为将所述栅极导电区域与所述半导体本体绝缘。
10.根据权利要求4所述的方法，其中，形成所述保护区域包括在所述沟槽中沉积绝缘材料。
11.一种半导体电子器件，包括：
半导体本体，具有彼此相对的第一侧和第二侧；
本体区，在所述半导体本体中；
源极区域，在所述半导体本体中；
漏极区域，在所述半导体本体中；以及
沟槽栅极，在所述半导体本体中从所述第一侧朝向所述第二侧延伸，所述沟槽栅极包括被掩埋在所述半导体本体中的多孔氧化硅的电介质区域，以及在所述多孔氧化硅的电介质区域与所述第一侧之间延伸的栅极导电区域，
其中栅极电介质在所述栅极导电区域与所述半导体本体之间延伸，
其中所述沟槽栅极进一步包括在所述多孔氧化硅的电介质区域与所述栅极导电区域之间的保护区域，所述保护区域将所述多孔氧化硅的电介质区域与所述栅极导电区域分离，
其中所述保护区域由电介质材料或电绝缘材料制成，所述保护区域具有比所述电介质区域更高的密度。
12.根据权利要求11所述的器件，其中，所述沟槽栅极在所述半导体本体中延伸穿过所述本体区和所述源极区域。
13.根据权利要求11所述的器件，其中：
所述半导体本体具有第一导电类型；
所述本体区具有与所述第一导电类型相反的第二导电类型，并且面对所述第一侧；
所述源极区域具有所述第一导电类型并且在所述本体区中至少部分地延伸；以及
所述漏极区域具有所述第一导电类型并且在所述半导体本体的第二侧处延伸。
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