CN110021557B - 半导体装置封装及相关方法 - Google Patents

半导体装置封装及相关方法 Download PDF

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CN110021557B
CN110021557B CN201811440546.3A CN201811440546A CN110021557B CN 110021557 B CN110021557 B CN 110021557B CN 201811440546 A CN201811440546 A CN 201811440546A CN 110021557 B CN110021557 B CN 110021557B
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semiconductor
semiconductor device
support structure
stack
wafer
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CN110021557A (zh
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仲野英一
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Micron Technology Inc
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Micron Technology Inc
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

本申请案涉及半导体装置封装及相关方法。半导体装置封装可包含其中具有电连接的支撑结构。半导体装置模块可位于所述支撑结构的表面上。模制材料可至少部分地环绕所述支撑结构的所述表面上的每一半导体模块。热管理装置可在所述半导体装置模块的与所述支撑结构相对的一侧上操作性地连接到所述半导体装置模块。所述半导体装置模块中的至少一些可包含半导体裸片的堆叠，所述堆叠中的至少两个半导体裸片通过导电元件的导电材料的彼此扩散而彼此固定。

Description

半导体装置封装及相关方法
优选权主张
本申请案主张2017年12月1日申请的针对“半导体装置封装及相关方法(SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS)”的序列号为15/828,819的美国专利申请案的申请日的权益。
技术领域
本发明大体上涉及半导体装置封装及制作半导体装置封装的方法。更具体来说，所揭示的实施例涉及制作半导体装置封装的方法，其可降低封装高度并增加用于电连接的带宽，并且涉及此类半导体装置封装。
背景技术
电子工业中的一般趋势是减小组件的大小，同时增加所述组件的带宽。举例来说，晶片上芯片技术通常可消除个别半导体裸片的结合垫与半导体晶片之间的相对高或厚的导电元件(焊料凸块)，以有利于通过热压结合来促进较小的导电元件，例如铜柱及端子垫。额外技术试图减少专用于生产最终不起作用的封装的资源的花费。举例来说，扇出封装技术可结合使用合格的半导体裸片提供更多数量的针对信号及电力的引脚分配，仅使用被确认为在衬底上起作用的那些半导体裸片(通常称为“已知良好的裸片”)，并在已知良好的裸片周围形成重组晶片。然而，此类常规技术较昂贵并且需要额外设备及处理动作。
发明内容
通过执行根据本发明的方法产生的半导体装置结构可包含具有横向间隔封装位置的再分布层，每一封装位置包含导电迹线及在再分布层的相对侧上的电连接。半导体装置模块组可电连接到再分布层的表面上的对应封装位置。模制材料可至少部分地环绕再分布层上的每一半导体模块。每一组的半导体装置模块中的至少部分可包含通过其面向表面上的邻近导电元件之间的热压结合相互电连接的半导体裸片的堆叠。
根据本发明的半导体装置封装可包含其中具有电连接的支撑结构。半导体装置模块可位于支撑结构的表面上。模制材料可至少部分地环绕支撑结构的表面上的每一半导体模块，并且可连接到其电连接。半导体装置模块中的至少部分可包含在经单个化半导体晶片区段上的半导体裸片的堆叠，半导体裸片及经单个化半导体晶片区段通过热压结合及通孔电连接。模制材料可至少部分地环绕并接触支撑结构的表面上的每一半导体模块的每一半导体裸片及经单个化晶片区段的侧。
制作半导体装置封装的方法可涉及在半导体晶片的作用表面上的集成电路的横向间隔区上堆叠半导体裸片。位于半导体晶片附近的每一堆叠中的第一半导体裸片可通过热压结合连接到半导体晶片的集成电路的区。半导体裸片的每一堆叠可包含在其与第一半导体晶片相对的一侧上暴露的导电元件。可经由导电元件测试半导体裸片的每一堆叠。包括半导体裸片的堆叠及半导体晶片的集成电路的区的半导体装置模块可经单个化。在通过与半导体裸片的堆叠相对的集成电路的区的导电元件的测试期间被确认为起作用的半导体装置模块组可电连接到支撑结构的表面上的对应封装位置的电连接。每一半导体模块可在支撑结构的表面上被至少部分地环绕在模制材料中。可单个化半导体装置封装，每一半导体装置封装包括一组半导体装置模块及支撑结构的对应位置。
附图说明
虽然本发明以特别指出并清楚地主张特定实施例的权利要求书作出结论，但当结合附图阅读时，可从以下描述中更容易地确定本发明范围内的实施例的各种特征及优点，其中：图1是制作半导体装置封装的方法的第一阶段中的半导体晶片的一部分的示意性横截面侧视图；
图2是在制作半导体装置封装的方法的第二阶段中的包含导电元件的图1的半导体晶片的部分的示意性横截面侧视图；
图3是在制作半导体装置封装的方法的第三阶段中的临时固定到载体衬底的图2的半导体晶片的部分的示意性横截面侧视图；
图4是在制作半导体装置封装的方法的第四阶段中的减薄过程之后的图3的半导体晶片的部分的示意性横截面侧视图；
图5是在制作半导体装置封装的方法的第五阶段中的包含额外导电元件的图4的半导体晶片的部分的示意性横截面侧视图；
图6是在制作半导体装置封装的方法的第六阶段中的缺少载体衬底的图5的半导体晶片的部分的示意性横截面侧视图；
图7是在制作半导体装置封装的方法的第七阶段中的经单个化半导体裸片的示意性横截面侧视图；
图8是在制作半导体装置封装的方法的第八阶段中的堆叠在另一半导体晶片上的图7的半导体裸片的示意性横截面侧视图；
图9是在制作半导体装置封装的方法的第九阶段中的堆叠在图8的另一半导体晶片上的额外半导体裸片的示意性横截面侧视图；
图10是在制作半导体装置封装的方法的第十阶段中的用于测试图9的半导体裸片及其它半导体晶片的堆叠的测试设备的示意性透视图；
图11是在制作半导体装置封装的方法的第十一阶段中的在半导体装置模块的单个化期间的图10的半导体裸片及其它半导体晶片的示意性透视图；
图12是在制作半导体装置封装的方法的第十二阶段中的另一载体衬底的横截面侧视图；
图13是在制作半导体装置封装的方法的第十三阶段中的包含在其中具有电连接的支撑结构的图12的载体衬底的横截面侧视图；
图14是在制作半导体装置封装的方法的第十四阶段中的在其上包含图11的半导体装置模块的图13的支撑结构的横截面侧视图；
图15是在制作半导体装置封装的方法的第十四阶段中的包含模制材料的图11的支撑结构及半导体装置模块的横截面侧视图；
图16是在制作半导体装置封装的方法的第十六阶段中的缺少载体衬底的图15的支撑结构、半导体装置模块及模制材料的横截面侧视图；及
图17是从图16的支撑结构、半导体装置模块及模制材料形成的半导体装置封装的横截面侧视图。
具体实施方式
本发明中呈现的说明并不意在为任何特定半导体装置封装或其组件或在制作半导体装置封装的过程中的中间产品的组件的任何特定布置的实际视图，而仅仅是用于描述说明性实施例的理想化表示。因此，不一定按比例绘制图式。
所揭示的实施例大体上涉及制作半导体装置封装的方法，所述半导体装置封装可降低封装高度并增加电连接的带宽。更具体来说，所揭示的是制作半导体装置封装的方法的实施例，所述方法在形成与扇出封装的修改版本组合的半导体裸片的堆叠时可采用经修改的晶片上芯片技术，此时组装所述堆叠与其它电组件以产生半导体装置封装。
如在本说明书中所使用，关于给定参数、性质或条件的术语“大体上”及“约”意指并且在某种程度上包含所属领域的技术人员将理解给定参数、性质或条件在小变异度下得到满足，例如在可接受的制造公差内。举例来说，大体上或约为指定值或条件的参数可为指定值或条件的至少约90％，指定值或条件的至少约95％，或甚至指定值或条件的至少约99％。
图1展示根据本发明的制作半导体装置封装的方法的实施例的第一阶段中的第一半导体晶片100的一部分的横截面侧视图。半导体晶片100可包含作用表面102及非作用表面106，作用表面102承载集成电路104的相异横向间隔区，非作用表面106位于半导体晶片100的与作用表面102相对的一侧上，非作用表面106缺少此集成电路。半导体晶片100可包含半导体材料，例如(举例来说)硅。半导体晶片100中的集成电路104可经配置以执行期望的操作，例如(举例来说)充当计算机存储器(例如，快闪存储器、PROM、EPROM、EEPROM、DRAM、SRAM)。
盲孔108可从作用表面102朝向非作用表面106延伸。盲孔108可包含位于盲孔108内的导电材料110。导电材料110可包含金属或金属合金，例如(举例来说)铜、银、金、铝或其合金。导电材料110可提供到作用表面102的集成电路104的起作用的电连接。导电材料110可通过(例如)溅射或电镀定位在盲孔108中。盲孔108可定位在(例如)位于集成电路104的相异区的中心附近并在集成电路104的相异区的横向外围远端的镶嵌区(sets)中，集成电路104的相异区经配置以形成个别半导体裸片。换句话说，盲孔108可定位并相互布置，以界定邻近于将成为离散半导体裸片122的部分的中心线的两行，如下文描述。当然，盲孔108的位置不如此受限，可实现任何合适的布置，包含盲孔108的列及行的矩阵，或者邻近于预期裸片外围的盲孔108的一或多个行，这取决于裸片电路的功能性。盲孔108可通过例如各向异性蚀刻或激光钻孔形成。在其它实施例中，孔可不为盲孔108，而是可完全延伸穿过半导体晶片100的厚度，使得导电材料110可在作用表面102及非作用表面106处暴露。
图2是在制作半导体装置封装的方法的第二阶段中的包含第一组导电元件112的图1的半导体晶片100的部分的示意性横截面侧视图。第一组导电元件112可位于导电材料110的暴露端上，使得第一组导电元件112可操作性地及电连接到作用表面102的集成电路104。第一组导电元件112可包括例如由导电材料(例如，金属或金属合金)组成的柱、螺柱、球、凸块或垫。第一组导电元件112可利用例如球栅阵列形成、电镀或无电镀技术定位在盲孔108中的导电材料110上。
图3是在制作半导体装置封装的方法的第三阶段中的倒置并临时固定到载体衬底114的图2的第一半导体晶片100的部分的横截面侧视图。载体衬底114可经配置以在后续处置及处理期间在结构上支撑第一半导体晶片100。载体衬底114可包含例如半导体材料(例如，硅酮)、陶瓷材料或玻璃材料。第一半导体晶片100可通过粘合材料116固定到载体衬底114。更具体来说，粘合材料116可插入在第一半导体晶片100的作用表面102与载体衬底114之间。第一组导电元件112可至少部分地嵌入在粘合材料116的厚度内，使得导电元件112与载体衬底114的面向表面之间的粘合材料116的厚度可小于直接在作用表面102与载体衬底114之间延伸的粘合材料的厚度。当第一半导体晶片100固定到载体衬底114时，晶片100的非作用表面106可保持暴露。
图4是在制作半导体装置封装的方法的第四阶段中的减薄过程之后的图3的第一半导体晶片100的部分的横截面侧视图。可从非作用表面106去除第一半导体晶片100的半导体材料，以将第一半导体晶片100减薄到最终厚度。可从非作用表面106去除第一半导体晶片100的半导体材料，至少直到暴露先前称为盲孔108(现在简称为孔108)内的导电材料110。去除过程形成从作用表面102延伸到非作用表面106的通孔118，从而利用导电材料110提供作用表面102与非作用表面106之间的电连接。可利用例如研磨工艺、蚀刻工艺或其组合来减薄第一半导体晶片100，其中通常称为“背面研磨”的研磨从非作用表面106去除第一半导体晶片100的大部分材料，在这之后采用蚀刻工艺来暴露导电材料110而没有受到应力或涂抹导电材料110。
图5是在制作半导体装置封装的方法的第五阶段中的包含第二组导电元件120的图4的第一半导体晶片100的部分的横截面侧视图。第二组导电元件120可位于通孔118中的导电材料110的靠近非作用表面106的端部上，在通孔118的与第一组导电元件112相对的一侧上。第二组导电元件120可包含由导电材料(例如，金属或金属合金)组成的柱、螺柱、球、凸块或垫。第二组导电元件120可利用例如球栅阵列形成、电镀或无电镀技术定位在通孔118中的导电材料110上。在一些实施例中，可通过使测试设备(例如，一或多个探针)接触第一组导电元件112及第二组导电元件120中的任一或两者并检测集成电路104对所施加信号的响应来测试集成电路104的每一区的操作特性。
图6是在制作半导体装置封装的方法的第六阶段中的在以非导电膜的形式施加电介质底部填充材料140并去除载体衬底114(参见图5)之后的图5的第一半导体晶片100的部分的横截面侧视图。可通过例如弱化由粘合材料116(参见图5)提供的结合并使第一半导体晶片100及载体衬底114(参见图5)相对于彼此移位来去除载体衬底114(参见图5)。更具体来说，粘合材料116(参见图5)粘合可响应于暴露于热(例如，在炉中或来自激光器)而被弱化，并且可将载体衬底114(参见图5)横向滑动(即，在平行于第一半导体晶片100的作用表面102的方向上)或者相对于第一半导体晶片100从一侧提升到另一侧直到其间的粘合结合释放。
图7是制作半导体装置封装的方法的第七阶段中的经单个化半导体裸片122的横截面侧视图。第一半导体晶片100(参见图1到6)当被支撑在载体结构(例如膜框架或晶片卡盘)上时，可利用所属领域中已知的切割设备124(例如，锯)单个化成半导体裸片122，所述切割设备124可用于沿着集成电路104的邻近独立区之间的锯切道完全切穿第一半导体晶片100的半导体材料(参见图1到6)。所得半导体裸片122可包含例如承载集成电路104的作用表面102。第一组导电元件112可在作用表面102处暴露，并且通孔118可从第一组导电元件112延伸，穿过半导体裸片122，到在非作用表面106处暴露的第二组导电元件120。
图8是在制作半导体装置封装的方法的第八阶段中堆叠在第二半导体晶片126上的图7的半导体裸片122的横截面侧视图。第二半导体晶片126可包含半导体材料，例如硅，并且可具有作用表面128及非作用表面132，作用表面128承载集成电路130的相异横向间隔区，非作用表面132定位在第二半导体晶片126的与作用表面128相对的一侧上。集成电路130可经配置以执行所要操作，例如(举例来说)充当相关联计算机存储器的逻辑控制器。第二半导体晶片126可进一步包含从作用表面128延伸到非作用表面132的通孔134，位于通孔134的靠近作用表面128的一端处的第三组导电元件136及位于通孔134的靠近非作用表面132的相对端处的第四组导电元件138。第二半导体晶片可利用粘合材料141临时固定到载体衬底114，载体衬底114及粘合材料141可为与用于第一半导体晶片100的那些载体衬底及粘合材料相同的载体衬底114及相同类型的粘合材料141或与之不同。第二半导体晶片126可通过执行至少大体上类似于先前结合图1到5结合第一半导体晶片描述的动作的动作来形成。值得注意的是，第二半导体晶片126可为均质的硅晶片，而不是包括在将半导体裸片施加到其并随后封装及附接再分布层之前重新形成为重组晶片的数个先前经单个化晶片区段。因此，可减少制造时间及费用，并且避免来自将晶片区段处置及加工成重组晶片的潜在损害。
半导体裸片122可被倒置并定位在第二半导体晶片126上的集成电路130的区的对应的相互对准的位置上。举例来说，可使半导体裸片122的第一组导电元件112与集成电路130的区的第四组导电元件138接触，使得半导体裸片122的作用表面102可位于第二半导体晶片126的非作用表面132附近，且第二半导体晶片126的作用表面128可位于第二半导体晶片126的与半导体裸片122相对的一侧上。可施加压力以将半导体裸片122推向第二半导体晶片126，可控制气氛(例如，通过引入惰性气体，例如氩气，或者通过形成至少大体上真空)，并且可施加热量(例如，利用熔炉或激光器)。所施加的热量可例如小于第一组导电元件112及第四组导电元件138的金属或金属合金材料的熔化温度。第一组导电元件112及第四组导电元件138的金属或金属合金材料可彼此扩散，形成热压结合。已经预先放置在半导体裸片122上的底部填充材料140插入在半导体裸片122的作用表面102与第二半导体晶片126的非作用表面132之间。如上所述，底部填充材料140可为非导电膜。可使用其它底部填充材料代替非导电膜，例如，电介质毛细管底部填充物、预先施加的非导电膏或模制底部填充物。
特别是与其它技术相比，例如回流与另一个组件的端子垫接触的焊料球，利用第一组导电元件112及第四组导电元件138形成的电互连的高度可最小化，因为可使用热压结合。另外，热压结合可使得能够针对第一组导电元件112及第四组导电元件138使用更精细的间距，因为此技术可减少(例如，消除)熔化的金属材料可能横向流动并形成非计划电连接及后续短路的风险。举例来说，第一组导电元件112及第四组导电元件138中的每一者的间距(通过采用第一组导电元件112或第四组导电元件138的邻近对之间的最小横向距离来测量)可为约100μm或更小。更具体来说，第一组导电元件112及第四组导电元件138中的每一者的间距可为约90μm或更小。
图9是在制作半导体装置封装的方法的第九阶段中堆叠在图8的第二半导体晶片126上的额外半导体裸片122的横截面侧视图。虽然仅说明额外半导体裸片122的一个层级，但本发明不限于此。举例来说，第二半导体晶片126上的半导体裸片122的堆叠可包括四个、八个、十二个或十六个半导体裸片122。额外半导体裸片122可至少大体上类似于已经放置在第二半导体晶片126上并操作性地连接到第二半导体晶片126的半导体裸片122。另外，在一些实施例中，可利用热压结合将额外半导体裸片122固定到下伏半导体裸片122。举例来说，可使上覆半导体裸片122的第一组导电元件112可与下伏半导体裸片122的第二组导电元件120接触，使得上覆半导体裸片122的作用表面102可位于下伏半导体裸片122的非作用表面106附近，并且下伏半导体裸片122的作用表面102可位于下伏半导体裸片122的与上覆半导体裸片122相对的一侧上。可施加压力来推动半导体裸片122朝向彼此，可控制气氛，并且可施加热量，例如，小于第一组导电元件112及第二组导电元件120的金属或金属合金材料的熔化温度。第一组导电元件112及第二组导电元件120的金属或金属合金材料可彼此扩散，形成热压结合。底部填充材料140可插入在上覆半导体裸片122的作用表面102及下伏半导体裸片122的非作用表面106之间。在其它实施例中，可利用焊料放置及回流工艺将额外半导体裸片122固定到下伏半导体裸片122；然而，在此情况下可包括间距及组装高度要求。
半导体裸片122的完成堆叠的最大高度H1(如在至少大体上垂直于作用表面102的方向上从第二半导体晶片126的第四组导电元件138到最上面的半导体裸片122的第二组导电元件120测量)在堆叠中可为每半导体裸片122约0.1mm或更小。更具体来说，半导体裸片122的完成堆叠的最大高度H1在堆叠中可为例如每半导体裸片122约0.095mm或更少。作为特定非限制性实例，半导体裸片122的完成堆叠的最大高度H1在堆叠中可为每半导体裸片122约0.09mm或更少。作为特定实例，在半导体裸片122的八高堆叠的情况下，堆叠的高度可为小于约0.8mm。
图10是在制作半导体装置封装的方法的第十阶段中的用于测试图9的半导体裸片122的堆叠及第二半导体晶片126的测试设备142的一部分的示意性透视图。第二半导体晶片126及半导体裸片122的堆叠可支撑在晶片处置设备144上，例如(举例来说)卡盘或膜框架。可使可操作地耦合到测试控制器(未展示)的探测工具146(其包含在其下侧上的呈探针形式的电触点)靠近半导体裸片122的堆叠，可使电触点与暴露的第二组导电元件120进行物理及电接触，且可将信号从探针发送到半导体裸片122的堆叠中的每一者的第二组导电元件120中。半导体裸片122的每一堆叠的响应及第二半导体晶片126的对应位置可由探测工具146检测，并且响应可由测试设备142的测试控制器存储以用于半导体裸片122的操作性堆叠及第二半导体晶片126的对应位置的特性化及识别。
图11是在制作半导体装置封装的方法的第十一阶段中在半导体装置模块150的单个化期间的图10的半导体裸片122及第二半导体晶片126的透视图。在测试之后，切割设备152(例如，锯)(其可与切割设备124(参见图7)相同或不同)可在半导体裸片122的堆叠之间延伸并沿着集成电路104的邻近独立区之间的锯切道154切穿第二半导体晶片126的半导体材料，从而创建第二半导体晶片126的经单个化区段，每一区段承载先前经单个化半导体裸片的堆叠。所得半导体装置模块150可包含例如第二半导体晶片126的位置中的一者及其上的半导体裸片122的堆叠。
图12是制作半导体装置封装的方法的第十二阶段中的另一载体衬底156的横截面侧视图。载体衬底156可包含例如半导体材料(例如硅)、陶瓷材料或玻璃材料。载体衬底156的至少一个主表面158可包含分离材料160。主表面158的分离材料160可包含例如粘合材料。作为特定非限制性实例，分离材料160可包含例如光热转换释放涂层(LTHC)、LC-3200粘合材料或ATT-4025粘合剂材料，其每一者可从明尼苏达州梅普尔伍德的3M公司(3M ofMaplewood,MN)购得。
图13是在制作半导体装置封装的方法的第十三阶段中的包含在其中具有电连接164的支撑结构162的图12的载体衬底156的横截面侧视图。支撑结构162可包含例如再分布层，所述再分布层包括由电介质材料分离的一或多个层级的导电迹线。更具体来说，可通过以下步骤来形成呈再分布层形式的支撑结构162：在载体衬底156上循序地放置电介质材料166(例如光敏聚酰亚胺)的一或多层；通过光刻及蚀刻来图案化及去除电介质材料166的部分来在电介质材料166中形成呈某种图案的沟槽168的一或多个层级；并且在支撑结构162包括再分布层的实施例中将导电材料170放置在沟槽168中以形成用于电连接164的迹线。包括迹线的导电材料170的层级之间的垂直连接可通过图案化在迹线层级之间的电介质材料166的层级中的孔并填充有导体材料170来形成。除电连接164之外，例如电阻器、电容器及电感器的无源组件可形成在支撑结构162中，如此项技术中已知。
支撑结构162的电连接164可包含位于支撑结构162的与载体衬底156相对的一侧上的多个暴露的结合位置172。结合位置172可包含暴露用于支撑结构162的与载体衬底156相对的表面174处的电连接的导电材料170的部分。电连接164可进一步包含位于支撑结构162的靠近载体衬底156的一侧上的至少一个连接器位置176。连接器位置176可包含暴露用于通过分离材料160临时固定到载体衬底156的支撑结构162的另一表面178处的电连接的导电材料170的一或多个部分。
支撑结构162可比用于此类半导体装置模块的常规支撑件(例如(举例来说)印刷电路板)更薄。举例来说，支撑结构162的最大高度H2(如在至少大体上垂直于支撑结构162的主平面的方向上测量)可为约50μm或更小。更具体来说，支撑结构162的最大高度H2可为约45μm或更小。
支撑结构162可包含多个离散横向间隔封装位置182，每一封装位置经配置以接收一组半导体装置模块150，每一半导体装置模块包括其上的至少两个半导体装置模块150(参见图14)。然后，每一封装位置182可经配置用于与其它封装位置182分离以形成半导体装置封装。
图14是在制作半导体装置封装的方法的第十四阶段中的在其上包含图11的半导体装置模块150的图13的支撑结构162的横截面侧视图。可直接通过热压结合或经由中间导电元件180(例如，焊料球)使从每一半导体装置模块150中的第二半导体晶片126(参见图9)单个化的最下面的半导体裸片122(参见图9)的作用表面128(参见图9)上的第三组导电元件136与支撑结构162的对应结合位置172接触。半导体装置模块150可通过例如热压结合或执行焊料回流以将第三组导电元件136结合到对应结合位置172而物理地且操作性地连接到支撑结构162。
图15是在制作半导体装置封装的方法的第十四阶段中的包含电介质模制材料184的图11的支撑结构162及半导体装置模块150的横截面侧视图。在修改的扇出封装过程中，模制材料184可至少部分地围绕半导体装置模块150定位在支撑结构162的表面174上方。更具体来说，模制材料184的前体可至少横向围绕半导体装置模块150在支撑结构162的表面上方流动并随后固化以形成模制材料184。如果囊封半导体装置模块150的与支撑结构162相对的表面的模制材料是非所要的，那么可通过背面研磨将其去除到与模块表面共面的水平面。模制材料184可包含例如电介质囊封剂材料。作为特定非限制性实例，模制材料184可为液体化合物R4502-H1或R4502-A1，可从日本大阪的长濑产业株式会社(Nagase ChemteXCorp.of Osaka,Japan)购得；粒状化合物X89279，可从日本东京的住友商事株式会社(Sumitomo Corp.of Tokyo)购得；粉末化合物GE-100-PWL2-imp1c，来自日本东京的日立化学株式会社(Hitachi Chemical Co.,Ltd.ofTokyo)；粒状化合物XKE G7176，可从日本川口的京瓷化学株式会社(Kyocera ChemicalCorp.of Kawaguchi,Japan)购得；或片状化合物SINR DF5770M9或SMC-851，来自日本东京的信越化学工业株式会社(Shin-Etsu ChemicalCo.of Tokyo,Japan)。
在一些实施例中并且如上所述，半导体装置模块150可暴露在模制材料184与支撑结构162相对的表面处。举例来说，半导体装置模块150的与支撑结构162相对的表面及模制材料184的横向邻近半导体装置模块150的表面可为共面的，此布置有利于从半导体装置模块150的热传递，或者如下文描述的第二支撑结构的附接。在其它实施例中，半导体装置模块150可完全嵌入模制材料184内，使得半导体装置模块150的与支撑结构162相对的表面可隐藏在模制材料184内。
图16是在制作半导体装置封装的方法的第十六阶段中的缺少载体衬底156的图15的支撑结构162、半导体装置模块150及模制材料184的横截面侧视图。可通过例如弱化分离材料160(参见图15)并使支撑结构162及载体衬底156(参见图15)相对于彼此移位来去除载体衬底156(参见图15)。更具体来说，分离材料160(参见图15)可响应于暴露于热(例如，在熔炉中或来自激光器)而被弱化，载体衬底156(参见图15)可相对于支撑结构162横向滑动或从其提升直到其间的临时结合释放。
在这个制造阶段，可制造第二支撑结构(未展示)并将其连接到例如组合件的与支撑结构162相对的一侧上的离散封装位置182的最上面的半导体裸片122的导电元件120，以便提供额外信号及电力引脚。第二支撑结构可如上文关于结合图13的支撑结构162的制造所描述那样执行并如本文先前所描述那样连接。
换句话说，通过执行根据本发明的方法产生的半导体装置结构可包含具有横向间隔封装位置的再分布层，每一封装位置包含在再分布层的相对侧上的导电迹线及电连接。半导体装置模块组可电连接到再分布层的表面上的对应封装位置。模制材料可至少部分环绕再分布层上的每一半导体模块。每一组的半导体装置模块中的至少一些可包含通过其面向表面上的邻近导电元件之间的热压结合相互电连接的半导体裸片的堆叠。
图17是在图16的组合件经单个化为单独封装190之后从图16的支撑结构162、半导体装置模块150及模制材料184形成的半导体装置封装190的横截面侧视图。在一些实施例中，半导体装置封装190可包含热管理装置192，热管理装置192操作性地连接到半导体装置模块150的与支撑结构162相对的一侧上的半导体装置模块150。热管理装置192可在封装190的单个化之前或之后放置在半导体装置模块150上，并且如果是之前，那么与封装一起单个化。热管理装置192可经配置为例如散热片或散热器，或主动冷却系统。更具体来说，热管理装置192可包含大量高导热性材料(例如，铜、铝、其合金)，其位于半导体装置模块150的与支撑结构162相对的表面附近。在一些实施例中。可在半导体装置模块150与热管理装置192之间插入热界面材料。与提供类似功能性的常规组合件不同，半导体装置模块150及支撑结构162的减小的厚度可使热管理装置192能够与半导体装置封装190的其它组件一体地被包含在内，而不是仅在垂直空间允许时作为单独组件添加。
半导体装置封装190可进一步包含一组导电元件194，例如以着陆垫的形式，其可操作地连接到支撑结构162内的连接器位置176。导电元件194可经配置以操作性地将半导体装置封装190连接到接纳插座，并且可在支撑结构162的三个表面上方延伸。更具体来说，导电元件194可例如符合双列直插式存储器模块(DIMM)的标准化规范，并且可从支撑结构162的与半导体装置模块150相对的侧上的连接器位置176延伸，横向向外到支撑结构162的侧表面196，在侧表面196上方并在模制材料184的共面部分上方，并在位于模制材料184的与支撑结构162相对的一侧上的模制材料184的表面上方。
根据本发明的实施例，使用修改的扇出封装技术实现封装高度降低连同速度增益及功率耗散增强。此外，制造过程消除了过程动作，消除了一些设备，并降低最终组合件中采用的组件损坏的可能性。
换句话说，根据本发明的半导体装置封装可包含其中具有电连接的支撑结构。半导体装置模块可位于支撑结构的表面上。模制材料可至少部分地环绕支撑结构的表面上的每一半导体模块，并且可连接到其电连接。半导体装置模块中的至少一些可包含在经单个化半导体晶片区段上的半导体裸片的堆叠，半导体裸片及经单个化半导体晶片区段通过热压结合及通孔电连接。模制材料可至少部分地环绕并接触支撑结构的表面上的每一半导体模块的每一半导体裸片及经单个化晶片区段的侧。
制作半导体装置封装的方法可涉及在半导体晶片的作用表面上的集成电路的横向间隔区上堆叠半导体裸片。位于半导体晶片附近的每一堆叠中的第一半导体裸片可通过热压结合连接到半导体晶片的集成电路的区。半导体裸片的每一堆叠可包含在其与第一半导体晶片相对的一侧上暴露的导电元件。可经由导电元件测试半导体裸片的每一堆叠。包括半导体裸片的堆叠及半导体晶片的集成电路的区的半导体装置模块可经单个化。在通过与半导体裸片的堆叠相对的集成电路的区的导电元件的测试期间确认为起作用的半导体装置模块组可电连接到支撑结构的表面上的对应封装位置的电连接。每一半导体模块可在支撑结构的表面上被至少部分地环绕在模制材料中。可单个化半导体装置封装，每一半导体装置封装包括一组半导体装置模块及支撑结构的对应位置。
虽然已经结合图式描述某些说明性实施例，但所属领域的一般技术人员将认识并了解，本发明的范围不限于在本发明中明确展示及描述的那些实施例。而是，可对本发明中描述的实施例进行许多添加、删除及修改以产生本发明范围内的实施例，例如本文特定主张实施例，包含合法等效物。另外，如发明者所预期，来自一个所揭示的实施例的特征可与另一所揭示的实施例的特征组合，同时仍在本发明的范围内。

Claims (23)

1.一种制作半导体装置封装的方法，其包括：
在半导体晶片的作用表面上的集成电路的横向间隔区上堆叠半导体裸片，位于所述半导体晶片附近的每一堆叠中的第一半导体裸片通过热压结合连接到所述半导体晶片的集成电路的区，所述半导体裸片的每一堆叠包含在其与所述半导体晶片相对的一侧上暴露的导电元件；
经由所述导电元件测试所述半导体裸片的每一堆叠；
单个化半导体装置模块，所述半导体装置模块包括所述半导体裸片的堆叠及所述半导体晶片的集成电路的区；
将在通过与半导体裸片堆叠相对的集成电路的所述区的导电元件的测试期间确认为起作用的半导体装置模块组电连接到支撑结构的表面上的对应横向邻近的封装位置的电连接；
在单个化所述半导体装置模块以及将所述半导体装置模块组电连接到所述支撑结构的所述表面上的所述对应横向邻近的封装位置的所述电连接之后，将所述支撑结构的所述表面上的每一半导体模块的所述半导体晶片的侧表面至少部分地环绕在单一整块模制材料中；
将在测试期间确认为起作用的所述半导体装置模块组电连接到所述半导体装置模块的与所述支撑结构相对的所述侧的暴露表面上的另一支撑结构的表面上的对应封装位置的电连接；
单个化半导体装置封装，每一半导体装置封装包括一组所述半导体装置模块及所述支撑结构的对应位置；以及
在单个化所述半导体装置封装之后，在所述支撑结构的与所述一组所述半导体装置模块相对的一侧上形成操作性地连接到所述支撑结构的所述电连接的导电组件，所述导电组件从所述支撑结构的与所述半导体装置模块相对的侧上的连接器位置延伸，横向向外到所述支撑结构的侧表面，在所述侧表面上方并在所述模制材料的共面部分上方，并在位于所述模制材料的与所述支撑结构相对的侧上的所述模制材料的表面上方。
2.根据权利要求1所述的方法，其进一步包括在至少一组半导体装置模块的与所述支撑结构相对的一侧上将热管理装置放置在所述至少一组半导体装置模块上。
3.根据权利要求2所述的方法，其中将所述热管理装置放置在所述至少一组半导体装置模块上是在所述半导体装置封装的单个化之前实现。
4.根据权利要求1所述的方法，
其中将所述半导体装置模块组电连接到所述支撑结构的所述表面上的所述对应封装位置的电连接包括将所述半导体装置模块组电连接到再分布层的表面上的所述对应封装位置；以及
进一步包括在所述电连接所述半导体装置模块组之前形成所述再分布层。
5.根据权利要求4所述的方法，其进一步包括：
在载体上形成所述再分布层；以及
将所述半导体装置模块组电连接到支撑在所述载体上的所述再分布层。
6.根据权利要求1所述的方法，其进一步包括在所述半导体裸片的所述堆叠之前通过以下步骤形成所述半导体裸片：
在另一半导体晶片中制造通孔，所述另一半导体晶片包括作用表面及非作用表面，所述作用表面承载集成电路，所述非作用表面位于所述另一半导体晶片的与所述作用表面相对的一侧上；
将连接到所述通孔的第一组导电元件放置在所述作用表面上；
将连接到所述通孔的第二组导电元件放置在所述非作用表面上；以及
将所述半导体裸片彼此单个化。
7.根据权利要求6所述的方法，其中在所述另一半导体晶片中制造所述通孔包括形成从所述作用表面朝向所述非作用表面延伸的盲孔，以及用导电材料至少部分地填充所述盲孔。
8.根据权利要求7所述的方法，
其进一步包括减薄所述另一半导体晶片以从非作用表面去除所述另一半导体晶片的半导体材料以暴露位于所述盲孔内的所述导电材料。
9.根据权利要求6所述的方法，其进一步包括：在所述另一半导体晶片的单个化之前，在所述另一半导体晶片的面向所述半导体晶片的一侧上将非导电膜放置在所述另一半导体晶片的表面上方以进行所述堆叠。
10.根据权利要求1所述的方法，其进一步包括通过以下步骤在在所述半导体晶片上所述堆叠半导体裸片之前形成所述半导体晶片：
在承载另一半导体晶片的集成电路的区中制造通孔，所述另一半导体晶片包括作用表面及位于所述另一半导体晶片的与所述作用表面相对的一侧上的非作用表面；
将连接到所述通孔的第一组导电元件放置在所述作用表面上；以及
将连接到所述通孔的第二组导电元件放置在所述非作用表面上。
11.一种半导体装置封装结构，其包括：
支撑结构，其中包括电连接；
半导体装置模块，其彼此横向邻近地位于所述支撑结构的表面上并连接到所述支撑结构的所述电连接；
其中所述半导体装置模块中的至少一些包括：
半导体裸片的堆叠，其在经单个化半导体晶片区段上，所述半导体裸片及所述经单个化半导体晶片区段通过热压结合及通孔电连接；及
单一整块模制材料，其至少部分地环绕并接触所述支撑结构的所述表面上的每一半导体模块的每一半导体裸片及经单个化晶片区段的侧；以及
导电元件，其操作性地连接到所述支撑结构内的所述电连接，所述导电元件从所述支撑结构的与所述半导体装置模块相对的侧上的连接器位置延伸，横向向外到所述支撑结构的侧表面，在所述侧表面上方并在所述模制材料的共面部分上方，并在位于所述模制材料的与所述支撑结构相对的侧上的所述模制材料的表面上方。
12.根据权利要求11所述的半导体装置封装结构，其进一步包括热管理装置，所述热管理装置在所述半导体装置模块的与所述支撑结构相对的一侧上操作性地连接到所述半导体装置模块。
13.根据权利要求12所述的半导体装置封装结构，其中所述热管理装置包括散热器。
14.根据权利要求12所述的半导体装置封装结构，其中所述热管理装置包括散热片。
15.根据权利要求12所述的半导体装置封装结构，其中所述热管理装置包括主动冷却系统。
16.根据权利要求11所述的半导体装置封装结构，其中在垂直于所述堆叠中的所述半导体裸片的作用表面的方向上测量的所述堆叠的最大高度等于所述堆叠中每半导体裸片及晶片区段0.1mm乘以所述堆叠中的半导体裸片及晶片区段的数目或更小。
17.根据权利要求11所述的半导体装置封装结构，其中在垂直于所述堆叠中的所述半导体裸片的作用表面的方向上测量的所述支撑结构的最大高度为50μm或更小。
18.根据权利要求11所述的半导体装置封装结构，其中所述导电元件的间距为100μm或更小。
19.一种半导体装置结构，包括：
再分布层，其包括横向间隔封装位置，每一封装位置包括导电迹线及在所述再分布层的相对侧上的电连接；
横向邻近的半导体装置模块组，其电连接到所述再分布层的表面上的对应封装位置；
单一整块模制材料，其至少部分地横向环绕所述再分布层上的每一半导体模块；
其中每一组的所述半导体装置模块中的至少一些包括：
半导体裸片的堆叠，其通过所述半导体裸片的面向表面上的邻近导电元件之间的热压结合相互电连接；以及
导电元件，其操作性地连接到所述再分布层的所述电连接，所述导电元件从所述再分布层的与所述半导体装置模块相对的侧上的连接器位置延伸，横向向外到所述再分布层的侧表面，在所述侧表面上方并在所述模制材料的共面部分上方，并在位于所述模制材料的与所述再分布层相对的侧上的所述模制材料的表面上方。
20.根据权利要求19所述的半导体装置结构，其中所述半导体装置模块的与所述再分布层相对定位的表面及所述模制材料的横向邻近所述半导体装置模块而定位的表面是共面的。
21.根据权利要求19所述的半导体装置结构，其中半导体裸片的所述堆叠中的半导体裸片的数目是8，且其中在垂直于所述堆叠中的所述半导体裸片的作用表面的方向上测量的所述堆叠的最大高度为0.8mm或更小。
22.根据权利要求19所述的半导体装置结构，其中在垂直于所述堆叠中的所述半导体裸片的作用表面的方向上测量的所述再分布层的最大高度为50μm或更小。
23.根据权利要求19所述的半导体装置结构，其中所述导电元件的间距为100μm或更小。
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