CN110010496A - 一种带高密度侧壁焊盘的系统级封装互联结构的制作方法 - Google Patents
一种带高密度侧壁焊盘的系统级封装互联结构的制作方法 Download PDFInfo
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- CN110010496A CN110010496A CN201811596613.0A CN201811596613A CN110010496A CN 110010496 A CN110010496 A CN 110010496A CN 201811596613 A CN201811596613 A CN 201811596613A CN 110010496 A CN110010496 A CN 110010496A
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
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- 229910052716 thallium Inorganic materials 0.000 claims description 5
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
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- 229910052719 titanium Inorganic materials 0.000 claims description 5
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201811596613.0A CN110010496B (zh) | 2018-12-26 | 2018-12-26 | 一种带高密度侧壁焊盘的系统级封装互联结构的制作方法 |
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CN201811596613.0A CN110010496B (zh) | 2018-12-26 | 2018-12-26 | 一种带高密度侧壁焊盘的系统级封装互联结构的制作方法 |
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CN110010496A true CN110010496A (zh) | 2019-07-12 |
CN110010496B CN110010496B (zh) | 2023-04-28 |
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CN201811596613.0A Active CN110010496B (zh) | 2018-12-26 | 2018-12-26 | 一种带高密度侧壁焊盘的系统级封装互联结构的制作方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111952244A (zh) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | 一种柔性电路板侧壁互联工艺 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1260591A (zh) * | 1998-12-29 | 2000-07-19 | 现代电子产业株式会社 | 半导体封装及其制造方法 |
CN101542726A (zh) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | 具有硅通孔和侧面焊盘的半导体芯片 |
CN106206423A (zh) * | 2016-09-08 | 2016-12-07 | 华进半导体封装先导技术研发中心有限公司 | 芯片封装侧壁植球工艺 |
-
2018
- 2018-12-26 CN CN201811596613.0A patent/CN110010496B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1260591A (zh) * | 1998-12-29 | 2000-07-19 | 现代电子产业株式会社 | 半导体封装及其制造方法 |
CN101542726A (zh) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | 具有硅通孔和侧面焊盘的半导体芯片 |
CN106206423A (zh) * | 2016-09-08 | 2016-12-07 | 华进半导体封装先导技术研发中心有限公司 | 芯片封装侧壁植球工艺 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111952244A (zh) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | 一种柔性电路板侧壁互联工艺 |
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Inventor after: Feng Guangjian Inventor before: Feng Guangjian Inventor before: Wang Zhiyu Inventor before: Zhang Bing Inventor before: Zhou Qi Inventor before: Zhang Xun Inventor before: Yu Faxin |
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Effective date of registration: 20200804 Address after: 313100 Workshop No. 8, North Park, Second Division of Changxing National University Science and Technology Park, Chenwang Road and Taihu Road Intersection, Changxing County Economic and Technological Development Zone, Huzhou City, Zhejiang Province Applicant after: ZHEJIANG JIMAIKE MICROELECTRONIC Co.,Ltd. Address before: 310030 Building 6, No. 3, Xiyuan Third Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province Applicant before: HANGZHOU ZHENLEI MICROWAVE TECHNOLOGY Co.,Ltd. |
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