CN109994455B - One-dimensional arrangement double-sided misplaced three-dimensional detector, preparation method thereof and array - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L31/0224—Electrodes
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention discloses a one-dimensional arrangement double-sided misplaced three-dimensional detector, a preparation method and an array thereof, wherein the detector comprises a first trench electrode and a second trench electrode, and the first trench electrode and the second trench electrode are etched on the surface of a third semiconductor substrate respectively; the first trench electrode is embedded with a first central electrode, and a first semiconductor matrix is filled between the first central electrode and the first trench electrode; the second central electrode is embedded in the second groove electrode, and a second semiconductor matrix is filled between the second groove electrode and the second central electrode; the outer widths of the first trench electrode and the second trench electrode are 2R X, and the second trench electrode is positioned below the first trench electrode and is vertically separated by d3 and horizontally separated by Rx. And generating a silicon dioxide layer on the surface of the chip through a gettering oxidation process, transferring a detector pattern onto the silicon dioxide layer through marking and photoetching, etching and chemical deposition diffusion of a cathode electrode and an anode electrode, and finally repairing and packaging damage.
Description
Technical Field
The invention belongs to the technical field of photon (including X-ray, laser and X-ray free electron laser) or particle detection, and relates to a one-dimensional arrangement double-sided misplaced three-dimensional detector, a preparation method thereof and an array thereof.
Background
The detector is mainly used in the fields of high-energy physics, celestial physics, aerospace, military, medical technology and the like. The three-dimensional groove electrode detector has the advantages that the position resolution is equal to the length of the electrode spacing, if high position resolution is required, the electrode spacing is required to be small, so that the number of electronic reading paths is large, electronics is complex, and the cost is high; and the electrode spacing is small, so that breakdown can be caused, and the electrode is easier to break down under the condition of high depletion voltage. In addition, the central collector and the outer layer groove of the three-dimensional groove electrode silicon detector are formed by etching and filling, the width of the etched groove is related to the depth of the groove, namely the width-depth ratio of the deep etching technology can be 1:30, which means that a groove penetrating through a chip is etched in a chip with the thickness of 300 microns, the width of the groove is 10 microns at the minimum, and the groove cannot collect charges, so the groove cannot be used as a sensitive area and becomes a dead zone, and the dead zone area is increased and the area of the sensitive area is reduced due to the fact that the dead zone area is not small in the whole detector.
Disclosure of Invention
The invention aims to provide a one-dimensional arrangement double-sided misplaced three-dimensional detector, which solves the problems of complex electronics, easy breakdown and low position resolution caused by the fact that the sensitivity of the existing three-dimensional trench electrode detector is low and the number of electronic reading paths is large.
It is another object of the present invention to provide a one-dimensional array double-sided offset three-dimensional detector array.
The invention further aims to provide a preparation method of the one-dimensional arrangement double-sided misplaced three-dimensional detector.
In order to solve the technical problems, the technical scheme adopted by the invention is that the one-dimensional arrangement double-sided misplaced three-dimensional detector comprises a first groove electrode, a second groove electrode and a third semiconductor substrate, wherein the first groove electrode is etched on the upper surface of the third semiconductor substrate, and the second groove electrode is etched on the lower surface of the third semiconductor substrate; the first trench electrode is embedded with a first central electrode, and a first semiconductor matrix is filled between the first central electrode and the first trench electrode; the second semiconductor substrate is filled between the second trench electrode and the second central electrode; the outer length of the first trench electrode and the second trench electrode is 2R X, the second trench electrode is positioned below the first trench electrode, the upper surface of the second trench electrode is vertically separated from the lower surface of the first trench electrode by d3, and the center of the first central electrode is horizontally separated from the center of the second central electrode by Rx.
Further, the first trench electrode and the second trench electrode have the same specification, and are both hollow cylinder structures; the outer length and the outer width of the first groove electrode and the second groove electrode are equal; the first central electrode and the second central electrode have the same specification; the height of the third semiconductor substrate is the sum of the height of the first trench electrode, the height of the second trench electrode and the vertical distance d3 between the first trench electrode and the second trench electrode.
Further, the vertical distance d3 between the first trench electrode and the second trench electrode satisfies d3=r1=r2, r1 is the electrode spacing between the first trench electrode and the first central electrode, and r2 is the electrode spacing between the second trench electrode and the second central electrode; the first central electrode is positioned at the center of the first trench electrode, and the second central electrode is positioned at the center of the second trench electrode.
Further, the first central electrode and the second central electrode are both n-type heavily doped semiconductor matrixes; the first trench electrode and the second trench electrode are p-type heavily doped semiconductor matrixes; the first semiconductor substrate, the second semiconductor substrate and the third semiconductor substrate are p-type lightly doped semiconductor substrates or n-type lightly doped semiconductor substrates.
Further, the first central electrode and the second central electrode are p-type heavily doped semiconductor matrixes; the first trench electrode and the second trench electrode are both n-type heavily doped semiconductor matrixes; the first semiconductor substrate, the second semiconductor substrate and the third semiconductor substrate are p-type lightly doped semiconductor substrates or n-type lightly doped semiconductor substrates; the n-type semiconductor substrate, the p-type semiconductor substrate, the n-type heavily doped semiconductor substrate and the p-type heavily doped semiconductor substrate are all semiconductor substrates made of Si.
Further, the doping concentration of the first semiconductor substrate, the second semiconductor substrate and the third semiconductor substrate is 1×10 12cm-3; the doping concentration of the first groove electrode and the second groove electrode is 1 multiplied by 10 18cm-3～5×1019cm-3; the doping concentration of the first central electrode and the second central electrode is 1 multiplied by 10 18cm-3～5×1019cm-3; the n-type semiconductor substrate, the p-type semiconductor substrate, the n-type heavily doped semiconductor substrate and the p-type heavily doped semiconductor substrate can be replaced by semiconductor substrates made of any one of Ge, hgI 2、GaAs、TiBr、CdTe、CdZnTe、CdSe、GaP、HgS、PbI2 or AlSb.
The other technical scheme adopted by the invention is that the one-dimensional arrangement double-sided misplaced three-dimensional detector array is formed by arranging the one-dimensional arrangement double-sided misplaced three-dimensional detectors side by side.
The preparation method of the one-dimensional arranged double-sided misplaced three-dimensional detector adopts another technical scheme, and comprises the following specific steps:
step S1, cleaning and oxidizing: washing the chip with deionized water until the surface is free of floating dust, putting the chip into a clean oxidation furnace, and performing impurity absorption oxidation in a mixed gas of high-purity oxygen and high-purity nitrogen;
Step S2, high-precision marking and photoetching: corresponding photoetching marks are made at a plurality of positions on the chip, and a photoetching machine is aligned to the photoetching marks on the chip, so that a mask plate is accurately attached to the chip; after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that the detector pattern on the mask plate is transferred to the chip, and the detector pattern is developed;
Step S3, etching upper and lower anode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower peripheral grooves, adding phosphine gas into silane gas, and chemically depositing the mixed gas in the upper and lower peripheral grooves to generate polysilicon, so that the polysilicon is continuously diffused and filled in the upper and lower peripheral grooves, and forming anode electrodes, namely a first groove electrode and a second groove electrode;
Step S4, etching upper and lower cathode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower central grooves, and keeping the depths of the upper and lower central grooves consistent; adding diborane gas into silane gas, and chemically depositing the mixed gas in the upper and lower central grooves to generate polysilicon, so that the polysilicon is continuously diffused and filled in the upper and lower central grooves, and a cathode electrode, namely a first central electrode and a second central electrode, is manufactured;
Step S5, annealing: placing the chip in an annealing furnace, heating in a vacuum environment or a mixed gas of nitrogen and argon, preserving heat, and then cooling to room temperature to obtain an annealed chip;
Step S6, photoetching metallization, electrode extraction: after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that a detector pattern on the mask plate is transferred onto the chip, the mask plate pattern is developed, then oxide layers of a first groove electrode, a second groove electrode, a first central electrode and a second central electrode area on the chip after photoetching development are etched, and then metal is plated on the surface of the chip;
Step S7, packaging: the detector unit or array is marked on the silicon wafer, the detector unit or array is fixed on the supporting base, the electrode points on the detector are connected with the pins outside through welding by using metal wires, and finally the detector unit or array is sealed by using a plastic tube shell.
Further, in the step S1, the cleaning of the oxidation furnace is performed by adding halogen gas into the high-purity oxygen gas stream at a high temperature, wherein the volume percentage of the halogen gas is less than or equal to 15%.
Further, in the step S5, the temperature is raised to 700-1000 ℃, the annealing time is 50S-100 min, the temperature is raised to 50-1000S, and the heat preservation time is 2-10 min.
The one-dimensional arrangement double-sided staggered embedded three-dimensional detector, the preparation method and the array thereof have the advantages that firstly, the depth of a groove needing single-sided etching is reduced due to the adoption of double-sided etching, so that the widths of a central electrode and a groove electrode can be reduced by half, dead zones of the electrodes are greatly reduced, and when the heights of the detectors are consistent, the dead zones of the electrodes are only half of those of the conventional three-dimensional groove electrode detector, so that the dead zones of the electrodes are reduced, and the sensitivity is improved; secondly, the trench electrodes are not etched to the bottom, the distance between the two trench electrodes in the vertical direction is d3, the two trench electrodes can be kept from being in contact with each other, short circuit is avoided, and meanwhile chips can be mechanically connected with each other; d3 is equal to the distance between the trench electrode and the central electrode, so that when the detector is exhausted, the exhaust width in the vertical direction is approximately equal to the exhaust width in the horizontal direction, the electric field distribution in the detector can be more uniform, and the treatment is facilitated; the detected particle and photon transverse minimum position change of vertical incidence is thatThe minimum position change of the detected particles and photons which are vertically incident is smaller than that of the traditional detector, so that the position resolution is improved; the detector has large width and length, and the breakdown risk is greatly reduced; under the condition of keeping the same position resolution, the one-dimensional arrangement double-sided misplaced three-dimensional detector 2*1 array is equivalent to the traditional three-dimensional trench electrode detector 6*1 array, the number of electronic readout paths is small, the cost is low, and when the array with a large area is spliced, the difference of the two detectors in the number of electronic paths is more obvious.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a one-dimensional array double-sided misplaced three-dimensional detector;
FIG. 2 is a schematic diagram of another structure of a one-dimensional array double-sided misplaced three-dimensional detector;
FIG. 3 is a top view of a one-dimensional array of double-sided offset three-dimensional detectors;
FIG. 4 is a schematic diagram of an array of one-dimensional double-sided offset three-dimensional detectors 2*1;
FIG. 5 is a schematic diagram of a conventional array of three-dimensional trench electrode detectors 6*1;
FIG. 6 is a schematic diagram of an array of one-dimensional double-sided offset three-dimensional detectors 3*1;
FIG. 7 is a schematic diagram of another 3*1 array of one-dimensional array double-sided offset three-dimensional detectors.
In the figure, 1. First semiconductor substrate, 2. First trench electrode, 3. First center electrode, 4. Second semiconductor substrate, 5. Second trench electrode, 6. Second center electrode, 7. Third semiconductor substrate.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
The one-dimensional arrangement double-sided staggered embedded three-dimensional detector is shown in figures 1 to 3, and comprises a first groove electrode 2 and a second groove electrode 5 which are etched on a third silicon substrate 7 with the thickness of (d1+d2+d3) on two sides, wherein the specifications of the first groove electrode 2 and the second groove electrode 5 are the same; the first trench electrode 2 is of a hollow cylinder structure, and has an outer length of 2R Y, an outer width of 2R X and an outer height of d1; the first trench electrode 2 is embedded with a first central electrode 3, and a first semiconductor substrate 1 is filled between the first central electrode 3 and the first trench electrode 2; the second trench electrode 5 is located below the first trench electrode 2, and is vertically separated by d3 and horizontally separated by Rx, and d3=r1, r1 is the electrode distance between the first central electrode 3 and the first trench electrode 2; the second trench electrode 5 is a hollow cylinder structure, the outer length of which is 2R Y, the outer width of which is 2R X, the outer height of which is d2, and d2=d1, R X＝RY; the second trench electrode 5 is embedded with a second central electrode 6, a second semiconductor matrix 4 is filled between the second trench electrode 5 and the second central electrode 6, d3=r2, and r2 is the electrode distance between the second central electrode 6 and the second trench electrode 5; the first semiconductor substrate 1, the second semiconductor substrate 4 and the third semiconductor substrate 7 are all ultra-pure high-resistance silicon and are p-type silicon substrates with doping concentration of 1×10 12cm-3 (light doping); the first trench electrode 2 and the second trench electrode 5 are p-type heavily doped silicon matrixes with doping concentration of 1×10 18cm-3; the first central electrode 3 and the second central electrode 6 are n-type heavily doped silicon substrates with a doping concentration of 1 x 10 18cm-3.
Example 2
Unlike embodiment 1, the first trench electrode 2 and the second trench electrode 5 of this embodiment are p-type heavily doped silicon substrates having a doping concentration of 25×10 18cm-3; the first central electrode 3 and the second central electrode 6 are n-type heavily doped silicon substrates with a doping concentration of 25 x10 18cm-3.
Example 3
Unlike embodiments 1 to 2, the first trench electrode 2 and the second trench electrode 5 of this embodiment are p-type heavily doped silicon substrates having a doping concentration of 5×10 19cm-3; the first central electrode 3 and the second central electrode 6 are n-type heavily doped silicon substrates with a doping concentration of 5 x10 19cm-3.
Example 4
Unlike embodiments 1 to 3, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are p-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are n-type heavily doped silicon bodies having a doping concentration of 1×10 18cm-3; the first central electrode 3 and the second central electrode 6 are p-type heavily doped silicon substrates with a doping concentration of 1x 10 18cm-3.
Example 5
Unlike embodiments 1 to 4, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are p-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are n-type heavily doped silicon bodies having a doping concentration of 25×10 18cm-3; the first central electrode 3 and the second central electrode 6 are p-type heavily doped silicon substrates with a doping concentration of 25 x 10 18cm-3.
Example 6
Unlike embodiments 1 to 5, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are p-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are n-type heavily doped silicon bodies having a doping concentration of 5×10 19cm-3; the first central electrode 3 and the second central electrode 6 are p-type heavily doped silicon substrates with a doping concentration of 5 x 10 19cm-3.
Example 7
Unlike embodiments 1 to 6, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are n-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are p-type heavily doped silicon bodies having a doping concentration of 1×10 18cm-3; the first central electrode 3 and the second central electrode 6 are n-type heavily doped silicon substrates with a doping concentration of 1x 10 18cm-3.
Example 8
Unlike embodiments 1 to 7, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are n-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are p-type heavily doped silicon bodies having a doping concentration of 25×10 18cm-3; the first central electrode 3 and the second central electrode 6 are n-type heavily doped silicon substrates with a doping concentration of 25 x 10 18cm-3.
Example 9
Unlike embodiments 1 to 8, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are n-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are p-type heavily doped silicon bodies having a doping concentration of 5×10 19cm-3; the first central electrode 3 and the second central electrode 6 are n-type heavily doped silicon substrates with a doping concentration of 5 x 10 19cm-3.
Example 10
Unlike embodiments 1 to 9, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are n-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are n-type heavily doped silicon bodies having a doping concentration of 1×10 18cm-3; the first central electrode 3 and the second central electrode 6 are p-type heavily doped silicon substrates with a doping concentration of 1x 10 18cm-3.
Example 11
Unlike embodiments 1 to 10, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are n-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are n-type heavily doped silicon bodies having a doping concentration of 25×10 18cm-3; the first central electrode 3 and the second central electrode 6 are p-type heavily doped silicon substrates with a doping concentration of 25 x 10 18cm-3.
Example 12
Unlike embodiments 1 to 11, the first semiconductor body 1, the second semiconductor body 4, and the third semiconductor body 7 of this embodiment are n-type silicon bodies having a doping concentration of 1×10 12cm-3, and the first trench electrode 2 and the second trench electrode 5 are n-type heavily doped silicon bodies having a doping concentration of 5×10 19cm-3; the first central electrode 3 and the second central electrode 6 are p-type heavily doped silicon substrates with a doping concentration of 5 x 10 19cm-3.
The embodiments 4 to 6 provide the detectors of the embodiments 7 to 9 with the sensitive regions of p-type lightly doped silicon, the central electrode of p-type heavily doped silicon and the trench electrode of n-type heavily doped silicon so that the PN junction is located near the trench electrode, the sensitive regions of n-type lightly doped silicon, the central electrode of n-type heavily doped silicon and the trench electrode of p-type heavily doped silicon, and the PN junction is located near the trench electrode so that the electric field is smooth, the electric field variation is small, and the detectors are not easy to break down during operation. In addition, the heavy doping concentrations of the embodiment 4 and the embodiment 7 are optimal, so that damage is not formed in the doping process and the first semiconductor substrate 1, the second semiconductor substrate 4 and the third semiconductor substrate 7 are more easily depleted, because the heavy doping electrode has too large doping concentration, damage is formed in the doping process, and if the doping concentration is greater than 10 20cm-3, the damage is not easily removed, the heavy doping electrode has too small doping concentration, and a single-side abrupt junction cannot be formed, so that the first semiconductor substrate 1, the second semiconductor substrate 4 and the third semiconductor substrate 7 are not easily depleted. In the embodiments 1 and 4, the sensitive region is p-type lightly doped silicon, and in the embodiments 7 and 9, the sensitive region is n-type lightly doped silicon, so that the embodiments 1 and 4 are more resistant to radiation than the embodiments 7 and 9; in the embodiments 4 and 7, the PN junction is located near the trench electrode, the electric field is smooth, the electric field variation is small, and the PN junction is not easy to break down during operation. Thus, example 4 and example 7 are less prone to localized breakdown than example 1 and example 9. Under high radiation (high energy physical experiment), the performance is from strong to weak as example 4, example 1, example 7, example 9; at low radiation (e.g., photon detection), there is no significant difference in performance.
The detector is depleted along the first trench electrode 2 to the first central electrode 3 and depleted along the second trench electrode 6 to the second central electrode 5, so that the silicon substrate between the trench electrode and the central electrode is called depletion region or sensitive region, i.e. the first semiconductor substrate 1 and the second semiconductor substrate 4 are sensitive regions of the detector of the invention, which are both n-type silicon or p-type silicon, but since n-type silicon is converted into p-type silicon in a high radiation environment, p-type silicon is generally used in a high radiation environment, and the radiation resistance is better. The doping concentrations of the first semiconductor substrate 1 and the second semiconductor substrate 4 are selected so that the silicon substrate is ultra-pure high-resistance silicon, and the silicon substrate is the concentration of ultra-pure silicon which can be formed by the prior art, namely the concentration of ultra-pure silicon which just forms high-resistance silicon, the prior art cannot be used for preparing the silicon with the concentration being larger, the resistivity of the silicon with the concentration being smaller, and the leakage current is larger, so that the doping concentrations of the first semiconductor substrate 1, the second semiconductor substrate 4 and the third semiconductor substrate 7 are selected to be 1 multiplied by 10 12cm-3. The range of the heavily doped silicon doping concentration of the first trench electrode 2, the second trench electrode 5, the first central electrode 3 and the second central electrode 6 is to keep several orders of magnitude with the concentration difference of the first semiconductor substrate 1 and the second semiconductor substrate 4 (lightly doped silicon), so that a unilateral abrupt junction is formed, and the first semiconductor substrate 1, the second semiconductor substrate 4 and the third semiconductor substrate 7 are more easily depleted.
When R X and R Y are not equal, the central electrode is elongated, the capacitance is increased, and the energy resolution of the detector is reduced, so R X＝RY.
The maximum electric field of the PN junction near the trench electrode is far smaller than that of the PN junction near the center electrode, examples 4 to 6 set the first semiconductor substrate 1 and the second semiconductor substrate 4 to be p-type lightly doped silicon, the first center electrode 3 and the second center electrode 6 to be p-type heavily doped silicon, and the first trench electrode 2 and the second trench electrode 5 to be n-type heavily doped silicon, so that the PN junction near the first trench electrode 2 and the second trench electrode 5 is kept smooth, the electric field variation is small, the detector operating voltage is far greater than the depletion voltage, and the detector is not easily broken down during operation; and the first semiconductor substrate 1 and the second semiconductor substrate 4 are p-type semiconductor substrates, so that the radiation resistance is high.
The first trench electrode 2, the second trench electrode 5, the first central electrode 3 and the second central electrode 6 are provided as heavy doping with a doping concentration of 1 x 10 18cm-3～5×1019cm-3, the concentration difference between the semiconductor substrate and the lightly doped silicon (a semiconductor substrate 1 and a second semiconductor substrate 4) is kept to be several orders of magnitude, and a unilateral abrupt junction is formed, so that the breakdown voltage is different from the depletion voltage by several orders of magnitude, and the lightly doped silicon is more easily depleted.
The semiconductor detector preparation material is not limited to Si-based materials, and can be one of Ge, hgI 2、GaAs、TiBr、CdTe、CdZnTe、CdSe、GaP、HgS、PbI2 or AlSb, so that the application range is wide.
In theory, if the center electrode is located in the trench electrode, but if the center electrode is not located in the center of the trench electrode, the electric fields on both sides of the center electrode are larger and smaller, and the peak value of the signal (count rate) is reduced due to the difference, so that the peak width is widened, which is not beneficial to processing. It is preferred that the first central electrode 3 of the present invention is located at the center of the first trench electrode 2 and the second central electrode 6 is located at the center of the second trench electrode 5.
Since the number of electron-hole pairs generated by the incident mip particles in the detector medium is proportional to the path length traversed by the mip particles, the specifications of the first trench electrode 2 and the second trench electrode 5 are the same, and the specifications of the first central electrode 3 and the second central electrode 6 are the same, so that the number of electron-hole pairs generated by the incident mip particles in the first semiconductor substrate 1 and the second semiconductor substrate 4 (the sensitive region) are consistent, and the subsequent processing of read-out signals is facilitated.
The substrate with the thickness d3 is reserved in the middle of the third semiconductor substrate 7 and is not etched through, so that the first trench electrode 2 and the second trench electrode 5 can be kept from being contacted with each other, and short circuit is avoided; and mechanically interconnecting the first semiconductor body 1 and the second semiconductor body 4 and the third semiconductor body 7, ensuring that the detector does not fall off. In addition, d3=r1=r2, where r1 is the electrode distance between the first trench electrode 2 and the first central electrode 3, and r2 is the electrode distance between the second trench electrode 5 and the second central electrode 6, so that when the detector is depleted, the depletion width in the vertical direction is approximately equal to the depletion width in the horizontal direction, that is, the vertical distance between the first trench electrode 2 and the second trench electrode 6 is equal to the distance between the first trench electrode and the first central electrode, and is equal to the distance between the second trench electrode and the second central electrode, so that the electric field distribution inside the detector can be more uniform (the values of the electric fields are not greatly different); the values of the electric fields at two sides of the uneven electric field are larger and smaller, and the difference of the values of the electric fields can cause the peak value of the signal (counting rate) to be reduced, so that the peak width is widened, and the processing is not facilitated.
FIG. 3 is a top view of a one-dimensional array double-sided staggered three-dimensional detector with upper and lower collector numbers T, B, respectively consisting of trench electrodes, center electrodes, and semiconductor substrate, with the mipparticles incident normally, if T and B both have signals, indicating that the particles are in the overlapping region of T and B; if T has a signal, the particles are in the area where T is not overlapped with B; if B has a signal, it indicates that the particle is in a region where B does not overlap T. If the rectangular three-dimensional double-sided trench electrode detectors are arranged into a detector array, based on the principle, the incidence position of the perpendicular incidence mipparticles can be known according to the number of the collector T, B collecting the signals. According to the response conditions, one detector can be divided into three conditions of response of only an upper collector, response of both an upper collector and a lower collector and response of only the lower collector, and the detected particles and photons which are vertically incident have the minimum position change and are transversely: The position resolution of the traditional three-dimensional trench electrode silicon detector is strictly equal to the size of a unit, and the minimum position change of the vertical incidence particles and photons detected by the three-dimensional trench electrode silicon detector is smaller than that of the traditional detector, so that the position resolution is higher.
Fig. 4 shows an array of one-dimensional double-sided offset three-dimensional detectors 2*1, in which the upper and lower units are displaced R X in the x-direction. The detector upper and lower units have a 1/2 partial overlap at the chip level. According to the overlapping part between the units, the one-dimensional double-sided staggered three-dimensional detector 2*1 array is divided into a, b, c, d, e, f sections, which are respectively an upper unit response section in the first unit, an upper unit and a lower unit response section in the first unit, an upper unit response in the second unit, an upper unit and a lower unit response in the second unit, and a lower unit response in the second unit when particles are incident.
Because the position resolution of the conventional three-dimensional trench electrode silicon detector is strictly equal to the size of the cell, the array area of the conventional three-dimensional trench electrode detector 6*1 is equal to that of the one-dimensional double-sided staggered three-dimensional detector 2*1 array under the condition that the same position resolution is maintained. Fig. 5 is a schematic diagram of an array of conventional three-dimensional trench electrode detectors 6*1, in which the width and length of the conventional three-dimensional trench electrode silicon detector are small to easily break down the detector in order to maintain high position resolution. The one-dimensional arrangement double-sided misplaced three-dimensional detector can be large in width and length, and the breakdown risk is greatly reduced. And the array formed by the small-size detector units needs more electronic readout paths, has technical complexity and high cost, and as the conventional three-dimensional trench electrode detector 6*1 array needs six electronic readout paths, the one-dimensional arranged double-sided misplaced three-dimensional detector 2*1 array only needs 4, and when the array is spliced into a large-area array, the difference of the two detectors in the electronic paths is more obvious.
Fig. 6 and 7 are schematic views of an array of two-sided staggered three-dimensional detectors 3*1 according to the present invention, in which a 1 is an upper collector of the first detector composed of the first semiconductor substrate 1, the first trench electrode 2 and the first central electrode 3, b 1 is a lower collector of the first detector composed of the second semiconductor substrate 4, the second trench electrode 5 and the second central electrode 6, a 2 is an upper collector of the second detector, b 2 is a lower collector of the second detector, a 3 is an upper collector of the third detector, and b 3 is a lower collector of the third detector. The detector arrays shown in fig. 6 and fig. 7 have different performances due to the different shapes of the third semiconductor substrate 7, and the one-dimensional double-sided staggered three-dimensional detector 3*1 array shown in fig. 6 has a dead area larger than that of the one-dimensional double-sided staggered three-dimensional detector 3*1 array shown in fig. 7, but has fewer electronic readout paths; the one-dimensional array of double-sided offset three-dimensional detectors 3*1 shown in fig. 7 has a smaller dead area and a larger sensitive area than the one-dimensional array of double-sided offset three-dimensional detectors 3*1 shown in fig. 6, but has a correspondingly larger electronic readout path.
The dead zone volume of the detector is V＝(d1+d2)×((2RX)2-(2RX-2w)2+w2)＝(d1+d2)×(4RXw-3w2),, the dead zone volume of the detector is V＝(d1+d2+d3)×((2RX)2-(2RX-2w)2+w2)＝(d1+d2+d3)×(4RXw-3w2),w, the width of the grooves of the first groove electrode 2 and the second groove electrode 5 is reduced, and the sensitivity is improved; the position resolution of the detector is thatThe position resolution of the traditional detector is sigma X＝2RX, and the position resolution is improved.
The preparation method of the one-dimensional arrangement double-sided misplaced three-dimensional detector comprises the following specific steps:
Step S1, cleaning and oxidizing: and (3) cleaning the chip with deionized water until the surface is free of floating dust, putting the chip into a clean oxidation furnace, and performing impurity absorption oxidation in a mixed gas of high-purity nitrogen and high-purity oxygen.
The cleaning of the oxidation furnace is to add halogen gas into high-purity oxygen flow at high temperature, wherein the volume percentage of the halogen gas is less than or equal to 15%, the most common halogen gas is chlorine, most heavy metal atoms react with the chlorine to generate gaseous metal chloride, thereby greatly improving the cleanliness in the furnace, reducing ion contamination and improving the SiO 2/Si interface quality.
Through oxidation, an oxide layer is generated on the surface of the silicon wafer, so that dangling bonds on the surface of the silicon chip are reduced, surface passivation is achieved, and surface leakage current caused by external dirt is reduced. The introduction of oxygen can make the defects inside the chip more stable, reduce the recombination of carriers, improve the minority carrier lifetime of the chip, make the radiation resistance better, the leakage current lower, adsorb impurities, and make the impurities of the chip lower. And the oxide layer generated by high-temperature oxidation has hard texture, and can protect the chip from being scratched.
Step S2, high-precision marking and photoetching: corresponding photoetching marks are made at a plurality of positions on the chip, and a photoetching machine is aligned to the photoetching marks on the chip, so that a mask plate is accurately attached to the chip; after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that the detector pattern on the mask plate is transferred to the chip, and the detector pattern is developed;
Step S3, etching upper and lower anode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower peripheral grooves, adding phosphine gas into silane gas, and chemically depositing the mixed gas in the upper and lower peripheral grooves to generate polysilicon, so that the polysilicon continuously diffuses and fills the grooves to form anodes, namely a first groove electrode 2 and a second groove electrode 5;
Step S4, etching upper and lower cathode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower central grooves, and keeping the depths of the upper and lower central grooves consistent; adding diborane gas into silane gas, and chemically depositing the mixed gas in the upper and lower central grooves to generate polysilicon, so that the polysilicon continuously diffuses to fill the grooves, and forming cathodes, namely a first central electrode 3 and a second central electrode 6;
Step S5, annealing: placing the chip in an annealing furnace, heating in a vacuum environment or a mixed gas of nitrogen and argon, maintaining for a certain time, and then cooling to room temperature to obtain an annealed chip;
In the step S5, the temperature is 700-1000 ℃, the annealing time is 50S-100 min, the temperature is 50-1000S, and the heat preservation time is 2-10 min. The annealing aims to remove the damage in the chip, keep the temperature for a certain time to decompose the damage in the chip into simple defects, recover the minority carrier lifetime part, and prevent the leakage current and the depletion voltage of the chip from being too large due to the existence of the defects.
Step S6, photoetching metallization, electrode extraction: after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that a detector pattern on the mask plate is transferred onto the chip, the mask plate pattern is developed, then oxide layers in areas of a first groove electrode 2, a second groove electrode 5, a first central electrode 3 and a second central electrode 6 on the chip after photoetching development are etched, and metal is plated on the oxide layers;
Step S7, packaging: and drawing a detector unit array on the silicon wafer, fixing the detector unit array on a supported base, connecting electrode points on the detector with external pins through welding by using metal wires, and finally sealing by using a plastic tube shell to protect the detector chip and form the whole chip. Pins of the lead-out chip are utilized for connection to external devices.
It is noted that in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (7)
1. A preparation method of a one-dimensional arrangement double-sided misplaced three-dimensional detector is characterized in that,
The one-dimensional arrangement double-sided staggered embedded three-dimensional detector comprises a first groove electrode (2), a second groove electrode (5) and a third semiconductor substrate (7), wherein the first groove electrode (2) is etched on the upper surface of the third semiconductor substrate (7), and the second groove electrode (5) is etched on the lower surface of the third semiconductor substrate (7); the first trench electrode (2) is embedded with a first central electrode (3), and a first semiconductor substrate (1) is filled between the first central electrode (3) and the first trench electrode (2); the second trench electrode (5) is embedded with a second central electrode (6), and a second semiconductor substrate (4) is filled between the second trench electrode (5) and the second central electrode (6); the outer length of each of the first trench electrode (2) and the second trench electrode (5) is 2R X, the second trench electrode (5) is positioned below the first trench electrode (2), the upper surface of the second trench electrode (5) is vertically separated from the lower surface of the first trench electrode (2) by d3, and the center of the first central electrode (3) is horizontally separated from the center of the second central electrode (6) by Rx;
The vertical distance d3 between the first trench electrode (2) and the second trench electrode (5) satisfies d3=r1=r2, r1 is the electrode distance between the first trench electrode (2) and the first central electrode (3), and r2 is the electrode distance between the second trench electrode (5) and the second central electrode (6);
The first central electrode (3) is positioned at the center of the first trench electrode (2), and the second central electrode (6) is positioned at the center of the second trench electrode (5);
the method comprises the following specific steps:
step S1, cleaning and oxidizing: washing the chip with deionized water until the surface is free of floating dust, putting the chip into a clean oxidation furnace, and performing impurity absorption oxidation in a mixed gas of high-purity oxygen and high-purity nitrogen;
Step S2, high-precision marking and photoetching: corresponding photoetching marks are made at a plurality of positions on the chip, and a photoetching machine is aligned to the photoetching marks on the chip, so that a mask plate is accurately attached to the chip; after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that the detector pattern on the mask plate is transferred to the chip, and the detector pattern is developed;
Step S3, etching upper and lower anode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower peripheral grooves, adding phosphine gas into silane gas, and chemically depositing the mixed gas in the upper and lower peripheral grooves to generate polysilicon, so that the polysilicon is continuously diffused and filled in the upper and lower peripheral grooves to form anode electrodes, namely a first groove electrode (2) and a second groove electrode (5);
Step S4, etching upper and lower cathode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower central grooves, and keeping the depths of the upper and lower central grooves consistent; adding diborane gas into silane gas, and chemically depositing the mixed gas in the upper and lower central grooves to generate polysilicon, so that the polysilicon is continuously diffused and filled in the upper and lower central grooves, and a cathode electrode, namely a first central electrode (3) and a second central electrode (6), is manufactured;
Step S5, annealing: placing the chip in an annealing furnace, heating in a vacuum environment or a mixed gas of nitrogen and argon, preserving heat, and then cooling to room temperature to obtain an annealed chip;
Step S6, photoetching metallization, electrode extraction: after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that a detector pattern on the mask plate is transferred onto the chip, the mask plate pattern is developed, then oxide layers in areas of a first groove electrode (2), a second groove electrode (5), a first central electrode (3) and a second central electrode (6) on the chip after photoetching development are etched, and metal is plated on the surface of the chip;
Step S7, packaging: the detector unit or array is marked on the silicon wafer, the detector unit or array is fixed on the supporting base, the electrode points on the detector are connected with the pins outside through welding by using metal wires, and finally the detector unit or array is sealed by using a plastic tube shell.
2. The method for preparing a one-dimensional array double-sided misplaced three-dimensional detector according to claim 1, wherein the step S1 is characterized in that the step of cleaning the oxidation furnace is to add halogen gas into high-purity oxygen flow at high temperature, wherein the volume percentage of the halogen gas is less than or equal to 15%.
3. The method for manufacturing a one-dimensional array double-sided misplaced three-dimensional detector according to claim 1 or 2, wherein in the step S5, the temperature is raised to 700-1000 ℃, the annealing time is 50-100 min, the temperature is raised to 50-1000S, and the heat preservation time is 2-10 min.
4. The method for manufacturing a one-dimensional arranged double-sided misplaced three-dimensional detector according to claim 1, wherein the first trench electrode (2) and the second trench electrode (5) have the same specification and are both of a cylindrical structure with hollow inside;
the outer length and the outer width of the first groove electrode (2) and the second groove electrode (5) are equal;
The first central electrode (3) and the second central electrode (6) have the same specification;
The height of the third semiconductor substrate (7) is the sum of the height of the first trench electrode (2), the height of the second trench electrode (5) and the vertical distance d3 between the two.
5. The method for manufacturing a one-dimensional arranged double-sided misplaced three-dimensional detector according to claim 1, wherein the first central electrode (3) and the second central electrode (6) are both n-type heavily doped semiconductor matrixes;
The first trench electrode (2) and the second trench electrode (5) are p-type heavily doped semiconductor matrixes;
The first semiconductor substrate (1), the second semiconductor substrate (4) and the third semiconductor substrate (7) are p-type lightly doped semiconductor substrates or n-type lightly doped semiconductor substrates.
6. The method for manufacturing a one-dimensional arranged double-sided misplaced three-dimensional detector according to claim 1, wherein the first central electrode (3) and the second central electrode (6) are p-type heavily doped semiconductor matrixes;
the first trench electrode (2) and the second trench electrode (5) are both n-type heavily doped semiconductor matrixes;
The first semiconductor substrate (1), the second semiconductor substrate (4) and the third semiconductor substrate (7) are p-type lightly doped semiconductor substrates or n-type lightly doped semiconductor substrates;
The n-type lightly doped semiconductor substrate, the p-type lightly doped semiconductor substrate, the n-type heavily doped semiconductor substrate and the p-type heavily doped semiconductor substrate are all semiconductor substrates made of Si.
7. The method for manufacturing a one-dimensional arranged double-sided misplaced three-dimensional detector according to claim 5 or 6, characterized in that the doping concentration of the first semiconductor substrate (1), the second semiconductor substrate (4) and the third semiconductor substrate (7) is 1 x 10 12cm-3;
The doping concentration of the first trench electrode (2) and the second trench electrode (5) is 1 multiplied by 10 18cm-3～5×1019cm-3;
The doping concentration of the first central electrode (3) and the second central electrode (6) is 1 multiplied by 10 18cm-3～5×1019cm-3;
The n-type lightly doped semiconductor substrate, the p-type lightly doped semiconductor substrate, the n-type heavily doped semiconductor substrate and the p-type heavily doped semiconductor substrate can be replaced by semiconductor substrates made of any one of Ge, hgI 2、GaAs、TiBr、CdTe、CdZnTe、CdSe、GaP、HgS、PbI2 or AlSb.
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