CN114447149B - Edge incidence detector and manufacturing method thereof - Google Patents
Edge incidence detector and manufacturing method thereof Download PDFInfo
- Publication number
- CN114447149B CN114447149B CN202210036573.4A CN202210036573A CN114447149B CN 114447149 B CN114447149 B CN 114447149B CN 202210036573 A CN202210036573 A CN 202210036573A CN 114447149 B CN114447149 B CN 114447149B
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer
- forming
- edge
- detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 278
- 238000002955 isolation Methods 0.000 claims abstract description 59
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 210000000746 body region Anatomy 0.000 claims abstract description 37
- 239000002344 surface layer Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 56
- 239000000758 substrate Substances 0.000 claims description 37
- 239000004020 conductor Substances 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 8
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 66
- 238000005468 ion implantation Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000002591 computed tomography Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006388 chemical passivation reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000002059 diagnostic imaging Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/085—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors the device being sensitive to very short wavelength, e.g. X-ray, Gamma-rays
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Plasma & Fusion (AREA)
- Measurement Of Radiation (AREA)
Abstract
The invention provides an edge incidence detector and a manufacturing method thereof, wherein the detector comprises a semiconductor layer, an isolation layer, a first electrode layer, a conducting layer and a second electrode layer, wherein the semiconductor layer comprises a first conductive type doped layer positioned on the surface layer of the back surface of the semiconductor layer and a plurality of second conductive type body regions positioned on the surface layer of the front surface of the semiconductor layer, the isolation layer is positioned on the upper surface of the semiconductor layer and comprises a plurality of grooves which are arranged at intervals and first openings positioned at the bottoms of the grooves and exposing a body region, the first electrode layer is positioned on the upper surface of the isolation layer and fills the grooves and is electrically contacted with the body region through the first openings, the conducting layer is positioned on the side walls of the semiconductor layer and the isolation layer and is electrically contacted with the doped layer, and the second electrode layer is positioned on the back surface of the semiconductor layer and is electrically contacted with the doped layer. According to the invention, the first conductive type conductive layer which is in electrical contact with the semiconductor layer is arranged on the side wall of the semiconductor layer, so that the arrangement of the guard ring is avoided, the dead area is reduced, and the collection efficiency of X-rays is improved.
Description
Technical Field
The invention belongs to the field of X-ray detectors, and relates to an edge incidence detector and a manufacturing method thereof.
Background
The photon counting X-ray detector can analyze each incident photon as an independent event, can count the X-ray energy division region of a wide energy spectrum and judge the energy division region to which the photon counting X-ray detector belongs, thereby having energy spectrum resolution capability and excellent performance when applied to medical imaging equipment such as a Computed Tomography (CT).
Because of the low atomic number of silicon, in high-energy X-ray detection by computed tomography (Computed Tomography, CT), the silicon detector is required to be vertically placed so that the X-rays are incident from the side to increase the absorption depth of the X-rays, i.e., deep silicon detection.
To maximize the sensitive area of the detector, the detector operates in a fully depleted state, requiring at least 200V high voltage for a 500 μm thick silicon substrate, which increases the electric field at the surface, easily causing device breakdown; if the lateral depletion region expands to the lattice-damaged region introduced by the slice, the leakage current of the device increases.
At present, a plurality of suspension protection rings are generally arranged around a pixel of an edge incidence silicon strip detector to expand a surface electric field, so that breakdown voltage is increased, peripheral leakage is collected by a first protection ring, and leakage current of a pixel area is reduced. As shown in fig. 1 and fig. 2, a top view of the multi-guard ring detector structure and a cross-sectional structure of the multi-guard ring detector are shown, which include a guard ring 01, a contact hole 02, a pixel 03, a substrate 031, a body 032, a doped layer 033, a front electrode 034, a back electrode 035 and an isolation layer 036. The more guard rings, the more pronounced is the effect on increasing breakdown voltage. The overall width of the guard ring is typically 1.5 to 3 times the thickness of the substrate. However, the guard ring may form a dead zone for the detector, which in turn may cause the X-rays incident on the region to be unable to be collected, making the X-ray collection less efficient.
Therefore, there is an urgent need to find an edge incidence detector that improves the X-ray collection efficiency, reduces the dead area of the detector and avoids the use of guard rings over large areas.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an edge incidence detector and a manufacturing method thereof, which are used for solving the problems of large dead area and low X-ray collection efficiency caused by the application of protection rings in the prior art detector.
To achieve the above and other related objects, the present invention provides a method for manufacturing an edge-incidence detector, comprising the steps of:
providing a first conductivity type detector wafer, and forming a first conductivity type doped layer on the back surface of the wafer, wherein the wafer comprises at least one detector forming area;
providing a supporting substrate, bonding the wafer to the bearing substrate, enabling the back surface of the wafer to face the bearing substrate, and thinning the wafer to a preset thickness from the front surface of the wafer;
forming an isolation layer on the front surface of the wafer, forming a plurality of grooves in the isolation layer at intervals, and forming a second conductive type body region in the wafer through the grooves;
forming a groove penetrating through the isolation layer and the wafer at the edge of the detector forming area, wherein the bottom of the groove exposes the supporting substrate, a first conductive type conductive layer is formed on the side wall of the groove, and the conductive layer is in electrical contact with the doped layer;
forming a first opening at the bottom of the groove to expose the body region;
and forming a first electrode layer which is electrically contacted with the body region through the first opening, removing the bearing substrate, and forming a second electrode layer which is electrically contacted with the doping layer on the back surface of the wafer to form the detector.
Optionally, after thinning, the thickness of the wafer ranges from 150 μm to 500 μm.
Optionally, the thickness of the isolation layer ranges from
Optionally, the distance between the bottom of the groove and the front surface of the wafer is in the range of
Optionally, the body region is formed further comprising a step of annealing the activation impurity.
Optionally, forming the trench further includes the steps of:
forming a hard mask layer covering the isolation layer and filling the grooves on the upper surface of the isolation layer, and patterning the hard mask layer;
etching the isolation layer and the wafer based on the hard mask layer to form the groove penetrating through the isolation layer, the wafer and the bottom to expose the supporting substrate, and removing the hard mask layer.
Optionally, the width of the trench ranges from 15 μm to 25 μm.
Optionally, the method of forming the trench includes deep reactive ion etching.
Optionally, forming the conductive layer further includes the steps of:
forming a conductive material layer in the inner wall of the groove, the upper surface of the isolation layer and the groove;
and removing the conductive material layer on the upper surface of the isolation layer and in the groove to form the conductive layer on the inner wall of the groove.
Optionally, after forming the first electrode layer, a passivation layer is formed on an upper surface of the first electrode layer.
The invention also provides an edge incidence detector comprising:
a semiconductor layer including a first conductivity type doped layer located on a back surface layer of the semiconductor layer and a plurality of second conductivity type body regions located on a front surface layer of the semiconductor layer;
the isolation layer is positioned on the upper surface of the semiconductor layer and comprises a plurality of grooves which are arranged at intervals and a first opening which is positioned at the bottom of the grooves and exposes the body region;
a first electrode layer which is positioned on the upper surface of the isolation layer, fills the groove and is electrically contacted with the body region through the first opening;
the conductive layer is positioned on the side surfaces of the semiconductor layer and the isolation layer and is electrically contacted with the doped layer;
and the second electrode layer is positioned on the back surface of the semiconductor layer and is electrically contacted with the doped layer.
Optionally, the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type.
Optionally, a passivation layer is further disposed on the upper surface of the first electrode layer.
Optionally, the width of the first opening is smaller than the width of the bottom of the groove.
As described above, the edge incidence detector and the manufacturing method thereof of the invention adopt a deep reactive ion etching method to form a trench with the bottom of the detector forming region exposing the supporting substrate, thereby avoiding the lattice damage caused by the blade slicing, avoiding the overlarge leakage current, omitting the introduction of a protection ring for preventing the overlarge leakage current at the edge of the detector, reducing the area of dead zone, improving the filling factor (the ratio of photosensitive area to the whole pixel area) of the sensitive region of the detector, improving the collection efficiency of X-rays, forming a first conductive type conductive layer electrically contacted with the doped layer at the side wall of the trench, preventing the overlarge leakage current caused by lattice defects in the wafer when the trench is formed, and enabling the conductive layer at the side wall of the trench to be extension of the back plate ohmic contact, thereby obtaining the sensitive detector edge. In addition, the second electrode of the detector can be led to the front surface of the wafer through the conducting layer, so that the detector can be packaged conveniently, and the method has high industrial utilization value.
Drawings
Fig. 1 shows a top view of a multi-guard ring edge incidence detector.
FIG. 2 is a schematic cross-sectional view of a multi-guard ring edge incidence detector.
FIG. 3 is a flow chart of a method of fabricating an edge-incidence detector according to the present invention.
Fig. 4 is a schematic cross-sectional view showing a doped layer formed by the method for fabricating an edge incidence detector according to the present invention.
Fig. 5 is a schematic cross-sectional view showing a bonding support substrate of the method for manufacturing an edge incidence detector according to the present invention.
Fig. 6 is a schematic cross-sectional view of a thinned wafer front surface of the edge incidence detector according to the method of the present invention.
Fig. 7 is a schematic cross-sectional view showing a structure of an edge incidence detector according to the present invention after forming an isolation layer.
Fig. 8 is a schematic cross-sectional view showing a structure of the edge incidence detector according to the present invention after forming grooves.
Fig. 9 is a schematic cross-sectional view showing a structure of a body region formed by the method for fabricating an edge incidence detector according to the present invention.
Fig. 10 is a schematic cross-sectional view showing a structure of the edge incidence detector according to the present invention after forming a trench.
Fig. 11 is a schematic cross-sectional view showing a structure of the edge incidence detector according to the present invention after forming a conductive material layer.
Fig. 12 is a schematic cross-sectional view showing a conductive layer formed by the method for manufacturing an edge incidence detector according to the present invention.
Fig. 13 is a schematic cross-sectional view showing a first electrode layer formed by the method for manufacturing an edge incidence detector according to the present invention.
Fig. 14 is a schematic cross-sectional view showing a second electrode layer formed by the method for manufacturing an edge incidence detector according to the present invention.
Description of element reference numerals
01. Protection ring
02. Contact hole
03. Pixel dot
031. Substrate and method for manufacturing the same
032. Body region
033. Doped layer
034. Front electrode
035. Back electrode
036. Isolation layer
1. Wafer with a plurality of wafers
10. Detector formation area
11. Doped layer
12. Body region
13. Groove(s)
2. Support substrate
3. Isolation layer
31. Groove
32. An opening
4. Conductive material layer
41. Conductive layer
5. A first electrode layer
6. A second electrode layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 3 to 14. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a method for manufacturing an edge incidence detector, as shown in fig. 3, which is a flowchart for forming the method for manufacturing the edge incidence detector, and includes the following steps:
s1: providing a first conductivity type detector wafer, and forming a first conductivity type doped layer on the back surface of the wafer, wherein the wafer comprises at least one detector forming area;
s2: providing a supporting substrate, bonding the wafer to the bearing substrate, enabling the back surface of the wafer to face the bearing substrate, and thinning the wafer to a preset thickness from the front surface of the wafer;
s3: forming an isolation layer on the front surface of the wafer, forming a plurality of grooves in the isolation layer at intervals, and forming a second conductive type body region in the wafer through the grooves;
s4: forming a groove penetrating through the isolation layer and the wafer at the edge of the detector forming area, wherein the bottom of the groove exposes the supporting substrate, a first conductive type conductive layer is formed on the side wall of the groove, and the conductive layer is in electrical contact with the doped layer;
s5: forming a first opening at the bottom of the groove to expose the body region;
s6: and forming a first electrode layer which is electrically contacted with the body region through the first opening, removing the bearing substrate, and forming a second electrode layer which is electrically contacted with the doping layer on the back surface of the wafer to form the detector.
Referring to fig. 4 to 6, the steps S1 and S2 are performed: providing a first conductivity type detector wafer 1, and forming a first conductivity type doped layer 11 on the back surface of the wafer 1, wherein the wafer 1 comprises at least one detector forming area; a supporting substrate 2 is provided, the wafer 1 is bonded to the carrier substrate 2, and the back surface of the wafer 1 faces the carrier substrate 1, and the wafer 1 is thinned from the front surface of the wafer 1 to a predetermined thickness.
Specifically, the wafer 1 is a semiconductor wafer of a first conductivity type with high resistivity. In this embodiment, the first conductivity type is N-type, and an N-type silicon wafer with high resistivity is selected as the wafer 1, where the wafer 1 includes one of the probe forming regions.
Specifically, as shown in fig. 4, in order to form the cross-sectional structure of the doped layer 11, the doped layer 11 is formed on the back surface of the wafer 1 by ion implantation or other suitable methods. In this embodiment, a phosphorus ion source is used to perform ion implantation from the back surface of the wafer 1 by using an ion implantation method, where the phosphorus ion source includes phosphorus to obtain the doped layer 11, and the thickness of the doped layer 11 is determined according to practical situations and is not limited.
Specifically, the material of the support substrate 2 may include one of glass, ceramic and semiconductor, or may be other suitable materials. In this embodiment, a semiconductor wafer is used as the support substrate 2.
Specifically, as shown in fig. 5, for schematically illustrating a cross-sectional structure of the wafer 1 after bonding to the support substrate 2, the method for bonding the wafer 1 to the support substrate 2 includes adhesion, electrostatic bonding, direct bonding, or other suitable methods.
Specifically, the method for thinning the wafer 1 includes chemical mechanical polishing or other suitable methods.
As an example, as shown in fig. 6, the thickness of the wafer 1 after thinning is in the range of 150 μm to 500 μm, which is a schematic cross-sectional structure of the wafer 1 after thinning.
Referring to fig. 7 to 9, the step S3 is performed: an isolation layer 3 is formed on the front surface of the wafer 1, a plurality of grooves 31 are formed in the isolation layer 3 at intervals, and a second conductive type body region 12 is formed in the wafer 1 through the grooves 31.
Specifically, the method of forming the isolation layer 3 includes a thermal oxidation method, a chemical vapor deposition method, a physical vapor deposition method, or other suitable method.
As an example, as shown in fig. 7, the thickness of the isolation layer 3 is in the range of
Specifically, the material of the isolation layer 3 includes silicon dioxide, silicon nitride or other suitable materials. In this embodiment, a silicon dioxide layer is used as the isolation layer 3.
Specifically, the method of forming the recess 31 includes dry etching, wet etching, or other suitable methods.
As an example, as shown in fig. 8, the bottom of the recess 31 is spaced from the front surface of the wafer 1 by a distance ranging from the bottom of the recess 31 to the front surface of the waferPreferably, the bottom of the recess 31 is at a distance +.>
Specifically, as shown in fig. 9, to form the body region 12, ion implantation or other suitable method is used to form the body region 12, which is schematically illustrated in a cross-sectional structure that is shown after the body region 12 is formed. In this embodiment, the second conductivity type is P-type, and the body region 12 is formed by ion implantation using a boron ion source, which may include B 2 H 6 ，BF 2 The thin isolation layer at the bottom of the groove 31 is used as a masking layer during ion implantation, so as to avoid generating a channel effect during ion implantation and causing uneven depth of the body region 12.
As an example, the body region 12 is formed further comprising a step of annealing the activated impurity. In this embodiment, by annealing, more impurity particles are activated, so that the impurity particles are heated and diffused, the impurity particles are prevented from accumulating on the surface of the detector forming region, and defects in the detector forming region due to ion implantation are repaired.
Referring to fig. 10 to 12, the steps S4 and S5 are performed: forming a trench 13 penetrating the isolation layer 3 and the wafer 1 at the edge of the probe forming region 10, wherein the bottom of the trench 13 exposes the support substrate 2, a first conductive type conductive layer 41 is formed on the sidewall of the trench 13, and the conductive layer 41 is in electrical contact with the doped layer 11; a first opening 32 is formed at the bottom of the recess 31 to expose the body region 12.
As an example, as shown in fig. 10, to schematically illustrate a cross-sectional structure after forming the trench 13, forming the trench 13 further includes the steps of:
forming a hard mask layer on the upper surface of the isolation layer 3 to cover the isolation layer 3 and fill the grooves 31, and patterning the hard mask layer;
etching the isolation layer 3 and the wafer 1 based on the hard mask layer to form the trench 13 penetrating the isolation layer 3 and the wafer 1 and the bottom to expose the support substrate 2, and removing the hard mask layer.
As an example, the width of the groove 13 ranges from 15 μm to 25 μm, and preferably the width of the groove 13 is 20 μm.
By way of example, the method of forming the trench 13 may include deep reactive ion etching or other suitable method.
As an example, forming the conductive layer 41 further includes the steps of:
forming a conductive material layer 4 in the inner wall of the groove 13, the upper surface of the isolation layer 3 and the groove 31;
the upper surface of the isolation layer 3 and the conductive material layer 4 in the recess 31 are removed to form the conductive layer 41 on the inner wall of the trench 13.
Specifically, as shown in fig. 11, in order to illustrate the cross-sectional structure of the conductive material layer 4 after forming the conductive material layer 4, the material of the conductive material layer 4 includes doped polysilicon of the first conductivity type or other suitable conductive materials, wherein the thickness of the conductive material layer 4 is determined according to the actual situation, which is not limited herein.
Specifically, the method of forming the conductive material layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. In this embodiment, the conductive material layer 4 is formed by chemical vapor deposition, and impurities of the first conductivity type are doped into the reaction gas during the deposition process, so that the conductivity type of the conductive material layer 4 is the first conductivity type.
Specifically, as shown in fig. 12, for the schematic cross-sectional structure after forming the conductive layer 41, the method for removing the conductive material layer 4 on the upper surface of the isolation layer 3 and in the recess 31 may include at least one of dry etching, wet etching and chemical mechanical polishing, and other suitable methods may be used.
Specifically, the conductivity type of the conductive material layer 4 of the inner wall of the trench 13 may be the first conductivity type by using a sidewall tilt ion implantation method.
Specifically, the method of forming the first opening 32 includes dry etching, wet etching, or other suitable methods.
Referring to fig. 13 to 14, the step S6 is performed: a first electrode layer 5 is formed in electrical contact with the body region 12 through the first opening 32, the carrier substrate 2 is removed, and a second electrode layer 6 is formed on the back side of the wafer 1 in electrical contact with the doped layer 11 to form the detector.
Specifically, forming the first electrode layer 5 further includes forming a first electrode conductive material layer (not shown) covering the upper surface of the isolation layer 3 and filling the recess 31 and the first opening 32, and patterning the first electrode layer material layer to form the first electrode layer 5.
Specifically, the method for forming the first electrode conductive material layer includes physical vapor deposition, chemical vapor deposition, electroplating, electroless plating or other suitable methods.
Specifically, as shown in fig. 13, the material of the first electrode layer 5 may be one of copper, aluminum, nickel, gold, silver and titanium, or other suitable conductive materials, which is a schematic cross-sectional structure of the first electrode layer 5 after being formed.
As an example, after the first electrode layer 5 is formed, a passivation layer (not shown) is formed on the upper surface of the first electrode layer 5.
Specifically, the passivation layer may be formed by one of chemical vapor deposition, physical vapor deposition, atomic layer deposition and chemical passivation, or by other suitable methods. In this embodiment, the passivation layer is formed on the upper surfaces of the isolation layer 3 and the first electrode layer 5 by chemical vapor deposition, and the passivation layer is patterned to form a second opening (not shown) in the passivation layer to expose the first electrode layer 5, so as to facilitate the extraction of the first electrode layer 5.
Specifically, the supporting substrate 2 is removed, and the portions of the probe forming region 10 on both sides of the trench 13 are removed.
Specifically, the method for removing the support substrate 2 includes chemical mechanical polishing, smart cut, or other suitable methods.
Specifically, as shown in fig. 14, to form the second electrode layer 6, the method of forming the second electrode layer 6 includes physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, or other suitable methods.
Specifically, the material of the second electrode layer 6 may include one of copper, aluminum, nickel, gold, silver and titanium, or may be other suitable conductive materials.
In the method for manufacturing the edge incidence detector of this embodiment, after the body region 12 is formed, the trench 13 penetrating through the isolation layer 3 and the wafer 1 is formed at the edge of the detector forming region 10 and the bottom of the trench is exposed out of the support substrate 2 by using a deep reactive ion etching method, so that the lattice defect of the wafer 1 caused by cutting a blade is prevented, and then the large leakage current caused by introducing the lattice defect by cutting a blade is reduced, the conductive layer 41 is formed on the inner wall of the trench 13, and the conductivity type of the conductive layer 41 is the same as that of the doped layer 11 and the doped layer 11, so that good electrical contact is formed between the conductive layer and the wafer 1 and between the conductive layer 11, thereby further reducing the leakage current caused by the lattice defect introduced by using the deep reactive ion etching method.
Example two
The present embodiment provides an edge incidence detector, as shown in fig. 14, which is a schematic cross-sectional structure of the edge incidence detector, and includes a semiconductor layer, an isolation layer 3, a first electrode layer 5, a conductive layer 41 and a second electrode layer 6, wherein the semiconductor layer includes a doped layer 11 of a first conductivity type located on a back surface layer of the semiconductor layer and a plurality of second conductivity type body regions 12 located on a front surface layer of the semiconductor layer, the isolation layer 3 is located on an upper surface of the semiconductor layer, and includes a plurality of grooves 31 disposed at intervals and a first opening 32 located at a bottom of the grooves 31 and exposing the body regions 12, the first electrode layer 5 is located on an upper surface of the isolation layer 3 and fills the grooves 31 and is electrically contacted with the body regions 12 through the first opening 32, the conductive layer 41 is located on a sidewall of the semiconductor layer and the isolation layer 3 and is electrically contacted with the doped layer 11, and the second electrode layer 6 is located on a back surface of the semiconductor layer and is electrically contacted with the doped layer 11.
As an example, the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.
Specifically, the thickness of the semiconductor layer ranges from 150 μm to 500 μm, wherein the semiconductor layer is obtained by thinning the probe formation region of the wafer in embodiment one.
Specifically, the doped layer 11 is used to form an ohmic contact of the semiconductor layer with the second electrode layer 6. The bias voltage is reversed between the second electrode layer 6 and the first electrode layer 5 so that a fully depleted layer (the concentration of electrons or holes is reduced to a very low level) is formed over the semiconductor layer, thereby forming a sensitive region of the detector.
As an example, the upper surface of the first electrode layer 5 is further provided with a passivation layer to improve corrosion resistance of the first electrode layer 5.
As an example, the width of the first opening 32 is smaller than the width of the bottom of the groove 31.
In particular, the body region 12, the recess 31, the opening 32 and the first electrode layer 5 constitute pixelated readout electrodes, each of which is connected to a separate readout electronics system for reading out the collected X-ray signals.
Specifically, the edge of the detector is the conductive layer 41, and the conductive layer 41 can sensitize the edge of the detector, so that the breakdown voltage of the detector is enhanced, and a protection ring for collecting peripheral leakage current is not required to be arranged.
Specifically, since the conductive layer 41 is in electrical contact with the doped layer 11 and the semiconductor layer, i.e. the conductive layer 41 may be regarded as an extension of the ohmic contact of the second electrode 6, the second electrode layer 6 located on the back side of the semiconductor layer may be led to the front side of the semiconductor layer through the conductive layer 41 located on the side wall of the detector, so as to facilitate packaging of the detector.
Specifically, the first electrode layer 5 is used for electrically connecting with a first electrode of the detector, and the second electrode layer 6 is used for electrically connecting with a second electrode of the detector.
According to the edge incidence detector, the side wall of the detector is provided with the conductive layer 41 which is electrically contacted with the semiconductor layer and the doped layer 11, a plurality of suspension protection rings are omitted from being arranged at the edge of the detector, the area of a dead zone of the detector is reduced, the filling factor of a sensitive area is increased, the collection efficiency of X-rays is improved, the breakdown voltage of the detector is enhanced, the conductive layer 41 extends to the second electrode layer 6, and the second electrode 6 can be led to the front surface of the semiconductor layer through the conductive layer 41, so that the packaging of the detector is facilitated.
In summary, the edge incidence detector and the manufacturing method thereof form the groove at the edge of the detector wafer by adopting the deep reactive ion etching method, so that excessive lattice damage to the wafer edge caused by cutting by a blade is avoided, leakage current increase caused by excessive lattice damage is avoided, a conductive layer electrically contacted with the wafer and the doped layer is formed on the side wall of the groove, leakage current caused by defects introduced by etching is reduced, breakdown voltage of the detector is enhanced, a protective ring for preventing the leakage current from being too large is omitted from being introduced at the edge of the detector, area of dead zone is reduced, filling factor of a sensitive area of the detector is improved, dead zone area of the detector during splicing is reduced, and collection efficiency of X rays is improved. Meanwhile, as the conducting layer on the side wall of the detector is in electrical contact with the wafer and the doping layer, the conducting layer becomes extension of ohmic contact of the second electrode layer, and the second electrode of the detector can be led to the front side of the detector through the conducting layer, so that the detector can be conveniently packaged. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (14)
1. A method of making an edge-incidence detector, comprising the steps of:
providing a first conductivity type detector wafer, and forming a first conductivity type doped layer on the back surface of the wafer, wherein the wafer comprises at least one detector forming area;
providing a supporting substrate, bonding the wafer to the supporting substrate, enabling the back surface of the wafer to face the supporting substrate, and thinning the wafer to a preset thickness from the front surface of the wafer;
forming an isolation layer on the front surface of the wafer, forming a plurality of grooves in the isolation layer at intervals, and forming a second conductive type body region in the wafer through the grooves;
forming a groove penetrating through the isolation layer and the wafer at the edge of the detector forming area, wherein the bottom of the groove exposes the supporting substrate, a first conductive type conductive layer is formed on the side wall of the groove, and the conductive layer is in electrical contact with the doped layer;
forming a first opening at the bottom of the groove to expose the body region;
and forming a first electrode layer electrically contacted with the body region through the first opening, removing the supporting substrate, and forming a second electrode layer electrically contacted with the doping layer on the back surface of the wafer to form the detector.
2. The method for manufacturing the edge-incidence detector according to claim 1, wherein: after thinning, the thickness of the wafer ranges from 150 mu m to 500 mu m.
3. The method for manufacturing the edge-incidence detector according to claim 1, wherein: the saidThe thickness of the isolation layer ranges from
4. The method for manufacturing the edge-incidence detector according to claim 1, wherein: the distance range between the bottom of the groove and the front surface of the wafer is
5. The method for manufacturing the edge-incidence detector according to claim 1, wherein: the body region is formed further comprising the step of annealing the activation impurity.
6. The method of fabricating an edge-incidence detector according to claim 1, wherein forming the trench further comprises:
forming a hard mask layer covering the isolation layer and filling the grooves on the upper surface of the isolation layer, and patterning the hard mask layer;
etching the isolation layer and the wafer based on the hard mask layer to form the groove penetrating through the isolation layer, the wafer and the bottom to expose the supporting substrate, and removing the hard mask layer.
7. The method for manufacturing the edge-incidence detector according to claim 1, wherein: the width of the groove ranges from 15 mu m to 25 mu m.
8. The method for manufacturing the edge-incidence detector according to claim 1, wherein: the method for forming the groove comprises deep reactive ion etching.
9. The method of fabricating an edge-incidence detector according to claim 1, wherein forming the conductive layer further comprises the steps of:
forming a conductive material layer in the inner wall of the groove, the upper surface of the isolation layer and the groove;
and removing the conductive material layer on the upper surface of the isolation layer and in the groove to form the conductive layer on the inner wall of the groove.
10. The method for manufacturing the edge-incidence detector according to claim 1, wherein: after the first electrode layer is formed, a passivation layer is formed on the upper surface of the first electrode layer.
11. An edge incidence detector manufactured by the manufacturing method of the edge incidence detector according to any one of claims 1 to 10, comprising:
a semiconductor layer including a first conductivity type doped layer located on a back surface layer of the semiconductor layer and a plurality of second conductivity type body regions located on a front surface layer of the semiconductor layer;
the isolation layer is positioned on the upper surface of the semiconductor layer and comprises a plurality of grooves which are arranged at intervals and a first opening which is positioned at the bottom of the grooves and exposes the body region;
a first electrode layer which is positioned on the upper surface of the isolation layer, fills the groove and is electrically contacted with the body region through the first opening;
the conductive layer is positioned on the side surfaces of the semiconductor layer and the isolation layer and is electrically contacted with the doped layer;
and the second electrode layer is positioned on the back surface of the semiconductor layer and is electrically contacted with the doped layer.
12. The edge-incidence detector of claim 11, wherein: the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type.
13. The edge-incidence detector of claim 11, wherein: the upper surface of the first electrode layer is also provided with a passivation layer.
14. The edge-incidence detector of claim 11, wherein: the width of the first opening is smaller than the width of the bottom of the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210036573.4A CN114447149B (en) | 2022-01-11 | 2022-01-11 | Edge incidence detector and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210036573.4A CN114447149B (en) | 2022-01-11 | 2022-01-11 | Edge incidence detector and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114447149A CN114447149A (en) | 2022-05-06 |
| CN114447149B true CN114447149B (en) | 2023-12-01 |
Family
ID=81366955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210036573.4A Active CN114447149B (en) | 2022-01-11 | 2022-01-11 | Edge incidence detector and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114447149B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114927535B (en) * | 2022-05-20 | 2023-09-22 | 无锡鉴微华芯科技有限公司 | X-ray detector with double three-dimensional full-surrounding protection ring and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972323A (en) * | 2013-01-31 | 2014-08-06 | 同方威视技术股份有限公司 | Radiation detector |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10126437B1 (en) * | 2017-05-15 | 2018-11-13 | Prismatic Sensors Ab | Detector for x-ray imaging |
| DE102020001839B3 (en) * | 2020-03-20 | 2021-09-23 | Azur Space Solar Power Gmbh | III-V semiconductor pixel x-ray detector |
-
2022
- 2022-01-11 CN CN202210036573.4A patent/CN114447149B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972323A (en) * | 2013-01-31 | 2014-08-06 | 同方威视技术股份有限公司 | Radiation detector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114447149A (en) | 2022-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3518292B1 (en) | Method for manufacturing a photodiode detector | |
| US6597025B2 (en) | Light sensitive semiconductor component | |
| US10056424B2 (en) | Semiconductor device, electrical device system, and method of producing semiconductor device | |
| CN112466946B (en) | Semiconductor device and method for manufacturing the same | |
| CN114447149B (en) | Edge incidence detector and manufacturing method thereof | |
| US6777729B1 (en) | Semiconductor photodiode with back contacts | |
| CN114300570B (en) | Detector and manufacturing method | |
| CN110212044B (en) | Deep-groove semiconductor light detection structure and manufacturing method thereof | |
| CN111628034A (en) | Method for manufacturing photoelectric detection device | |
| JP2002311146A (en) | Device and apparatus for detecting high-energy beam | |
| CN115332384A (en) | Single photon detector and manufacturing method thereof | |
| CN114784121A (en) | Three-dimensional groove electrode silicon detector and preparation method thereof | |
| JPH0695571B2 (en) | Photoelectric conversion device | |
| CN113871509A (en) | Double-groove type narrow-edge high-voltage-resistant silicon PIN radiation detector and preparation thereof | |
| CN209675281U (en) | The two-sided wrong embedded three dimension detector of one dimensional arrangement and its array | |
| CN209675301U (en) | The two-sided wrong embedded three dimension detector of two-dimensional arrangements and its array | |
| JP2021093559A (en) | Semiconductor device | |
| CN116960227A (en) | Side-incident photoelectric detector and preparation method thereof | |
| CN111584656A (en) | Drift detector and processing method thereof | |
| CN117239003A (en) | Drift detector and manufacturing method thereof | |
| US20130334639A1 (en) | Photodiode with reduced dead-layer region | |
| JP6780335B2 (en) | Manufacturing method of reverse blocking MOS type semiconductor device and reverse blocking MOS type semiconductor device | |
| CN113903800B (en) | Semiconductor device with a semiconductor device having a plurality of semiconductor chips | |
| KR101768704B1 (en) | photo multiplier and manufacturing method for the same | |
| CN116960209A (en) | Ultra-shallow junction depth low-energy electronic detector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |