CN209675301U - The two-sided wrong embedded three dimension detector of two-dimensional arrangements and its array - Google Patents
The two-sided wrong embedded three dimension detector of two-dimensional arrangements and its array Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The utility model discloses a kind of two-sided wrong embedded three dimension detector of two-dimensional arrangements and its arrays, including upper trench electrode and lower groove electrode, upper trench electrode and lower groove electrode is etched respectively in intermediate semiconductor matrix surface；Upper trench electrode is embedded with contre electrode, and semiconductor-on-insulator matrix is filled between upper contre electrode and upper trench electrode；Lower groove electrode is embedded with lower contre electrode, and lower semiconductor matrix is filled between lower groove electrode and lower contre electrode；Upper trench electrode is identical with lower groove electrode specification, and lower groove electrode is located at below upper trench electrode, and the two is vertically at a distance of d3, and the two horizontal direction a quarter position is overlapped, and upper contre electrode is identical with lower contre electrode specification.Upper contre electrode is located at upper trench electrode center, and lower contre electrode is located at lower groove electrode centers.Upper contre electrode and lower contre electrode are N-shaped heavily-doped semiconductor matrix, and upper trench electrode and lower groove electrode are p-type heavily-doped semiconductor matrix.
Description
Technical field
The utility model belongs to photon (including X-ray, laser, X-ray free-electron laser) or Particel Detection Methods field,
It is related to a kind of two-sided wrong embedded three dimension detector of two-dimensional arrangements and its array.
Background technique
Three-dimensional trench electrode silicon detector be by chip single side etch certain depth trench electrode and center
Electrode, if trench electrode forms a circuit through etching on chip, detector can be fallen on except chip.Therefore it uses
Single side etches the trench electrode and contre electrode of certain depth (being less than chip depth) on chip, is not surrounded by trench electrode
Bottom be dead zone, the sum of etching depth of trench electrode of bottom dead depth and single side etching is chip total depth.Therefore,
Bottom dead ratio is decided by the etching depth of the trench electrode of single side etching.It is carved in the single side of three-dimensional trench electrode silicon detector
When the trench electrode and contre electrode of erosion make, if wanting to minimize dead zone ratio, newest deep etching technology is needed (most
High-aspect-ratio index), the depth of trench electrode and contre electrode is accomplished into maximum in single side etching.This is to three-dimensional trench electrode
Deep etching technology in silicon detector manufacture requires very high.
Detector is mainly used for the fields such as high-energy physics, astrophysics, aerospace, military affairs, medical technology.Three-dimensional groove
Electrode probe, position resolution is equal to the length of electrode spacing, if expecting high position resolution, it is necessary to do electrode spacing
To very little, so that electronics reading number is more, cause electronics complicated, it is at high cost；And electrode spacing is accomplished into very little, it may
It causes punch through, in the case where itself exhausting voltage just height, it is easier to breakdown.In addition, three-dimensional trench electrode silicon detector
Central collector with outer layer groove is formed by etching, filling, and the width of the groove etched and the depth of groove are related, i.e.,
The breadth depth ratio of deep etching technology, the breadth depth ratio of deep etching can accomplish 1:30 at present, illustrate to carve in the chip of 300 micron thickness
Erosion one groove through chip, minimum 10 microns of groove width, and groove itself cannot collect charge, therefore itself is not
It can be regarded as sensitive volume, and become dead zone, no small ratio at last in this its tangible entire detector, dead zone area is caused to increase,
Sensitive volume area is reduced.
Utility model content
The purpose of this utility model is to provide a kind of two-sided wrong embedded three dimension detector of two-dimensional arrangements and its arrays, solve
Existing three-dimensional trench electrode detector sensitivity is low, electronics read number cause that electronics is complicated, it is breakdown to be easy more and
The low problem of position resolution.
The utility model is the technical scheme adopted is that the two-sided wrong embedded three dimension detector of two-dimensional arrangements, including upper groove
Electrode, lower groove electrode and intermediate semiconductor matrix, upper trench electrode etching is in intermediate semiconductor body upper surface, lower groove electricity
Pole is etched in intermediate semiconductor matrix lower surface；Upper trench electrode is rectangular parallelepiped structure, outer a length of 2RX, outer width 2RY, under
Trench electrode is identical as upper trench electrode specification, and lower groove electrode is located at below upper trench electrode, lower groove electrode top with
Upper trench electrode lower surface is vertically at a distance of d3, and the two has the overlapping of a quarter position in the horizontal direction；Upper trench electrode is embedded
There is upper contre electrode, semiconductor-on-insulator matrix is filled between upper contre electrode and upper trench electrode；Lower groove electrode is embedded with down
Contre electrode is filled with lower semiconductor matrix between lower groove electrode and lower contre electrode.
Further, the upper contre electrode is identical with lower contre electrode specification；The upper trench electrode and lower groove electricity
The vertical range d3 of pole meets d3=r1 or d3=r2, and r1 is the electrode spacing of upper trench electrode and upper contre electrode, under r2 is
The electrode spacing of trench electrode and lower contre electrode.
Further, the upper contre electrode is located at upper trench electrode center, and the lower contre electrode is located at lower groove electricity
Pole center；The RX=RY。
Further, the upper contre electrode and lower contre electrode are N-shaped heavily-doped semiconductor matrix；The upper groove
Electrode and lower groove electrode are p-type heavily-doped semiconductor matrix；The semiconductor-on-insulator matrix, lower semiconductor matrix and intermediate half
Conductor matrix is that semiconductor substrate is lightly doped or semiconductor substrate is lightly doped in N-shaped in p-type.
Further, the upper contre electrode and lower contre electrode are p-type heavily-doped semiconductor matrix；The upper groove
Electrode and lower groove electrode are N-shaped heavily-doped semiconductor matrix；The semiconductor-on-insulator matrix, lower semiconductor matrix and intermediate half
Conductor matrix is that semiconductor substrate is lightly doped or semiconductor substrate is lightly doped in N-shaped in p-type；The N-shaped be lightly doped semiconductor substrate,
It is half that material is Si that semiconductor substrate, N-shaped heavily-doped semiconductor matrix and p-type heavily-doped semiconductor matrix, which is lightly doped, in p-type
Conductor matrix.
Further, the doping concentration of the semiconductor-on-insulator matrix, lower semiconductor matrix and intermediate semiconductor matrix is 1
×1012cm-3；The upper trench electrode, upper contre electrode, lower groove electrode and lower contre electrode doping concentration be 1 ×
1018cm-3~5 × 1019cm-3；Semiconductor substrate is lightly doped in the N-shaped, semiconductor substrate is lightly doped in p-type, N-shaped heavy doping is partly led
It is Ge, HgI that body matrix and p-type heavily-doped semiconductor matrix, which also can be replaced material,2、GaAs、TiBr、CdTe、 CdZnTe、
CdSe、GaP、HgS、PbI2Or the semiconductor substrate of any one in AlSb.
Another technical solution used by the utility model is a kind of two-sided wrong embedded three dimension detector of application two-dimensional arrangements
Be arranged side by side the two-sided wrong embedded three dimension detector array of two-dimensional arrangements of composition.
The utility model has the beneficial effects that the two-sided wrong embedded three dimension detector of two-dimensional arrangements and its array, firstly, since
Using two-sided etching so that the trench depth for needing single side to etch becomes smaller, therefore can be by the width of contre electrode and trench electrode
Half is reduced, greatly reduces the dead zone that electrode itself acts as, when detector height is consistent, the utility model electrode is itself acted as
Dead zone be only conventional three-dimensional trench electrode detector half so that the dead zone served as of electrode is reduced, sensitivity enhancement；Its
Secondary, trench electrode does not etch into bottom, and the distance of two trench electrodes in the vertical direction is d3, and the two can be kept not mutual
Contact, avoids short circuit, while guaranteeing that chip can be interconnected mechanically；D3 is equal to the spacing of trench electrode and contre electrode, makes
Detector when exhausting, the depletion widths on vertical direction are approximately equal to the depletion widths in horizontal direction, can make in detector
Portion's field distribution is more uniform, is conducive to processing；The two-sided wrong embedded three dimension detector detectable two of the two-dimensional arrangements of the utility model
Particle, the photon change in location of the vertical incidence on direction are tieed up, and the particle of the vertical incidence detected, photon are horizontal and vertical
Minimum position variation beParticle, the photon minimum position of the vertical incidence detected change compared with conventional detection
Device is smaller, so that position resolution is promoted；The utility model detector array width x length can accomplish very big, breakdown risk
Lower significantly.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the two-sided wrong embedded three dimension detector structural schematic diagram of two-dimensional arrangements；
Fig. 2 is the top view of the two-sided wrong embedded three dimension detector of two-dimensional arrangements；
Fig. 3 is the two-sided wrong embedded three dimension detector 2*1 array top view of two-dimensional arrangements；
Fig. 4 is the two-sided wrong embedded three dimension detector 2*1 array main view of two-dimensional arrangements.
In figure, 1. semiconductor-on-insulator matrixes, trench electrode on 2., contre electrode on 3., 4. lower semiconductor matrixes, 5. lower grooves
Electrode, 6. lower contre electrodes, 7. intermediate semiconductor matrixes.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained, fall within the protection scope of the utility model.
Embodiment 1
The two-sided wrong embedded three dimension detector of two-dimensional arrangements, as shown in Figures 1 to 3, including third silicon substrate 7, third silicon substrate 7
Upper surface is etched with trench electrode 2, and 7 lower surface of third silicon substrate is etched with lower groove electrode 5, upper trench electrode 2 and lower ditch
Slot electrode 5 is the rectangular parallelepiped structure of inner hollow, and upper trench electrode 2 is embedded with contre electrode 3, and lower groove electrode 5 is embedded with
Lower contre electrode 6, between upper contre electrode 3 and upper trench electrode 2 be filled with semiconductor-on-insulator matrix 1, lower groove electrode 5 and it is lower in
It entreats and is filled with lower semiconductor matrix 4 between electrode 6.A length of 2R outside upper trench electrode 2X, outer width 2RY, upper contre electrode 3 is under
Both contre electrodes 6 center is vertically the electrode of upper contre electrode 3 and upper trench electrode 2 at a distance of d3, d3=r1 or d3=r2, r1
Spacing, r2 are the electrode spacing of lower contre electrode 6 and lower groove electrode 5.Upper trench electrode 2 is identical as 5 specification of lower groove electrode,
Upper contre electrode 3 is identical as lower 6 specification of contre electrode, and upper trench electrode 2 has a quarter with lower groove electrode 5 in the horizontal direction
Position overlapping, i.e., upper contre electrode 3 are horizontal and vertical at a distance of R in same level with lower contre electrode 6X.Semiconductor-on-insulator
Matrix 1, lower semiconductor matrix 4 and intermediate semiconductor matrix 7 are ultrapure High Resistivity Si, be doping concentration be 1 × 1012cm-3It is (light
Doping) p-type silicon matrix；Upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 1 × 1018cm-3P-type heavily doped silicon
Matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 1 × 1018cm-3N-shaped heavily doped silicon matrix.
Embodiment 2
Unlike the first embodiment, on the present embodiment trench electrode 2 and lower groove electrode 5 be doping concentration be 25 ×
1018cm-3P-type heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 25 × 1018cm-3N-shaped
Heavily doped silicon matrix.
Embodiment 3
Unlike Examples 1 to 2, on the present embodiment trench electrode 2 and lower groove electrode 5 be doping concentration be 5 ×
1019cm-3P-type heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 5 × 1019cm-3N-shaped weight
Adulterate silicon substrate.
Embodiment 4
Unlike Examples 1 to 3, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3P-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 1
×1018cm-3N-shaped heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 1 × 1018cm-3P
Type heavily doped silicon matrix.
Embodiment 5
Unlike Examples 1 to 4, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3P-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 25
×1018cm-3N-shaped heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 25 × 1018cm-3P
Type heavily doped silicon matrix.
Embodiment 6
Unlike Examples 1 to 5, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3P-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 5
×1019cm-3N-shaped heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 5 × 1019cm-3P
Type heavily doped silicon matrix.
Embodiment 7
Unlike Examples 1 to 6, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3N-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 1
×1018cm-3P-type heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 1 × 1018cm-3N
Type heavily doped silicon matrix.
Embodiment 8
Unlike Examples 1 to 7, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3N-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 25
×1018cm-3P-type heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 25 × 1018cm-3N
Type heavily doped silicon matrix.
Embodiment 9
Unlike Examples 1 to 8, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3N-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 5
×1019cm-3P-type heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 5 × 1019cm-3N
Type heavily doped silicon matrix.
Embodiment 10
Unlike Examples 1 to 9, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3N-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 1
×1018cm-3N-shaped heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 1 × 1018cm-3P
Type heavily doped silicon matrix.
Embodiment 11
Unlike Examples 1 to 10, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3N-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 25
×1018cm-3N-shaped heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 25 × 1018cm-3P
Type heavily doped silicon matrix.
Embodiment 12
Unlike embodiment 1~11, the present embodiment semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 is that doping concentration is 1 × 1012cm-3N-type silicon matrix, upper trench electrode 2 and lower groove electrode 5 are that doping concentration is 5
×1019cm-3N-shaped heavily doped silicon matrix；Upper contre electrode 3 and lower contre electrode 6 are that doping concentration is 5 × 1019cm-3P
Type heavily doped silicon matrix.
It is p-type lightly-doped silicon that sensitive volume, which is arranged, in embodiment 4~6, and contre electrode is p-type heavily doped silicon, trench electrode n
Type heavily doped silicon, so that PN junction position, near trench electrode, the detector of embodiment 7~9, sensitive volume is N-shaped lightly-doped silicon,
Contre electrode is N-shaped heavily doped silicon, and trench electrode is p-type heavily doped silicon, and PN junction position is also near trench electrode, so that electric
Smooth, electric field change is small, and when work is not easy breakdown.And the heavy dopant concentration of embodiment 4 and embodiment 7 is best, Bu Hui
Damage is formed during doping and semiconductor-on-insulator matrix 1, lower semiconductor matrix 4 and intermediate semiconductor matrix 7 is made to be easier to exhaust,
This is because the doping concentration of heavy doping electrode is excessive, damage can be formed during doping, and if doping concentration be greater than
1020cm-3, damage and be not easy to remove, the doping concentration of heavy doping electrode is too small, cannot form unilateral hetero-junctions, lead to semiconductor-on-insulator
Matrix 1, lower semiconductor matrix 4 and intermediate semiconductor matrix 7 are not easy to exhaust.In embodiment 1 and embodiment 4, sensitive volume is set
For p-type lightly-doped silicon, in embodiment 7 and embodiment 9, setting sensitive volume is N-shaped lightly-doped silicon, therefore embodiment 1 and embodiment 4
Than embodiment 7, the more radiation hardness of embodiment 9；In embodiment 4 and embodiment 7, so that PN junction position is near trench electrode, it is electric
Smooth, electric field change is small, and when work is not easy breakdown.Therefore embodiment 4 and embodiment 7 are more than embodiment 1, embodiment 9
It is not easy partial breakdown.Height radiate (high-energy physics experiment) under, performance by by force to it is weak be embodiment 4, embodiment 1, embodiment 7,
Embodiment 9；Under Low emissivity (such as photon detection), performance is without significant difference.
Detector is exhausted along the supreme contre electrode 3 of upper trench electrode 2, along lower groove electrode 6 to lower contre electrode 5
It exhausts, therefore the silicon substrate between trench electrode and contre electrode just claims depletion region or sensitive volume, i.e. 1 He of semiconductor-on-insulator matrix
Lower semiconductor matrix 4 is the sensitive volume of the utility model detector, all right for n-type silicon or p-type silicon, but since n type silicon exists
P-type silicon can be changed under high radiation environment, therefore under high radiation environment, generally use p-type silicon, radiation hardness ability is more preferable.On
The purpose of selection of 4 doping concentration of semiconductor substrate 1 and lower semiconductor matrix is to make the ultrapure High Resistivity Si of silicon substrate, is existing
The concentration for the hyperpure silicon that technique can be formed, and just form the concentration of High Resistivity Si, then pure silicon (concentration is smaller) prior art
It can not make, and the resistivity of concentration big silicon again becomes smaller, leakage current becomes larger, therefore selects semiconductor-on-insulator matrix 1 and lower semiconductor
The doping concentration of matrix 4 and intermediate semiconductor matrix 7 is 1 × 1012cm-3.Upper trench electrode 2, lower groove electrode 5, upper center electricity
The value range of the heavily doped silicon doping concentration of pole 3 and lower contre electrode 6 be in order to semiconductor-on-insulator matrix 1, lower semiconductor base
The concentration difference of body 4 (lightly-doped silicon) keeps several orders of magnitude, forms one-sided step junction, makes semiconductor-on-insulator matrix 1, lower semiconductor base
Body 4 and intermediate semiconductor matrix 7 are easier to exhaust.
RXAnd RYWhen unequal, contre electrode can be elongated, and capacitor can also increase with it, and detector energy resolution ratio reduces,
Therefore, RX=RY。
Maximum electricity of the maximum field much smaller than PN junction position in contre electrode when PN junction position is near trench electrode
, it is p-type lightly-doped silicon that semiconductor-on-insulator matrix 1 and lower semiconductor matrix 4, which is arranged, in embodiment 4~6, upper contre electrode 3 and it is lower in
Centre electrode 6 is p-type heavily doped silicon, and upper trench electrode 2 and lower groove electrode 5 are N-shaped heavily doped silicon, so that PN junction position is upper
Near trench electrode 2 and lower groove electrode 5, to keep electric field smooth, electric field change is small, so that detector operating voltage is much larger than
Exhaust voltage, when work is not easy breakdown；And semiconductor-on-insulator matrix 1 and lower semiconductor matrix 4 are p-type semiconductor matrix, anti-spoke
It is strong to penetrate ability.
Trench electrode 2, lower groove electrode 5, upper contre electrode 3 and lower contre electrode 6 are heavy doping, doping concentration in setting
It is 1 × 1018cm-3~5 × 1019cm-3, it is for the concentration difference with lightly-doped silicon (semiconductor-on-insulator matrix 1, lower semiconductor matrix 4)
Several orders of magnitude are kept, one-sided step junction is formed, makes breakdown voltage and exhausts the multiple orders of magnitude of voltage phase difference, make lightly-doped silicon more
It is easy to exhaust.
Semiconductor detector prepares material and is not limited to Si sill, can be Ge, HgI2、GaAs、TiBr、CdTe、
CdZnTe、CdSe、GaP、HgS、PbI2Or one of AlSb, have a wide range of application.
As long as theoretically contre electrode is located in trench electrode, if but not being located at trench electrode center, center
One, electric field of electrode two sides is big one small, and difference causes the peak value of signal (counting rate) to reduce, and peak width broadens, and is unfavorable for locating
Reason.It is advantageous to, the upper contre electrode 3 of the utility model is located at upper 2 center of trench electrode, and lower contre electrode 6 is located at lower ditch
5 center of slot electrode.
Due to the road that incident mip particle generates the quantity of electron-hole pair in detector medium and mip particle passes through
Electrical path length is directly proportional, thus make trench electrode 2 with 5 specification of lower groove electrode identical, upper contre electrode 3 and lower contre electrode 6
Specification is identical, so that the electronics-that incident mip particle generates in semiconductor-on-insulator matrix 1 and lower semiconductor matrix 4 (sensitive volume)
The quantity in hole pair is consistent, convenient for the processing of read output signal later.
The matrix with a thickness of d3 is reserved in the middle part of intermediate semiconductor matrix 7 be not etched and wear, can keep 2 He of trench electrode
Lower groove electrode 5 does not contact with each other, and avoids short circuit；And make semiconductor-on-insulator matrix 1 and lower semiconductor matrix 4 and intermediate semiconductor
Matrix 7 mechanically interconnects, and guarantees that detector is not fallen.In addition, d3=r1=r2, r1 are upper trench electrode 2 and upper center
The electrode spacing of electrode 3, r2 are the electrode spacing of lower groove electrode 5 and lower contre electrode 6, when so that detector exhausting, vertically
Depletion widths on direction are approximately equal to the depletion widths in horizontal direction, i.e., hanging down between upper trench electrode 2 and lower groove electrode 6
Straight distance be equal to upper trench electrode between upper contre electrode at a distance from, equal to lower groove electrode between lower contre electrode at a distance from,
Detector internal electric field can be made to be distributed more uniform (numerical value of electric field is not much different)；The electric field number of non-uniform electric field two sides
Value one big one small, the peak value that Electric Field Numerical difference will cause signal (counting rate) reduces, and peak width broadens, is unfavorable for handling.
Fig. 2 is the top view of the two-sided wrong embedded three dimension detector of two-dimensional arrangements, by it respectively by trench electrode, contre electrode
The number of collector up and down with semiconductor substrate composition is T, B, mip particle vertical incidence, if T and B all have signal, explanation
Particle is in the overlapping region T and B；If T has signal, illustrate particle be in T not with the overlapping region B；If B has signal, explanation
Particle be in B not with the overlapping region T.If detector array is lined up by the two-sided wrong embedded three dimension detector of two-dimensional arrangements, based on upper
Principle is stated, according to the mip particle incoming position of number vertical incidence where being collected into collector T, B of signal.According to sound
Answering situation that can be divided into a detector, only upper collector responds, upper and lower collector responds, only lower collector response three
Kind situation, then the particle of the vertical incidence detected, the variation of photon minimum position are horizontal and vertical equal are as follows:
The position resolution of conventional three-dimensional trench electrode silicon detector is strictly equal to the size of unit, and detects in the utility model
Vertical incidence particle, photon minimum position variation it is smaller compared with conventional detectors so that position resolution is higher.
Fig. 3 is the two-sided wrong embedded three dimension detector 2*1 array of two-dimensional arrangements, the two-sided wrong embedded three dimension detector of two-dimensional arrangements
Upper unit and lower unit are displaced R in the direction x and Y-directionX。a1It is the upper probe unit of first detector, a2It is second spy
Survey the upper probe unit of device, b1It is the lower probe unit of first detector, b2It is the lower probe unit of second detector, often
The probe unit up and down of a detector has 1/4 to partly overlap in chip level.It, will be two-dimentional according to the part being overlapped between unit
It arranges two-sided wrong embedded three dimension detector 2*1 array and is divided into the section a, b, c, d, e, f, g, the section a only has a1 when being particle incidence
The section of probe unit response, the section that a1 probe unit and b1 probe unit respond when the section b is particle incidence, the section c
The section that only b1 probe unit responds when being particle incidence, a2 probe unit and b1 probe unit are equal when the section d is particle incidence
The section of response, the section that only a2 probe unit responds when the section e is particle incidence, a2 detection is single when the section f is particle incidence
The section that member and b2 probe unit respond, the section g is the section of only b2 probe unit response, horizontal and vertical upper
The variation of particle position is detected, and resolution ratio correspondinglys increase.
Fig. 4 is the two-sided wrong embedded three dimension detector 4*1 array of two-dimensional arrangements, and dead zone area greatly reduces, and resolution ratio
It improves.In order to keep high position resolution, the width x length of conventional three-dimensional trench electrode silicon detector accomplishes very little, it is easy to
Puncture detector.And the width and length of the two-sided wrong embedded three dimension detector of the utility model two-dimensional arrangements can be accomplished very
Greatly, breakdown risk lowers significantly.And the array of the small detector cells composition of size needs more electronics to read number,
There is technology complexity and at high cost.
The utility model detector is V=(d by the dead space volume that electrode itself acts as1+d2)×((2RX)2-(2RX-2w)2+
w2)=(d1+d2)×(4RXw-3w2), conventional detectors are V=(d by the dead space volume that electrode itself acts as1+d2+d3)×
((2RX)2-(2RX-2w)2+w2)=(d1+d2+d3)×(4RXw-3w2), w is the groove of upper trench electrode 2 and lower groove electrode 5
Width is reduced, sensitivity enhancement by the dead space volume that electrode itself acts as；The horizontal and vertical position of the utility model detector
Resolution ratio isConventional detectors position resolution is σX=2RX, position resolution promotion.
The preparation method of the two-sided wrong embedded three dimension detector of two-dimensional arrangements, the specific steps are as follows:
Step S1, cleaning and oxidation: chip is cleaned to surface with deionized water without floating dust, the oxidation cleaned up is put into
In furnace, gettering oxidation is carried out in the mixed gas of high pure oxygen and High Purity Nitrogen, defect oxidation, low temperature knot are absorbed in gettering oxidation point
Crystalline substance nucleation and surface defect eliminate oxidation three phases.The interior absorption defect oxidation is under 1100~1400 DEG C of hot conditions
Oxidation 3~7 hours；The low temperature crystallization nucleation is aoxidized 3~7 hours under the conditions of 700~1000 DEG C of temperature；The surface lacks
Falling into and eliminating oxidation is aoxidized 18~24 hours under the conditions of 1000~1400 temperature.
The cleaning of oxidation furnace is at high temperature, halogen gas, the volume basis of halogen gas to be added in high purity oxygen gas stream
Than being less than or equal to 15%, most common halogen gas is chlorine, and most of heavy metal atoms and chlorine reaction generate gaseous metal
Chloride substantially improves the cleanliness in furnace, reduces ion and stains, improves SiO2/ Si interface quality.
Through peroxidating, silicon wafer surface generates oxide layer, reduces the dangling bonds of silicon chip surface, reach surface passivation,
Reduce the tracking current due to caused by external dirt.The introducing of oxygen can make the defect of chip interior more stable, reduce current-carrying
Son it is compound, improve the minority carrier life time of chip, be allowed to that radiation resistance is more preferable, and leakage current is lower, adsorbing contaminant makes the miscellaneous of chip
Matter reduces.Also, the oxide layer that high-temperature oxydation generates is hard, can protect chip from scratching.
Compare direct oxidation, with as interior suction remove oxidation technology made from the semiconductor devices that makes of ultrapure High Resistivity Si, tool
There are many performance advantage: the longer life expectancy of minority carrier, fully- depleted capacitor are smaller, interface state density want small, ion diffusion away from
From bigger and leakage current is smaller.The device of the monocrystalline silicon production directly aoxidized, the service life of minority carrier are 129 μ s,
Service life using the device minority carrier of interior absorption defect oxidation technology production can reach 720 μ s, extend more than 5 times.
Step S2, high-precision scale designation is to photoetching: corresponding photo-etching mark is done in multiple positions on chip, and litho machine is directed at chip
On photo-etching mark, be bonded mask plate precisely with chip；It will be put in after chip spin coating under mask plate and use ultraviolet photoetching, make to cover
Detector pattern in film version is transferred on chip, and development displays detector pattern；
Step S3, upper and lower anode electrode etching is spread with chemical deposition: with deep etching machine respectively from top and bottom by light
Chips in etching after carving development goes out hollow peripheral groove up and down, and silane gas is added in phosphine gas, mixed gas is made to exist
Chemical deposition generates polysilicon in upper and lower peripheral groove, is allowed to constantly spread and fills up groove, anode is made, i.e., upper trench electrode 2
With lower groove electrode 5；
Step S4, upper and lower cathode electrode etching is spread with chemical deposition: with deep etching machine respectively from top and bottom by light
Chips in etching after carving development goes out hollow groove central up and down, and keeps the depth of central groove up and down consistent；By diborane
Silane gas is added in gas, so that mixed gas is learned deposition in upper and lower central groove internalization and generates polysilicon, is allowed to constantly spread and fill out
The i.e. upper contre electrode 3 of cathode and lower contre electrode 6 is made in full groove；
Step S5, it anneals: chip is put in annealing furnace, in vacuum environment or the mixed gas of nitrogen and argon gas, rise
Temperature simultaneously maintains certain time, then cools the temperature to room temperature, the chip after being annealed；
In step S5, warming temperature be 700~1000 DEG C, annealing time be 50s~100min, the heating-up time be 50~
1000s, soaking time are 2~10min.The purpose of annealing is the damage removed inside chip, and held for some time makes in chip
Portion's damage is decomposed into simple defect, restores minority carrier life time part, and chip leakage current is unlikely to voltage is exhausted because of defect
There are excessive.
Step S6, extraction electrode: photolithographic after chip spin coating, is put under mask plate and uses ultraviolet photoetching, make to cover
Detector pattern in film version is transferred on chip, and development displays reticle pattern, then by the core after photoetching development
Trench electrode 2, lower groove electrode 5, upper contre electrode 3 and the oxide layer in lower 6 region of contre electrode etch away on piece, then at it
Top plating metal；
Step S7, it encapsulates: marking detector unit array on Silicon Wafer, be fixed on the pedestal of picking-up, then use
Metal wire is got up the electrode points on detector by welded connecting with external pin, is finally sealed with plastic case,
Detector chip is protected, it is whole to form chip.Using the pin for drawing chip, to be connected with external devices.
Each embodiment in this specification is all made of relevant mode and describes, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.
The above is only the preferred embodiment of the utility model only, is not intended to limit the protection model of the utility model
It encloses.Any modification, equivalent substitution, improvement and etc. made within the spirit and principle of the present invention, are all contained in this reality
With in novel protection scope.
Claims (7)
1. the two-sided wrong embedded three dimension detector of two-dimensional arrangements, which is characterized in that including upper trench electrode (2), lower groove electrode (5)
With intermediate semiconductor matrix (7), upper trench electrode (2) etching is in intermediate semiconductor matrix (7) upper surface, lower groove electrode (5)
Etching is in intermediate semiconductor matrix (7) lower surface；Upper trench electrode (2) is rectangular parallelepiped structure, outer a length of 2RX, outer width 2RY,
Lower groove electrode (5) is identical as upper trench electrode (2) specification, and lower groove electrode (5) is located at below upper trench electrode (2), lower ditch
Slot electrode (5) upper surface is vertical with upper trench electrode (2) lower surface at a distance of d3, and the two has a quarter position in the horizontal direction
Overlapping；Upper trench electrode (2) is embedded with contre electrode (3), is filled between upper contre electrode (3) and upper trench electrode (2)
Semiconductor-on-insulator matrix (1)；Lower groove electrode (5) is embedded with lower contre electrode (6), lower groove electrode (5) and lower contre electrode (6)
Between be filled with lower semiconductor matrix (4).
2. the two-sided wrong embedded three dimension detector of two-dimensional arrangements according to claim 1, which is characterized in that the upper center electricity
Pole (3) is identical with lower contre electrode (6) specification；
The vertical range d3 of the upper trench electrode (2) and lower groove electrode (5) meets d3=r1 or d3=r2, and r1 is upper groove
The electrode spacing of electrode (2) and upper contre electrode (3), r2 are the electrode spacing of lower groove electrode (5) and lower contre electrode (6).
3. the two-sided wrong embedded three dimension detector of two-dimensional arrangements according to claim 2, which is characterized in that the upper center electricity
Pole (3) is located at upper trench electrode (2) center, and the lower contre electrode (6) is located at lower groove electrode (5) center；
The RX=RY。
4. the two-sided wrong embedded three dimension detector of two-dimensional arrangements according to claim 3, which is characterized in that the upper center electricity
Pole (3) and lower contre electrode (6) are N-shaped heavily-doped semiconductor matrix；
The upper trench electrode (2) and lower groove electrode (5) are p-type heavily-doped semiconductor matrix；
The semiconductor-on-insulator matrix (1), lower semiconductor matrix (4) and intermediate semiconductor matrix (7) are that semiconductor is lightly doped in p-type
Semiconductor substrate is lightly doped in matrix or N-shaped.
5. the two-sided wrong embedded three dimension detector of two-dimensional arrangements according to claim 3, which is characterized in that the upper center electricity
Pole (3) and lower contre electrode (6) are p-type heavily-doped semiconductor matrix；
The upper trench electrode (2) and lower groove electrode (5) are N-shaped heavily-doped semiconductor matrix；
The semiconductor-on-insulator matrix (1), lower semiconductor matrix (4) and intermediate semiconductor matrix (7) are that semiconductor is lightly doped in p-type
Semiconductor substrate is lightly doped in matrix or N-shaped；
Semiconductor substrate is lightly doped in the N-shaped, semiconductor substrate is lightly doped in p-type, N-shaped heavily-doped semiconductor matrix and p-type are heavily doped
Miscellaneous semiconductor substrate is the semiconductor substrate that material is Si.
6. the two-sided wrong embedded three dimension detector of two-dimensional arrangements according to claim 5, which is characterized in that the semiconductor-on-insulator
The doping concentration of matrix (1), lower semiconductor matrix (4) and intermediate semiconductor matrix (7) is 1 × 1012cm-3；
The upper trench electrode (2), upper contre electrode (3), lower groove electrode (5) and lower contre electrode (6) doping concentration be 1
×1018cm-3~5 × 1019cm-3；
Semiconductor substrate is lightly doped in the N-shaped, semiconductor substrate is lightly doped in p-type, N-shaped heavily-doped semiconductor matrix and p-type are heavily doped
It is Ge, HgI that miscellaneous semiconductor substrate, which also can be replaced material,2、GaAs、TiBr、CdTe、CdZnTe、CdSe、GaP、HgS、PbI2Or
The semiconductor substrate of any one in AlSb.
The group 7. a kind of two-sided wrong embedded three dimension detector of the described in any item two-dimensional arrangements of application Claims 1 to 5 is arranged side by side
At the two-sided wrong embedded three dimension detector array of two-dimensional arrangements.
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| CN109935643B (en) * | 2019-04-01 | 2024-03-22 | 湘潭大学 | Two-dimensional arrangement double-sided misplaced three-dimensional detector, preparation method thereof and array |
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