CN109935643B - Two-dimensional arrangement double-sided misplaced three-dimensional detector, preparation method thereof and array - Google Patents
Two-dimensional arrangement double-sided misplaced three-dimensional detector, preparation method thereof and array Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention discloses a two-dimensional arrangement double-sided misplaced three-dimensional detector, a preparation method thereof and an array thereof, wherein the two-dimensional arrangement double-sided misplaced three-dimensional detector comprises an upper trench electrode and a lower trench electrode which are respectively etched on the surface of a middle semiconductor substrate; an upper central electrode is embedded in the upper trench electrode, and an upper semiconductor substrate is filled between the upper central electrode and the upper trench electrode; the lower central electrode is embedded in the lower trench electrode, and a lower semiconductor substrate is filled between the lower trench electrode and the lower central electrode; the outer widths of the upper trench electrode and the lower trench electrode are 2R X The lower trench electrode is positioned below the upper trench electrode, the two electrodes are vertically separated by d3, and the two electrodes are overlapped in a quarter part in the horizontal direction, and the upper central electrode and the lower central electrode have the same specification. And generating a silicon dioxide layer on the surface of the chip through gettering oxidation, transferring a detector pattern onto the silicon dioxide layer through marking and photoetching, etching and chemical deposition diffusion of a cathode electrode and an anode electrode, and finally repairing and packaging damage.
Description
Technical Field
The invention belongs to the technical field of photon (including X-ray, laser and X-ray free electron laser) or particle detection, and relates to a two-dimensional arrangement double-sided misplaced three-dimensional detector, a preparation method thereof and an array thereof.
Background
The three-dimensional trench electrode silicon detector is formed by etching a trench electrode and a central electrode with a certain depth on a single side of a chip, and if the trench electrode penetrates through the chip to form a loop, the detector can fall out of the chip. Therefore, a trench electrode and a central electrode with certain depth (smaller than the depth of the chip) are etched on one side of the chip, the bottom part which is not surrounded by the trench electrode is a dead zone, and the sum of the depth of the dead zone at the bottom and the etching depth of the trench electrode etched on one side is the total depth of the chip. Thus, the bottom dead zone ratio is determined by the etch depth of the single-sided etched trench electrode. When the single-sided etched trench electrode and the central electrode of the three-dimensional trench electrode silicon detector are manufactured, if the dead zone proportion is required to be reduced to the minimum, the latest deep etching technology (the highest depth-to-width ratio index) is required, and the depths of the trench electrode and the central electrode are maximized during the single-sided etching. The deep etching technology in the manufacture of the three-dimensional trench electrode silicon detector has high requirements.
The detector is mainly used in the fields of high-energy physics, celestial physics, aerospace, military, medical technology and the like. The three-dimensional groove electrode detector has the advantages that the position resolution is equal to the length of the electrode spacing, if high position resolution is required, the electrode spacing is required to be small, so that the number of electronic reading paths is large, electronics is complex, and the cost is high; and the electrode spacing is small, so that breakdown can be caused, and the electrode is easier to break down under the condition of high depletion voltage. In addition, the central collector and the outer layer groove of the three-dimensional groove electrode silicon detector are formed by etching and filling, the width of the etched groove is related to the depth of the groove, namely the width-depth ratio of the deep etching technology can be 1:30, which means that a groove penetrating through a chip is etched in a chip with the thickness of 300 microns, the width of the groove is 10 microns at the minimum, and the groove cannot collect charges, so the groove cannot be used as a sensitive area and becomes a dead zone, and the dead zone area is increased and the area of the sensitive area is reduced due to the fact that the dead zone area is not small in the whole detector.
Disclosure of Invention
The invention aims to provide a two-dimensional arrangement double-sided misplaced three-dimensional detector, a preparation method thereof and an array, and solves the problems of complex electronics, easy breakdown and low position resolution caused by low sensitivity and multiple electronic read-out paths of the existing three-dimensional trench electrode detector.
The invention further aims to provide a preparation method of the two-dimensional arrangement double-sided misplaced three-dimensional detector.
It is another object of the present invention to provide a two-dimensionally arranged double-sided offset three-dimensional detector array.
The technical scheme adopted by the invention is that the two-dimensional arrangement double-sided misplaced three-dimensional detector comprises an upper trench electrode, a lower trench electrode and a middle semiconductor substrate, wherein the upper trench electrode is etched on the upper surface of the middle semiconductor substrate, and the lower trench electrode is etched on the lower surface of the middle semiconductor substrate; the upper trench electrode has a cuboid structure with an outer length of 2R X The external width is 2R Y The lower trench electrode and the upper trench electrode have the same specification, the lower trench electrode is positioned below the upper trench electrode, the upper surface of the lower trench electrode is vertically separated from the lower surface of the upper trench electrode by d3, and the lower trench electrode and the upper trench electrode are overlapped in a quarter part in the horizontal direction; an upper central electrode is embedded in the upper trench electrode, and an upper semiconductor substrate is filled between the upper central electrode and the upper trench electrode; the lower trench electrode is embedded with a lower central electrode, and a lower semiconductor substrate is filled between the lower trench electrode and the lower central electrode.
Further, the upper central electrode and the lower central electrode have the same specification; the vertical distance d3 between the upper trench electrode and the lower trench electrode satisfies d3=r1 or d3=r2, r1 is the electrode distance between the upper trench electrode and the upper central electrode, and r2 is the electrode distance between the lower trench electrode and the lower central electrode.
Further, the upper central electrode is positioned at the center of the upper trench electrode, and the lower central electrode is positioned at the center of the lower trench electrode; the R is X ＝R Y 。
Further, the upper central electrode and the lower central electrode are both n-type heavily doped semiconductor matrixes; the upper trench electrode and the lower trench electrode are p-type heavily doped semiconductor matrixes; the upper semiconductor substrate, the lower semiconductor substrate and the middle semiconductor substrate are p-type lightly doped semiconductor substrates or n-type lightly doped semiconductor substrates.
Further, the upper central electrode and the lower central electrode are p-type heavily doped semiconductor matrixes; the upper trench electrode and the lower trench electrode are both n-type heavily doped semiconductor matrixes; the upper semiconductor substrate, the lower semiconductor substrate and the middle semiconductor substrate are p-type lightly doped semiconductor substrates or n-type lightly doped semiconductor substrates; the n-type semiconductor substrate, the p-type semiconductor substrate, the n-type heavily doped semiconductor substrate and the p-type heavily doped semiconductor substrate are all semiconductor substrates made of Si.
Further, the doping concentration of the upper semiconductor substrate, the lower semiconductor substrate and the intermediate semiconductor substrate is 1×10 12 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the upper trench electrode, the upper central electrode, the lower trench electrode and the lower central electrode is 1 multiplied by 10 18 cm -3 ～5×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The n-type semiconductor substrate, the p-type semiconductor substrate, the n-type heavily doped semiconductor substrate and the p-type heavily doped semiconductor substrate can be replaced by Ge and HgI 2 、GaAs、TiBr、CdTe、CdZnTe、CdSe、GaP、HgS、PbI 2 Or a semiconductor matrix of any of AlSb.
The invention adopts another technical scheme that a two-dimensional arrangement double-sided misplaced three-dimensional detector array formed by arranging two-dimensional arrangement double-sided misplaced three-dimensional detectors side by side is adopted.
The preparation method of the two-dimensional arrangement double-sided misplaced three-dimensional detector adopts another technical scheme, and comprises the following specific steps:
step S1, cleaning and oxidizing: washing the chip with deionized water until the surface is free of floating dust, putting the chip into a clean oxidation furnace, and performing impurity absorption oxidation in a mixed gas of high-purity oxygen and high-purity nitrogen, wherein the impurity absorption oxidation comprises three stages of defect absorption oxidation, low-temperature crystallization nucleation and surface defect elimination oxidation;
step S2, high-precision marking and photoetching: corresponding photoetching marks are made at a plurality of positions on the chip, and a photoetching machine is aligned to the photoetching marks on the chip, so that a mask plate is accurately attached to the chip; after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that the detector pattern on the mask plate is transferred to the chip, and the detector pattern is developed;
step S3, etching upper and lower anode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower peripheral grooves, adding phosphine gas into silane gas, and chemically depositing the mixed gas in the upper and lower peripheral grooves to generate polysilicon, so that the polysilicon is continuously diffused and filled in the upper and lower peripheral grooves, and forming anode electrodes, namely an upper groove electrode and a lower groove electrode;
step S4, etching upper and lower cathode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower central grooves, and keeping the depths of the upper and lower central grooves consistent; adding diborane gas into silane gas to enable the mixed gas to be chemically deposited in the upper central groove and the lower central groove to generate polysilicon, and enabling the polysilicon to be continuously diffused and filled in the upper central groove and the lower central groove to manufacture cathode electrodes, namely an upper central electrode and a lower central electrode;
step S5, annealing: placing the chip in an annealing furnace, heating in a vacuum environment or a mixed gas of nitrogen and argon, preserving heat, and then cooling to room temperature to obtain an annealed chip;
step S6, photoetching metallization, electrode extraction: after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that a detector pattern on the mask plate is transferred onto the chip, the mask plate pattern is developed, then oxide layers of upper groove electrodes, lower groove electrodes, upper central electrodes and lower central electrode areas on the chip after photoetching development are etched, and metal is plated on the surfaces of the upper groove electrodes, lower groove electrodes, upper central electrodes and lower central electrodes;
step S7, packaging: the detector unit or array is marked on the silicon wafer, the detector unit or array is fixed on the supporting base, the electrode points on the detector are connected with the pins outside through welding by using metal wires, and finally the detector unit or array is sealed by using a plastic tube shell.
Further, in the step S1, the cleaning of the oxidation furnace is to add halogen gas into the high-purity oxygen flow at high temperature, wherein the volume percentage of the halogen gas is less than or equal to 15%; the internal absorbing defect removal oxidation is carried out for 3 to 7 hours under the high temperature condition of 1100 to 1400 ℃; the low-temperature crystallization nucleation is carried out for 3 to 7 hours under the temperature condition of 700 to 1000 ℃; the surface defect eliminating oxidation is carried out for 18-24 hours under the temperature condition of 1000-1400 ℃.
Further, in the step S5, the temperature is raised to 700-1000 ℃, the annealing time is 50S-100 min, the temperature is raised to 50-1000S, and the heat preservation time is 2-10 min.
The two-dimensional arrangement double-sided misplaced three-dimensional detector, the preparation method and the array thereof have the beneficial effects that firstly, the depth of the groove needing single-sided etching is reduced due to the adoption of double-sided etching, so that the widths of a central electrode and a groove electrode can be reduced by half, the dead zone of the electrode is greatly reduced, and when the heights of the detectors are consistent, the electrode is provided with the inventionThe dead zone of the electrode is only half of that of the traditional three-dimensional groove electrode detector, so that the dead zone of the electrode is reduced, and the sensitivity is improved; secondly, the trench electrodes are not etched to the bottom, the distance between the two trench electrodes in the vertical direction is d3, the two trench electrodes can be kept from being in contact with each other, short circuit is avoided, and meanwhile chips can be mechanically connected with each other; d3 is equal to the distance between the trench electrode and the central electrode, so that when the detector is exhausted, the exhaust width in the vertical direction is approximately equal to the exhaust width in the horizontal direction, the electric field distribution in the detector can be more uniform, and the treatment is facilitated; the two-dimensional arrangement double-sided misplaced three-dimensional detector can detect the position change of the vertically incident particles and photons in the two-dimensional direction, and the detected minimum position changes of the vertically incident particles and photons in the transverse direction and the longitudinal direction are allThe minimum position change of the detected particles and photons which are vertically incident is smaller than that of the traditional detector, so that the position resolution is improved; the detector array of the invention has a large width and length, and the risk of breakdown is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a two-dimensional array double-sided misplaced three-dimensional detector;
FIG. 2 is a top view of a two-dimensional array of two-sided offset three-dimensional detectors;
FIG. 3 is a top view of an array of two-dimensionally arrayed double-sided offset three-dimensional detectors 2*1;
fig. 4 is a front view of an array of two-dimensionally arranged double-sided offset three-dimensional detectors 2*1.
In the figure, 1. Upper semiconductor body, 2. Upper trench electrode, 3. Upper center electrode, 4. Lower semiconductor body, 5. Lower trench electrode, 6. Lower center electrode, 7. Intermediate semiconductor body.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
The two-dimensional arrangement double-sided staggered embedded three-dimensional detector is shown in fig. 1 to 3, and comprises a third silicon substrate 7, wherein an upper groove electrode 2 is etched on the upper surface of the third silicon substrate 7, a lower groove electrode 5 is etched on the lower surface of the third silicon substrate 7, the upper groove electrode 2 and the lower groove electrode 5 are of a cuboid structure with hollow interiors, an upper central electrode 3 is embedded in the upper groove electrode 2, a lower central electrode 6 is embedded in the lower groove electrode 5, an upper semiconductor substrate 1 is filled between the upper central electrode 3 and the upper groove electrode 2, and a lower semiconductor substrate 4 is filled between the lower groove electrode 5 and the lower central electrode 6. The outer length of the upper trench electrode 2 is 2R X The external width is 2R Y The centers of the upper center electrode 3 and the lower center electrode 6 are vertically separated by d3, d3=r1 or d3=r2, r1 is the electrode spacing of the upper center electrode 3 and the upper trench electrode 2, and r2 is the electrode spacing of the lower center electrode 6 and the lower trench electrode 5. The upper trench electrode 2 and the lower trench electrode 5 have the same specification, the upper central electrode 3 and the lower central electrode 6 have the same specification, and the upper trench electrode 2 and the lower trench electrode 5 are overlapped in a quarter part in the horizontal direction, namely the upper central electrode 3 and the lower central electrode 6 are transversely and longitudinally separated by R on the same horizontal plane X . The upper semiconductor substrate 1, the lower semiconductor substrate 4 and the middle semiconductor substrate 7 are all ultra-pure high-resistance silicon with doping concentration of 1×10 12 cm -3 A (lightly doped) p-type silicon matrix; the upper trench electrode 2 and the lower trench electrode 5 are doped with a concentration of 1×10 18 cm -3 A p-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 are doped with a concentration of 1×10 18 cm -3 An n-type heavily doped silicon matrix.
Example 2
Unlike embodiment 1, the upper trench electrode 2 and the lower trench electrode 5 of this embodiment have a doping concentration of 25×10 18 cm -3 A p-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 have a doping concentration of 25×10 18 cm -3 An n-type heavily doped silicon matrix.
Example 3
Unlike examples 1 to 2, the upper trench electrode 2 and the lower trench electrode 5 of this example have a doping concentration of 5×10 19 cm -3 A p-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 are doped with a concentration of 5×10 19 cm -3 An n-type heavily doped silicon matrix.
Example 4
Unlike examples 1 to 3, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are doped with a concentration of 1×10 18 cm -3 An n-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 have a doping concentration of 1×10 18 cm -3 P-type heavily doped silicon matrix of (a).
Example 5
Unlike examples 1 to 4, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are doped with 25×10 of the doping concentration of the p-type silicon substrate 18 cm -3 An n-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 have a doping concentration of 25×10 18 cm -3 P-type heavily doped silicon matrix of (a).
Example 6
Unlike examples 1 to 5, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are dopedThe impurity concentration is 5 multiplied by 10 19 cm -3 An n-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 are doped with a concentration of 5×10 19 cm -3 P-type heavily doped silicon matrix of (a).
Example 7
Unlike examples 1 to 6, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are doped with a concentration of 1×10 18 cm -3 A p-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 have a doping concentration of 1×10 18 cm -3 An n-type heavily doped silicon matrix.
Example 8
Unlike examples 1 to 7, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are doped with a concentration of 25×10 18 cm -3 A p-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 have a doping concentration of 25×10 18 cm -3 An n-type heavily doped silicon matrix.
Example 9
Unlike examples 1 to 8, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are doped with a concentration of 5×10 19 cm -3 A p-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 are doped with a concentration of 5×10 19 cm -3 An n-type heavily doped silicon matrix.
Example 10
Unlike examples 1 to 9, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are doped with a concentration of 1×10 18 cm -3 An n-type heavily doped silicon matrix; upper central electricityThe electrode 3 and the lower central electrode 6 are doped with a concentration of 1X 10 18 cm -3 P-type heavily doped silicon matrix of (a).
Example 11
Unlike examples 1 to 10, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are doped with a concentration of 25×10 18 cm -3 An n-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 have a doping concentration of 25×10 18 cm -3 P-type heavily doped silicon matrix of (a).
Example 12
Unlike examples 1 to 11, the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 of this example are doped at a concentration of 1×10 12 cm -3 The upper trench electrode 2 and the lower trench electrode 5 are doped with a concentration of 5×10 19 cm -3 An n-type heavily doped silicon matrix; the upper central electrode 3 and the lower central electrode 6 are doped with a concentration of 5×10 19 cm -3 P-type heavily doped silicon matrix of (a).
The embodiments 4 to 6 provide the detectors of the embodiments 7 to 9 with the sensitive regions of p-type lightly doped silicon, the central electrode of p-type heavily doped silicon and the trench electrode of n-type heavily doped silicon so that the PN junction is located near the trench electrode, the sensitive regions of n-type lightly doped silicon, the central electrode of n-type heavily doped silicon and the trench electrode of p-type heavily doped silicon, and the PN junction is located near the trench electrode so that the electric field is smooth, the electric field variation is small, and the detectors are not easy to break down during operation. And the heavy doping concentrations of example 4 and example 7 are optimal, so that damage is not formed during doping and the upper semiconductor body 1, the lower semiconductor body 4 and the intermediate semiconductor body 7 are more easily depleted, because the heavy doping electrode has too high a doping concentration, damage is formed during doping, and if the doping concentration is more than 10 20 cm -3 The damage is not easy to remove, the doping concentration of the heavily doped electrode is too small to form a single-sided heterojunction, so that the upper semiconductor substrate 1, the lower semiconductor substrate 4 and the intermediate semiconductor substrate 7 are not easy to be depleted. Examples 1 and 14, the sensitive region is p-type lightly doped silicon, and in the embodiment 7 and the embodiment 9, the sensitive region is n-type lightly doped silicon, so that the embodiment 1 and the embodiment 4 are more radiation resistant than the embodiment 7 and the embodiment 9; in the embodiments 4 and 7, the PN junction is located near the trench electrode, the electric field is smooth, the electric field variation is small, and the PN junction is not easy to break down during operation. Thus, example 4 and example 7 are less prone to localized breakdown than example 1 and example 9. Under high radiation (high energy physical experiment), the performance is from strong to weak as example 4, example 1, example 7, example 9; at low radiation (e.g., photon detection), there is no significant difference in performance.
The detector is depleted along the upper trench electrode 2 to the upper central electrode 3 and depleted along the lower trench electrode 6 to the lower central electrode 5, so that the silicon substrate between the trench electrode and the central electrode is called depletion region or sensitive region, i.e. the upper semiconductor substrate 1 and the lower semiconductor substrate 4 are sensitive regions of the detector of the invention, which are both n-type silicon or p-type silicon, but since n-type silicon is converted into p-type silicon in a high radiation environment, p-type silicon is generally used in a high radiation environment, and the radiation resistance is better. The doping concentrations of the upper semiconductor substrate 1 and the lower semiconductor substrate 4 are selected so that the silicon substrate is ultra-pure high-resistance silicon, which is the concentration of ultra-pure silicon that can be formed by the prior art, or just the concentration of high-resistance silicon, which is not made by the prior art, and the resistivity of the silicon with the larger concentration becomes smaller and the leakage current becomes larger, so that the doping concentrations of the upper semiconductor substrate 1, the lower semiconductor substrate 4 and the intermediate semiconductor substrate 7 are selected to be 1×10 12 cm -3 . The range of heavily doped silicon doping concentrations of the upper trench electrode 2, the lower trench electrode 5, the upper central electrode 3 and the lower central electrode 6 is to keep a concentration difference of several orders of magnitude with the upper semiconductor substrate 1 and the lower semiconductor substrate 4 (lightly doped silicon), so that a single-side abrupt junction is formed, and the upper semiconductor substrate 1, the lower semiconductor substrate 4 and the intermediate semiconductor substrate 7 are more easily depleted.
R X And R is Y When the energy is not equal, the central electrode is lengthened, the capacitance is increased, and the energy resolution of the detector is reduced, so R X ＝R Y 。
The maximum electric field of the PN junction position near the trench electrode is far smaller than that of the PN junction position near the center electrode, examples 4 to 6 set the upper semiconductor substrate 1 and the lower semiconductor substrate 4 to be p-type lightly doped silicon, the upper center electrode 3 and the lower center electrode 6 to be p-type heavily doped silicon, the upper trench electrode 2 and the lower trench electrode 5 to be n-type heavily doped silicon, so that the PN junction position near the upper trench electrode 2 and the lower trench electrode 5 to keep the electric field smooth, the electric field variation is small, the detector operating voltage is far greater than the depletion voltage, and the detector is not easy to break down during operation; and the upper semiconductor substrate 1 and the lower semiconductor substrate 4 are p-type semiconductor substrates, so that the radiation resistance is high.
The upper trench electrode 2, the lower trench electrode 5, the upper central electrode 3 and the lower central electrode 6 are heavily doped with a doping concentration of 1×10 18 cm -3 ～5×10 19 cm -3 The concentration difference between the semiconductor substrate and the lightly doped silicon (the upper semiconductor substrate 1 and the lower semiconductor substrate 4) is kept to be several orders of magnitude, and a unilateral abrupt junction is formed, so that the breakdown voltage is different from the depletion voltage by several orders of magnitude, and the lightly doped silicon is more easily depleted.
The semiconductor detector preparation material is not limited to Si-based material, and can be Ge or HgI 2 、GaAs、TiBr、CdTe、CdZnTe、CdSe、GaP、HgS、PbI 2 Or AlSb, has wide application range and has adaptive modification of the preparation method.
In theory, if the center electrode is located in the trench electrode, but if the center electrode is not located in the center of the trench electrode, the electric fields on both sides of the center electrode are larger and smaller, and the peak value of the signal (count rate) is reduced due to the difference, so that the peak width is widened, which is not beneficial to processing. It is preferable that the upper center electrode 3 of the present invention is located at the center of the upper trench electrode 2 and the lower center electrode 6 is located at the center of the lower trench electrode 5.
Since the number of electron-hole pairs generated by the incident mip particles in the detector medium is proportional to the path length traversed by the mip particles, the upper trench electrode 2 and the lower trench electrode 5 are identical in specification, and the upper central electrode 3 and the lower central electrode 6 are identical in specification, so that the number of electron-hole pairs generated by the incident mip particles in the upper semiconductor substrate 1 and the lower semiconductor substrate 4 (the sensitive region) are consistent, and the subsequent processing of the readout signal is facilitated.
The middle part of the middle semiconductor substrate 7 is reserved to prevent the substrate with the thickness d3 from being etched through, so that the upper trench electrode 2 and the lower trench electrode 5 can be kept from being contacted with each other, and short circuit is avoided; and mechanically interconnects the upper semiconductor body 1 and the lower semiconductor body 4 and the intermediate semiconductor body 7, ensuring that the detector does not fall off. In addition, d3=r1=r2, where r1 is the electrode distance between the upper trench electrode 2 and the upper central electrode 3, and r2 is the electrode distance between the lower trench electrode 5 and the lower central electrode 6, so that when the detector is depleted, the depletion width in the vertical direction is approximately equal to the depletion width in the horizontal direction, that is, the vertical distance between the upper trench electrode 2 and the lower trench electrode 6 is equal to the distance between the upper trench electrode and the upper central electrode, and is equal to the distance between the lower trench electrode and the lower central electrode, so that the electric field distribution inside the detector can be more uniform (the values of the electric fields are not greatly different); the values of the electric fields at two sides of the uneven electric field are larger and smaller, and the difference of the values of the electric fields can cause the peak value of the signal (counting rate) to be reduced, so that the peak width is widened, and the processing is not facilitated.
FIG. 2 is a top view of a two-dimensional array double-sided staggered three-dimensional detector with upper and lower collector numbers T, B, each consisting of a trench electrode, a center electrode and a semiconductor substrate, with the mipparticles incident normally, indicating that the particles are in the overlapping region of T and B if T and B both have signals; if T has a signal, the particles are in the area where T is not overlapped with B; if B has a signal, it indicates that the particle is in a region where B does not overlap T. If two-dimensional two-sided staggered three-dimensional detectors are arranged into a detector array, the incidence position of the perpendicular incidence mip particles can be known according to the number of the collector T, B collecting the signals based on the principle. According to the response conditions, one detector can be divided into three conditions of response of only an upper collector, response of both an upper collector and a lower collector and response of only the lower collector, and the detected particles and photons which are vertically incident have the minimum position change, and the horizontal and the longitudinal directions are:rule of position resolution strictly equal to unit of traditional three-dimensional groove electrode silicon detectorHowever, the minimum position change of the vertical incidence particles and photons detected by the detector is smaller than that of the conventional detector, so that the position resolution is higher.
FIG. 3 shows an array of two-dimensional array double-sided offset three-dimensional detectors 2*1 in which the upper and lower units are displaced R in both the x-direction and the Y-direction X 。a 1 An upper detection unit, a, being the first detector 2 An upper detection unit of the second detector, b 1 A lower detection unit, b, being the first detector 2 Is the lower detection unit of the second detector, and the upper and lower detection units of each detector have 1/4 of the partial overlap at the chip level. According to the overlapping part between the units, the two-dimensional array of the two-sided staggered three-dimensional detector 2*1 is divided into a, b, c, d, e, f, g intervals, wherein the interval a is an interval in which only the a1 detection unit is responsive when particles are incident, the interval b is an interval in which both the a1 detection unit and the b1 detection unit are responsive when particles are incident, the interval c is an interval in which only the b1 detection unit is responsive when particles are incident, the interval d is an interval in which both the a2 detection unit and the b1 detection unit are responsive when particles are incident, the interval e is an interval in which only the a2 detection unit is responsive when particles are incident, the interval f is an interval in which both the a2 detection unit and the b2 detection unit are responsive when particles are incident, the change of the positions of the particles can be detected in both the transverse direction and the longitudinal direction, and the resolution is correspondingly improved.
Fig. 4 shows a two-dimensional array of two-sided offset three-dimensional detectors 4*1 with greatly reduced dead space and improved resolution. In order to maintain high position resolution, the width and the length of the traditional three-dimensional trench electrode silicon detector are small, and the detector is easy to break down. The two-dimensional arrangement double-sided misplaced three-dimensional detector can be large in width and length, and the breakdown risk is greatly reduced. And an array of small detector cells requires more electronic read-out paths, is technically complex and costly. The dead zone volume of the detector, which is acted by the electrode, is reduced, and the sensitivity is improved; the detector has lateral and longitudinal position resolution ofThe conventional detector has a position resolution sigma X ＝2R X The position resolution is improved.
The preparation method of the two-dimensional arrangement double-sided misplaced three-dimensional detector comprises the following specific steps:
step S1, cleaning and oxidizing: the chip is cleaned by deionized water until the surface has no floating dust, and is put into a clean oxidation furnace, and the mixed gas of high-purity oxygen and high-purity nitrogen is subjected to impurity absorption oxidation, wherein the impurity absorption oxidation comprises three stages of defect absorption oxidation, low-temperature crystallization nucleation and surface defect elimination oxidation. The internal absorbing defect removal oxidation is carried out for 3 to 7 hours under the high temperature condition of 1100 to 1400 ℃; the low-temperature crystallization nucleation is oxidation for 3-7 hours at the temperature of 700-1000 ℃; the surface defect eliminating oxidation is carried out for 18 to 24 hours under the temperature condition of 1000 to 1400 ℃.
The cleaning of the oxidation furnace is to add halogen gas into high-purity oxygen flow at high temperature, wherein the volume percentage of the halogen gas is less than or equal to 15%, the most common halogen gas is chlorine, most heavy metal atoms react with the chlorine to generate gaseous metal chloride, thereby greatly improving the cleanliness in the furnace, reducing ion contamination and improving SiO (silicon dioxide) 2 Si interface quality.
Through oxidation, an oxide layer is generated on the surface of the silicon wafer, so that dangling bonds on the surface of the silicon chip are reduced, surface passivation is achieved, and surface leakage current caused by external dirt is reduced. The introduction of oxygen can make the defects inside the chip more stable, reduce the recombination of carriers, improve the minority carrier lifetime of the chip, make the radiation resistance better, the leakage current lower, adsorb impurities, and make the impurities of the chip lower. And the oxide layer generated by high-temperature oxidation has hard texture, and can protect the chip from being scratched.
Compared with direct oxidation, a semiconductor device manufactured by using ultra-pure high-resistance silicon prepared by a systematic removal oxidation process has a plurality of performance advantages: minority carriers have longer lifetimes, less total depletion capacitance, less interface state density, greater ion diffusion distance, and less leakage current. The service life of minority carriers of a device manufactured by directly oxidizing monocrystalline silicon is 129 mu s, and the service life of minority carriers of the device manufactured by applying a defect-removing oxidation process can reach 720 mu s, so that the service life of minority carriers of the device is prolonged by more than 5 times.
Step S2, high-precision marking and photoetching: corresponding photoetching marks are made at a plurality of positions on the chip, and a photoetching machine is aligned to the photoetching marks on the chip, so that a mask plate is accurately attached to the chip; after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that the detector pattern on the mask plate is transferred to the chip, and the detector pattern is developed;
step S3, etching upper and lower anode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower peripheral grooves, adding phosphine gas into silane gas, and chemically depositing the mixed gas in the upper and lower peripheral grooves to generate polysilicon, so that the polysilicon continuously diffuses and fills the grooves to form anodes, namely an upper groove electrode 2 and a lower groove electrode 5;
step S4, etching upper and lower cathode electrodes and performing chemical deposition diffusion: etching the chips subjected to photoetching development from the top and the bottom by using a deep etching machine to form hollow upper and lower central grooves, and keeping the depths of the upper and lower central grooves consistent; adding diborane gas into silane gas, and chemically depositing the mixed gas in the upper and lower central grooves to generate polysilicon, so that the polysilicon continuously diffuses to fill the grooves, and forming a cathode, namely an upper central electrode 3 and a lower central electrode 6;
step S5, annealing: placing the chip in an annealing furnace, heating in a vacuum environment or a mixed gas of nitrogen and argon, maintaining for a certain time, and then cooling to room temperature to obtain an annealed chip;
in the step S5, the temperature is 700-1000 ℃, the annealing time is 50S-100 min, the temperature is 50-1000S, and the heat preservation time is 2-10 min. The annealing aims to remove the damage in the chip, keep the temperature for a certain time to decompose the damage in the chip into simple defects, recover the minority carrier lifetime part, and prevent the leakage current and the depletion voltage of the chip from being too large due to the existence of the defects.
Step S6, photoetching metallization, electrode extraction: after the chip is evenly glued, the chip is placed under a mask plate and is exposed by ultraviolet light, so that a detector pattern on the mask plate is transferred onto the chip, the mask plate pattern is developed, then oxide layers in areas of an upper groove electrode 2, a lower groove electrode 5, an upper central electrode 3 and a lower central electrode 6 on the chip after photoetching development are etched, and metal is plated on the oxide layers;
step S7, packaging: and drawing a detector unit array on the silicon wafer, fixing the detector unit array on a supported base, connecting electrode points on the detector with external pins through welding by using metal wires, and finally sealing by using a plastic tube shell to protect the detector chip and form the whole chip. Pins of the lead-out chip are utilized for connection to external devices.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (7)
1. The two-dimensional arrangement double-sided staggered embedded three-dimensional detector is characterized by comprising an upper trench electrode (2), a lower trench electrode (5) and a middle semiconductor substrate (7), wherein the upper trench electrode (2) is etched on the upper surface of the middle semiconductor substrate (7), and the lower trench electrode (5) is etched on the lower surface of the middle semiconductor substrate (7); the upper trench electrode (2) is of a cuboid structure with an external length of 2R X The external width is 2R Y The lower trench electrode (5) and the upper trench electrode (2) have the same specification, the lower trench electrode (5) is positioned below the upper trench electrode (2), the upper surface of the lower trench electrode (5) is vertically separated from the lower surface of the upper trench electrode (2) by d3, and the two electrodes are overlapped in a quarter part in the horizontal direction; an upper central electrode (3) is embedded in the upper trench electrode (2), and an upper semiconductor substrate (1) is filled between the upper central electrode (3) and the upper trench electrode (2); a lower central electrode (6) is embedded in the lower trench electrode (5), and the lower trench electrodeA lower semiconductor substrate (4) is filled between the electrode (5) and the lower center electrode (6).
2. The two-dimensional arranged double-sided misplaced three-dimensional detector according to claim 1, characterized in that the upper central electrode (3) and the lower central electrode (6) have the same specification;
the vertical distance d3 between the upper trench electrode (2) and the lower trench electrode (5) satisfies d3=r1 or d3=r2, r1 is the electrode distance between the upper trench electrode (2) and the upper central electrode (3), and r2 is the electrode distance between the lower trench electrode (5) and the lower central electrode (6).
3. The two-dimensional arranged double-sided offset three-dimensional detector according to claim 2, wherein the upper central electrode (3) is located at the center of the upper trench electrode (2), and the lower central electrode (6) is located at the center of the lower trench electrode (5);
the R is X = R Y 。
4. A two-dimensional arranged double-sided offset three-dimensional detector according to claim 3, characterized in that the upper central electrode (3) and the lower central electrode (6) are both n-type heavily doped semiconductor matrices;
the upper trench electrode (2) and the lower trench electrode (5) are p-type heavily doped semiconductor matrixes;
the upper semiconductor substrate (1), the lower semiconductor substrate (4) and the middle semiconductor substrate (7) are p-type lightly doped semiconductor substrates or n-type lightly doped semiconductor substrates.
5. A two-dimensional arranged double-sided offset three-dimensional detector according to claim 3, characterized in that the upper central electrode (3) and the lower central electrode (6) are both p-type heavily doped semiconductor substrates;
the upper trench electrode (2) and the lower trench electrode (5) are both n-type heavily doped semiconductor matrixes;
the upper semiconductor substrate (1), the lower semiconductor substrate (4) and the middle semiconductor substrate (7) are p-type lightly doped semiconductor substrates or n-type lightly doped semiconductor substrates;
the n-type lightly doped semiconductor substrate, the p-type lightly doped semiconductor substrate, the n-type heavily doped semiconductor substrate and the p-type heavily doped semiconductor substrate are all semiconductor substrates made of Si.
6. The two-dimensional array double-sided offset three-dimensional probe according to any one of claims 1 to 5, wherein the doping concentration of the upper semiconductor substrate (1), the lower semiconductor substrate (4) and the intermediate semiconductor substrate (7) is 1×10 12 cm -3 ；
The doping concentration of the upper trench electrode (2), the upper central electrode (3), the lower trench electrode (5) and the lower central electrode (6) is 1 multiplied by 10 18 cm -3 ～5×10 19 cm -3 ；
The n-type lightly doped semiconductor substrate, the p-type lightly doped semiconductor substrate, the n-type heavily doped semiconductor substrate and the p-type heavily doped semiconductor substrate can be replaced by Ge and HgI 2 、GaAs、TiBr、CdTe、CdZnTe、CdSe、GaP、HgS、PbI 2 Or a semiconductor matrix of any of AlSb.
7. A two-dimensional array of two-dimensional staggered three-dimensional detectors comprising two-dimensional array two-dimensional staggered three-dimensional detectors according to any one of claims 1 to 5 arranged side by side.
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