CN109994388B - Manufacturing method of semiconductor device, semiconductor device and electronic device - Google Patents
Manufacturing method of semiconductor device, semiconductor device and electronic device Download PDFInfo
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- CN109994388B CN109994388B CN201711477771.XA CN201711477771A CN109994388B CN 109994388 B CN109994388 B CN 109994388B CN 201711477771 A CN201711477771 A CN 201711477771A CN 109994388 B CN109994388 B CN 109994388B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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Abstract
The invention provides a method for manufacturing a semiconductor device, a semiconductor device and an electronic apparatus, the method comprising: providing a semiconductor substrate, and forming a terminal ring area and a cell area on the semiconductor substrate; and forming a protective layer covering the terminal ring area and a support structure positioned on the cell area on the semiconductor substrate, wherein the top of the support structure is lower than the top of the protective layer or is flush with the top of the protective layer. According to the manufacturing method of the semiconductor device, the semiconductor device and the electronic device, the supporting structure located in the cell area is formed on the semiconductor substrate, the height difference between the top of the cell area structure and the top of the terminal ring area structure before the back of the wafer is thinned is reduced, the risk of fragments caused by a film uncovering process and a film uncovering process which are caused by the fact that an organic protective film is used as a buffer layer in the subsequent grinding and thinning process is avoided, the process flow is simplified, and meanwhile the occurrence of fragments or microcracks is reduced.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of manufacturing a semiconductor device, and an electronic apparatus.
Background
Insulated Gate Bipolar Transistors (IGBTs) have become one of the most important high-power mainstream devices in the field of power electronics. As high power discrete devices, reducing static (Vcesat) and dynamic (Eoff) power consumption has been a development direction for IGBTs. Theoretically, static (Vcesat) and dynamic (Eoff) power consumption are mutually constrained (trade-off).
In the existing IGBT structure, the static (Vcesat) and dynamic (Eoff) power consumption can be optimized simultaneously by further reducing the thickness of the device. The method is also a development direction of a new generation of IGBT in international mainstream IGBT factories. However, as the device thickness is reduced, the grinding process and subsequent laser annealing (LTA) process pose significant challenges.
A typical IGBT structure includes a terminal ring region and a cell region (cell), wherein on a front surface of the IGBT, due to a terminal ring region having a terminal ring structure and a protective layer, such as a polyimide (polyimide) film, covering the terminal ring region, a height difference exists between the terminal ring region and the cell (cell) region on the front surface, and this height difference often causes chips or microcracks in a back grinding and thinning process. The debris causes device failure and the microcracks, in the subsequent laser annealing process, also cause wafer chipping. To this end, the present invention provides a new method of manufacturing a semiconductor device, and an electronic apparatus to solve the problems in the prior art.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, and forming a terminal ring area and a cell area on the semiconductor substrate;
and forming a protective layer covering the terminal ring area and a support structure positioned on the cell area on the semiconductor substrate, wherein the top of the support structure is lower than the top of the protective layer or is flush with the top of the protective layer.
Illustratively, the support structure and the protective layer are provided as the same material layer.
Illustratively, the protective layer and the support structure comprise a passivation layer and a polyimide film layer stacked in sequence from bottom to top
Illustratively, the support structures are arranged in a criss-cross line pattern in the cell region.
Illustratively, the support structure is formed in the same step as the protective layer.
Illustratively, the step of forming the protective layer and the support structure includes:
forming a passivation layer on the semiconductor substrate, wherein the passivation layer covers the terminal ring region and a region, where the support structure is to be formed, in the cell region;
and forming a polyimide film layer on the semiconductor substrate, wherein the polyimide film layer is laminated on the passivation layer and has a shape consistent with the passivation layer.
Illustratively, the step of forming a passivation layer on the semiconductor substrate includes:
depositing to form a passivation film material layer;
forming a patterned photoresist layer on the passivation film material layer, wherein the patterned photoresist layer covers the terminal ring region and a region, to be formed with the support structure, in the cell region;
etching the passivation film material layer by taking the patterned photoresist layer as a mask to form the passivation layer;
and removing the patterned photoresist layer.
Illustratively, the step of forming a polyimide film layer on the semiconductor substrate includes:
coating and forming a polyimide material layer on the semiconductor substrate;
and patterning the polyimide material layer by adopting a photoetching process to form a polyimide film layer stacked on the passivation layer.
Illustratively, the semiconductor device includes an IGBT.
The present invention also provides a semiconductor device comprising:
the semiconductor device comprises a semiconductor substrate, wherein a terminal ring area and a cell area are formed on the semiconductor substrate;
a protective layer covering the terminal ring region; and
a support structure on the cell region, wherein the top of the support structure is lower than or level with the top of the protection layer.
Illustratively, the protective layer and the support structure are provided as the same layer of material.
Illustratively, the protective layer and the support structure include a passivation layer and a polyimide film layer stacked in sequence from bottom to top.
Illustratively, the support structures are arranged in a criss-cross line pattern in the cell region.
Illustratively, the semiconductor device includes an IGBT.
The invention also provides an electronic device comprising the semiconductor device as described above.
According to the manufacturing method of the semiconductor device, the semiconductor device and the electronic device, the supporting structure located in the cell area is formed on the semiconductor substrate, so that the height difference between the top of the cell area before the back of the wafer is thinned and the top of the terminal ring area is reduced, the risk of fragments caused by a film uncovering process and a film uncovering process due to the fact that an organic protective film is used as a buffer layer in the subsequent grinding and thinning process is avoided, the process flow is simplified, the occurrence of fragments or microcracks in the grinding process is reduced, the failure of the device is reduced, and the yield of products is improved; meanwhile, due to the reduction of the height difference, the window of the thinning process is greatly optimized.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A and 1B are a schematic structural view and a schematic plan view of a semiconductor device;
FIGS. 2A-2F are schematic structural and plan views of a semiconductor device formed in a method of fabricating a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method of manufacturing a semiconductor device according to one embodiment of the present invention;
fig. 4 is a schematic diagram of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
In the following description, a detailed description will be given to illustrate a method of manufacturing a semiconductor device according to the present invention, in order to thoroughly understand the present invention. It will be apparent that the invention may be practiced without limitation to specific details that are within the skill of one of ordinary skill in the semiconductor arts. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same elements are denoted by the same reference numerals, and thus the description thereof will be omitted.
In the existing IGBT structure, the static (Vcesat) and dynamic (Eoff) power consumption can be optimized simultaneously by further reducing the thickness of the device. However, as the device thickness is reduced, the grinding process and subsequent laser annealing (LTA) process pose significant challenges.
A typical IGBT structure includes a terminal ring region and a cell (cell) region, wherein on a front surface of the IGBT, since the terminal ring region has a terminal ring structure and a protective layer, such as a polyimide (polyimide) film layer, covering the terminal ring region, a height difference exists between the terminal ring region and the cell region on the front surface, and this height difference often causes chips or microcracks to occur in a back grinding and thinning process.
As shown in fig. 1A, a semiconductor substrate 100 on the front surface of the IGBT includes a cell region and a terminal ring region formed thereon, wherein the cell region includes a drift region (not shown) formed on the semiconductor substrate 100, a trench-type gate structure 102 formed in the drift region, a base region 101 formed on both sides of the trench-type gate structure, a source region 103 formed in the base region 101 on both sides of the trench-type gate structure 102, an interlayer dielectric layer 104 formed over the trench-type gate structure 102, and an emitter 105 formed over the interlayer dielectric layer 104 and in contact with the source region 103; the termination ring region includes Field Oxide (FOX)106 formed in the semiconductor substrate 100 at intervals over a drift region (not shown), a field plate 107 partially covering the field oxide 106 and exposing the semiconductor substrate 100, and an interlayer dielectric layer 104 covering the field plate 107 and the field oxide 106 and partially exposing the field plate 107 and the semiconductor substrate 100, a metal field plate 108 formed on the interlayer dielectric layer 104 and contacting the semiconductor substrate, and a protective layer film 109 formed on the terminal ring region. Fig. 1B shows a schematic plan view of a semiconductor device, and the front surface of the IGBT structure includes a cell region and a terminal ring region, wherein the terminal ring region is covered by a protective layer film 109, and an emitter 105 is on top of the cell region. Since the formed termination ring region has the field oxide 106, the field plate 107 and the protection film 109 covering the termination ring region, the height difference between the top of the finally formed termination ring region and the top of the cell (cell) region is the height difference H (as shown in fig. 1A) between the top of the protection film 109 and the top of the emitter 105, and this height difference often causes chipping or microcracking in the polishing process. The debris causes device failure and the microcracks, in the subsequent laser annealing process, also cause wafer chipping.
The method for solving the problem is that before a grinding and thinning process, an organic film is pasted on the front surface of the IGBT device to serve as a protective film, and a soft organic film serves as a buffer layer, so that stress caused by height difference of the front surface in the grinding process is reduced, and generation and occurrence of fragments and microcracks are reduced. However, this method brings about a film peeling process for peeling off the organic film after thinning, and a typical film peeling process is to heat the organic film to a certain temperature (e.g. 40 ℃ to 60 ℃) and then manually or mechanically peel off the organic film from one end of the wafer surface to the other end, and since the organic film has a certain viscosity, the risk of wafer fragments is very likely to be caused during the film peeling process after thinning the wafer. Meanwhile, the organic protective film can only be used as a buffer layer, and the height difference of the protective layer on the terminal ring area and the cell area on the device cannot be directly eliminated, so that the thinning process window is very narrow, and the method for further improving the performance of the device through thinning is limited.
In order to solve the technical problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a terminal ring area and a cell area on the semiconductor substrate;
and forming a protective layer covering the terminal ring area and a support structure positioned on the cell area on the semiconductor substrate, wherein the top of the support structure is lower than the top of the protective layer or is flush with the top of the protective layer.
According to the manufacturing method of the semiconductor device, the supporting structure located in the cell area is formed on the semiconductor substrate, so that the height difference between the top of the cell area and the top of the terminal ring area before the back of the wafer is thinned is reduced, the risk of fragments caused by a film uncovering process and a film uncovering process due to the fact that an organic protective film is used as a buffer layer in the subsequent grinding and thinning process is avoided, the process flow is simplified, the occurrence of fragments or microcracks in the grinding process is reduced, the failure of the device is reduced, and the yield of the product is improved; meanwhile, due to the reduction of the height difference, the window of the thinning process is greatly optimized.
A method of manufacturing a semiconductor device and a semiconductor device according to the present invention are exemplarily illustrated with reference to fig. 2A to 2E and fig. 3, and fig. 2A to 2E are a schematic structural view and a schematic plan view of a semiconductor device formed in a method of manufacturing a semiconductor device according to an embodiment of the present invention; fig. 3 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
The present embodiment is described by taking the manufacturing process of the IGBT device as an example, and it should be understood that the description of the IGBT device manufacturing process is only exemplary, and any semiconductor device having a cell region and a terminal ring region, which is covered with a protection layer in the terminal ring region, is suitable for the present invention.
First, referring to fig. 3, step S1 is performed: providing a semiconductor substrate, and forming an IGBT structure on the semiconductor substrate, wherein the IGBT structure comprises a terminal ring area and a cellular area.
As shown in fig. 2A, a semiconductor substrate 200 is provided, which may be, in particular, at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like.
An IGBT structure including a terminal ring region and a cell region is formed on the semiconductor substrate 200. Specifically, the cell region includes a front structure forming an IGBT device, such as a base region, an emitter region, a gate oxide layer, a gate, an emitter, and the like of the IGBT. Referring to fig. 2A, the cell region includes: the semiconductor device includes a semiconductor substrate 200, a drift region (not shown) of a first conductive type formed on the semiconductor substrate 200, a trench-type gate structure 201 formed on the semiconductor substrate 200, a base region 202 of a second conductive type formed on both sides of a bottom of the trench-type gate structure 201, a source region 203 of the first conductive type formed in the base region 202, an interlayer dielectric layer 204 covering the semiconductor substrate and partially exposing the base region, and an emitter 205 formed on the interlayer dielectric layer 204 and contacting the base region. The terminal ring region includes at least one field limiting ring surrounding the cell region and formed in a drift region of the terminal ring region. The terminal ring area includes: the field plate comprises field limiting rings (not shown) formed in the semiconductor substrate 200, Field Oxide (FOX)206 arranged at intervals, a field plate 207 covering the field oxide 206, an interlayer dielectric layer 208 covering the field plate 207 and partially exposing the field plate 207, and a metal field plate 209 covering the interlayer dielectric layer 208 and contacting the field plate 207 and the semiconductor substrate 200. The terminal ring area surrounds the cell area, and is used for protecting the cell area so as to improve the critical breakdown electric field of the surface area of the cell area, namely improve the breakdown voltage. Fig. 2B shows a schematic plan view of a semiconductor device formed with an IGBT structure according to an embodiment of the present invention. The terminal ring region is disposed around the cell region, the terminal ring region is formed with a metal field plate 209 and an interlayer dielectric layer 208, and the cell region is formed with an emitter 205.
Illustratively, the step of forming the cell region includes: firstly, forming a drift region in a semiconductor substrate, wherein the drift region has a first conduction type; then, forming a groove type grid structure in the semiconductor substrate; then, forming a base region located in the drift region in the semiconductor substrate on two sides of the trench type gate structure, wherein the base region has a second conduction type; forming a source region having a first conductive type in the base region; forming an interlayer dielectric layer on the semiconductor substrate, and exposing partial openings of the source region and the base region; and forming an emitter on the semiconductor substrate. The first conductivity type and the second conductivity type are generally referred to as P-type or N-type, for example, the first conductivity type is one of P-type, low-doped P-type and high-doped P + type, and the second conductivity type is one of N-type, low-doped N-type and high-doped N + type. Or conversely, the first conductivity type is one of an N-type, a low-doped N-type, and a high-doped N + type, and the second conductivity type is one of a P-type, a low-doped P-type, and a high-doped P + type. The material of the emitter comprises at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al, or other suitable metal materials. The step of forming the front structure of the cell region may be a step known to those skilled in the art, and is not described herein.
Illustratively, the step of forming the terminal loop region includes: firstly, forming a field limiting ring on a semiconductor substrate; then, forming field oxygen arranged at intervals on the semiconductor substrate, wherein two sides of each field limiting ring are respectively provided with one field oxygen; next, forming field plates on the semiconductor substrate, wherein each field plate extends from a part of the surface of the semiconductor substrate between adjacent field oxygen to a part of the surface of the field oxygen; then, forming an interlayer dielectric layer which covers the exposed semiconductor substrate, the field plate and the field oxide; forming a plurality of first openings and a plurality of second openings in the interlayer dielectric layer, wherein the first openings expose part of the surface of the semiconductor substrate, and the second openings expose part of the field plate; and forming a plurality of metal field plates arranged at intervals on the surface of the semiconductor substrate and part of the interlayer dielectric layer, wherein the metal field plates fill the first opening and the second opening. The field limiting rings may be formed by, for example, ion implantation, and have a second conductivity type opposite to the drift region, for example, the drift region of the first conductivity type is an N-type drift region, especially an N-type lightly doped drift region, and the field limiting rings of the second conductivity type are P-type field limiting rings. The field plate material may comprise any material known to those skilled in the art that can be used as a field plate, and in this embodiment the field plate material comprises polysilicon. The material of the metal field plate comprises at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al, or other suitable metal materials. The step of forming the terminal loop region may be a step well known to those skilled in the art and will not be described herein.
It should be understood that, in the actual process, the steps of forming the cell region and the terminal ring region are not performed separately, and some of the same processes may be performed in the same step, such as the step of forming an interlayer dielectric layer, the step of forming a field limiting ring and a source region, the step of forming an emitter and a metal field plate, and so on, and those skilled in the art can select the steps according to actual needs.
Next, with continued reference to fig. 3, step S2 is performed: and forming a protective layer covering the terminal ring region and a support structure positioned in the cell region on the front surface of the IGBT structure, wherein the top of the support structure is lower than the top of the protective layer or is flush with the top of the protective layer.
Because the IGBT can continuously or discontinuously bear certain reverse withstand voltage in the conventional forward conduction, reverse bearing and switch working processes, a protective layer with certain insulation strength is required to cover a device terminal ring area, so that the breakdown voltage reduction and leakage current increase of a device are avoided, the normal work of the device is ensured, and particularly, the stability of the leakage current of the device is ensured and the reliability of the device is ensured under the conditions of high temperature and strong electric field for long-term work.
A supporting structure which is lower than the top of the protective layer or is flush with the top of the protective layer is formed in the cell area of the IGBT structure, so that the height difference between the top of the cell area and the top of the terminal ring area before the back of the wafer is thinned is reduced, the occurrence of fragments or microcracks in the grinding process is reduced, the risk of fragments caused by a film uncovering process and a film uncovering process which are caused by the fact that an organic protective film is used as a buffer layer is avoided, the process flow is simplified, the failure of a device is reduced, and the yield of products is improved; meanwhile, due to the reduction of the height difference, the window of the IGBT thinning process is greatly optimized.
Illustratively, the protective layer is provided as the same material layer as the support structure. Providing the protective layer and the support structure as the same material may incorporate the step of forming the support structure into the step of forming the protective layer during the manufacturing process, simplifying the process steps and flow. In one example, the protective layer includes a passivation layer and a polyimide film layer stacked in this order from bottom to top. The step of forming the protective layer and the support structure comprises: forming a passivation layer on the semiconductor substrate, wherein the passivation layer covers the terminal ring region and a region, where the support structure is to be formed, in the cell region; and forming a polyimide film layer on the semiconductor substrate, wherein the polyimide film layer is laminated on the passivation layer and has a shape consistent with the passivation layer.
Referring to fig. 2B, a passivation layer 210 is first formed on the semiconductor substrate 200, the passivation layer 210 covering the interlayer dielectric layer 208 of the terminal ring region, the metal field plate 209 and the region of the cell where the support structure is to be formed. The method of forming the passivation layer 210 includes the steps of:
firstly, a passivation film material layer is formed and deposited on the semiconductor substrate. The passivation film material layer can be a silicon nitride layer or a silicon oxynitride layer, and is used for increasing the moisture-resistant and ion-contamination-resistant capacity of the protective layer and reducing the film stress of the protective layer. The method of forming the passivation film material layer may be by Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Metal Organic Chemical Vapor Deposition (MOCVD), and Atomic Layer Deposition (ALD) or other methods known to those skilled in the art.
And then, forming a patterned photoresist layer on the surface of the passivation film material layer by utilizing a photoetching process, wherein the photoresist layer covers the terminal ring region and the support structure region to be formed by covering the cell region.
Then, with the patterned photoresist layer as a mask, etching the passivation film layer to form the passivation film layer covering the terminal ring region and the cell region and covering the region to be formed with the support structure; the etching process may be any process known to those skilled in the art, such as wet etching, dry etching, and the like.
Finally, removing the patterned photoresist layer. The method for removing the photoresist layer comprises ashing, plasma photoresist removing process and the like.
Illustratively, the support structures are arranged in a criss-cross line pattern in the cell region. Referring to fig. 2D, a schematic plan view of a device is shown in which a passivation layer is formed during the formation of a semiconductor device. The passivation layer 210 covers the terminal ring region, and a crisscross line pattern is formed in a region of the cell region where the support structure is to be formed. The supporting structure is set to be a cross linear pattern, on one hand, a 'beam house' structure with a stable structure is formed, so that the front side of a cellular area is supported and stress buffered to the maximum extent in the thinning process of the back side of a semiconductor, the impact caused by the height difference of the cellular area and a terminal ring area is reduced, the probability of fragments and cracks is reduced, on the other hand, the packaging area of the cellular area of a device occupied by the supporting structure is reduced, and the packaging area of the device and the electrical performance of the packaged device are prevented from being influenced by the cellular area of the supporting structure occupying a larger area.
Referring to fig. 2E, after forming a passivation layer 210 on a semiconductor substrate 200, a polyimide film layer 211 is then formed on the semiconductor substrate, the polyimide film layer 211 being stacked on the passivation layer 210 to have a shape corresponding to the passivation layer 210. The passivation layer 210 and the polyimide film layer 211 covering the terminal ring region form a protection layer, and the passivation layer 210 and the polyimide film layer 211 located in the cell region form a support structure. The height difference H1 between the top of the formed support structure and the top of the protection layer (i.e. the top of the polyimide film layer 211) is smaller than the height difference between the top of the emitter 205 and the top of the protection layer, so that the height difference between the top of the cellular region and the top of the terminal ring region before the back of the wafer is thinned is greatly reduced, and the risk of fragments and cracks in the grinding and thinning process is avoided.
The method of forming the polyimide film layer 211 includes the steps of:
first, a polyimide material layer is formed on a semiconductor substrate by coating.
And photoetching the formed polyimide material layer by adopting a photoetching process, wherein the photoetching process is consistent with the photoetching process adopted in the step of forming the patterned photoresist layer in the process of forming the passivation layer, so that the polyimide film layer formed by the polyimide material layer after the photoetching process is superposed on the passivation layer to form the polyimide film layer covering the terminal ring area and the area of the cell area, which is to form the support structure. As shown in fig. 2F, a schematic plan view of the device after forming a polyimide film layer on a semiconductor substrate is shown. The terminal ring region of the device is covered with a polyimide film layer 211, wherein the polyimide film layer is stacked on the passivation layer 210, and the polyimide film layer 211 formed in the cell region is stacked on the passivation layer 210 and has a crisscross linear pattern.
It should be understood that the embodiment is described by taking the example that the support structure and the protection layer are formed by the same material layer and the same process step, and the top of the support structure formed in the cell region is slightly lower than the top of the protection layer covered in the terminal ring region, which is only an alternative example of the present invention. Those skilled in the art may choose to form the support structure after the protective layer is formed, to form the support structure in a different material than the protective layer, and/or to form the top of the support structure flush with the top of the protective layer, all of which are suitable for use in the present invention.
Meanwhile, it should be understood that the embodiment is only exemplary in which the passivation layer and the polyimide film layer are sequentially stacked from bottom to top as the protective layer, and those skilled in the art can select the passivation layer and the polyimide film layer as needed, and it should be understood that the embodiment is only exemplary in which the support structure is illustrated as a crisscross line-shaped pattern formed on the cell region, and any support structure formed on the cell region and having a top lower than or flush with the top of the protective layer is suitable for the present invention.
Further, it should be understood that the present embodiment is illustrated by taking the manufacturing process of the IGBT device as an example, which is merely exemplary, and any semiconductor device having a cell region and a terminal ring region, which is covered with a protection layer in the terminal ring region, and a process of forming a support structure with a top lower than or flush with the top of the protection layer in the cell region is applicable to the present invention.
To this end, after forming the protective layer and the support structure, in an actual process, a process of thinning a back surface of the semiconductor substrate is further included, wherein before the thinning process, the front surface of the semiconductor substrate is bonded to the support wafer, and then the back surface of the semiconductor substrate is thinned by using methods such as mechanical grinding, Chemical Mechanical Polishing (CMP), chemical etching, plasma etching, and the like, and the process of thinning the back surface of the semiconductor substrate may use a process known to those skilled in the art, and is not described herein again.
The present invention also provides a semiconductor device, the device comprising: the semiconductor device comprises a semiconductor substrate, wherein a terminal ring area and a cell area are formed on the semiconductor substrate; a protective layer overlying the terminal ring region; and a support structure located in the cell region, wherein a top of the support structure is lower than or level with a top of the protective layer.
Referring to fig. 2E, a schematic diagram of a semiconductor device according to the present invention is shown. The semiconductor device includes a semiconductor substrate 200. The semiconductor substrate 200 is a bulk silicon substrate, which may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like. In the following, the present embodiment is described by taking an IGBT device as an example, and it should be understood that the present embodiment is only exemplary, and any semiconductor device having a cell region and a terminal ring region, wherein the terminal ring region is covered with a protection layer, and a support structure having a top lower than or flush with the top of the protection layer is formed in the cell region, is suitable for the present invention.
An IGBT structure including a terminal ring region and a cell region is formed on the semiconductor substrate 200. Specifically, the cell region includes a front structure forming an IGBT device, such as a base region, an emitter region, a gate oxide layer, a gate, an emitter, and the like of the IGBT.
Referring to fig. 2E, the cell region includes: the semiconductor device includes a semiconductor substrate 200, a drift region of a first conductivity type formed on the semiconductor substrate 200, a trench-type gate structure 201 formed on the semiconductor substrate 200, base regions 202 of a second conductivity type formed on both sides of the bottom of the trench-type gate structure 201, source regions 203 of the first conductivity type formed in the base regions 202, an interlayer dielectric layer 204 covering the semiconductor substrate and partially exposing the base regions, and an emitter 205 formed on the semiconductor substrate. The first conductivity type and the second conductivity type are generally referred to as P-type or N-type, for example, the first conductivity type is one of P-type, low-doped P-type and high-doped P + type, and the second conductivity type is one of N-type, low-doped N-type and high-doped N + type. Or conversely, the first conductivity type is one of an N-type, a low-doped N-type, and a high-doped N + type, and the second conductivity type is one of a P-type, a low-doped P-type, and a high-doped P + type. The material of the emitter comprises at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al, or other suitable metal materials.
The terminal ring area surrounds the cell area, and is used for protecting the cell area so as to improve the critical breakdown electric field of the surface area of the cell area, namely improve the breakdown voltage. The terminal ring region includes at least one field limiting ring surrounding the cell region and formed in a drift region of the terminal ring region. With continued reference to fig. 2E, the terminal loop area includes: the field plate comprises field limiting rings (not shown) formed in the semiconductor substrate 200, Field Oxide (FOX)206 arranged at intervals, a field plate 207 covering the field oxide 206, an interlayer dielectric layer 208 covering the field plate 207 and partially exposing the field plate 207, and a metal field plate 209 covering the interlayer dielectric layer 208 and contacting the field plate 207 and the semiconductor substrate 200. The field limiting rings have a second conductivity type opposite to the drift region, for example, the drift region of the first conductivity type is an N-type drift region, in particular an N-type lightly doped drift region, and the field limiting rings of the second conductivity type are P-type field limiting rings. The field plate material may comprise any material known to those skilled in the art that can be used as a field plate, and in this embodiment the field plate material comprises polysilicon. The material of the metal field plate comprises at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al, or other suitable metal materials.
The semiconductor device further comprises a protective layer covering the terminal ring region and a support structure located in the cell region, wherein the top of the support structure is lower than the top of the protective layer or is flush with the top of the protective layer. A supporting structure which is lower than the top of the protective layer or is flush with the top of the protective layer is formed in the cell area of the IGBT structure, so that the height difference between the top of the cell area and the top of the terminal ring area before the back of the wafer is thinned is reduced, the occurrence of fragments or microcracks in the grinding process is reduced, the risk of fragments caused by a film uncovering process and a film uncovering process which are caused by the fact that an organic protective film is used as a buffer layer is avoided, the process flow is simplified, the failure of a device is reduced, and the yield of products is; meanwhile, due to the reduction of the height difference, the window of the IGBT thinning process is greatly optimized.
Illustratively, the protective layer and the support structure are provided as the same layer of material. Providing the protective layer and the support structure as the same material may incorporate the step of forming the support structure into the step of forming the protective layer during the manufacturing process, simplifying the process steps and flow. Illustratively, the protective layer and the support structure include a passivation layer and a polyimide film layer stacked in sequence from bottom to top. With continued reference to fig. 2D, a passivation layer 210 and a polyimide film layer 211 are formed on the semiconductor substrate, which are sequentially stacked from bottom to top, wherein a portion of the passivation layer 210 and the polyimide film layer 211 covering the terminal ring region form a protection layer, and a portion of the passivation layer 210 and the polyimide film layer 211 located in the cell region form a support structure. The passivation film material layer can be a silicon nitride layer or a silicon oxynitride layer, and is used for increasing the moisture-resistant and ion-contamination-resistant capacity of the protective layer and reducing the film stress of the protective layer.
Illustratively, the support structures are arranged in a criss-cross line pattern in the cell region. Referring to fig. 2F, a schematic plan view of a semiconductor device according to one embodiment of the invention. The passivation layer 210 and the polyimide film layer 211 stacked in sequence from bottom to top cover the terminal ring region, and a crisscross linear pattern is formed in a region where a support structure is to be formed in the cell region. The supporting structure is set to be a cross linear pattern, on one hand, a 'beam house' structure with a stable structure is formed, so that the front side of a cellular area is supported and stress buffered to the maximum extent in the thinning process of the back side of a semiconductor, the impact caused by the height difference of the cellular area and a terminal ring area is reduced, the probability of fragments and cracks is reduced, on the other hand, the packaging area of the cellular area of a device occupied by the supporting structure is reduced, and the electrical performance of the packaged device is prevented from being influenced by the cellular area occupying a larger area.
The invention also provides an electronic device comprising the semiconductor device of the second embodiment, and the semiconductor device is prepared according to the method of the first embodiment.
The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.
Wherein figure 4 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
Wherein the mobile phone handset comprises the semiconductor device of embodiment two, the semiconductor device comprising: the semiconductor device comprises a semiconductor substrate, wherein an IGBT structure is formed on the semiconductor substrate and comprises a terminal ring area and a cellular area; a protective layer overlying the terminal ring region; and a support structure located in the cell region, wherein a top of the support structure is lower than or level with a top of the protective layer.
In summary, according to the manufacturing method of the semiconductor device, the semiconductor device and the electronic apparatus of the present invention, the supporting structure located in the cell region is formed on the semiconductor substrate, so that the height difference between the top of the cell region before thinning the back of the wafer and the top of the terminal ring region is reduced, the risk of fragments caused by the film uncovering process and the film uncovering process due to the use of the organic protective film as the buffer layer in the subsequent grinding and thinning process is avoided, the process flow is simplified, the occurrence of fragments or microcracks in the grinding process is reduced, the device failure is reduced, and the product yield is improved; meanwhile, due to the reduction of the height difference, the window of the thinning process is greatly optimized.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a terminal ring area and a cell area on the semiconductor substrate;
forming a protective layer covering the terminal ring area and a support structure positioned on the cell area on the semiconductor substrate, wherein the top of the support structure is lower than the top of the protective layer or is flush with the top of the protective layer, the protective layer is an insulating layer, the support structure and the protective layer are arranged into the same material layer formed in the same step, and the support structure is arranged into a cross linear pattern positioned in the cell area.
2. The method of claim 1, wherein the protective layer and the support structure comprise a passivation layer and a polyimide film layer stacked in sequence from bottom to top.
3. The method of claim 2, wherein the step of forming the protective layer and the support structure comprises:
forming a passivation layer on the semiconductor substrate, wherein the passivation layer covers the terminal ring region and a region, where the support structure is to be formed, in the cell region;
and forming a polyimide film layer on the semiconductor substrate, wherein the polyimide film layer is laminated on the passivation layer and has a shape consistent with the passivation layer.
4. The method of claim 3, wherein forming a passivation layer on the semiconductor substrate comprises:
depositing to form a passivation film material layer;
forming a patterned photoresist layer on the passivation film material layer, wherein the patterned photoresist layer covers the terminal ring region and a region, to be formed with the support structure, in the cell region;
etching the passivation film material layer by taking the patterned photoresist layer as a mask to form the passivation layer;
and removing the patterned photoresist layer.
5. The method of claim 3, wherein forming a polyimide film layer on the semiconductor substrate comprises:
coating and forming a polyimide material layer on the semiconductor substrate;
and patterning the polyimide material layer by adopting a photoetching process to form a polyimide film layer stacked on the passivation layer.
6. The method of claim 1, wherein the semiconductor device comprises an IGBT.
7. A semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, wherein a terminal ring area and a cell area are formed on the semiconductor substrate;
a protective layer covering the terminal ring region; and
the supporting structure is arranged on the cellular area, wherein the top of the supporting structure is lower than the top of the protective layer or is flush with the top of the protective layer, the protective layer is an insulating layer, the supporting structure and the protective layer are arranged to be the same material layer formed in the same step, and the supporting structure is arranged to be a cross-shaped linear pattern in the cellular area.
8. The semiconductor device according to claim 7, wherein the protective layer and the support structure comprise a passivation layer and a polyimide film layer stacked in this order from bottom to top.
9. The semiconductor device according to claim 7, wherein the semiconductor device comprises an IGBT.
10. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 7 to 9.
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