CN109994388A - A kind of manufacturing method of semiconductor devices, semiconductor devices and electronic device - Google Patents
A kind of manufacturing method of semiconductor devices, semiconductor devices and electronic device Download PDFInfo
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- CN109994388A CN109994388A CN201711477771.XA CN201711477771A CN109994388A CN 109994388 A CN109994388 A CN 109994388A CN 201711477771 A CN201711477771 A CN 201711477771A CN 109994388 A CN109994388 A CN 109994388A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
Abstract
The present invention provides manufacturing method, semiconductor devices and the electronic device of a kind of semiconductor devices, which comprises provides semiconductor substrate, is formed with terminal ring region and cellular region on the semiconductor substrate；Formation covers the protective layer of the terminal ring region, and the support construction on the cellular region on the semiconductor substrate, wherein flushes at the top of the support construction lower than at the top of the protective layer or with the protective layer top.The manufacturing method and semiconductor devices and electronic device of semiconductor device according to the invention; the support construction for being located at cellular region is formed on a semiconductor substrate; reduce the difference in height at the top of the preceding cellular region structural top of thinning back side of silicon wafer and end ring plot structure; it avoids and organic protective film is used to take off membrane process as buffer layer bring and take off fragment risk caused by membrane process in subsequent grinding reduction process, simplification of flowsheet while reduces the generation of fragment or micro-crack.
Description
Technical field
The present invention relates to field of semiconductor manufacture, manufacturing method, semiconductor devices in particular to semiconductor devices
And electronic device.
Background technique
Insulated gate bipolar transistor (IGBT) has become one of most important high-power mainstream device of field of power electronics.
As high-power discrete device, reduces static (Vcesat) and dynamic (Eoff) power consumption is always the developing direction of IGBT.It is theoretical
On, static (Vcesat) and dynamic (Eoff) power consumption are (trade-off) mutually restricted.
Static (Vcesat) and dynamic (Eoff) may be implemented by the way that thickness of detector is further thinned in existing IGBT structure
Optimize while power consumption.This is also the developing way of big a new generation, the factory IGBT of international mainstream IGBT.However, with thickness of detector
It is thinned, grinding technics and subsequent laser annealing (LTA) process bands is greatly challenged.
Typical IGBT structure includes terminal ring region and cellular region (cell), wherein in the front IGBT, due to terminal ring region
There are terminal ring structures and the protective layer for covering terminal ring region to lead to terminal ring region such as polyimides (polyimide) film layer
With the area cellular (cell) in front there are difference in height, this difference in height often leads to fragment occur in grinding back surface reduction process
Or micro-crack.Fragment leads to component failure, and micro-crack also results in wafer fragmentation in post laser annealing process.For this purpose, this
Invention provides manufacturing method, semiconductor devices and the electronic device of a kind of new semiconductor devices, to solve the prior art
The problems in.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention provides a kind of manufacturing methods of semiconductor devices, which comprises semiconductor substrate is provided, in institute
It states and is formed with terminal ring region and cellular region in semiconductor substrate；
The protective layer for covering the terminal ring region is formed on the semiconductor substrate, and on the cellular region
Support construction, wherein flushed at the top of the support construction lower than at the top of the protective layer or with the protective layer top.
Illustratively, the support construction and the protective layer are set as identical material layer.
Illustratively, the protective layer and the support construction include that the passivation layer stacked gradually from top to bottom and polyamides are sub-
Amine film layer
Illustratively, the support construction is arranged to the right-angled intersection threadiness figure positioned at the cellular region.
Illustratively, the support construction is formed in same step with the protective layer.
Illustratively, the formation protective layer and the step of support construction, include:
Passivation layer is formed on the semiconductor substrate, and the passivation layer covers in the terminal ring region and the cellular region
The quasi- region for forming the support construction；
Polyimide film is formed on the semiconductor substrate, and the polyimide film is layered on the passivation layer
And there is consistent shape with the passivation layer.
Illustratively, on the semiconductor substrate formed passivation layer the step of include:
Deposition forms passivation membrane layers；
Patterned photoresist layer is formed in the passivation membrane layers, described in the patterned photoresist layer covering
Intend being formed the region of the support construction in terminal ring region and the cellular region；
Using the patterned photoresist layer as exposure mask, the passivation membrane layers are etched to form the passivation layer；
Remove the patterned photoresist layer.
Illustratively, on the semiconductor substrate formed polyimide film the step of include:
Coating forms polyimide material on the semiconductor substrate；
The polyimide material is patterned using photoetching process, is layered on the passivation layer with being formed to be located at
Polyimide film.
Illustratively, the semiconductor devices includes IGBT.
The present invention also provides a kind of semiconductor devices, comprising:
Semiconductor substrate is formed with terminal ring region and cellular region in the semiconductor substrate；
Cover the protective layer of the terminal ring region；And
Support construction on the cellular region, wherein at the top of the support construction lower than at the top of the protective layer or
It is flushed at the top of the protective layer.
Illustratively, the protective layer and the support construction are set as identical material layer.
Illustratively, the protective layer and the support construction include that the passivation layer stacked gradually from top to bottom and polyamides are sub-
Amine film layer.
Illustratively, the support construction is arranged to the right-angled intersection threadiness figure positioned at the cellular region.
Illustratively, the semiconductor devices includes IGBT.
The present invention also provides a kind of electronic device, the electronic device includes foregoing semiconductor devices.
Manufacturing method, semiconductor devices and the electronic device of semiconductor device according to the invention, on a semiconductor substrate
The support construction for being located at cellular region is formed, to reduce the height at the top of the preceding cellular region of thinning back side of silicon wafer and at the top of terminal ring region
Difference is spent, avoids and organic protective film is used to take off membrane process as buffer layer bring and take off film in subsequent grinding reduction process
Fragment risk caused by technique, simplifying reduces the hair for occurring fragment or micro-crack in grinding technics while process flow
It is raw, component failure is reduced, product yield is promoted；Simultaneously as the reduction of difference in height, has been greatly optimized the window of reduction process.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A and 1B is the structural schematic diagram and floor map of a kind of semiconductor devices；
Fig. 2A -2F partly leads for what is formed in the manufacturing method according to a kind of semiconductor devices of one embodiment of the present of invention
The structural schematic diagram and floor map of body device；
Fig. 3 is the flow chart according to a kind of manufacturing method of semiconductor devices of one embodiment of the present of invention；
Fig. 4 is the schematic diagram according to the electronic device of one embodiment of the present of invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, it is of the present invention to illustrate
The manufacturing method of semiconductor devices.Obviously, execution of the invention is not limited to the spy that the technical staff of semiconductor field is familiar with
Different details.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have
Other embodiments.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singular
It is intended to include plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or their combination.
Now, an exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
Static (Vcesat) and dynamic (Eoff) may be implemented by the way that thickness of detector is further thinned in existing IGBT structure
Optimize while power consumption.However, being thinned with thickness of detector, to grinding technics and subsequent laser annealing (LTA) technique
Bring great challenge.
Typical IGBT structure includes terminal ring region and the area cellular (cell), wherein in the front IGBT, due to terminal ring region
There are terminal ring structures and the protective layer for covering terminal ring region to lead to terminal ring region such as polyimides (polyimide) film layer
With cellular region in front there are difference in height, this difference in height often leads to occur fragment or fine fisssure in grinding back surface reduction process
Line.
It as shown in Figure 1A, include above being formed with cellular region and terminal ring region in the positive semiconductor substrate 100 of IGBT,
In, cellular region includes the drift region (not shown) to be formed on a semiconductor substrate 100, the groove type grid being formed in drift region
Structure 102 is formed in the base region 101 of groove type grid structure two sides, is formed in the base region 101, is described groove-shaped
The source region 103 of 102 two sides of gate structure is formed in the interlayer dielectric layer 104 of 102 top of groove type grid structure and is formed in
The emitter 105 contacted on interlayer dielectric layer 104 with the source region 103；Terminal ring region includes being formed in semiconductor substrate 100
In drift region (not shown) on spaced field oxygen (FOX) 106, partially cover the field oxygen 106 and expose semiconductor
The field plate 107 of substrate 100 and the covering field plate 107 and field oxygen 106 simultaneously partially expose the field plate 107 and the semiconductor
The interlayer dielectric layer 104 of substrate 100, the Metal field plate 108 for being formed on interlayer dielectric layer 104 and being contacted with semiconductor substrate,
And it is formed in the protection layer film 109 for covering the terminal ring region.Figure 1B shows a kind of plane signal of semiconductor devices
Figure, IGBT structure front include cellular region and terminal ring region, and wherein terminal ring region protected seam film 109 covers, cellular region top
Portion is emitter 105.Since the terminal ring region of formation has field oxygen 106, field plate 107 and the protective layer for covering terminal ring region
Film 109, so that the difference in height at the top of finally formed terminal ring region and at the top of the area cellular (cell) is to protect layer film 109
Height difference H (showing in such as Figure 1A) between 105 top of top and emitter, this difference in height often lead to go out in grinding technics
Existing fragment or micro-crack.Fragment leads to component failure, and micro-crack also results in wafer fragmentation in post laser annealing process.
A kind of solution is that, using before grinding reduction process, in IGBT device front, patch organic film is as protection
Film is used as buffer layer by soft organic film, reduces positive difference in height bring stress in grinding technics, reduce fragment with
The generation and appearance of micro-crack.However, this way is brought after being thinned in the membrane process of taking off for taking organic film off, film work is typically taken off
Skill is after organic film to be heated to certain temperature (such as 40 DEG C~60 DEG C), using artificial or machine by organic film from crystal column surface
One end is gradually opened to the other end, this after wafer is thinned to take off in membrane process easily since organic film has certain viscosity
Cause the risk of wafer fragment.Organic protective film is only capable of as buffer layer simultaneously, cannot directly in abatement device terminal ring region and
Because difference in height existing for protective layer, keeps reduction process window very narrow, to further improve by being thinned on cellular region
The method of device performance is limited.
The technical issues of in order to solve in the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, institutes
The method of stating includes:
Semiconductor substrate is provided, is formed with terminal ring region and cellular region on the semiconductor substrate；
The protective layer for covering the terminal ring region is formed on the semiconductor substrate, and on the cellular region
Support construction, wherein flushed at the top of the support construction lower than at the top of the protective layer or with the protective layer top.
The manufacturing method of semiconductor device according to the invention forms the support knot for being located at cellular region on a semiconductor substrate
Structure is avoided and is ground subsequent to reduce at the top of the preceding cellular region of thinning back side of silicon wafer with the difference in height at the top of terminal ring region
Organic protective film is used to take off membrane process as buffer layer bring and take off fragment risk caused by membrane process in mill reduction process, letter
Having changed reduces the generation for occurring fragment or micro-crack in grinding technics while process flow, reduce component failure, is promoted and is produced
Product yield；Simultaneously as the reduction of difference in height, has been greatly optimized the window of reduction process.
Referring now to Fig. 2A -2E, Fig. 3 to the manufacturing method and semiconductor of a kind of semiconductor devices proposed of the invention
Device illustrates, and Fig. 2A -2E is the manufacturing method according to a kind of semiconductor devices of one embodiment of the present of invention
The structural schematic diagram and floor map of the semiconductor devices of middle formation；Fig. 3 is one kind according to one embodiment of the present of invention
The flow chart of the manufacturing method of semiconductor devices.
Illustratively, the present embodiment is illustrated using the manufacturing process of IGBT device as example, it is to be understood that this
Embodiment is illustrated as example using the manufacturing process of IGBT device and is only exemplary, any to have cellular region and end ring
The semiconductor devices in area is suitable for the present invention in terminal ring region protective mulch.
Firstly, referring to Fig. 3, executing step S1: providing semiconductor substrate, be formed with IGBT knot on the semiconductor substrate
Structure, the IGBT structure include terminal ring region and cellular region.
As shown in Figure 2 A, semiconductor substrate 200 is provided, specifically, can be at least one in the following material being previously mentioned
Kind: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors further include
The multilayered structure etc. that these semiconductors are constituted, or for silicon (SSOI), insulator is laminated on silicon-on-insulator (SOI), insulator
Upper stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
It is formed with IGBT structure on semiconductor substrate 200, the IGBT structure includes terminal ring region and cellular region.Specifically
, the cellular region includes the Facad structure to form IGBT device, as the base area of IGBT, emitter region, grid oxic horizon, grid and
Emitter etc..Referring to Fig. 2A, the cellular region includes: semiconductor substrate 200, first formed in institute's semiconductor substrate 200
The drift region (not shown) of conduction type forms groove type grid structure 201 on semiconductor substrate 200, in groove-shaped grid
The two sides of the bottom of pole structure 201 are formed with the base region 202 of the second conduction type, and the first conduction is formed in base region 202
The source region 203 of type, covering semiconductor substrate and part expose base region interlayer dielectric layer 204 and are formed in interlayer dielectric layer
The emitter 205 contacted on 204 with base region.The terminal ring region includes at least one field limiting ring, and the field limiting ring is surround
The cellular region, and the field limiting ring is formed in the drift region of terminal ring region.The terminal ring region includes: to be formed in partly to lead
Field limiting ring (not shown) in body substrate 200, spaced field oxygen (FOX) 206, covers the field plate 207 of the field oxygen 206,
It covers the field plate 207 and partially exposes the interlayer dielectric layer 208 of the field plate 207 and be covered on the interlayer dielectric layer
The Metal field plate 209 contacted on 208 and with the field plate 207 and semiconductor substrate 200.The terminal ring region is looped around cellular region
Around, terminal ring region to improve the critical breakdown electric field of cellular region surface region, namely is improved for protecting to cellular region
Breakdown voltage.As Fig. 2 B shows the plane of the semiconductor devices according to an embodiment of the invention for being formed with IGBT structure
Schematic diagram.Wherein, terminal ring region is arranged around cellular region, and terminal ring region is formed with Metal field plate 209 and interlayer dielectric layer
208, cellular region is formed with emitter 205.
Illustratively, the step of forming the cellular region include: firstly, form drift region in the semiconductor substrate, it is described
Drift region has the first conduction type；Then, groove type grid structure is formed in the semiconductor substrate；Then, in the groove
The base region being located in drift region is formed in the semiconductor substrate of type gate structure two sides, the base region has the second conductive-type
Type；The source region with the first conduction type is formed in the base region；Interlayer dielectric layer is formed on the semiconductor substrate,
And the opening of exposed portion source region and base region；Emitter is formed on the semiconductor substrate.First conduction type and second
Conduction type refers to p-type or N-type, for example the first conduction type is p-type, low-doped P-type, one of highly doped P+ type, and second
Conduction type is N-type, low-doped N-type, one of highly doped N+ type.Or on the contrary, the first conduction type is N-type, low-mix
Miscellaneous N-type, one of highly doped N+ type, the second conduction type is p-type, low-doped P-type, one of highly doped P+ type.Institute
The material for stating emitter includes at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al or other suitable gold
Belong to material.The step of Facad structure for forming cellular region, can be step well-known to those skilled in the art, herein not
It repeats again.
Illustratively, the step of forming the terminal ring region includes: firstly, forming field limiting ring on a semiconductor substrate；It connects
, spaced field oxygen is formed on a semiconductor substrate, wherein a field oxygen is respectively arranged in the two sides of each field limiting ring；Then,
Field plate is formed on a semiconductor substrate, wherein each field plate extends to portion from the part semiconductor substrate surface between opposite field oxygen
The surface of branch oxygen；Then, interlayer dielectric layer, the semiconductor substrate of the interlayer dielectric layer covering exposing, the field plate are formed
With the field oxygen；Then, several first openings and several second openings are formed in the interlayer dielectric layer, wherein first opens
Mouth exposes the part of the surface of semiconductor substrate, field plate described in the second opening exposed portion；In the semiconductor substrate surface and portion
Form several spaced Metal field plates on point interlayer dielectric layer, the Metal field plate filling first opening and the
Two openings.The field limiting ring can be formed for example, by the method for ion implanting, and the field limiting ring has and the drift region phase
The second anti-conduction type, for example, the drift region of the first conduction type be N-type drift region, especially N-type lightly doped drift zone,
And the field limiting ring of the second conduction type is then p-type field limiting ring.The material of the field plate may include that those skilled in the art institute is ripe
Any material that may be used as field plate known, the material of field plate described in the present embodiment includes polysilicon.The Metal field plate
Material includes at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al or other suitable metal materials.It is described
The step of forming terminal ring region can be step well-known to those skilled in the art, and details are not described herein.
It is to be appreciated that during actual process, the step of forming the cellular region and the terminal ring region, is not
It separately carries out, part of same process can be realized in same step, such as the step of forming interlayer dielectric layer, form field
The step of the step of limiting ring and source region, formation emitter and Metal field plate etc., those skilled in the art can be according to practical need
It is selected.
Then, it with continued reference to Fig. 3, executes step S2: being formed in the front of the IGBT structure and be covered on the end ring
Protective layer on area, and the support construction positioned at the cellular region, wherein be lower than the protection at the top of the support construction
Layer top is flushed with the protective layer top.
Since IGBT is in conventional forward conduction, reverse pressure-bearing and the switch course of work, it can continue or undertake by phased manner
Certain reverse withstand voltage needs the protective layer with certain dielectric strength to be covered in device terminal ring region at this time, device is avoided to hit
Voltage decline is worn, leakage current increases, and guarantees that proper device operation, especially long-term work under high temperature and strong electric field condition, are protected
The stability for demonstrate,proving device creepage, guarantees the reliability of device.
The cellular region of IGBT structure formed lower than at the top of protective layer or with the support construction that is flushed at the top of protective layer, thus
Reduce at the top of the preceding cellular region of thinning back side of silicon wafer with the difference in height at the top of terminal ring region, reduce in grinding technics occur it is broken
The generation of piece or micro-crack avoids that organic protective film is used to take off membrane process as buffer layer bring and take off broken caused by membrane process
Piece risk reduces component failure while simplifying process flow, promote product yield；Simultaneously as the reduction of difference in height, greatly
Width optimizes the window of IGBT reduction process.
Illustratively, the protective layer and the support construction are set as identical material layer.By protective layer and support knot
Structure, which is set as same material, will be incorporated into the step of forming protective layer the step of forming support construction in the fabrication process,
Simplify processing step and process.In one example, the protective layer includes the passivation layer and polyamides stacked gradually from top to bottom
Imines film layer.The step of formation protective layer and the support construction includes: to form passivation layer on the semiconductor substrate,
The passivation layer covers the region for intending being formed the support construction in the terminal ring region and the cellular region；In the semiconductor
Polyimide film is formed on substrate, the polyimide film is layered on the passivation layer and has one with the passivation layer
The shape of cause.
Referring to Fig. 2 B, passivation layer 210 is formed on semiconductor substrate 200 first, institute's passivation layer 210 covers the end ring
Intend being formed the region of support construction in the interlayer dielectric layer 208 in area, Metal field plate 209 and the cellular.Form the passivation layer
210 method the following steps are included:
Firstly, forming deposition on the semiconductor substrate forms passivation membrane layers.The passivation membrane layers can be with
It is silicon nitride layer, silicon oxynitride layer, the anti-ion contamination ability of moisture resistance to increase protective layer reduces protection tunic ply stress.
The method for forming the passivation membrane layers can be through low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical
It is vapor-deposited (PECVD), Metallo-Organic Chemical Vapor deposits (MOCVD) and atomic layer deposition (ALD) or other art technologies
Method known to personnel.
Then, patterning photoresist layer, the photoresist are formed in the passivating film material surface using photoetching process
Layer covers the terminal ring region and the covering positioned at the cellular region is intended forming the support structure region.
Then, using the patterning photoresist layer as exposure mask, the passivation film is etched, is formed and covers the terminal ring region
With the passivation film for intending being formed the support structure region positioned at the cellular region, covering；The etching technics can be
Technique known to the anyone skilled in the art such as wet etching, dry etching.
Finally, the removal patterned photoresist layer.The method for removing photoresist layer includes ashing, removing of photoresist by plasma work
Skill etc..
Illustratively, the support construction is arranged to the right-angled intersection threadiness figure positioned at the cellular region.Referring to Fig. 2 D,
It shows in semiconductor devices forming process, forms the device plane schematic diagram of passivation layer.Wherein, passivation layer 210 covers end
End ring area, and the quasi- region for forming support construction is formed with right-angled intersection threadiness figure in cellular region.Support construction is arranged
At right-angled intersection threadiness figure, " house beam " structure with rock-steady structure is on the one hand formed, so that being thinned in semiconductor back surface
There are support and stress buffer to greatest extent to the front of cellular region in technique, reduces the difference in height because of cellular region and terminal ring region
Different bring impact, reduces fragment and crackle probability, on the other hand reduces the package area that support construction occupies device cellular region,
Prevent support construction from influencing the device electric property after the package area and encapsulation of device because occupying the cellular region of large area.
It referring to Fig. 2 E, is formed after passivation layer 210, then, is formed on a semiconductor substrate poly- on semiconductor substrate 200
Acid imide film layer 211, the polyimide film 211 are layered on the passivation layer 210, are had with institute passivation layer 210 consistent
Shape.Wherein, the passivation layer 210 and the polyimide film 211 for being covered on terminal ring region constitute protective layer, are located at
The passivation layer 210 and the polyimide film 211 of the cellular region constitute support construction.At the top of the support construction of formation
It is less than at the top of 205 top of emitter and protective layer with the height difference H 1 at (i.e. 211 top of polyimide film) at the top of protective layer
Difference in height thus greatly reduces at the top of the preceding cellular region of thinning back side of silicon wafer with the difference in height at the top of terminal ring region, avoids grinding
Grind fragment and cracked risk in reduction process.
Form the method for the polyimide film 211 the following steps are included:
Firstly, coating forms polyimide material on a semiconductor substrate.
Then, using photoetching process to be formed by polyimide material carry out photoetching, wherein herein photoetching process with
Photoetching process employed in the step of forming patterning photoresist layer during passivation layer formation is consistent, so that polyamides is sub-
The polyimide film layer stackup that amine material layer is formed after photoetching process is located on passivation layer, formed covering terminal ring region and
The polyimide film in the quasi- region for forming support construction in cellular region.As shown in Figure 2 F, it shows and is formed on a semiconductor substrate
Device plane schematic diagram after polyimide film.It is covered with polyimide film 211 in the terminal ring region of device, wherein polyamides is sub-
Amine film layer is laminated on passivation layer 210, is laminated on passivation layer 210 and has in the polyimide film 211 that cellular region is formed
There is right-angled intersection threadiness figure.
It is to be appreciated that being walked with support construction and protective layer using identical material layer and same technique in the present embodiment
Be formed as example in rapid to be illustrated, the guarantor for being slightly below covered on terminal ring region at the top of the support construction of cellular region of formation
At the top of sheath, the only example of a selectivity of the invention.Those skilled in the art can choose formed protective layer it
Support construction, the support construction of formation different from protective layer material, and/or the support construction top formed and protection are re-formed afterwards
The mode that layer top flushes, is suitable for the present invention.
Also, it is understood that the present embodiment is that the passivation layer stacked gradually from top to bottom and polyamides are sub- with protective layer
Amine film layer is illustrated for example and is only exemplary, and those skilled in the art, which can according to need, to be selected, and needs simultaneously
It is to be understood that the present embodiment is to illustrate support construction to be only with the right-angled intersection threadiness figure being formed on cellular region
Illustratively, any being formed on cellular region and top is lower than the protective layer top or neat with the protective layer top
Flat support construction is suitable for the present invention.
Further, it is to be understood that the present embodiment is illustrated using the manufacturing process of IGBT device as example, only
Illustratively, any semiconductor devices with cellular region and terminal ring region, in terminal ring region protective mulch, in cellular region
Process of the top lower than the support construction flushed at the top of the protective layer or with the protective layer top is formed, this hair is suitable for
It is bright.
So far, exemplary introduction of the invention is completed, in actual process, formed protective layer and support construction it
It afterwards, further include that thinned technique is carried out to semiconductor substrate back, wherein first by semiconductor substrate front before reduction process
It is bonded with support wafer, then using using mechanical lapping, chemically mechanical polishing (CMP), chemical attack, plasma etching etc.
Method the back side of semiconductor substrate is carried out it is thinned, the back side to semiconductor substrate carry out thinned technique can using this
Technique known to the technical staff of field, details are not described herein.
The present invention also provides a kind of semiconductor devices, the device includes: semiconductor substrate, in the semiconductor substrate
It is formed with terminal ring region and cellular region；The protective layer being covered on the terminal ring region；And in the cellular region
Support construction, wherein flushed at the top of the support construction lower than at the top of the protective layer or with the protective layer top.
Referring to Fig. 2 E, a kind of structural schematic diagram of semiconductor devices according to the present invention is shown.Semiconductor devices includes
Semiconductor substrate 200.The semiconductor substrate 200 is body silicon substrate, can be at least one in the following material being previously mentioned
Kind: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors further include
The multilayered structure etc. that these semiconductors are constituted, or for silicon (SSOI), insulator is laminated on silicon-on-insulator (SOI), insulator
Upper stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..In the following, with
IGBT device is that example is illustrated the present embodiment, it is to be understood that the present embodiment with IGBT device be example into
Row explanation is only exemplary, and any semiconductor devices with cellular region and terminal ring region is covered in terminal ring region
Protective layer, cellular region be formed with top lower than at the top of the protective layer or with the support construction that is flushed at the top of the protective layer,
It is suitable for the present invention.
It is formed with IGBT structure on semiconductor substrate 200, the IGBT structure includes terminal ring region and cellular region.Specifically
, the cellular region includes the Facad structure to form IGBT device, as the base area of IGBT, emitter region, grid oxic horizon, grid and
Emitter etc..
Referring to Fig. 2 E, the cellular region includes: semiconductor substrate 200, and first formed in institute's semiconductor substrate 200 is led
The drift region of electric type forms groove type grid structure 201 on semiconductor substrate 200, in groove type grid structure 201
Two sides of the bottom are formed with the base region 202 of the second conduction type, and the source region of the first conduction type is formed in base region 202
203, covering semiconductor substrate simultaneously partially exposes the emitter of base region interlayer dielectric layer 204 and formation on a semiconductor substrate
205.First conduction type and the second conduction type refer to p-type or N-type, for example the first conduction type is p-type, low-doped P-type,
One of highly doped P+ type, the second conduction type are N-types, low-doped N-type, one of highly doped N+ type.Or it is opposite
Ground, the first conduction type are N-types, low-doped N-type, and one of highly doped N+ type, the second conduction type is p-type, low-doped P-
Type, one of highly doped P+ type.The material of the emitter include in Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al extremely
A kind of few or other suitable metal materials.
The terminal ring region is looped around around cellular region, and terminal ring region is for protecting cellular region, to improve cellular
The critical breakdown electric field of area's surface region, namely improve breakdown voltage.The terminal ring region includes at least one field limiting ring, described
Field limiting ring is around the cellular region, and the field limiting ring is formed in the drift region of terminal ring region.It is described with continued reference to Fig. 2 E
Terminal ring region includes: the field limiting ring (not shown) being formed in semiconductor substrate 200, and spaced field oxygen (FOX) 206 is covered
The field plate 207 for covering the field oxygen 206, cover the field plate 207 and partially expose the interlayer dielectric layer 208 of the field plate 207 with
And the Metal field plate 209 for being covered on the interlayer dielectric layer 208 and being contacted with the field plate 207 and semiconductor substrate 200.Institute
Field limiting ring is stated with second conduction type opposite with the drift region, for example, the drift region of the first conduction type is N-type drift
Area, especially N-type lightly doped drift zone, and the field limiting ring of the second conduction type is then p-type field limiting ring.The material of the field plate can
To include any material that may be used as field plate well-known to those skilled in the art, the material packet of field plate described in the present embodiment
Include polysilicon.The material of the Metal field plate includes at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al, or
Other suitable metal materials.
The semiconductor devices further includes the protective layer for covering the terminal ring region and the support knot positioned at the cellular region
Structure, wherein flushed at the top of the support construction lower than at the top of the protective layer or with the protective layer top.In IGBT structure
Cellular region formed lower than at the top of protective layer or with the support construction that is flushed at the top of protective layer, to reduce thinning back side of silicon wafer
With the difference in height at the top of terminal ring region at the top of preceding cellular region, reduce the generation for occurring fragment or micro-crack in grinding technics,
It avoids that organic protective film is used to take off membrane process as buffer layer bring and take off fragment risk caused by membrane process, simplifies technique stream
Component failure is reduced while journey, promotes product yield；Simultaneously as the reduction of difference in height, has been greatly optimized IGBT and work is thinned
The window of skill.
Illustratively, the protective layer and the support construction are set as identical material layer.By protective layer and support knot
Structure, which is set as same material, will be incorporated into the step of forming protective layer the step of forming support construction in the fabrication process,
Simplify processing step and process.Illustratively, the protective layer and the support construction include stack gradually from top to bottom it is blunt
Change layer and polyimide film.With continued reference to Fig. 2 D, it is formed with the passivation layer stacked gradually from top to bottom on a semiconductor substrate
210 and polyimide film 211, wherein the part that passivation layer 210 and polyimide film 211 cover terminal ring region, which is constituted, to be protected
The part that sheath, passivation layer 210 and polyimide film 211 are located at cellular region constitutes support construction.The passivation membrane layers
It can be silicon nitride layer, silicon oxynitride layer, the anti-ion contamination ability of the moisture resistance to increase protective layer reduces protective layer film layer and answers
Power.
Illustratively, the support construction is arranged to the right-angled intersection threadiness figure positioned at the cellular region.Referring to Fig. 2 F,
The floor map of semiconductor devices according to an embodiment of the invention.Wherein, the passivation layer stacked gradually from top to bottom
210 and polyimide film 211 cover terminal ring region, and in cellular region intend formed support construction region be formed with cross friendship
Pitch threadlike graph.Support construction is arranged to right-angled intersection threadiness figure, on the one hand being formed, there is " house beam " of rock-steady structure to tie
Structure is reduced so that having support and stress buffer to greatest extent to the front of cellular region in the reduction process of semiconductor back surface
Because the difference in height bring of cellular region and terminal ring region is impacted, fragment and crackle probability are reduced, on the other hand reduces support knot
Structure occupies the package area of device cellular region, prevents support construction from influencing the device after encapsulation because occupying the cellular region of large area
Electric property.
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment two, the semiconductor device
Part is prepared according to one the method for embodiment.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, it can also be any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to having used above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 4 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein the mobile phone handsets include semiconductor devices described in embodiment two, and the semiconductor devices includes:
Semiconductor substrate is formed with IGBT structure in the semiconductor substrate, and the IGBT structure includes terminal ring region and cellular region；It covers
Cover the protective layer on the terminal ring region；And the support construction in the cellular region, wherein the support construction
Top is flushed lower than at the top of the protective layer or with the protective layer top.
In conclusion the manufacturing method of semiconductor device according to the invention, semiconductor devices and electronic device, are partly leading
The support construction for being located at cellular region is formed in body substrate, to reduce the preceding cellular region top of thinning back side of silicon wafer and terminal ring region
The difference in height at top avoids and uses organic protective film to take off film work as buffer layer bring in subsequent grinding reduction process
Skill and fragment risk caused by membrane process is taken off, reduces in grinding technics while simplifying process flow and fragment or fine fisssure occur
The generation of line reduces component failure, promotes product yield；Simultaneously as the reduction of difference in height, has been greatly optimized reduction process
Window.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (15)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the described method includes:
Semiconductor substrate is provided, is formed with terminal ring region and cellular region on the semiconductor substrate；
The protective layer for covering the terminal ring region, and the support on the cellular region are formed on the semiconductor substrate
Structure, wherein flushed at the top of the support construction lower than at the top of the protective layer or with the protective layer top.
2. the method as described in claim 1, which is characterized in that the support construction and the protective layer are set as identical material
The bed of material.
3. the method as described in claim 1, which is characterized in that the protective layer and the support construction include from top to bottom according to
The passivation layer and polyimide film of secondary stacking.
4. the method as described in claim 1, which is characterized in that the support construction is arranged to the cross positioned at the cellular region
Intersect threadlike graph.
5. method as claimed in claim 3, which is characterized in that the support construction and protective layer shape in same step
At.
6. method as claimed in claim 5, which is characterized in that the step of the formation protective layer and the support construction
Include:
Passivation layer is formed on the semiconductor substrate, and the passivation layer, which covers, intends shape in the terminal ring region and the cellular region
At the region of the support construction；
Form polyimide film on the semiconductor substrate, the polyimide film be layered on the passivation layer and with
The passivation layer has consistent shape.
7. method as claimed in claim 6, which is characterized in that the step of forming passivation layer on the semiconductor substrate is wrapped
It includes:
Deposition forms passivation membrane layers；
Patterned photoresist layer is formed in the passivation membrane layers, the patterned photoresist layer covers the terminal
Intend being formed the region of the support construction in ring region and the cellular region；
Using the patterned photoresist layer as exposure mask, the passivation membrane layers are etched to form the passivation layer；
Remove the patterned photoresist layer.
8. method as claimed in claim 6, which is characterized in that form the step of polyimide film on the semiconductor substrate
Suddenly include:
Coating forms polyimide material on the semiconductor substrate；
The polyimide material is patterned using photoetching process, to form the polyamides for being located at and being layered on the passivation layer
Imines film layer.
9. the method as described in claim 1, which is characterized in that the semiconductor devices includes IGBT.
10. a kind of semiconductor devices characterized by comprising
Semiconductor substrate is formed with terminal ring region and cellular region in the semiconductor substrate；
Cover the protective layer of the terminal ring region；And
Support construction on the cellular region, wherein at the top of the support construction lower than at the top of the protective layer or with institute
It states and is flushed at the top of protective layer.
11. semiconductor devices as claimed in claim 10, which is characterized in that the protective layer and the support construction are set as
Identical material layer.
12. semiconductor devices as claimed in claim 10, which is characterized in that the protective layer and the support construction include from
Under to the passivation layer and polyimide film above stacked gradually.
13. semiconductor devices as claimed in claim 10, which is characterized in that the support construction is arranged to be located at the cellular
The right-angled intersection threadiness figure in area.
14. semiconductor devices as claimed in claim 10, which is characterized in that the semiconductor devices includes IGBT.
15. a kind of electronic device, which is characterized in that the electronic device includes as described in claim 10 to 14 any one
Semiconductor devices.
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| CN115332325A (en) * | 2022-10-11 | 2022-11-11 | 深圳市威兆半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
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