CN109256422B

CN109256422B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN109256422B
Application number: CN201710566154.0A
Authority: CN
Inventors: 刘剑
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-07-12
Filing date: 2017-07-12
Publication date: 2022-04-29
Anticipated expiration: 2037-07-12
Also published as: CN109256422A

Abstract

The invention provides a semiconductor device, a method of manufacturing the same, and an electronic apparatus, including: the device comprises a device substrate, a first electrode and a second electrode, wherein the device substrate comprises a cellular area and a terminal protection ring area surrounding the cellular area; the first injection region is arranged on the back surface of the device substrate and is opposite to the terminal protection ring region; a second implanted region disposed on the back surface and opposite to the cell region, the first implanted region surrounding the second implanted region; and the third injection region is arranged in the first injection region and close to the second injection region, wherein the doping concentration of the second injection region and the doping concentration of the third injection region are both greater than that of the first injection region.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

How to promote the reverse turn-off safe working area of an Insulated Gate Bipolar Transistor (IGBT for short) device is always a difficult point and a key point in the design of IGBT devices. The most common reverse turn-off failure of an IGBT device occurs in an edge cell (cell) of the device, and the mechanism is mainly triggered by a latch-up effect, resulting in the failure of the device. From the structure of the device, the front cell region is responsible for the on and off of current, the terminal protection ring (terminal ring) region is responsible for the transverse voltage resistance of the device, and the back electrode of the device has no pattern (pattern) and is responsible for the on and off of current. Therefore, the current channel areas of the front and back surfaces of the device are not uniform, and the area of the back surface is larger than that of the front surface (i.e., the area of the unit cell). In the device turn-off process, corresponding in-vivo hole carriers below the terminal protection ring are gathered together and flow out of the edge cells (the cells closest to the terminal protection ring), and when the gathered hole current is large enough, the latch-up effect of the edge cells is triggered, so that the device fails, as shown in fig. 1, wherein an arrow curve in fig. 1 shows a reverse turn-off current path. In addition, the higher the voltage level of the IGBT device is, the larger the area of the terminal protection ring is, and the failure rate of the edge cells is also greatly improved.

Therefore, in order to solve the above technical problems, the present invention proposes a new method for manufacturing a semiconductor device.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the shortcomings of the prior art, one aspect of the present invention provides a semiconductor device, comprising:

the device comprises a device substrate, a first electrode and a second electrode, wherein the device substrate comprises a cellular area and a terminal protection ring area surrounding the cellular area;

the first injection region is arranged on the back surface of the device substrate and is opposite to the terminal protection ring region;

a second implanted region disposed on the back surface and opposite to the cell region, the first implanted region surrounding the second implanted region;

and the third injection region is arranged in the first injection region and close to the second injection region, wherein the doping concentration of the second injection region and the doping concentration of the third injection region are both greater than that of the first injection region.

Illustratively, the first implant region is polygonal and the third implant region is located in a region outside at least one corner of the first implant region.

Illustratively, the first implant region includes four corners and the third implant region is located in a region other than the four corners of the first implant region.

Illustratively, the third implantation region includes a plurality of strip-shaped implantation regions arranged at intervals in a radial direction of the first implantation region, wherein an extending direction of the strip-shaped implantation regions is parallel to an extending direction of an edge of the second implantation region, which is close to the strip-shaped implantation regions; and/or the presence of a gas in the gas,

the third injection region comprises a plurality of block injection regions which are arranged at intervals along part of the edge of the second injection region.

Illustratively, the doping concentrations of the second and third implanted regions are the same.

Illustratively, the second implant region is in the shape of a polygon with one missing corner, and the third implant region is also located on the missing corner of the polygon;

the device substrate further includes a gate pad region located outside the third implant region on the missing corner.

Illustratively, the first, second and third implanted regions have the same junction depth and/or the first, second and third implanted regions have the same conductivity type.

Illustratively, the second and third implant regions are heavily doped implant regions and the first implant region is a lightly doped implant region.

Illustratively, the device substrate further comprises a transition region surrounding the cell region and located between the terminal guard ring region and the cell region, wherein the first implant region is further opposite the transition region and the third implant region is opposite the transition region.

Illustratively, the semiconductor device is an IGBT device.

Still another aspect of the present invention provides a method of manufacturing a semiconductor device, including:

providing a device substrate, wherein the device substrate comprises a cellular area and a terminal protection ring area surrounding the cellular area;

forming a first implantation region, wherein the first implantation region is formed on the back surface of the device substrate and is opposite to the terminal protection ring region;

and forming a second injection region and a third injection region, wherein the second injection region is formed on the back surface and is opposite to the cellular region, the third injection region is formed in the first injection region and is close to the second injection region, and the doping concentration of the second injection region and the doping concentration of the third injection region are both greater than that of the first injection region.

Illustratively, the method of forming the first, second and third implant regions comprises:

performing a first ion implantation on the back side of the device substrate to form a first implanted region in the device substrate;

forming a patterned mask layer on the back surface of the device substrate, wherein the mask layer exposes regions of the device substrate, where the second injection region and the third injection region are scheduled to be formed;

performing second ion implantation by taking the mask layer as a mask to form a second implantation area and a third implantation area;

and removing the mask layer.

Illustratively, after removing the mask layer, the method further includes a step of performing an annealing process to activate the dopant ions in the first implanted region, the second implanted region, and the third implanted region.

Illustratively, the first implant region is in the shape of a polygonal ring and the third implant region is located in a region outside at least one corner of the first implant region.

Illustratively, the semiconductor device is an IGBT device.

Another aspect of the present invention provides an electronic apparatus including the semiconductor device described above.

The semiconductor device of the invention comprises a first injection region which is arranged in the device substrate and is close to the back surface and opposite to the terminal protection ring region, a second injection region which is arranged in the device substrate and is close to the back surface and opposite to the cellular region, and a third injection region which is arranged in the first injection region and is close to the second injection region, wherein the doping concentration of the second injection region is greater than that of the first injection region, the doping concentration of the third injection region is greater than that of the first injection region, the first injection region with low doping concentration is arranged in the region opposite to the terminal protection ring region far away from the cellular region, the gain is further reduced, the large injection effect is reduced, the reverse turn-off safe working region is increased, the third injection region with high doping concentration is arranged in the region opposite to the terminal protection ring region near the cellular region, the degradation of the conduction voltage drop Vcesat can be avoided. Therefore, the semiconductor device of the present invention has high performance and reliability.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1 shows a schematic cross-sectional view of an IGBT device according to an embodiment of the related art;

fig. 2A shows a top view of the back side of an IGBT device according to another embodiment of the prior art;

fig. 2B shows a schematic partial cross-sectional view of the IGBT device taken along the section line AA' in fig. 2A;

fig. 3A shows a top view of the back side of an IGBT device according to an embodiment of the invention;

fig. 3B shows a top view of the back side of an IGBT device according to another embodiment of the invention;

fig. 3C shows a schematic partial cross-sectional view of the IGBT device taken along the section line AA' in fig. 3A, wherein the arrow curve in fig. 3C shows the reverse turn-off current path;

fig. 4A to 4C are schematic cross-sectional views of devices obtained at the relevant steps of the method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 5 shows a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the invention;

fig. 6 shows a schematic diagram of an electronic device in an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, and the corresponding dimensions, may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

At present, aiming at the improvement of a reverse turn-off safe working area of an IGBT device, a back side graphic process is introduced, and on the premise of keeping the injection concentration of a P + injection area corresponding to the back side below a front side cell (cell) area, namely a collector area (collector), unchanged, the injection concentration of a P + injection area corresponding to the back side below an overall terminal protection ring area is reduced, for example, the injection concentration is reduced to a P-injection area, wherein a gate pad area on one corner of the cell area reduces the area gain, and the large injection effect is weakened. In the turn-off process of the device, the concentration of the corresponding internal hole carrier below the terminal protection ring is reduced, so that the hole current gathered and flowing out through the edge cells is reduced from the source, and the reverse turn-off safe working area of the device is increased, as shown in fig. 2A and 2B.

However, the disadvantages of this solution are: the lower concentration of the corresponding back P + implant below the overall termination guard ring region may cause degradation of the overall conduction voltage drop Vcesat of the device.

In order to solve the foregoing technical problem, the present invention provides a semiconductor device, which mainly includes:

Example one

The semiconductor device of the present invention is described in detail below with specific reference to fig. 3A to 3C. Fig. 3A shows a top view of the back side of an IGBT device according to an embodiment of the invention; fig. 3B shows a top view of the back side of an IGBT device according to another embodiment of the invention; fig. 3C shows a schematic partial cross-sectional view of the IGBT device taken along the section line AA' in fig. 3A, wherein the arrow curve in fig. 3C shows the reverse turn-off current path.

Specifically, as shown in fig. 3A to 3C, in one example, the semiconductor device of the present invention may be an IGBT device, or may be another semiconductor device.

As an example, as shown in fig. 3C, the semiconductor device of the present invention includes a device substrate 300, the device substrate 300 including a front surface and a back surface opposite to the front surface. The front side of the device substrate includes a cell region 31 and a terminal guard ring region 33 surrounding the cell region 31.

The device substrate 300 is a bulk silicon substrate, which may be at least one of the materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like. Further, the substrate can also be an N-type substrate or a P-type substrate. In this embodiment, the device substrate 300 is preferably an N-type lightly doped substrate (N-substrate).

In one example, a number of isolation structures are formed on the front surface of the device substrate in the cell region, and the isolation structures are Shallow Trench Isolation (STI) structures or local oxidation of silicon (LOCOS) isolation structures. Various well structures and channel layers on the surface of the substrate are also formed in the semiconductor substrate.

In one example, the cell region 31 includes a gate structure disposed on the front surface of the device substrate, an emitter region in contact with the gate structure, an N + emitter region connected to the emitter region, the N + emitter region being located in a P-type body region, the P-type body region being located in an N- (N-type lightly doped) device substrate, or an N-drift region disposed in the device substrate, the P-type body region being located in the N-drift region, and an emitter disposed on the emitter region. In each cell unit, a gate structure is formed on surfaces of two N + emitter regions and a channel region, the gate structure including a gate layer and a gate dielectric layer located below the gate layer, opposite the N + emitter regions and the channel region through the gate dielectric layer.

In one example, as shown in fig. 3C, the device substrate 300 further includes a transition region 32, the transition region 32 is disposed on the front surface of the device substrate 300, and the transition region 32 surrounds the cell region 31 and is located between the terminal guard ring region 33 and the cell region 31.

Illustratively, the transition region includes a equipotential ring 321 formed in the device substrate 300, and a top surface of the equipotential ring 321 is flush with a front surface of the device substrate 300, the equipotential ring 321 is connected with the cell and surrounds the cell region, the equipotential ring is equipotential with an emitter or a cathode of the cell when being manufactured, and the equipotential ring has several functions of reducing a curvature effect of the outermost cell, reducing an electric field intensity of the outermost cell and strengthening a voltage resistance of the device because the equipotential ring is connected with the cell and the emitter or the cathode of the cell; and thirdly, because the transition region is wider, a layout space can be provided for the grid wiring of the grid-controlled power device during layout design.

In one example, the equipotential ring 321 has an opposite conductivity type than the device substrate or drift region, e.g., the device substrate is an N-type substrate, then the equipotential ring 321 is a P-type equipotential ring, and in particular a P + -type equipotential ring.

In one example, field oxide and a field plate on the field oxide are sequentially disposed on a region of the front surface of the device substrate 300 opposite to the equipotential ring 321, wherein a material of the field plate may include polysilicon or metal, or may include polysilicon and metal stacked from bottom to top, and a dielectric layer may be disposed between the metal and the polysilicon, wherein the metal may include aluminum, copper, gold, tin, or the like, or an alloy thereof.

In one example, a body lead-out region is further disposed in the body region of the cell region, for example, if the body region is a P-type body region, the body lead-out region is heavily P-type doped, and an equipotential ring lead-out region having the same conductivity type as that of the equipotential ring is formed in the equipotential ring, the equipotential ring lead-out region having a doping concentration richer than that of the equipotential ring.

Illustratively, a metal interconnection structure electrically connected with the body lead-out region and the equipotential ring lead-out region, such as a metal interconnection structure comprising a contact hole and an interconnection metal layer, is further formed above the gate structure on the front surface of the device substrate, and the metal may comprise copper, aluminum or other metal materials.

In one example, as shown in fig. 3C, at least one field limiting ring 331 is formed in the device substrate 300 of the terminal guard ring region 33, and the field limiting ring 331 surrounds the cell region 31 and is further outside the transition region. The field limiting rings 331 may be formed by, for example, ion implantation, and have a conductivity type opposite to that of the device substrate, for example, the device substrate 300 is an N-type substrate, especially an N-type lightly doped substrate, and the field limiting rings 331 are P-type field limiting rings, for example, P-type heavily doped field limiting rings.

Illustratively, the number of the field limiting rings 331 is reasonably selected according to the requirements of an actual device, and may include 1, 2, 3 to n field limiting rings, for example.

Illustratively, the field limiting rings 331 and the equipotential rings 321 are spaced apart in the device substrate 300.

Illustratively, several field plate structures are further disposed on the front surface of the device substrate in the terminal protective ring region 33, wherein the number of field plate structures may be set according to the number of field limiting rings, for example, one field plate structure is disposed on each of two sides of each of the field limiting rings 331, wherein each of the field plate structures includes a field oxide and a field plate on a surface of the field oxide, wherein the field oxide generally includes silicon oxide, the material of the field plate may include polysilicon or metal, and may also include polysilicon and metal stacked from bottom to top, and a dielectric layer may be further disposed between the metal and the polysilicon, wherein the metal may include aluminum, copper, gold, tin, or the like, or an alloy thereof.

In one example, a number of interconnect structures electrically connected to the field stop rings 331 are also disposed on the front side of the device substrate 300, and include contact holes between adjacent field plate structures and a metal layer over the contact holes, which connect the surfaces of the field stop rings.

Illustratively, a channel stop region is further disposed in the device substrate at the edge of the terminal guard ring region away from the cell region, for example, the channel stop region has a conductivity type opposite to that of the field limiting ring, which is N type, especially N + type in this embodiment.

In one example, as shown in fig. 3A and 3B, the device substrate 300 further includes a gate pad (pad) region disposed on the front surface of the device substrate, the gate pad region including a pad electrically connected to the gate through an interconnect structure.

In one example, the gate pad region is located at one corner of the cell region as viewed from a top view.

It is worth mentioning that the above description regarding the cell region, the transition region and the terminal guard ring region included in the device substrate is only an example, and any other structure type cell region, transition region and terminal guard ring region known to those skilled in the art may also be applied to the present application.

Further, as shown in fig. 3A to 3C, the semiconductor device of the present invention further includes a first implantation region 301, and the first implantation region 301 is disposed on the back surface of the device substrate 300 and is opposite to the terminal guard ring region 33.

Illustratively, the first implantation region 301 serves as a collector region of an IGBT device, and particularly, a collector region (collector) of a terminal guard ring region of the IGBT device.

In one example, the first implantation region 301 has a conductivity type opposite to that of the device substrate 300 or the drift region formed on the front surface of the device substrate 300, for example, if the device substrate 300 is N-type, the first implantation region 301 is P-type, and in this embodiment, the first implantation region 301 is preferably P-type lightly doped, that is, the first implantation region is P-implantation region, and the doping concentration of the P-implantation region may be any suitable doping concentration range known to those skilled in the art, and is not particularly limited herein.

In one example, the junction depth of the first implanted region 301, which is the distance between the bottom of the first implanted region 301 in the device substrate 300 and the backside, may be in a range of 0.2 μm to 0.4 μm, or other suitable range.

Further, the device substrate 300 includes a transition region, and the first implantation region 301 is disposed on the back surface of the device substrate 300 opposite to both the terminal guard ring region and the transition region, that is, the first implantation region 301 is formed on the back surface of the device substrate 300 in the region opposite to both the terminal guard ring region and the transition region.

Illustratively, the device substrate includes a gate pad region located at one corner of the cell region, and the first implant region 301 is further disposed in a portion of the device substrate 300 opposite to the gate pad region on the back surface of the device substrate, as shown in fig. 3A and 3B.

Illustratively, the semiconductor device of the present invention further includes a second implantation region 302, the second implantation region 302 is disposed on the back surface of the device substrate 300 and opposite to the cell region 31, and the first implantation region 301 surrounds the second implantation region 302.

In one example, the second implanted region has the same conductivity type as the first implanted region, e.g., the conductivity type of the second implanted region 302 and the first implanted region 301 are both P-type.

In one example, the doping concentration of the second implantation region 302 is greater than the doping concentration of the first implantation region 301, for example, the first implantation region is a P-type lightly doped implantation region (P-implantation region), and the second implantation region 302 is a P-type heavily doped implantation region (P + implantation region).

Illustratively, since the first implantation region 301 is disposed opposite the terminal guard ring region 33 and the transition region 32, and the second implantation region 302 is disposed opposite the cell region 31, the first implantation region 301 formed on the backside of the device substrate 300 surrounds the second implantation region 302, as shown in fig. 3A, 3B and 3C.

In one example, as shown in fig. 3A, 3B and 3C, a third implantation region 303 disposed in the first implantation region 301 and adjacent to the second implantation region 302 is further included, wherein a doping concentration of the third implantation region 303 is greater than a doping concentration of the first implantation region 301.

It is worth mentioning that the proximity of the third implantation region 303 to the second implantation region means that the distance from the third implantation region 303 to the adjacent inner edge of the first implantation region 301 is smaller than the distance from the third implantation region 303 to the adjacent outer edge of the first implantation region 301.

Optionally, the third implantation region 303 has the same conductivity type as the first implantation region 301 and the second implantation region 302, for example, both P-type.

Illustratively, the second and

third implantation regions

302 and 303 may both be P-type heavily doped implantation regions, for example, the second and

third implantation regions

302 and 303 have substantially the same doping concentration.

In one example, the doping concentration of the third implantation region 303 may also be made greater than the doping concentration of the first implantation region 301, while the doping concentration of the second implantation region 302 is greater than the doping concentration of the third implantation region 303.

Illustratively, the first implantation region 301, the second implantation region 302 and the third implantation region 303 have the same junction depth, that is, the three implantation regions are located at the same depth in the device substrate, and as can be seen from fig. 3C, the third implantation region 303 penetrates through the first implantation region 301.

Illustratively, the first implant region has a polygonal ring shape, and the third implant region 303 is located in a region other than at least one corner of the first implant region, for example, as shown in fig. 3A and 3B, the first implant region 301 includes four corners each having an inner edge and an outer edge in a circular arc shape. The third implantation regions 303 are located in the regions outside the four corners of the first implantation region 301, that is, in the regions of the back surface of the device substrate opposite to the terminal guard ring region 33, especially at the positions of the four corners, the first implantation regions 301 with low doping concentration are arranged to reduce the gain, weaken the large implantation effect, and increase the reverse turn-off safe operating region, while the third implantation regions may be arranged in the regions outside the four corners of the first implantation regions 301 to balance the degradation problem of the turn-on voltage drop Vcesat caused by the back surface pattern design.

It should be noted that, in this embodiment, the four corners are preferably only the first implantation region 301, but may also be selectively set according to the requirement of the actual device, for example, the first implantation region 301 may also be disposed only in the region of one corner, two corners or three corners, and since the top view shape of the second implantation region may also be other polygons, such as a triangle, a pentagon, a hexagon or other irregular shapes, besides the shapes shown in fig. 3A and 3B, the top view shape may also be other reasonable choices, and the shape of the corresponding first implantation region surrounding the second implantation region may also be other triangle rings, five rings, six rings, etc.

In one example, as shown in fig. 3A and 3B, the second implant region 302 and the third implant region 303 are separated by a portion of the first implant region 301.

Illustratively, the second implantation region 302 opposite the cell region 31 may also be selectively extended outward to cover a portion of the transition region 32.

Illustratively, the third implantation region 303 is disposed at a position close to the second implantation region 302, and the first implantation region 301 outside the third implantation region 303 is far from the cell region and has a low impurity doping concentration, so that it can still play a role in reducing the gain, weakening the large implantation effect, and increasing the reverse turn-off safety region.

In an example, the third implantation region 303 may be further disposed in the first implantation region 301 opposite to the transition region 32, may be further disposed in the first implantation region 301 opposite to the terminal guard ring region in a portion adjacent to the transition region, and may be further disposed from an inner edge to an outer edge of the terminal guard ring region.

In one example, as shown in fig. 3A, the third implantation region 303 includes a plurality of stripe-shaped implantation regions spaced apart from each other in a radial direction of the first implantation region 301, wherein an extending direction of the stripe-shaped implantation regions is parallel to an extending direction of an edge of the second implantation region 302 near the stripe-shaped implantation regions, and further, the stripe-shaped implantation regions are spaced apart from an inner edge of the first implantation region 301 toward an outer edge.

The number of the strip-shaped injection regions can be reasonably set according to the actual device requirements, for example, at least one strip-shaped injection region is respectively arranged at the outer sides of the four edges of the first injection region, two strip-shaped injection regions at intervals can be respectively arranged, and three strip-shaped injection regions at intervals can be also arranged.

In one example, as shown in fig. 3B, the third implantation region 303 includes several block implantation regions, the block implantation regions are arranged at intervals along a part of the edge of the second implantation region, and further, several block implantation regions are arranged at intervals from the inner edge of the first implantation region to the outer edge, so that the block implantation regions outside each edge of the second implantation region are arranged in an array.

It is noted that the third implant region includes a plurality of spaced apart bulk implant regions and may therefore also be referred to as a honeycomb implant region.

Optionally, the top view shape of each of the block-shaped implantation regions is a rectangle, a circle, an ellipse, a triangle, a pentagon, or a hexagon, or other shapes, which are not limited herein.

In one example, as shown in fig. 3A and 3B, the second implant region 302 is a polygon with one missing corner, such as a triangle, a quadrangle, a pentagon, a hexagon, etc., the third implant region 303 is also located on the missing corner of the polygon, the device substrate further includes a gate pad region located outside the third implant region 303 on the missing corner, and a back surface region of the device substrate of the gate pad region has the same implant region as the first implant region 301.

For example, the second implantation region 302 is a quadrilateral with one missing corner, the three corners of the quadrilateral are arc-shaped, the third implantation region 303 is further located on the missing corner of the quadrilateral, the front surface of the device substrate further includes a gate pad region, the gate pad region is opposite to the missing corner of the polygon, the gate pad region is located outside the third implantation region 303 on the missing corner, as shown in fig. 3A, the missing corner of the second implantation region 302 includes two straight edges, at least one strip-shaped implantation region is located outside one straight edge, and preferably, one strip-shaped implantation region, a plurality of strip-shaped implantation regions may also be located, or, as shown in fig. 3B, a plurality of block-shaped implantation regions are located at intervals along the two straight edges.

It is to be noted that although fig. 3A and 3B show the case where the third implantation region is a stripe implantation region and the third implantation region is a bulk implantation region, respectively, the third implantation region may be configured to include both the stripe implantation region and the bulk implantation region.

In one example, the back surface of the device substrate 300 is further provided with a buffer region 304, the top of the buffer region 304 is in contact with the bottom surfaces of the first, second and

third injection regions

301, 302, 303 in the device substrate, and the bottom of the buffer region 304 is located in the device substrate 300, for example, when the front surface of the device substrate 300 is provided with a drift region, the buffer region is arranged between the first, second and

third injection regions

301, 302, 303 and the drift region, wherein the buffer region 304 has the same conductivity type as the drift region or the device substrate, for example, the conductivity type of the buffer region 304 is N-type, especially N-type heavily doped buffer region.

Illustratively, the first, second and

third implantation regions

301, 302 and 303 may be used as collector regions of IGBT devices.

Further, collector layers are also provided on the surfaces of the first, second, and

third implantation regions

301, 302, and 303, and the collector layers are metal layers, and may be, for example, metals such as aluminum and gold.

Thus, the introduction of the semiconductor device of the present invention is completed, and the complete device also includes other structures and components, which are not described in detail herein.

In summary, in the semiconductor device of the present invention, the second implantation region (for example, P + implantation region) with high doping concentration is disposed on the back surface of the device substrate opposite to the cell region, the first implantation region (for example, P-implantation region) with low doping concentration is disposed on the back surface of the device substrate opposite to the terminal protection ring region far from the cell region, and particularly, the first implantation region is disposed outside the corners of the cell region (for example, outside the four corners of the cell region), so that the gain can be reduced, the large implantation effect can be weakened, and the reverse turn-off safe operation region can be increased, and the third implantation region (for example, P + implantation region) with moderate doping concentration is disposed on the back surface of the device substrate opposite to the terminal protection ring region near the cell region, which can balance the problem of degradation of the turn-on voltage Vcesat due to the back surface pattern design, and in addition, the semiconductor device of the present invention can also be in the process of turning off the device, the convergence of corresponding in-vivo hole carriers below the terminal ring is weakened, further the hole current converged together is weakened, and the problem that the device fails due to the latch-up effect of the triggering edge cells is solved, so that the semiconductor device has high performance and reliability.

Example two

The present invention also provides a method for manufacturing a semiconductor device in the first embodiment, as shown in fig. 5, the method mainly includes the following steps:

step S1, providing a device substrate, wherein the device substrate comprises a cellular area and a terminal protection ring area surrounding the cellular area;

step S2, forming a first implantation region, wherein the first implantation region is formed on the back surface of the device substrate and is opposite to the terminal protection ring region;

step S3, forming a second implantation region and a third implantation region, wherein the second implantation region is formed on the back surface and opposite to the cell region, the third implantation region is formed in the first implantation region and close to the second implantation region, and the doping concentrations of the second implantation region and the third implantation region are both greater than the doping concentration of the first implantation region.

Next, a method for manufacturing a semiconductor device of the present invention is described in detail with specific reference to fig. 3A to 3C, fig. 4A to 4C, and fig. 5. In one example, the semiconductor device of the present invention may be an IGBT device, and may also be another semiconductor device.

Firstly, a first step is executed, and a device substrate is provided and comprises a cellular area and a terminal protection ring area surrounding the cellular area.

Specifically, as shown in fig. 4A, a device substrate 300 is provided, the device substrate 300 including a cell region and a terminal guard ring region surrounding the cell region.

For simplicity, in fig. 4A to 4C, the device substrate 300 is shown in a blank frame, but it is conceivable that various element structures constituting the cell region, the element structure constituting the terminal guard ring region, and the like are already formed on the front surface of the device substrate before the process is performed on the back surface of the device substrate, and these structures may be any IGBT structures known to those skilled in the art, or may be the same or similar structures as those described in the foregoing embodiment, and details are not repeated here to avoid repetition.

In order to make the device substrate smaller in size, the back surface of the device substrate 300 is also subjected to thinning treatment.

In this step, the thinning method may be a method commonly used in the art, for example, a method such as mechanical grinding, Chemical Mechanical Polishing (CMP), chemical etching, plasma etching, or the like may be used. Optionally, the thickness of the thinned device substrate 300 ranges from 50 μm to 200 μm.

Illustratively, in order to facilitate the operation on the back side of the device substrate, before the thinning, the method further comprises the following steps:

first, a bonding layer (not shown) is formed on the front side of the device substrate.

The bonding layer is bonding glue, the bonding glue can be but not limited to organic polymer materials or ultraviolet-modified organic materials, and the bonding glue has viscosity.

A bond paste layer may be formed on the front side of the device substrate using a method such as coating.

Then, a supporting substrate is provided, and the bonding layer and the supporting substrate are jointed.

The support substrate may be a semiconductor substrate such as a silicon substrate, glass, or a ceramic material. The device substrate is used for supporting the device substrate, and the back side of the device substrate is convenient to operate.

Illustratively, to facilitate handling of the back side of the device substrate, the front side of the device substrate may also be bonded to a support substrate, which serves to support the device substrate.

And then, executing a second step to form a first injection region, wherein the first injection region is formed on the back surface of the device substrate and is opposite to the terminal protection ring region.

In one example, before forming the first implantation region, ion implantation may be further selectively performed on the back surface of the device substrate to form a buffer layer (not shown) in the device substrate. Optionally, when the buffer layer is an N-type buffer layer, the implanted ions of the ion implantation are N-type doped ions, including but not limited to at least one of phosphorus or arsenic.

The buffer layer can be realized by ion implantation on the back of the substrate, and the depth of the ion implantation is controlled by controlling the implantation energy. Optionally, the implantation energy range of the first ion implantation is 2Mev to 3Mev, and the implantation dose range is 1E12 to 5E13atom/cm²This range of values is by way of example only.

Further, as shown in fig. 4A, the method of forming the first implantation region includes: a first ion implantation is performed on the backside of the device substrate 300 to form a first implanted region 301 in the device substrate 300. In this step, since the ion implantation is performed on the back surface of the entire device substrate without using a mask (mask), the first implantation region formed first also covers the back surface of the entire device substrate 300.

In one example, the first implanted region 301 and the buffer region have opposite conductivity types, e.g., the buffer region is N-type, then the first implanted region 301 is P-type, and in particular, the first implanted region 301 is lightly doped P-type.

Illustratively, the first implantation region 301 is formed by ion implantation, and when the first implantation region 301 is P-type, the type of implanted ions is P-type doped impurities, such as boron.

Illustratively, the depth of the ion implantation is controlled by controlling the implantation energy, for example, the implantation energy of the first ion implantation is in the range of 20 Kev-40 Kev, and the implantation dose can be in the range of 1E 11-5E 12atom/cm²These numerical ranges are exemplary only and are not intended to be limiting.

The first implantation region 301 formed by the above ion implantation may be a P-type lightly doped implantation region.

And then, performing a third step to form a second implantation region and a third implantation region, wherein the second implantation region is formed on the back surface of the device substrate and is opposite to the cell region, the third implantation region is formed in the first implantation region and is close to the second implantation region, and the doping concentrations of the second implantation region and the third implantation region are both greater than that of the first implantation region.

Specifically, as shown in fig. 4B and 4C, the method of forming the second and third implantation regions further includes the steps of:

first, as shown in fig. 4B, a patterned mask layer 305 is formed on the back surface of the device substrate 300, and the mask layer 305 exposes the region of the device substrate 300 where the second implantation region and the third implantation region are to be formed.

Specifically, the mask layer 305 may comprise any of several mask materials, including but not limited to: a hard mask material and a photoresist mask material. In this embodiment, the mask layer 305 includes a photoresist mask material.

A suitable mask may be designed according to the pattern shapes of the second implantation region and the third implantation region in the first embodiment, and the mask may be used to perform exposure, development, and the like on the photoresist mask material coated on the back surface of the device substrate 300 to form a mask layer defining the patterns of the second implantation region and the third implantation region.

The pattern shape and position of the second implantation region and the third implantation region to be formed are described in detail in the first embodiment, and are not described herein again to avoid redundancy.

Next, as shown in fig. 4B, a second ion implantation is performed by using the mask layer 305 as a mask to form the second implantation region 302 and the third implantation region 303.

In particular, the second and third implanted

regions

302, 303 and the first implanted region 301 have the same conductivity type, for example both P-type. And the doping concentration of the second implantation region 302 and the third implantation region 303 are both greater than that of the first implantation region 301, so that the adjustment of the doping concentration can be realized by controlling the implantation dosage.

For example, the implanted ions of the second ion implantation may be P-type dopant ions, which may include boron, for example.

Optionally, the implantation dose range of the second ion implantation can be 1E 13-5E 13atom/cm²These numerical ranges are exemplary only and are not intended to be limiting.

Illustratively, the second and

third implantation regions

302 and 303 may be formed as P-type heavily doped implantation regions.

Further, the second and third implanted regions have the same junction depth as the first implanted region, which can be achieved by having the first and second ion implants both have substantially the same implant energy.

Subsequently, as shown in fig. 4C, the mask layer is removed. The masking layer may be removed by any suitable method selected based on the material of the particular masking layer, for example, an ashing process may be used to remove the masking layer from the photoresist material.

Further, after removing the mask layer, an annealing step is further included to activate the doping ions in the first implantation region 301, the second implantation region 302, and the third implantation region 303, and perform defect repair, for example, repair the lattice damage of the device substrate due to ion implantation.

Illustratively, the annealing may use any annealing process known to those skilled in the art, including but not limited to rapid thermal annealing, furnace annealing, spike annealing, laser annealing, and the like. In this embodiment, the annealing is preferably performed by laser annealing, which has the advantage of local heating, and can anneal only the region to be annealed without causing thermal damage to other regions except the region.

Finally, the first implantation region 301, the second implantation region 302 and the third implantation region 303 in the first embodiment are formed on the back surface of the device substrate.

For avoiding repetition, the first implantation region 301, the second implantation region 302, and the third implantation region 303 are not described herein, and specific details thereof can be found in the description of the first embodiment.

Subsequently, in an example, a metal layer may also be formed on the surfaces of the first implantation region 301, the second implantation region 302, and the third implantation region 303, and an annealing process is performed to form a metal silicide, and the metal layer may include, for example, Ti metal.

Illustratively, a collector (not shown) may also be formed on the surfaces of the first, second, and

third implant regions

301, 302, 303. Wherein the material of the collector comprises a metal including, but not limited to, aluminum, copper, titanium, or chromium, etc.

Subsequently, in one example, a de-bonding process is performed to separate the device substrate and the support substrate.

Specifically, the device substrate and the supporting substrate may be separated by any method known to those skilled in the art for debonding, for example, heating at a high temperature to denature the bonding layer such as bonding paste to lose adhesiveness, and then peeling the bonding layer from which adhesiveness is lost.

Thus, the introduction of the key steps of the method for manufacturing a semiconductor device of the present invention is completed, and other steps are required for the complete device fabrication, which is not described in detail herein.

Since the manufacturing method of the present invention prepares the semiconductor device in the first embodiment, the manufacturing method of the present invention has the same advantages as those in the first embodiment.

EXAMPLE III

The invention also provides an electronic device comprising the semiconductor device of the first embodiment, and the semiconductor device is prepared according to the method of the second embodiment.

The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.

Wherein figure 6 shows an example of a mobile telephone handset. The mobile phone handset 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.

Wherein the mobile phone handset comprises the semiconductor device of embodiment one, the semiconductor device comprising:

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A semiconductor device, comprising:

and the third injection region is arranged in the first injection region and is close to the second injection region, wherein the first injection region, the second injection region and the third injection region have the same conductivity type, and the doping concentration of the second injection region and the doping concentration of the third injection region are all greater than that of the first injection region.

2. The semiconductor device of claim 1, wherein the first implant region is in the shape of a polygonal ring and the third implant region is located in a region outside at least one corner of the first implant region.

3. The semiconductor device of claim 2, wherein the first implanted region includes four corners, and the third implanted region is located in a region outside the four corners of the first implanted region.

4. The semiconductor device according to claim 1, wherein the third implantation region comprises a plurality of strip-shaped implantation regions arranged at intervals in a radial direction of the first implantation region, wherein an extending direction of the strip-shaped implantation regions is parallel to an extending direction of edges of the second implantation regions to which the strip-shaped implantation regions are close; and/or the presence of a gas in the gas,

5. The semiconductor device of claim 1, wherein the doping concentration of the second and third implanted regions is the same.

6. The semiconductor device of claim 1, wherein the second implant region is in the shape of a polygon with one missing corner, and the third implant region is also located on the missing corner of the polygon;

7. The semiconductor device according to claim 1,

the first, second and third implanted regions have the same junction depth.

8. The semiconductor device of claim 1, wherein the second and third implanted regions are heavily doped implanted regions and the first implanted region is a lightly doped implanted region.

9. The semiconductor device of claim 1, wherein the device substrate further comprises a transition region surrounding the cell region and located between the terminal guard ring region and the cell region, wherein the first implant region is further opposite the transition region and the third implant region is opposite the transition region.

10. The semiconductor device according to claim 1, wherein the semiconductor device is an IGBT device.

11. A method of manufacturing a semiconductor device, comprising:

and forming a second injection region and a third injection region, wherein the second injection region is formed on the back surface and is opposite to the cellular region, the third injection region is formed in the first injection region and is close to the second injection region, the first injection region, the second injection region and the third injection region have the same conductivity type, and the doping concentration of the second injection region and the doping concentration of the third injection region are all greater than that of the first injection region.

12. The method of manufacturing of claim 11, wherein forming the first, second, and third implant regions comprises:

and removing the mask layer.

13. The method of claim 12, further comprising a step of performing an annealing process to activate dopant ions in the first, second, and third implanted regions after removing the mask layer.

14. The method of manufacturing of claim 12 wherein the first implant region is in the shape of a polygonal ring and the third implant region is located in a region outside at least one corner of the first implant region.

15. The method of manufacturing of claim 14, wherein the first implanted region comprises four corners and the third implanted region is located in a region other than the four corners of the first implanted region.

16. The method of claim 12, wherein the third implant region comprises a plurality of stripe-shaped implant regions spaced apart along a radial direction of the first implant region, wherein an extending direction of the stripe-shaped implant regions is parallel to an extending direction of edges of the second implant regions adjacent to the stripe-shaped implant regions; and/or the presence of a gas in the gas,

17. The method of manufacturing of claim 11 wherein the second implant region is in the shape of a polygon with one missing corner, and the third implant region is further located on the missing corner of the polygon;

the semiconductor substrate further includes a gate pad region located outside the third implant region on the missing corner.

18. The manufacturing method according to claim 11,

the first, second and third implanted regions have the same junction depth.

19. The method of manufacturing of claim 11, wherein the second and third implanted regions are heavily doped implanted regions and the first implanted region is a lightly doped implanted region.

20. The method of manufacturing of claim 11, wherein the device substrate further comprises a transition region surrounding the cell region and located between the terminal guard ring region and the cell region, wherein the first implant region is further opposite the transition region and the third implant region is opposite the transition region.

21. The manufacturing method according to claim 11, wherein the semiconductor device is an IGBT device.

22. An electronic device, characterized in that the electronic device comprises the semiconductor device according to one of claims 1 to 10.