CN109256422A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN109256422A CN109256422A CN201710566154.0A CN201710566154A CN109256422A CN 109256422 A CN109256422 A CN 109256422A CN 201710566154 A CN201710566154 A CN 201710566154A CN 109256422 A CN109256422 A CN 109256422A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method and electronic device, comprising: device substrate, including cellular region and around the terminal protection ring region of the cellular region；The back side of the device substrate and opposite with the terminal protection ring region is arranged in first injection region；Second injection region, setting is in the back side and, first injection region circular second injection region opposite with the cellular region；Third injection region is arranged in first injection region and close to second injection region, wherein second injection region, the third injection region doping concentration be all larger than the doping concentration of first injection region.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technique
How insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviation IGBT) is promoted
The reversed shutdown safety operation area of device is always the difficult point and emphasis of IGBT device design.IGBT device is most common reversed
Edge cellular (cell) in device occurs for shutdown failure, and mechanism is mainly triggered by latch-up, leads to component failure.From device
It is seen in the structure of part, positive cell region is responsible for the turn-on and turn-off of electric current, and the terminal protection ring region (terminal ring) is negative
Blaming device, laterally pressure resistance, device rear electrode do not have figure (pattern), are responsible for the turn-on and turn-off of electric current.Therefore, device is being just
The current channel area at face and the back side is inconsistent, and backside area is greater than front face area (namely area of cellular).It is turned off in device
In the process, corresponding internal holoe carrier below terminal protection ring, can be gathered together, from edge cellular (near terminal
The cellular of protection ring) outflow, when the hole current being gathered together is sufficiently large, the latch-up of edge cellular can be triggered, is caused
Component failure, as shown in Figure 1, wherein the arrow curve in Fig. 1 shows reversed cut-off current approach.Moreover, voltage class is higher
IGBT device, terminal protection anchor ring product it is bigger, the crash rate of edge cellular can also be substantially improved.
Therefore, in order to solve the above-mentioned technical problem, the present invention proposes a kind of manufacturing method of new semiconductor devices.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, one aspect of the present invention provides a kind of semiconductor devices, comprising:
Device substrate, including cellular region and around the terminal protection ring region of the cellular region；
The back side of the device substrate and opposite with the terminal protection ring region is arranged in first injection region；
Second injection region, setting is at the back side and opposite with the cellular region, and first injection region is around described the
Two injection regions；
Third injection region is arranged in first injection region and close to second injection region, wherein second note
Enter area, the doping concentration of the third injection region is all larger than the doping concentration of first injection region.
Illustratively, first injection region is in polygon, and the third injection region is located at first injection region extremely
In region other than a few angle.
Illustratively, first injection region includes four angles, and the third injection region is located at first injection region
In region other than four angles.
Illustratively, the third injection region includes the strip note that several spaced radials along first injection region are arranged
Enter area, wherein the side of the extending direction of the strip injection region and close second injection region in the strip injection region
The extending direction of edge is parallel；And/or
The third injection region includes several blocky injection regions, part of the bulk injection region along second injection region
Edge is alternatively arranged.
Illustratively, second injection region is identical with the doping concentration of the third injection region.
Illustratively, second injection region is in the polygon of one of corner missing, the third injection region also position
In on the corner of polygon missing；
The device substrate further includes gate pads area, and the gate pads area is located at the third on the corner of the missing
The outside of injection region.
Illustratively, first injection region, second injection region and the third injection region junction depth having the same,
And/or first injection region, second injection region and the third injection region conduction type having the same.
Illustratively, second injection region and the third injection region are the injection region of heavy doping, first injection
Area is the injection region being lightly doped.
Illustratively, the device substrate further includes transition region, and the transition region is around the cellular region and is located at described
Between terminal protection ring region and the cellular region, wherein the first injection region is also opposite with the transition region, the third injection region
It is opposite with the transition region.
Illustratively, the semiconductor devices is IGBT device.
Further aspect of the present invention provides a kind of manufacturing method of semiconductor devices, comprising:
Device substrate is provided, the device substrate includes cellular region and the terminal protection ring region around the cellular region；
Form the first injection region, wherein first injection region be formed in the back side of the device substrate and with the end
End protection ring region is opposite；
Form the second injection region and third injection region, wherein second injection region be formed in the back side and with it is described
Cellular region is opposite, and the third injection region is formed in first injection region and close second injection region, and described second
Injection region, the third injection region doping concentration be all larger than the doping concentration of first injection region.
Illustratively, the method for formation first injection region, the second injection region and the third injection region includes:
First ion implanting is carried out to the back side of the device substrate, to form the first note in the device substrate
Enter area；
Patterned mask layer is formed on the back side of the device substrate, it is pre- that the mask layer exposes the device substrate
It is shaped as the region of second injection region and the third injection region；
Using the mask layer as exposure mask, the second ion implanting is carried out, to form second injection region and third note
Enter area；
Remove the mask layer.
It illustratively, further include being made annealing treatment after removing the mask layer, to activate first injection
The step of Doped ions in area, second injection region and the third injection region.
Illustratively, first injection region is in polygonal annular, and the third injection region is located at first injection region
In region other than at least one angle.
Illustratively, first injection region includes four angles, and the third injection region is located at first injection region
In region other than four angles.
Illustratively, the third injection region includes the strip note that several spaced radials along first injection region are arranged
Enter area, wherein the side of the extending direction of the strip injection region and close second injection region in the strip injection region
The extending direction of edge is parallel；And/or
The third injection region includes several blocky injection regions, part of the bulk injection region along second injection region
Edge is alternatively arranged.
Illustratively, second injection region is in the polygon of one of corner missing, the third injection region also position
In on the corner of polygon missing；
The device substrate further includes gate pads area, and the gate pads area is located at the third on the corner of the missing
The outside of injection region.
Illustratively, first injection region, second injection region and the third injection region junction depth having the same,
And/or first injection region, second injection region and the third injection region conduction type having the same.
Illustratively, second injection region and the third injection region are the injection region of heavy doping, first injection
Area is the injection region being lightly doped.
Illustratively, the device substrate further includes transition region, and the transition region is around the cellular region and is located at described
Between terminal protection ring region and the cellular region, wherein the first injection region is also opposite with the transition region, the third injection region
It is opposite with the transition region.
Illustratively, the semiconductor devices is IGBT device.
Another aspect of the present invention provides a kind of electronic device, and the electronic device includes semiconductor devices above-mentioned.
Semiconductor devices of the invention includes being arranged in the device substrate and protecting close to the back side and the terminal
The first opposite injection region of retaining ring area, be arranged in the device substrate and close to the back side it is opposite with the cellular region
Two injection regions, and the third injection region in first injection region and close to second injection region is set, wherein it is described
The doping concentration of second injection region is greater than the doping concentration of first injection region, and the doping concentration of the third injection region is greater than
The doping concentration of first injection region, dense with far from the opposite region setting doping of the terminal protection ring region of the cellular region
Spend the first low injection region, further decrease gain, weaken big injection effect, increase reversed shutdown safety operation area, with lean on
The high third injection region of the opposite region setting doping concentration of the terminal protection ring region of the nearly cellular region, can be avoided conducting pressure
The deterioration of Vcesat is dropped.Therefore, semiconductor devices of the invention has high Performance And Reliability.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the diagrammatic cross-section of the IGBT device of an existing embodiment；
Fig. 2A shows the back side top view of the IGBT device of existing another embodiment；
Fig. 2 B shows the partial cutaway schematic along Fig. 2A section line AA ' IGBT device obtained；
Fig. 3 A shows the back side top view of the IGBT device of one embodiment of the present invention；
Fig. 3 B shows the back side top view of the IGBT device of another embodiment of the present invention；
Fig. 3 C shows the partial cutaway schematic along Fig. 3 A section line AA ' IGBT device obtained, wherein Fig. 3 C
Middle arrow curve shows reversed cut-off current approach；
Fig. 4 A to Fig. 4 C shows the correlation step institute of the manufacturing method of the semiconductor devices of one embodiment of the present invention
The diagrammatic cross-section of the device of acquisition；
Fig. 5 shows the process flow chart of the manufacturing method of the semiconductor devices of one embodiment of the present invention；
Fig. 6 shows the schematic diagram of the electronic device in one embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size in the area Ceng He and corresponding size may be exaggerated.From beginning extremely
Whole same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram as desirable embodiment (and intermediate structure) of the invention
Bright embodiment.As a result, it is contemplated that from the variation of shown shape as caused by such as manufacturing technology and/or tolerance.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as the injection region of rectangle usually has round or bending features and/or implantation concentration ladder at its edge
Degree, rather than binary from injection region to non-injection regions changes.Equally, which can lead to by the disposal area that injection is formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the invention.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, it is proposed by the present invention to illustrate
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have
There are other embodiments.
The improvement of safety operation area is reversely turned off for IGBT device at present, the solution of mainstream is to introduce back side figure
Technique is keeping the note of the injection region P+ at the corresponding back side namely collecting zone (collector) below the region front cellular (cell)
Enter concentration it is constant under the premise of, reduce the implantation concentration of the injection region corresponding back side P+ below whole terminal protection ring region for example
It is reduced to the injection region P-, wherein the gate pads area on an angle of cellular region reduces the region gain, big injection effect
Weaken.In device turn off process, corresponding internal hole is reduced below terminal protection ring, is reduced from source
The hole current for converging and flowing out through edge cellular increases the reversed shutdown safety operation area of device, as shown in Figure 2 A and 2 B.
But the shortcomings that this scheme is: corresponding back side P+ implantation concentration reduces below whole terminal protection ring region,
It will lead to the conduction voltage drop Vcesat deterioration of device entirety.
In order to solve aforementioned technical problem, the present invention provides a kind of semiconductor devices, specifically includes that
Device substrate, including cellular region and around the terminal protection ring region of the cellular region；
The back side of the device substrate and opposite with the terminal protection ring region is arranged in first injection region；
Second injection region, setting is at the back side and opposite with the cellular region, and first injection region is around described the
Two injection regions；
Third injection region is arranged in first injection region and close to second injection region, wherein second note
Enter area, the doping concentration of the third injection region is all larger than the doping concentration of first injection region.
Semiconductor devices of the invention includes being arranged in the device substrate and protecting close to the back side and the terminal
The first opposite injection region of retaining ring area, be arranged in the device substrate and close to the back side it is opposite with the cellular region
Two injection regions, and the third injection region in first injection region and close to second injection region is set, wherein it is described
The doping concentration of second injection region is greater than the doping concentration of first injection region, and the doping concentration of the third injection region is greater than
The doping concentration of first injection region, dense with far from the opposite region setting doping of the terminal protection ring region of the cellular region
Spend the first low injection region, further decrease gain, weaken big injection effect, increase reversed shutdown safety operation area, with lean on
The high third injection region of the opposite region setting doping concentration of the terminal protection ring region of the nearly cellular region, can be avoided conducting pressure
The deterioration of Vcesat is dropped.Therefore, semiconductor devices of the invention has high Performance And Reliability.
Embodiment one
Semiconductor devices of the invention is described in detail referring in particular to Fig. 3 A to Fig. 3 C.Wherein, Fig. 3 A is shown
The back side top view of the IGBT device of one embodiment of the present invention；Fig. 3 B shows the IGBT of another embodiment of the present invention
The back side top view of device；Fig. 3 C shows the partial cutaway schematic along Fig. 3 A section line AA ' IGBT device obtained,
Wherein, arrow curve shows reversed cut-off current approach in Fig. 3 C.
Specifically, as shown in Fig. 3 A to Fig. 3 C, in one example, semiconductor devices of the invention can be IGBT device
Part, or other semiconductor devices in the present embodiment, mainly by taking IGBT device as an example, carry out method of the invention
Explanation and illustration.
As an example, as shown in Figure 3 C, semiconductor devices of the invention includes device substrate 300, the device substrate 300
Including front and the back side opposite with the front.The front of the device substrate includes cellular region 31 and surround described
The terminal protection ring region 33 of cellular region 31.
Device substrate 300 is body silicon substrate, can be following at least one of the material being previously mentioned: Si, Ge,
SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, further include these semiconductors
The multilayered structure etc. of composition, or be silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, germanium is laminated on insulator
Silicon (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Further, the substrate is also
It can be N-type substrate or P type substrate.In the present embodiment, preferably device substrate 300 is that substrate (N- substrate) is lightly doped in N-type.
In one example, several isolation structures, the isolation junction are formed in the front of the device substrate of cellular region
Structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.It is also formed in the semiconductor substrate
The channel layer of various trap (well) structures and substrate surface.
In one example, the cellular region 31 includes being arranged in the positive gate structure of device substrate and gate structure
The emitter region of contact, the N+ emitter region being connect with emitter region, the area PXing Ti being connect with emitter region, N+ emitter position
In in the area PXing Ti, the area PXing Ti is located in the device substrate of N- (N-type is lightly doped), alternatively, being provided in device substrate
The drift region N-, the area PXing Ti are located in the drift region N-, and emitter is arranged in the emitter region.In each cellular unit, grid
Structure is formed on the surface of two N+ emitter regions and channel region, and the gate structure includes grid layer and is located under grid layer
The gate dielectric of side is opposite with N+ emitter region and channel region by gate dielectric.
In one example, as shown in Figure 3 C, the device substrate 300 further includes transition region 32, and the setting of transition region 32 exists
The front of the device substrate 300, the transition region 32 is around the cellular region 31 and is located at 33 He of terminal protection ring region
Between the cellular region 31.
Illustratively, the transition region includes the equal potential belt 321 being formed in the device substrate 300, and described etc.
The top surface of position ring 321 and the front flush of the device substrate 300, the equal potential belt 321 connect with cellular and surround the member
Born of the same parents area, equal potential belt are connected because of it with cellular during fabrication, therefore have following with the emitter of cellular or cathode equipotential, equal potential belt
Several effects, one reduce the curvature effect of outermost layer cellular because it extends outermost layer cellular and junction depth is deeper, drop
The low electric field strength of outermost layer cellular, the firm pressure resistance of device；Second, introduce transition region also increase it is bipolar when shutdown
Path is extracted in the hole of type gated device, so that the reliability of device shutdown is improved, third, because transition region is wider, thus
When layout design arrangement space can be provided for the grid cabling of gated power device.
In one example, the equal potential belt 321 has the conduction type opposite with device substrate or drift region, such as institute
Stating device substrate is N-type substrate, then the equal potential belt 321 is p-type equal potential belt, especially P+ type equal potential belt.
In one example, region opposite with the equal potential belt 321 on the front of the device substrate 300 is also successively
It is provided with oxygen and the field plate on the oxygen of field, wherein the material of field plate may include polysilicon or metal, also may include
The polysilicon and metal stacked from bottom to top collectively constitutes, and dielectric layer can also be arranged between metal and polysilicon, wherein metal
It may include aluminium, copper, gold, tin etc. or their alloy.
In one example, it is additionally provided with body draw-out area in the body area of the cellular region, for example, the body area is p-type
Body area, then the body draw-out area is p-type heavy doping, and equal potential belt draw-out area is formed in the equal potential belt, which draws
Area has conduction type identical with equal potential belt, and the equal potential belt draw-out area has the doping concentration denseer than the equal potential belt.
Illustratively, be also formed with above the gate structure on the front of the device substrate with the body draw-out area and
The metal interconnection structure of the equal potential belt draw-out area electrical connection, the metal for example including contact hole and interconnecting metal layer mutually link
Structure, the metal may include copper, aluminium or other metal materials.
In one example, illustratively, as shown in Figure 3 C, in the device substrate of the terminal protection ring region 33
At least one field limiting ring 331 is formed in 300, the field limiting ring 331 is further located at described around the cellular region 31
On the outside of transition region.Wherein, the field limiting ring 331 can be formed for example, by the method for ion implanting, the field limiting ring have with
The opposite conduction type of the device substrate, for example, the device substrate 300 is that substrate is lightly doped in N-type substrate, especially N-type,
Field limiting ring 331 is then p-type field limiting ring, such as p-type heavy doping field limiting ring.
Illustratively, the number of the field limiting ring 331 reasonably select according to practical devices, for example, can be with
Including 1,2,3 to n field limiting ring.
Illustratively, the field limiting ring 331 and the equal potential belt 321 are arranged at intervals in the device substrate 300.
Illustratively, several field plate structures are additionally provided on the front of the device substrate of the terminal protection ring region 33,
Wherein, the number of field plate structure can be set according to the number of field limiting ring, such as respectively be set in the two sides of each field limiting ring 331
Set the field plate structure, wherein each field plate structure includes oxygen and the field plate on the oxygen surface of field, wherein
The field oxygen generally includes silica, and the material of the field plate may include polysilicon or metal, also may include from lower and
The polysilicon and metal of upper stacking collectively constitute, and dielectric layer can also be arranged between metal and polysilicon, wherein metal can wrap
Include aluminium, copper, gold, tin etc. or their alloy.
In one example, several and 331 electricity of field limiting ring are additionally provided on the front of the device substrate 300
The interconnection structure of connection, the interconnection structure include contact hole between adjacent field plate structure and above contact hole
Metal layer, the contact hole connect the surface of the field limiting ring.
Illustratively, at the edge of the terminal protection ring region far from being additionally provided with ditch in the device substrate of the cellular region
Road cut-off region, for example, the channel cutoff area have the conduction type opposite with field limiting ring, two kinds of this implementation, the channel cutoff area
Conduction type be N-type, especially N+ type.
In one example, as shown in Figure 3A and Figure 3B, the device substrate 300 further includes the area gate pads (pad), institute
The front that the device substrate is arranged in gate pads area is stated, gate pads area includes pad, and the pad is by mutually linking
Structure is electrically connected with grid.
In one example, as viewed from overlook direction, the gate pads area is located on an angle of the cellular region.
It is noted that the description of the above-mentioned cellular region for including about device substrate, transition region and terminal protection ring region
Only as an example, for the cellular region of any other structure type well known to those skilled in the art, transition region and terminal protection
Ring region is readily applicable to the application.
Further, as shown in Fig. 3 A to Fig. 3 C, semiconductor devices of the invention further includes the first injection region 301, and first
The back side of the device substrate 300 and opposite with the terminal protection ring region 33 is arranged in injection region 301.
Illustratively, the terminal that first injection region 301 is used as the collecting zone of IGBT device, especially IGBT device is protected
The collecting zone (collector) in retaining ring area.
In one example, first injection region 301 has and the device substrate 300 or is formed in device substrate
The opposite conduction type in 300 positive drift regions, for example, the device substrate 300 is N-type, then first injection region 301 is
P-type, in the present embodiment, preferably, first injection region 301 is lightly doped for p-type namely the first injection region is the injection region P-,
The doping concentration of the injection region P- can be the concentration range of any suitable doping well known to those skilled in the art, then this does not do
It is specific to limit.
In one example, the junction depth of first injection region 301 may range from 0.2 μm~0.4 μm or other are suitable
The range of conjunction, the junction depth refer to the distance between the bottom that the first injection region 301 is located in device substrate 300 and back side.
Further, the device substrate 300 includes transition region, then the first injection region 301 is arranged in the device substrate
300 back side and the terminal protection ring region and the transition region are opposite, namely the back side and the end in device substrate 300
End protection ring region and the opposite region of the transition region are each formed with first injection region 301.
Illustratively, the device substrate includes gate pads area, and the gate pads area is located at the one of the cellular region
On a angle, first injection region 301 is additionally arranged at described in the back side part opposite with the gate pads area of device substrate
In device substrate 300, as shown in Figure 3A and Figure 3B.
Illustratively, semiconductor devices of the invention further includes the second injection region 302, and the second injection region 302 is arranged in institute
State the back side of device substrate 300 and, first injection region 301 circular second injection region opposite with the cellular region 31
302。
In one example, second injection region has conduction type identical with the first injection region, for example, described the
The conduction type of two injection regions 302 and the first injection region 301 is p-type.
In one example, the doping concentration of second injection region 302 is dense greater than the doping of first injection region 301
Degree, for example, first injection region is that p-type is lightly doped injection region (injection region P-), and the second injection region 302 is p-type heavy doping
Injection region (injection region P+).
Illustratively, it is oppositely arranged due to first injection region 301 with terminal protection ring region 33 and transition region 32, and the
Two injection regions 302 are oppositely arranged with cellular region 31, therefore, are formed in first injection region 301 at 300 back side of device substrate around the
Two injection regions 302, as shown in 3A, Fig. 3 B and Fig. 3 C.
It in one example, further include being arranged in first injection region 301 simultaneously as shown in Fig. 3 A, Fig. 3 B and Fig. 3 C
Close to the third injection region 303 of second injection region 302, wherein the doping concentration of the third injection region 303 is greater than described
The doping concentration of first injection region 301.
It is noted that third injection region 303 refers to the third injection region 303 to institute close to second injection region
The distance for stating the adjacent inward flange of the first injection region 301 is less than the third injection region 303 to first injection region 301
Adjacent outer peripheral distance.
Optionally, the third injection region 303 has and the first injection region 301 and the second injection region 302 is identical leads
Electric type, such as be p-type.
Illustratively, second injection region 302 and the third injection region 303 can be p-type heavily-doped implant area,
For example, the second injection region 302 and third injection region 303 have the doping concentration being substantially the same.
In one example, the doping that the doping concentration of third injection region 303 can also be made to be greater than the first injection region 301 is dense
Degree, and the doping concentration of the second injection region 302 is greater than the doping concentration of third injection region 303.
Illustratively, first injection region 301, second injection region 302 and the third injection region 303 have phase
The depth that same junction depth namely three injection regions is located in device substrate is identical, can be seen that third injection region 303 from Fig. 3 C
Through the first injection region 301.
Illustratively, first injection region is in polygonal annular, and the third injection region 303 is located at first injection region
At least one angle other than region in, for example, as shown in Figure 3A and Figure 3B, first injection region 301 includes four angles, should
Four angles all have arc-shaped inward flange and outer edge.The third injection region 303 is located at the four of first injection region 301
In region other than a angle, namely in the region at the back side of the device substrate opposite with terminal protection ring region 33, especially exist
The first injection region 301 of low doping concentration is arranged in the position at four angles, to reduce gain, weakens big injection effect, increases reversed
Safety operation area is turned off, and third injection region can be set in the region other than four angles of the first injection region 301, to balance back
Face graphic designs bring conduction voltage drop Vcesat deteriorates problem.
It is noted that preferably the position at four angles is only the first injection region 301 in the present embodiment, but
Selection setting can be carried out according to the needs of practical devices, such as can also be only in the area at an angle, two angles or three angles
The first injection region 301 is arranged in domain, and since the plan view shape of the second injection region can also be in addition to shown by Fig. 3 A and Fig. 3 B
Other polygons other than shape, such as triangle, pentagon, hexagon or other irregular shape, therefore can be with
It is reasonably selected by others, and the shape around the first injection region of second injection region may be others three accordingly
The annular etc. in annular, six of square ring shape, five.
In one example, as shown in Figure 3A and Figure 3B, second injection region 302 and the third injection region 303 it
Between separated by part first injection region 301.
Illustratively, it is also an option that property make second injection region 302 opposite with the cellular region 31 to extension
It stretches and covers with the part transition region 32 relatively.
Illustratively, third injection region 303 is positioned close at the position of second injection region 302, and third is injected
First injection region 301 in 303 outside of area far from the cellular region and has low impurity doping concentration, therefore still can play
Reduce gain, weaken big injection effect, increases the effect of reversed shutdown safety zone.
In one example, described opposite with the transition region 32 can also be arranged in the third injection region 303
In one injection region 301, can also further be provided in part that transition region is closed on it is opposite with terminal protection ring region first
In injection region 301, it can also be arranged from the inward flange of terminal protection ring region to outer edge.
In one example, as shown in Figure 3A, the third injection region 303 includes several along first injection region 301
Spaced radial setting strip injection region, wherein the extending direction of the strip injection region is leaned on the strip injection region
The extending direction at the edge of close second injection region 302 is parallel, and further, the strip injection region is from first note
Enter the outside edge direction interval setting of inward flange in area 301.
The number of reasonable set strip injection region can be needed according to practical devices, for example, at four of the first injection region
An at least strip injection region is respectively set on the outside of edge, the strip injection region at two intervals can also be respectively set,
Also the strip injection region at three intervals can be set.
In one example, as shown in Figure 3B, the third injection region 303 includes several blocky injection regions, the bulk
Part edge of the injection region along second injection region is alternatively arranged, and further, several bulk injection regions can also be from described
The outside edge direction of the inward flange of first injection region is alternatively arranged, and makes the blocky injection on the outside of each edge in the second injection region
Area is arranged in array.
It is worth noting that third injection region includes several spaced blocky injection regions, therefore bee can also be referred to as
The injection region nest shape (cellular).
Optionally, the plan view shape of each blocky injection region be rectangle, circle, ellipse, triangle, pentagon or
Person's hexagon, or other shapes, are not specifically limited herein.
In one example, as shown in Figure 3A and Figure 3B, second injection region 302 is in the more of one of corner missing
Side shape, such as triangle, quadrangle, pentagon, hexagon etc., the third injection region 303 are also located at the polygon missing
Corner on, the device substrate further includes gate pads area, and the gate pads area is located on the corner of the missing
The rear surface regions in the outside of three injection regions 303, the device substrate in the gate pads area have and first injection region 301 is identical
Injection region.
For example, second injection region 302 is in the quadrangle of one of corner missing, three corners of the quadrangle
Side be it is arc-shaped, the third injection region 303 be also located at the quadrangle missing corner on, the device substrate front also wrap
Gate pads area is included, the gate pads area is opposite with the corner that polygon lacks, and the gate pads area is located at the missing
The outside of third injection region 303 on corner, as shown in Figure 3A, the second injection described in the edge of the second injection region 302 missing
Area 302 includes two linear edges, at least one strip injection region is arranged in the outside at straight line edge, wherein being preferably
One strip injection region is set, multiple strip injection regions also can be set, alternatively, as shown in Figure 3B, along two linear edges
Several blocky injection regions of interval setting.
It is noted that although respectively illustrating third injection region in Fig. 3 A and Fig. 3 B is that strip injection region and third are infused
The case where entering area for blocky injection region, but third injection region can also be set to not only including strip injection region but also including bulk
Injection region.
In one example, the back side of the device substrate 300 is additionally provided with buffer area 304, the top of the buffer area 304
Portion connects with the bottom surface of first injection region 301, the second injection region 302, third injection region 303 being located in device substrate
Touching, the bottom of the buffer area 304 are located in the device substrate 300, for example, in the front setting of the device substrate 300
When having drift region, the setting buffers are in first injection region 301, the second injection region 302, third injection region 303 and drift
It moves between area, wherein the buffer area 304 has conduction type identical with drift region or device substrate, for example, described slow
The conduction type for rushing area 304 is N-type, the especially buffer area of N-type heavy doping.
Illustratively, first injection region 301, the second injection region 302, third injection region 303 may be used as IGBT device
The collecting zone of part.
Further, it is also set up on the surface of first injection region 301, the second injection region 302, third injection region 303
There is collector layer, collector layer is metal layer, can be, for example, the metals such as aluminium, gold.
So far complete the introduction to semiconductor devices of the invention, for complete device further include other structures and
Component does not do repeat one by one herein.
In conclusion semiconductor devices of the invention cellular region it is opposite the device substrate back side setting doping concentration it is high
Second injection region (such as the injection region P+) is mixed with far from the opposite device substrate back side setting of the terminal protection ring region of cellular region
Outside (such as four angles of cellular region at the first low injection region of miscellaneous concentration (such as the injection region P-), the especially angle of cellular region
Outside) the first injection region of setting, gain can be reduced, weaken big injection effect, increase reversed shutdown safety operation area, and
It is injected with close to the moderate third of the opposite device substrate back side setting doping concentration in the terminal protection ring region part of cellular region
Area (such as the injection region P+), the setting can be balanced since back side graphic designs bring conduction voltage drop Vcesat deteriorates problem,
In addition, semiconductor devices of the invention can also weaken corresponding internal hole below end ring and carry in device turn off process
The convergence of son is flowed, and then weakens the hole current being gathered together, the latch-up of triggering edge cellular is avoided and leads to device
The problem of failure, occurs, and therefore, semiconductor devices of the invention has high Performance And Reliability.
Embodiment two
The present invention also provides a kind of aforementioned manufacturing methods for implementing the semiconductor devices in one, as shown in figure 5, the method
It mainly comprises the steps that
Step S1, provides device substrate, and the device substrate includes that cellular region and the terminal around the cellular region are protected
Retaining ring area；
Step S2, formed the first injection region, wherein first injection region be formed in the back side of the device substrate and with
The terminal protection ring region is opposite；
Step S3 forms the second injection region and third injection region, wherein second injection region is formed in the back side simultaneously
Opposite with the cellular region, the third injection region is formed in first injection region and close to second injection region, institute
State the second injection region, the doping concentration of the third injection region is all larger than the doping concentration of first injection region.
In the following, with specific reference to 3A to Fig. 3 C, the manufacturing method of Fig. 4 A to Fig. 4 C and Fig. 5 to semiconductor devices of the invention
It is described in detail.In one example, semiconductor devices of the invention can be IGBT device, or other semiconductors
Device in the present embodiment, mainly by taking IGBT device as an example, is explained and illustrated method of the invention.
Firstly, executing step 1, device substrate is provided, the device substrate includes cellular region and the circular cellular region
Terminal protection ring region.
Specifically, as shown in Figure 4 A, device substrate 300 is provided, the device substrate 300 is including cellular region and around institute
State the terminal protection ring region of cellular region.
To put it more simply, only showing the device substrate 300 in Fig. 4 A to Fig. 4 C with a blank picture frame, but can think
To being already formed with various structures in the front of device substrate before the back side to device substrate carries out making technology
At the component structure of cellular region and the component structure etc. of composition terminal protection ring region, those structures can be those skilled in the art
Any IGBT structure, is also possible to the same or similar structure as described in previous embodiment one known to member, in order to
It avoids repeating, does not do repeat one by one herein.
In order to make the smaller of device substrate, also need to carry out reduction processing to the back side of device substrate 300.
In this step, the thining method can select method commonly used in the art, for example, can using mechanical lapping,
Chemically-mechanicapolish polish the methods of (CMP), chemical attack, plasma etching.Optionally, the thickness model of device substrate 300 after being thinned
Enclose is 50 μm~200 μm.
Illustratively, operated for the ease of the back side to device substrate, carry out it is described be thinned before, further include with
Lower step:
Firstly, the front in the device substrate forms bonded layer (not shown).
The bonded layer is bonding glue, and it is high-molecular organic material or can ultraviolet denaturation which, which can be, but not limited to,
Organic material, and the bonding glue has viscosity.
Bonding glue-line is formed in the front of device substrate by the method that such as coating can be used.
Then, support substrate is provided, the bonded layer and the support substrate are engaged.
The support substrate can be semiconductor substrate such as silicon substrate, glass or ceramic material.For being served as a contrast to device
Bottom plays a supportive role, and operates convenient for the back side to device substrate.
Illustratively, it is operated for the ease of the back side to device substrate, it can also be by the front of device substrate and branch
Support substrate engages, and support substrate is for playing a supportive role to device substrate.
Then, step 2 is executed, forms the first injection region, wherein first injection region is formed in the device substrate
The back side and opposite with the terminal protection ring region.
In one example, before forming the first injection region, it is also an option that the back side to the device substrate of property
Ion implanting is carried out, to form buffer layer (not shown) in the device substrate.Optionally, slow for N-type in the buffer layer
When rushing layer, the injection ion of ion implanting is n-type doping ion, including but not limited at least one of phosphorus or arsenic.
The buffer layer can be realized by way of carrying out ion implanting to substrate back, pass through the energy control of control injection
The depth of ion implanting processed.Optionally, the Implantation Energy range of first ion implanting is 2Mev~3Mev, implantation dosage model
It encloses for 1E12~5E13atom/cm2, which is only used as example.
Further, as shown in Figure 4 A, the method for forming first injection region includes: to the device substrate 300
The back side carries out the first ion implanting, to form the first injection region 301 in the device substrate 300.Wherein, the step
In, light shield (mask) is not needed, ion implanting, therefore the first injection region being initially formed are carried out to the back side of entire device substrate
Also the back side of entire device substrate 300 can be covered.
In one example, first injection region 301 and the buffer area have opposite conduction type, for example, institute
Stating buffer area is N-type, then first injection region 301 is p-type, and especially, first injection region 301 is lightly doped for p-type.
Illustratively, first injection region 301 is formed by the method for ion implanting, in first injection region 301
When for p-type, the type for injecting ion is p-type impurity, such as boron.
Illustratively, the depth that ion implanting is controlled by the energy of control injection, for example, first ion implanting
Implantation Energy range be 20Kev~40Kev, implantation dosage may range from 1E11~5E12atom/cm2, those numerical value models
It encloses only as an example, not being construed as limiting the invention.
Injection region can be lightly doped for p-type in the first injection region 301 formed by above-mentioned ion implanting.
Then, step 3 is executed, forms the second injection region and third injection region, wherein second injection region is formed in
The back side of the device substrate is simultaneously opposite with the cellular region, and the third injection region is formed in first injection region and leans on
Nearly second injection region, second injection region, the third injection region doping concentration be all larger than first injection region
Doping concentration.
Specifically, as shown in figs. 4 b and 4 c, the method for forming second injection region and third injection region further include with
Lower step:
Firstly, as shown in Figure 4 B, patterned mask layer 305 is formed on the back side of the device substrate 300, it is described to cover
Film layer 305 exposes the predetermined region for forming second injection region and the third injection region of the device substrate 300.
Specifically, which may include any one of several mask materials, including but not limited to: hard mask
Material and photoresist mask material.In the present embodiment, mask layer 305 includes photoresist mask material.
Suitable light shield can be designed according to the graphics shape of the second injection region and third injection region in previous embodiment one,
Development etc. is exposed to the photoresist mask material for being coated in 300 back side of device substrate using the light shield, is had to form definition
The mask layer of the pattern of second injection region and third injection region.
Wherein, pattern form position in relation to predetermined the second injection region formed and third injection region etc. is in example 1
It is described in detail, in order to avoid repeating, this will not be repeated here.
Then, continue as shown in Figure 4 B, to be exposure mask with the mask layer 305, carry out the second ion implanting, described in being formed
Second injection region 302 and the third injection region 303.
Specifically, second injection region 302 and the third injection region 303 and first injection region 301 have
Identical conduction type, such as be p-type.And the doping concentration of the second injection region 302 and third injection region 303 is all larger than first
Injection region 301, therefore the adjusting to doping concentration can be realized by control implantation dosage.
For example, the injection ion of the second ion implanting can be p-type Doped ions, for example, may include boron.
Optionally, the implantation dosage of the second ion implanting may range from 1E13~5E13atom/cm2, those numerical value models
It encloses only as an example, not being construed as limiting the invention.
Illustratively, second injection region 302 and the third injection region 303 of formation can be the heavily doped pragma of p-type
Enter area.
Further, the second injection region and third injection region and the first injection region junction depth having the same, can be by making
First ion implanting and the second ion implanting have the Implantation Energy being substantially the same to realize.
Then, as shown in Figure 4 C, the mask layer is removed.Suitable side can be selected according to the material of specific mask layer
Method removes the mask layer, and the mask layer of the method removal Other substrate materials of ashing can be used for example.
Further, after removing mask layer, further include the steps that annealing, to activate first injection region 301, the
The Doped ions of two injection regions 302, third injection region 303, and defect repair is carried out, such as repair because caused by ion implanting
The lattice damage of device substrate.
Illustratively, any annealing method well known to those skilled in the art can be used in annealing, including but not
It is limited to rapid thermal annealing, furnace anneal, peak value annealing, laser annealing etc..In the present embodiment, preferably the annealing uses laser
Annealing, laser annealing have the advantages that local heating, can only anneal to the region of predetermined annealing, without to the area
Cause thermal damage in other regions other than domain.
Finally, the back side of device substrate form it is aforementioned implement one in the first injection region 301, the second injection region 302,
Third injection region 303.
In order to avoid repeating, no longer the first injection region 301, the second injection region 302, third injection region 303 are retouched herein
It states, concrete details feature can refer to the content in previous embodiment one.
It then, in one example, can also be in the first injection region 301, second injection region 302, third injection region 303
Forming metal layer on surface, and made annealing treatment, to form metal silicide, metal layer for example may include Ti metal.
Illustratively, it can also be formed on the surface of the first injection region 301, the second injection region 302, third injection region 303
Collector (not shown).Wherein the material of collector includes metal, and the metal includes but is not limited to aluminium, copper, titanium or chromium etc..
Then, in one example, solution bonding technology is carried out, so that the device substrate and support substrate separation.
Specifically, the method that any solution bonding well known to those skilled in the art can be used, discrete device substrate and described
Support substrate, for example, high-temperature heating makes the bonded layer denaturation for being for example bonded glue lose viscosity, then device substrate and support lining
Bottom, then the bonded layer for losing viscosity is removed.
So far the introduction for completing the committed step of the manufacturing method to semiconductor devices of the invention, for complete device
The step of part production also needs other, does not do repeat one by one herein.
Since the manufacturing method of the present invention has prepared the semiconductor devices in previous embodiment one, the present invention
Manufacturing method have the advantages that with it is aforementioned implement one in it is identical.
Embodiment three
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment one, the semiconductor device
Part is prepared according to two the method for embodiment.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, it can also be any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to having used above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 6 shows the example of mobile phone handsets.Mobile phone handsets 400, which are equipped with, to be included in shell 401
Display portion 402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
Wherein the mobile phone handsets include semiconductor devices described in embodiment one, and the semiconductor devices includes:
Device substrate, including cellular region and around the terminal protection ring region of the cellular region；
The back side of the device substrate and opposite with the terminal protection ring region is arranged in first injection region；
Second injection region, setting is at the back side and opposite with the cellular region, and first injection region is around described the
Two injection regions；
Third injection region is arranged in first injection region and close to second injection region, wherein second note
Enter area, the doping concentration of the third injection region is all larger than the doping concentration of first injection region.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (22)
1. a kind of semiconductor devices characterized by comprising
Device substrate, including cellular region and around the terminal protection ring region of the cellular region；
The back side of the device substrate and opposite with the terminal protection ring region is arranged in first injection region；
Second injection region, setting is in the back side and, first injection region circular second note opposite with the cellular region
Enter area；
Third injection region is arranged in first injection region and close to second injection region, wherein second injection
Area, the third injection region doping concentration be all larger than the doping concentration of first injection region.
2. semiconductor devices as described in claim 1, which is characterized in that first injection region is in polygonal annular, and described the
Three injection regions are located in the region other than at least one angle of first injection region.
3. semiconductor devices as claimed in claim 2, which is characterized in that first injection region includes four angles, and described the
Three injection regions are located in the region other than four angles of first injection region.
4. semiconductor devices as described in claim 1, which is characterized in that the third injection region includes several along described first
The strip injection region of the spaced radial setting of injection region, wherein the extending direction and the strip of the strip injection region inject
The extending direction at the edge of close second injection region in area is parallel；And/or
The third injection region includes several blocky injection regions, part edge of the bulk injection region along second injection region
It is alternatively arranged.
5. semiconductor devices as described in claim 1, which is characterized in that second injection region and the third injection region
Doping concentration is identical.
6. semiconductor devices as described in claim 1, which is characterized in that second injection region is lacked in one of corner
Polygon, the third injection region is also located on the corner of polygon missing；
The device substrate further includes gate pads area, and the gate pads area is located at the injection of the third on the corner of the missing
The outside in area.
7. semiconductor devices as described in claim 1, which is characterized in that
First injection region, second injection region and the third injection region junction depth having the same, and/or, described
One injection region, second injection region and the third injection region conduction type having the same.
8. semiconductor devices as described in claim 1, which is characterized in that second injection region and the third injection region are
The injection region of heavy doping, first injection region are the injection region being lightly doped.
9. semiconductor devices as described in claim 1, which is characterized in that the device substrate further includes transition region, the mistake
Area is crossed around the cellular region and between the terminal protection ring region and the cellular region, wherein the first injection region also with
The transition region is opposite, and the third injection region is opposite with the transition region.
10. semiconductor devices as described in claim 1, which is characterized in that the semiconductor devices is IGBT device.
11. a kind of manufacturing method of semiconductor devices characterized by comprising
Device substrate is provided, the device substrate includes cellular region and the terminal protection ring region around the cellular region；
Form the first injection region, wherein first injection region is formed in the back side of the device substrate and protects with the terminal
Retaining ring area is opposite；
Form the second injection region and third injection region, wherein second injection region be formed in the back side and with the cellular
Area is opposite, and the third injection region is formed in first injection region and close to second injection region, second injection
Area, the third injection region doping concentration be all larger than the doping concentration of first injection region.
12. manufacturing method as claimed in claim 11, which is characterized in that formed first injection region, the second injection region and
The method of the third injection region includes:
First ion implanting is carried out to the back side of the device substrate, to form the first injection in the device substrate
Area；
Patterned mask layer is formed on the back side of the device substrate, the mask layer exposes the device substrate preboarding
At the region of second injection region and the third injection region；
Using the mask layer as exposure mask, the second ion implanting is carried out, to form second injection region and the third injection region；
Remove the mask layer.
13. manufacturing method as claimed in claim 12, which is characterized in that further include carrying out after removing the mask layer
Annealing, to activate the step of the Doped ions in first injection region, second injection region and the third injection region
Suddenly.
14. manufacturing method as claimed in claim 12, which is characterized in that first injection region is in polygonal annular, and described the
Three injection regions are located in the region other than at least one angle of first injection region.
15. manufacturing method as claimed in claim 14, which is characterized in that first injection region includes four angles, and described the
Three injection regions are located in the region other than four angles of first injection region.
16. manufacturing method as claimed in claim 12, which is characterized in that the third injection region includes several along described first
The strip injection region of the spaced radial setting of injection region, wherein the extending direction and the strip of the strip injection region inject
The extending direction at the edge of close second injection region in area is parallel；And/or
The third injection region includes several blocky injection regions, part edge of the bulk injection region along second injection region
It is alternatively arranged.
17. manufacturing method as claimed in claim 11, which is characterized in that second injection region is lacked in one of corner
Polygon, the third injection region is also located on the corner of polygon missing；
The semiconductor substrate further includes gate pads area, and the gate pads area is located at the note of the third on the corner of the missing
Enter the outside in area.
18. manufacturing method as claimed in claim 11, which is characterized in that
First injection region, second injection region and the third injection region junction depth having the same, and/or, described
One injection region, second injection region and the third injection region conduction type having the same.
19. manufacturing method as claimed in claim 11, which is characterized in that second injection region and the third injection region are
The injection region of heavy doping, first injection region are the injection region being lightly doped.
20. manufacturing method as claimed in claim 11, which is characterized in that the device substrate further includes transition region, the mistake
Area is crossed around the cellular region and between the terminal protection ring region and the cellular region, wherein the first injection region also with
The transition region is opposite, and the third injection region is opposite with the transition region.
21. manufacturing method as claimed in claim 11, which is characterized in that the semiconductor devices is IGBT device.
22. a kind of electronic device, which is characterized in that the electronic device includes partly leading as described in one of claims 1 to 10
Body device.
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