WO2023241070A1

WO2023241070A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2023241070A1
Application number: PCT/CN2023/074941
Authority: WO
Inventors: 何乃龙; 张森; 赵景川
Original assignee: 无锡华润上华科技有限公司
Priority date: 2022-06-17
Filing date: 2023-02-08
Publication date: 2023-12-21
Also published as: CN117293131A

Abstract

The present application relates to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a first metal layer, which is arranged on a substrate; a dielectric layer, which is arranged on the side of the first metal layer that faces away from the substrate; a buffer layer, which is arranged on the side of the dielectric layer that is away from the first metal layer; a second metal layer, which is arranged on the side of the buffer layer that is away from the dielectric layer; and a metal ring, which is arranged on the side of the buffer layer that is away from the dielectric layer, and surrounds an outer side of the second metal layer. The potential of the second metal layer is higher than the potential of the first metal layer.

Description

Semiconductor device and preparation method thereof

Cross-references to related applications

This application claims priority to the Chinese patent application filed with the China Patent Office on June 17, 2022, with the application number 2022106872573 and the invention title "Semiconductor Device and Preparation Method thereof", the entire content of which is incorporated into this application by reference.

Technical field

The present application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a preparation method thereof.

technical background

Electrical isolation (Galvanicisolation) refers to a way to prevent current from flowing directly from one area to another in a circuit, that is, without establishing a path for direct current flow between two areas. Initially, isolators mostly used optocoupler isolators. However, with the continuous advancement of CMOS technology, digital isolation technology began to make great strides and was gradually recognized by the market. Its high reliability and high speed far exceed that of traditional optocoupler technology. limit.

Currently, commonly used CMOS high-voltage isolation capacitors are prepared using a surface dielectric stacking process, which involves first depositing a layer of metal on the surface of the silicon wafer as the lower plate of the high-voltage isolation capacitor, and then growing a thick layer of silicon dioxide on the metal lower plate. Or a composite layer of silicon dioxide and silicon nitride, used as the dielectric layer of the high-voltage isolation capacitor, and finally a layer of metal is deposited on the dielectric layer as the upper plate of the high-voltage isolation capacitor.

However, in traditional high-voltage isolation capacitors, the dielectric layer at the edge of the upper plate is easily broken down in advance, which reduces the service life of the high-voltage isolation capacitor.

Contents of the invention

According to various exemplary embodiments of the present application, a semiconductor device and a manufacturing method thereof are provided.

In a first aspect, this application provides a semiconductor device, including:

base;

A first metal layer, disposed on the substrate;

A dielectric layer, disposed on the side of the first metal layer facing away from the substrate;

A buffer layer, disposed on the side of the dielectric layer away from the first metal layer;

A second metal layer is disposed on a side of the buffer layer away from the dielectric layer; the potential of the second metal layer is higher than the potential of the first metal layer; and

A metal ring is disposed on a side of the buffer layer away from the dielectric layer, and the metal ring is disposed around the outside of the second metal layer.

In the above-mentioned semiconductor device, on the one hand, by providing a metal ring, the field plate effect of the metal ring can optimize the electric field distribution at the edge of the second metal layer, thereby reducing the electric field intensity at the edge of the second metal layer and improving the withstand voltage of the semiconductor device. , to prevent the dielectric layer from being broken down in advance; on the other hand, by arranging a buffer layer on the dielectric layer, the buffer layer can protect the dielectric layer and reduce the damage to the dielectric layer caused by processes such as plasma bombardment or etching. It avoids defects in the dielectric layer, thereby improving the withstand voltage of the semiconductor device, preventing the dielectric layer from being broken down in advance, and increasing the service life of the semiconductor device.

In one embodiment, the buffer layer includes an electrically isolated first buffer layer and a second buffer layer; the second metal layer is disposed on a side of the first buffer layer away from the dielectric layer, so The metal ring is disposed on a side of the second buffer layer away from the dielectric layer.

In one embodiment, along a direction perpendicular to the surface of the substrate, the cross-sectional width of the first buffer layer gradually increases from a side of the first buffer layer close to the dielectric layer to an opposite side thereof. large; and/or the cross-sectional width of the second buffer layer gradually increases from the side of the second buffer layer close to the dielectric layer to the opposite side.

In one embodiment, the semiconductor device includes a plurality of metal rings, and the plurality of metal rings surround the second metal layer and are spaced apart from each other.

In one embodiment, the buffer layer includes a plurality of second buffer layers; each second buffer layer is correspondingly disposed on a side of each metal ring close to the dielectric layer; and two adjacent ones The two second buffer layers are electrically isolated from each other.

In one embodiment, a trench is provided between the first buffer layer and the second buffer layer.

In one embodiment, the dielectric constant of the buffer layer is greater than the dielectric constant of the dielectric layer and less than the dielectric constant of the second metal layer.

In one embodiment, the thickness of the buffer layer is between about 200 nm and 500 nm.

In one embodiment, the semiconductor device further includes a passivation layer, and the passivation layer is disposed on a side of the metal ring away from the dielectric layer. The passivation layer covers the exposed surface of the dielectric layer, the exposed surface of the buffer layer and part of the surface of the second metal layer.

In one embodiment, the semiconductor device further includes an isolation structure, and the isolation structure is disposed on the substrate. The capacitor formed by the first metal layer, the dielectric layer and the second metal layer is disposed between adjacent isolation structures.

In a second aspect, this application also provides a method for preparing a semiconductor device, including:

forming a first metal layer on the substrate;

forming a dielectric layer on the first metal layer;

forming a buffer layer on the dielectric layer; and

A second metal layer and a metal ring are formed on the buffer layer; wherein the metal ring is arranged around the outside of the second metal layer.

The above-mentioned preparation method of a semiconductor device, on the one hand, by arranging a metal ring, the field plate effect of the metal ring can optimize the electric field distribution at the edge of the second metal layer, thereby reducing the electric field intensity at the edge of the second metal layer and improving the efficiency of the semiconductor device. The withstand voltage prevents the dielectric layer from being broken down in advance; on the other hand, by setting a buffer layer on the dielectric layer, the buffer layer can protect the dielectric layer and reduce the impact of processes such as plasma bombardment or etching on the dielectric layer. damage to the dielectric layer to avoid defects in the dielectric layer, thereby improving the withstand voltage of the semiconductor device, preventing the dielectric layer from being broken down in advance, and extending the service life of the semiconductor device.

In one embodiment, the step of forming a second metal layer and a metal ring on the buffer layer includes:

forming a metal material layer on the buffer layer; and

The metal material layer is etched to form the second metal layer and the metal ring.

In one embodiment, the step of forming a second metal layer and a metal ring on the buffer layer Afterwards, the method further includes:

Etching the exposed portion of the surface of the buffer layer to form a first buffer layer and a second buffer layer that are electrically isolated from each other; and

A passivation layer is formed on the metal ring; wherein the passivation layer covers the exposed surface of the dielectric layer, the exposed surface of the buffer layer and part of the surface of the second metal layer.

Description of the drawings

In order to more clearly explain the technical solutions in the embodiments of the present application or the traditional technology, the drawings needed to be used in the description of the embodiments or the traditional technology will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of explaining the embodiments or the technical solutions of the traditional technology. For some embodiments of the application, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

FIG. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application.

FIG. 2 is a perspective view of a partial structure of another semiconductor device provided in an embodiment of the present application.

FIG. 3 is a top view of a partial structure of yet another semiconductor device provided in an embodiment of the present application.

FIG. 4 is a schematic diagram of electric field distribution simulation of a semiconductor device without a metal ring provided in an embodiment of the present application.

FIG. 5 is a schematic diagram of electric field distribution simulation of a semiconductor device provided with a metal ring according to an embodiment of the present application.

FIG. 6 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

FIG. 7 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application after the first metal layer and dielectric layer are formed.

FIG. 8 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application after the buffer layer is formed.

FIG. 9 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application after the metal material layer is formed.

FIG. 10 is a schematic structural diagram of the semiconductor device provided in an embodiment of the present application after the second metal layer and metal ring are formed.

FIG. 11 is a schematic structural diagram of the buffer layer of a semiconductor device provided in an embodiment of the present application after etching.

FIG. 12 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application after the passivation layer is formed.

Explanation of reference symbols:
100-semiconductor device; 110-substrate; 120-first metal layer; 130-dielectric layer; 140-buffer layer;
141-first buffer layer; 142-second buffer layer; 143-trench; 150-second metal layer; 151-metal material layer; 160-metal ring; 170-passivation layer; 180-isolation structure; 190- interconnect structure.

Detailed ways

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the application are given in the accompanying drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing specific embodiments only and is not intended to limit the application.

It will be understood that when an element or layer is referred to as being "on,""adjacent,""connectedto" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on,""directlyadjacent,""directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer. It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. point.

Spatial relational terms such as "under", "under", "under", "under", "on", "above", etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a," "an," and "the" may include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "comprising" or "having" and the like specify the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not exclude the presence or addition of one or more Possibility of other features, integers, steps, operations, components, parts or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations in the shapes shown are contemplated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein but include deviations in shapes due, for example, to manufacturing techniques. For example, an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

It should be noted that the high electric field region at the edge of the plate forming the high-voltage capacitor limits the breakdown voltage of the high-voltage capacitor. Take the upper plate of a high-voltage capacitor connected to a high potential as an example to illustrate. On the one hand, the electric field intensity between the upper and lower plates is relatively uniform, while the electric field intensity is stronger at the edge of the upper plate. On the other hand, due to the influence of the preparation process of the high-voltage capacitor, the gap between the upper plate and the lower plate There will be defects in the dielectric layer between them, especially near the edge of the upper plate. The superposition of the above two factors causes the dielectric layer at the edge of the upper plate to be easily broken down in advance, reducing the service life of the high-voltage isolation capacitor.

In view of the problem that the dielectric layer at the edge of the upper plate in traditional high-voltage isolation capacitors is prone to premature breakdown, embodiments of the present application provide a semiconductor device and a preparation method thereof.

Embodiments of the present application provide a semiconductor device, which may be a high-voltage isolation capacitor. The semiconductor device 100 includes a substrate 110. The material of the substrate 110 may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon-on-insulator (SOI) or low temperature polysilicon (Low Temperature Poly-Silicon, (referred to as LTPS), etc., or other materials known to those skilled in the art. The base 110 can provide a supporting foundation for structures on the base 110 .

As shown in FIG. 1 , the semiconductor device 100 further includes a first metal layer 120 disposed on a substrate 110 , a dielectric layer 130 disposed on a side of the first metal layer 120 away from the substrate 110 , and a dielectric layer 130 disposed on a side away from the first metal layer 120 . The buffer layer 140 on one side of the metal layer 120 , the second metal layer 150 disposed on the side of the buffer layer 140 away from the dielectric layer 130 , and the metal ring 160 disposed on the side of the buffer layer 140 away from the dielectric layer 130 .

The dielectric layer 130 includes an insulating medium. For example, the material of the dielectric layer 130 may be silicon dioxide, silicon nitride, silicon oxynitride, or the like. The first metal layer 120 and the second metal layer 150 are both used for electrical connection with external circuits. The potential of the second metal layer 150 is higher than the potential of the first metal layer 120 . The metal ring 160 is disposed around the outside of the second metal layer 150 .

The above-mentioned semiconductor device 100 is provided with a metal ring 160. The field plate effect of the metal ring 160 can be used to optimize the electric field distribution at the edge of the second metal layer 150, thereby reducing the electric field intensity at the edge of the second metal layer 150. It can be understood that a capacitor is formed between the metal ring 160 and the second metal layer 150, and the capacitor will form a field plate effect. The electric field of the capacitor will evenly disperse the high-density electric field at the edge of the second metal layer 150, thereby The electric field peak at the edge of the second metal layer 150 is suppressed, the withstand voltage of the semiconductor device 100 is improved, the dielectric layer 130 is prevented from being broken down in advance, and the service life of the semiconductor device 100 is improved. It can also be understood that if the second metal layer 150 is connected to a high potential, part of the charges originally flowing between the second metal layer 150 and the dielectric layer 130 will be transferred between the second metal layer 150 and the gold layer. The lateral flow between the metal rings 160 changes the electric field distribution at the edge of the second metal layer 150 and reduces the electric field intensity at the edge of the second metal layer 150 , thereby increasing the breakdown voltage of the semiconductor device 100 .

In addition, due to the influence of the preparation process, processes such as plasma bombardment or etching can easily cause damage to the surface of the dielectric layer 130 , resulting in defects on the surface of the dielectric layer 130 . A buffer layer 140 is provided on the dielectric layer 130. The buffer layer 140 can protect the dielectric layer 130, reduce damage to the dielectric layer 130 by processes such as plasma bombardment or etching, and avoid defects in the dielectric layer 130, thereby improving the semiconductor quality. The withstand voltage of the device 100 prevents the dielectric layer 130 from premature breakdown, thereby increasing the service life of the semiconductor device 100 .

In one embodiment, the dielectric constant of the buffer layer 140 is greater than the dielectric constant of the dielectric layer 130 and less than the dielectric constant of the second metal layer 150 .

It should be noted that during the etching process, more charged ions will be generated when plasma bombardment is used. If the dielectric constant of the buffer layer 140 is larger, the absorbing ability of the buffer layer 140 for charged ions is stronger; conversely, if the dielectric constant of the buffer layer 140 is smaller, the absorbing ability of the buffer layer 140 for charged ions is weaker. Therefore, by making the dielectric constant of the buffer layer 140 greater than the dielectric constant of the dielectric layer 130, the ability of the buffer layer 140 to absorb charged ions can be greater than the ability of the dielectric layer 130 to absorb charged ions. In this way, when plasma bombardment is used, the charged ions heading toward the dielectric layer 130 are absorbed by the buffer layer 140 , thereby reducing damage to the dielectric layer 130 caused by the plasma bombardment. Making the dielectric constant of the buffer layer 140 smaller than the dielectric constant of the second metal layer 150 can, on the one hand, prevent the buffer layer 140 from having too strong conductivity and affecting the working performance of the semiconductor device 100; on the other hand, the buffer layer 140 can absorb charged electricity. The ability of the ions is less than the ability of the second metal layer 150 to absorb the charged ions. The second metal layer 150 is a metal material layer before being formed. When plasma bombardment is used to etch the metal material layer, most of the charged ions can be absorbed by the metal material layer, so that the metal material layer is etched to form the second metal layer 150 .

In one embodiment, the buffer layer 140 includes a first buffer layer 141 and a second buffer layer 142 that are electrically isolated. The second metal layer 150 is disposed on the side of the first buffer layer 141 away from the dielectric layer 130 , and the metal ring 160 is disposed on the side of the second buffer layer 142 away from the dielectric layer 130 .

Since both the second metal layer 150 and the metal ring 160 are in direct contact with the buffer layer 140, correspondingly Disposing the first buffer layer 141 and the second buffer layer 142 and electrically isolating the first buffer layer 141 and the second buffer layer 142 can prevent the second metal layer 150 and the metal ring 160 from being electrically connected through the buffer layer 140, preventing The metal ring 160 affects the operating performance of the semiconductor device 100 .

In the embodiment of the present application, as shown in FIG. 11 , a trench 143 is provided between the first buffer layer 141 and the second buffer layer 142 so that the first buffer layer 141 and the second buffer layer 142 are not in direct contact. The purpose of electrical isolation.

In one embodiment, along the direction perpendicular to the surface of the substrate 110 , the cross-sectional width of the first buffer layer 141 gradually increases from the side of the first buffer layer 141 close to the dielectric layer 130 to the opposite side. The width refers to the orthographic projection of the first buffer layer 141 on the substrate 110 and the dimension perpendicular to the extending direction of the first buffer layer 141 . The cross-sectional width of the second buffer layer 142 gradually increases from the side of the second buffer layer 142 close to the dielectric layer 130 to the opposite side. The cross-sectional width refers to the orthogonal projection of the second buffer layer 142 on the substrate 110 perpendicular to The size in the extension direction of the second buffer layer 142 . As shown in FIG. 3 , W1 represents the cross-sectional width of the first buffer layer 141 , and W2 represents the cross-sectional width of the second buffer layer 142 .

Since there is a trench 143 between the first buffer layer 141 and the second buffer layer 142, the above arrangement can make the area of the dielectric layer 130 covered by the first buffer layer 141 and the second buffer layer 142 large enough, reducing the impact of the etching process on the dielectric. The degree of damage to layer 130. It can also be understood that this can make the bottom area of the trench 143 smaller and the exposed area of the dielectric layer 130 smaller.

As shown in FIG. 1 , along the direction perpendicular to the paper surface, the cross-sectional shapes of the first buffer layer 141 and the second buffer layer 142 may be trapezoidal. It can be understood that the cross-sectional shapes of the first buffer layer 141 and the second buffer layer 142 can also be other irregular shapes, and the embodiments of the present application do not limit the cross-sectional shapes of the first buffer layer 141 and the second buffer layer 142 .

In one embodiment, as shown in FIG. 1 , the semiconductor device 100 includes a plurality of metal rings 160 that surround the second metal layer 150 and are spaced apart from each other.

This arrangement is equivalent to "covering" multiple metal rings 160 on the outside of the second metal layer 150 , so that the multiple metal rings 160 can optimize the electric field in a wider range and reduce the electric field outside the second metal layer 150 . The electric field intensity in a wide range improves the withstand voltage of the semiconductor device 100 and avoids the dielectric layer 130 It is broken down in advance and the service life of the semiconductor device 100 is improved.

In one embodiment, as shown in FIG. 1 , the buffer layer 140 includes a plurality of second buffer layers 142 , and each second buffer layer 142 is disposed between each metal ring 160 and the dielectric layer 130 in one-to-one correspondence. Two adjacent second buffer layers 142 are electrically isolated.

Similarly, as shown in FIG. 11 , a trench 143 is provided between two adjacent second buffer layers 142 so that the two adjacent second buffer layers 142 are not in direct contact to achieve electrical isolation.

In one embodiment, the thickness of the buffer layer 140 is between approximately 200 nm and 500 nm. The thickness of the buffer layer 140 refers to the distance from the upper surface of the buffer layer 140 to the lower surface of the buffer layer 140 . The thickness of the buffer layer 140 is within the above range. On the one hand, it can ensure that the buffer layer 140 better protects the dielectric layer 130 and reduces damage to the dielectric layer 130; on the other hand, it can minimize the thickness of the semiconductor device 100.

In one embodiment, as shown in FIG. 1 , the semiconductor device 100 further includes a passivation layer 170 , and the passivation layer 170 is disposed on a side of the metal ring 160 away from the dielectric layer 130 . The passivation layer 170 covers the exposed surface of the dielectric layer 130 , the exposed surface of the buffer layer 140 and part of the surface of the second metal layer 150 . The passivation layer 170 can play the role of protection and insulation, on the one hand to prevent the metal ring 160 from being electrically connected to external devices, and on the other hand to prevent external force from damaging the metal ring 160 . The passivation layer 170 may be made of silicon oxide, silicon nitride, or the like.

Referring to FIGS. 2 and 3 , it can be understood that the number of metal rings 160 may be only one.

It should be noted that the shapes of the first metal layer 120 and the second metal layer 150 are the same, and the shapes of the first metal layer 120 and the second metal layer 150 may be rectangular, elliptical, circular, etc. In addition, the sizes of the first metal layer 120 and the second metal layer 150 may be the same or different.

Please refer to Figures 4 and 5. The inventor simulated the electric field distribution of a semiconductor device without a metal ring and a semiconductor device with a metal ring 160 respectively. Figure 4 shows a semiconductor device without a metal ring. 5 is a schematic diagram of the electric field distribution simulation of a semiconductor device provided with a metal ring 160 . By comparison, it can be seen that the electric field intensity at the edge of the second metal layer 150 in FIG. 5 is smaller than the electric field intensity at the edge of the second metal layer 150 in FIG. 4 . also, Simulation data shows that the breakdown voltage of the semiconductor device in Figure 4 is 60V, and the breakdown voltage of the semiconductor device in Figure 5 is 66V. It can be seen that providing the metal ring 160 can optimize the electric field distribution at the edge of the second metal layer 150 and improve the withstand voltage of the semiconductor device.

In this embodiment of the present application, an isolation structure 180 may also be provided on the substrate 110 , and a capacitor formed by the first metal layer 120 , the dielectric layer 130 and the second metal layer 140 may be provided between adjacent isolation structures 180 . In addition, the substrate 110 may also be provided with an interconnection structure 190 for energizing the electronic components on the substrate 110 .

Embodiments of the present application also provide a method for manufacturing a semiconductor device. As shown in Figure 6, the method for manufacturing a semiconductor device includes:

S100: Form a first metal layer on the substrate. For example, a pattern of the first metal layer 120 may be formed through a mask, and then the first metal layer 120 may be deposited.

It can be understood that the material of the substrate 110 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI for short) or low temperature polysilicon (Low Temperature Poly-Silicon for short, LTPS for short). ), etc., or other materials known to those skilled in the art, the substrate 110 can provide a supporting foundation for the structure on the substrate 110 . The material of the first metal layer 120 may be copper, aluminum, or any metal or metal alloy suitable for semiconductor processing.

S200: Form a dielectric layer on the first metal layer. For example, a pattern of the dielectric layer 130 may be formed through a mask, and then the dielectric layer 130 may be deposited. The material of the dielectric layer 130 may be silicon dioxide. The structure after the first metal layer 120 and the dielectric layer 130 are formed is shown in FIG. 7 .

S300: Form a buffer layer on the dielectric layer. For example, a pattern of the buffer layer 140 may be formed through a mask, and then the buffer layer 140 may be deposited. The material of the buffer layer 140 may be silicon nitride, silicon oxynitride, or the like. The structure after the buffer layer 140 is formed is shown in FIG. 8 .

S400: Form a second metal layer and a metal ring on the buffer layer; wherein, the metal ring 160 is arranged around the outside of the second metal layer 150. The material of the metal ring 160 may be the same as the material of the first metal layer 120 .

The above-mentioned preparation method of the semiconductor device, on the one hand, by arranging the metal ring 160, the field plate effect of the metal ring 160 can optimize the electric field distribution at the edge of the second metal layer 150, thereby reducing the The electric field intensity at the edge of the metal layer 150 improves the withstand voltage of the semiconductor device 100 and prevents the dielectric layer 130 from premature breakdown; on the other hand, by disposing the buffer layer 140 on the dielectric layer 130, the buffer layer 140 can 130 plays a protective role, reducing the damage to the dielectric layer 130 caused by processes such as plasma bombardment or etching, and avoiding defects in the dielectric layer 130, thereby improving the withstand voltage of the semiconductor device 100, preventing the dielectric layer 130 from being broken down in advance, and improving the The service life of the semiconductor device 100.

In one embodiment, S400: the step of forming a second metal layer and a metal ring on the buffer layer includes:

S410: Form a metal material layer on the buffer layer. The material of the metal material layer 151 may be aluminum or tungsten. The structure of the metal material layer 151 after formation is shown in FIG. 9 .

S420: Etch the metal material layer to form a second metal layer and a metal ring. The metal material layer 151 may be etched using a dry etching process. The structure after the formation of the second metal layer 150 and the metal ring 160 is shown in FIG. 10 .

In one embodiment, S400: after the step of forming the second metal layer and the metal ring on the buffer layer, the above method further includes:

S500: Etch the exposed part of the surface of the buffer layer to form a first buffer layer and a second buffer layer that are electrically isolated from each other. The buffer layer 140 can be etched using a dry etching process. The etched structure of the buffer layer 140 is as shown in FIG. 11 .

S600: Form a passivation layer on the metal ring; wherein, the passivation layer 170 covers the exposed surface of the dielectric layer 130, the exposed surface of the buffer layer 140, and part of the surface of the second metal layer 150. The material of the passivation layer 170 may be silicon oxide. The preparation process of the passivation layer 170 may be the same as the preparation process of the dielectric layer 130 , which will not be described again in the embodiment of the present application. The structure after the passivation layer 170 is formed is shown in FIG. 12 .

It should be understood that although each step in the flowchart of FIG. 6 is shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 6 may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these steps or stages is also It does not necessarily have to be done sequentially, but can be done with Other steps or at least part of steps or stages within other steps are performed in turn or alternately.

In the description of this specification, reference to the terms "some embodiments," "other embodiments," "ideal embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included herein. In at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all fall within the protection scope of the present application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

A semiconductor device including:

base;

A first metal layer, disposed on the substrate;

A dielectric layer, disposed on the side of the first metal layer facing away from the substrate;

A buffer layer, disposed on the side of the dielectric layer away from the first metal layer;

A second metal layer is disposed on a side of the buffer layer away from the dielectric layer; the potential of the second metal layer is higher than the potential of the first metal layer; and

A metal ring is disposed on a side of the buffer layer away from the dielectric layer, and the metal ring is disposed around the outside of the second metal layer.
The semiconductor device according to claim 1, wherein the buffer layer includes a first buffer layer and a second buffer layer that are electrically isolated;

Wherein, the second metal layer is disposed on a side of the first buffer layer away from the dielectric layer, and the metal ring is disposed on a side of the second buffer layer away from the dielectric layer.
The semiconductor device according to claim 2, wherein along a direction perpendicular to the substrate, the cross-sectional width of the first buffer layer is from a side of the first buffer layer close to the dielectric layer to an opposite side thereof. side gradually increases.
The semiconductor device according to claim 2, wherein along a direction perpendicular to the substrate, the cross-sectional width of the second buffer layer is from a side of the second buffer layer close to the dielectric layer to an opposite side thereof. side gradually increases.
The semiconductor device according to claim 2, wherein the semiconductor device includes a plurality of metal rings, the plurality of metal rings being spaced apart from each other around the second metal layer.
The semiconductor device according to claim 5, wherein the buffer layer includes a plurality of second buffer layers; each second buffer layer is correspondingly disposed on a side of each metal ring close to the dielectric layer. ; And the two adjacent second buffer layers are electrically isolated.
The semiconductor device according to claim 2, wherein a trench is provided between the first buffer layer and the second buffer layer.
The semiconductor device according to claim 1, wherein a dielectric constant of the buffer layer is greater than a dielectric constant of the dielectric layer and less than a dielectric constant of the second metal layer.
The semiconductor device of claim 1, wherein the buffer layer has a thickness between about 200 nm and 500 nm.
The semiconductor device according to claim 1, further comprising a passivation layer disposed on a side of the metal ring away from the dielectric layer; wherein the passivation layer covers the exposed surface of the dielectric layer, the buffer layer The exposed surface and part of the surface of the second metal layer.
The semiconductor device according to claim 1, further comprising an isolation structure disposed on the substrate; wherein the capacitor formed by the first metal layer, the dielectric layer and the second metal layer is disposed adjacent to each other. between the above isolation structures.
A method for preparing a semiconductor device, including:

forming a first metal layer on the substrate;

forming a dielectric layer on the first metal layer;

forming a buffer layer on the dielectric layer; and

A second metal layer and a metal ring are formed on the buffer layer; wherein the metal ring is arranged around the outside of the second metal layer.
The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming a second metal layer and a metal ring on the buffer layer includes:

forming a metal material layer on the buffer layer; and

The metal material layer is etched to form the second metal layer and the metal ring.
The method for manufacturing a semiconductor device according to claim 12, after forming the second metal layer and the metal ring on the buffer layer, further comprising:

Etching the exposed portion of the surface of the buffer layer to form a first buffer layer and a second buffer layer that are electrically isolated from each other; and

A passivation layer is formed on the metal ring; wherein the passivation layer covers the exposed surface of the dielectric layer, the exposed surface of the buffer layer and part of the surface of the second metal layer.