CN107275385A - Gallium nitride semiconductor device and preparation method thereof - Google Patents
Gallium nitride semiconductor device and preparation method thereof Download PDFInfo
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- CN107275385A CN107275385A CN201710488980.8A CN201710488980A CN107275385A CN 107275385 A CN107275385 A CN 107275385A CN 201710488980 A CN201710488980 A CN 201710488980A CN 107275385 A CN107275385 A CN 107275385A
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- gallium nitride
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 178
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 118
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000002360 preparation method Methods 0.000 title claims description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 105
- 239000002184 metal Substances 0.000 claims abstract description 105
- 150000001875 compounds Chemical class 0.000 claims abstract description 93
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 63
- 230000004888 barrier function Effects 0.000 claims abstract description 61
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 19
- 230000002708 enhancing effect Effects 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 238000001312 dry etching Methods 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 24
- 229910045601 alloy Inorganic materials 0.000 claims description 23
- 239000000956 alloy Substances 0.000 claims description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- 239000004411 aluminium Substances 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052733 gallium Inorganic materials 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 229910017083 AlN Inorganic materials 0.000 claims description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 37
- 239000012535 impurity Substances 0.000 description 17
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 16
- 239000010936 titanium Substances 0.000 description 16
- 229910052719 titanium Inorganic materials 0.000 description 16
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 15
- 230000008569 process Effects 0.000 description 14
- 239000011248 coating agent Substances 0.000 description 13
- 238000000576 coating method Methods 0.000 description 13
- 238000007667 floating Methods 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 238000001755 magnetron sputter deposition Methods 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- 239000012528 membrane Substances 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000011259 mixed solution Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000010129 solution processing Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 3
- 230000002378 acidificating effect Effects 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- -1 aluminium copper silicon gold Chemical compound 0.000 description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 239000012895 dilution Substances 0.000 description 3
- 238000010790 dilution Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 3
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
Include the present invention relates to technical field of semiconductor there is provided a kind of gallium nitride semiconductor device：Epitaxial layer of gallium nitride；And, the silicon nitride and plasma enhancing tetraethoxysilance compound medium layer being arranged on the epitaxial layer of gallium nitride；Source electrode, drain and gate on the compound medium layer are arranged at, the source electrode, drain and gate extend through the compound medium layer and be connected with the epitaxial layer of gallium nitride；It is arranged at the insulating barrier on the source electrode, drain and gate and the compound medium layer, and the field plate metal layer being arranged on the insulating barrier.The gallium nitride semiconductor device of the present invention is less prone to the phenomenon for puncturing aluminum gallium nitride; and then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture; gallium nitride semiconductor device is effectively protected, the reliability of gallium nitride semiconductor device is enhanced.
Description
Technical field
The present invention relates to field of semiconductor technology, more particularly to a kind of gallium nitride semiconductor device and preparation method thereof.
Background technology
Gallium nitride have big energy gap, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, it is corrosion-resistant and
The advantages of radiation resistance, so as to make semi-conducting material using gallium nitride, and obtain gallium nitride semiconductor device.
In the prior art, the preparation method of gallium nitride semiconductor device is：Nitrogen is formed on the surface of epitaxial layer of gallium nitride
SiClx layer, etches on silicon nitride layer and is deposited in source contact openings and drain contact hole, source contact openings and drain contact hole
Metal, so as to form source electrode and drain electrode；The aluminum gallium nitride in etch nitride silicon layer and epitaxial layer of gallium nitride, forms one again
Groove, in a groove deposited metal layer, so as to form grid；Then deposited silicon dioxide layer and field plate metal layer so that shape
Into gallium nitride semiconductor device.
But in the prior art, because electric field density is larger, thus can cause gallium nitride semiconductor device electric leakage and
The problem of puncturing, and then gallium nitride semiconductor device can be damaged, reduce the reliability of gallium nitride semiconductor device.Further,
It is desirable to improve electric flux, reduction surface field to improve device performance.
The content of the invention
To solve the above problems, the present invention provides a kind of gallium nitride semiconductor device, including：Epitaxial layer of gallium nitride；And,
The compound medium layer on the epitaxial layer of gallium nitride is arranged at, the material of the compound medium layer is silicon nitride and waited
Gas ions strengthen tetraethoxysilance；
Source electrode, drain and gate on the compound medium layer are arranged at, the source electrode, drain and gate extend through institute
Compound medium layer is stated to be connected with the epitaxial layer of gallium nitride；
It is arranged at the insulating barrier on the source electrode, drain and gate and the compound medium layer, the material of the insulating barrier
Matter is silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer runs through the insulating barrier and institute
State source electrode connection.
Also include several grid field plates, at least one described grid field plate is arranged on the insulating barrier, and through described
Insulating barrier is connected with the grid.
The present invention also provides the preparation method of this gallium nitride semiconductor device there is provided an epitaxial layer of gallium nitride, wherein, institute
State layer-of-substrate silicon, gallium nitride layer and aluminum gallium nitride that epitaxial layer of gallium nitride includes from bottom to top setting gradually；
In the epitaxy of gallium nitride layer surface deposited silicon nitride and plasma enhancing tetraethoxysilance, complex media is formed
Layer, the compound medium layer material is silicon nitride and plasma enhancing tetraethoxysilance；
The acquisition of source contact openings and drain contact hole：The compound medium layer is etched, to form separate source electrode
Contact hole and drain contact hole, the source contact openings, the drain contact hole reach the nitrogen through the compound medium layer
Change gallium aluminium layer；
In the source contact openings and the drain contact hole and on the surface of the compound medium layer, deposition the
One metal, to obtain source electrode, drain electrode；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, connect with to be contained in the source contact openings and the drain electrode
First metal in contact hole forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the compound medium layer and the nitridation
Gallium aluminium layer carries out dry etching, forms gate contact hole, wherein, bottom and the aluminum gallium nitride in the gate contact hole
There is pre-determined distance between bottom；
The second metalwork is deposited in the outward flange in the gate contact hole, the gate contact hole, to obtain grid, now
Obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Deposit field plate metal layer in the perforate and the insulating barrier, the projection of field plate metal layer at least cover the perforate,
And from the source contact openings to the region between the gate contact hole.
Dry etching is carried out on the insulating barrier, to form the second perforate, second perforate is corresponding with the grid
Connection；Insulating barrier in second perforate and around the second perforate, and insulation corresponding between source electrode, drain electrode
Layer region, respectively deposited metal AlSiCu form several grid field plates.
Beneficial effect：
The present invention applies novel materials by the compound medium layer on the surface of epitaxial layer of gallium nitride, also passes through deposition the
One metal is carrying out the high temperature anneal, to be reacted by the first metal after the etching contacted with each other with aluminum gallium nitride
Alloy is formed afterwards, to reduce the contact resistance of the first metal and aluminum gallium nitride after etching；
The present embodiment combines grid field plate and high-k medium PETEOS, and grid field plate improves device by suppressing current collapse
Part breakdown characteristics；High-k media more effectively transmit or extracted electric flux from semiconductor surface, reduce device surface electric field, with
This improves device performance.
Brief description of the drawings
Fig. 1 a are the structural representation of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 1 b are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 1 c are the preparation flow schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 2 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 2 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 b are the grid structure schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 c are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
It refer to shown in Fig. 1 a, a kind of gallium nitride semiconductor device be provided in embodiments of the present invention, it is wrapped from bottom to up
Include：Epitaxial layer of gallium nitride 310, compound medium layer 320, source electrode 331 and drain electrode 332, grid 333, insulating barrier 340, field plate metal
Layer 350.
Wherein, epitaxial layer of gallium nitride 310 is by silicon (Si) substrate 312, gallium nitride (GaN) layer 313 and aluminium gallium nitride alloy (AlGaN)
Layer 314 is constituted, wherein, silicon substrate 312, gallium nitride layer 313 and aluminum gallium nitride 314 are from bottom to top set gradually.
Compound medium layer 320 is arranged on the epitaxial layer of gallium nitride 310；The compound medium layer 320 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 331, drain electrode 332 and grid 333 are arranged on the compound medium layer 320.Specifically, source electrode 331, drain electrode
332 and the outer image " nail " of grid 333 as a part be inserted into the compound medium layer 320, the source electrode 331, drain electrode
332 and grid 333 extend through the compound medium layer 320 and be connected with the epitaxial layer of gallium nitride 310；And a part is protruded from
The top of compound medium layer 320.The source electrode 331 and/or drain electrode 332 are made up of the first metal.The wherein group of the first metal
Separation structure is same as the previously described embodiments.Using the source electrode 331 of the first metal material formation, drain electrode 332, it can be moved back in higher device temperature
Reacted during fire with the aluminum gallium nitride layer 314 in the epitaxial layer of gallium nitride 310, alloy is generated, so that source electrode
331st, 332 contacts with the contact surface of aluminum gallium nitride of drain electrode are good, can effectively reduce source electrode 331, drain electrode 332 and nitrogen
Change the contact resistance of gallium aluminium layer；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, with reference to shown in Fig. 1 b, the grid 333 of the present embodiment includes two connected side by side parts：Shorter is
It is enhanced first grid portion 333a, longer for depletion type second gate portion 333b.The first grid portion 333a and the aluminium gallium nitride alloy
314 surface of layer connection, the second gate portion 333b is stretched into the aluminum gallium nitride 314.What this long and short two part was constituted
Grid is different from existing grid, and " abnormal shape " is presented.
Further, the width D 1 of the first grid portion 333a is preferably not less than second gate portion 333b width D 2.When
So, in other embodiments, first grid portion 333a and second gate portion 333b right position can also be exchanged.
The grid 333b can be extended into down in the aluminum gallium nitride 314, and the grid 333b bottoms are described in
The bottom of aluminum gallium nitride 314 be preferably apart from H the whole aluminum gallium nitride 314 half.Whole grid 333 is by the second gold medal
Category composition, second metal is Ni, Au alloy.
Insulating barrier 340 is arranged at drain electrode 332, grid 333 and the top of a part of source electrode 331, and exposes the whole come
On compound medium layer 320, the material of the insulating barrier 340 is silica.Wherein, insulating barrier 340 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 331, drain electrode 332, the presence of grid 333, so that in source electrode
Insulating barrier 340 between 331 and grid 333, the insulating barrier 340 between grid 33 and drain electrode 332 are, to lower recess, can to lead to
Later continuous lapping process is allowed to smooth.
It can also for example include field plate metal layer 350, it is arranged on the insulating barrier 340.The field plate metal layer 350
It is connected through the insulating barrier 340 with the source electrode 331.Preferably, the material of the field plate metal layer 350 is aluminium copper silicon gold
Belong to layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As illustrated in figure 1 c, specific steps include：
Step 301：Gallium nitride layer 313 and aluminum gallium nitride 314 are sequentially depositing on silicon substrate 312, is formed outside gallium nitride
Prolong layer 310.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 310
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 120.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 302, dry etching is carried out to the compound medium layer 320, forms the He of source contact openings 321 being oppositely arranged
Drain contact hole 322.
In order that the source contact openings 321, the few impurity of the cleaning of drain contact hole 322 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 320, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
At the alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then acidic mixed solution using hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Step 303, in the present embodiment, in source contact openings 321 and drain contact hole 322 and compound medium layer
The first metal is deposited on 120 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound is situated between
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of metal level may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 319 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 319；Through Ohm contact electrode window 319, it can be seen that the portion of compound medium layer 320
Divide surface.In this way, the first metal on source contact openings 121 constitutes on the source electrode 331 of device, drain contact hole 322
One metal constitutes the drain electrode 332 of device.Now, in order to be able to clear expression process of the present invention, the device that name is now obtained is
First assembly.
Step 104, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category and aluminum gallium nitride, 314 reacted after formation alloy.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 314 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 314 can be reduced.That is, reduction source electrode 331, drain electrode 332 and aluminium nitride
Contact resistance between gallium layer 314.
Step 305, by Ohm contact electrode window, 319, compound medium layer 320 and aluminum gallium nitride 314 are carried out
Dry etching, forms gate contact hole 323, wherein, the bottom and the bottom of aluminum gallium nitride 314 in gate contact hole 323 have
Pre-determined distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 319, to compound medium layer
320 and partial aluminum gallium nitride 314, dry etching is carried out, and then form on the first device a gate contact hole
323。
Wherein, when etching for the first time, only carried out in the part of compound medium layer 320, obtain the first shallower contact hole
323a；It is amesiality among the first obtained contact hole 323a of first time etching during second of dry etching to carry out, and carve
Erosion runs through after whole compound medium layer 320 deeply to be carried out into partial nitridation gallium aluminium layer 314 again, forms deeper second contact
Hole 323b；So obtain overall gate contact hole 323.By controlling etch process parameters to adjust gate contact hole 323b width
Degree, to control width D 1, the proportionate relationship of the width D 2 in second gate portion in first grid portion.Then in the gate contact hole
323a, gate contact hole 323b and part compound medium layer 320 deposition Ni/Au, metal thickness be 0.01~0.04 μm/
0.08~0.4 μm；Obtain grid 333.It follows that be actually interconnected between two gate contact holes, first grid portion
333a, second gate portion 333b preparation are also integrally formed.
Preferably, the second contact hole 323b completely breaks through compound medium layer 320, and passes through the aluminum gallium nitride of part
314 so that the second contact hole 323b bottom is preferably aluminum gallium nitride 314 apart from H with the bottom of aluminum gallium nitride 314
Half.
In the present embodiment, formed after a gate contact hole 323, can there is impurity, particle in gate contact hole 323
And the impurity thing such as ion, will be miscellaneous in gate contact hole 320 so as to using hydrochloric acid solution cleaning gate contact hole 320
Matter thing is got rid of.
Specifically, the present embodiment is by after dry etching is carried out to compound medium layer 320, using DHF+SC1+SC2
Method removal devices on impurity thing；And formed after gate contact hole 323, using hydrochloric acid solution by gate contact hole 323
Interior impurity thing is got rid of.It is clear in the surface and gate contact hole 323 of compound medium layer so as to be effectively guaranteed
It is clean, and then ensure that the performance of gallium nitride semiconductor device.
Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 307, a layer insulating, 340 are deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 340.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 331, drain electrode 332 and the presence of grid 333, so that in source electrode 331 and grid
Insulating barrier 340 between pole 333, the insulating barrier 340 between grid 333 and drain electrode 332 are to lower recess, using polishing
Technique is allowed to smooth.
Step 308, after to the progress dry etching of insulating barrier 340 of the top of source contact openings 331, perforate 341 is formed.Institute
Stating grid 333 has the protuberance 333a protruded from outside the gate contact hole 323, and the width of the perforate 341 is less than described
Protuberance 333a width.
Step 309, the insulation of the top of gate contact hole 323 is extended in perforate 341 and from source contact openings 331
Field plate metal 350 is deposited on layer 340, field plate metal layer 350 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 341 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 321 above outer peripheral first metal in gate contact hole 323
Field plate metal is deposited on 320, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 350.The thickness of field plate metal layer 350
Degree be it is uniform, field plate metal layer 350 at the position of perforate 341 and source contact openings 221 and gate contact hole 223 it
Between position at be that, to lower recess, can be allowed to smooth by the technique that polishes in subsequent step.
Beneficial effect：
The gallium nitride semiconductor device of the present embodiment is using mixing grid structure, including short belongs to enhanced first grid portion
The 333a and long second gate portion 333b for belonging to depletion type.Under the conditions of OFF state, first grid portion 333a shut-offs, and second gate portion
333b can pin groove potential under drain voltage, and there is provided high blocking ability；During ON state, enhancement type channel and depletion type ditch
Road provides low channel resistance, it is ensured that high conducting electric current and low conducting resistance.The gallium nitride semiconductor that the present embodiment is obtained
Device can be applied in the technical fields such as power electronic element, wave filter, radio communication element, before good application
Scape.
As shown in Figure 2 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 410, compound medium layer 420, source electrode 431 and drain electrode 432, grid 433, insulating barrier 440, field plate metal layer 450, grid
Field plate 460.
Wherein, epitaxial layer of gallium nitride 410 is by silicon (Si) substrate 412, gallium nitride (GaN) layer 413 and aluminium gallium nitride alloy (AlGaN)
Layer 414 is constituted, wherein, silicon substrate 412, gallium nitride layer 413 and aluminum gallium nitride 414 are from bottom to top set gradually.
Compound medium layer 420 is arranged on the epitaxial layer of gallium nitride 410；The compound medium layer 420 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 431, drain electrode 432 and grid 433 are arranged on the compound medium layer 420.Specifically, source electrode 431, drain electrode
432 and the outer image " nail " of grid 433 as a part be inserted into the compound medium layer 420, the source electrode 431, drain electrode
432 and grid 433 extend through the compound medium layer 420 and be connected with the epitaxial layer of gallium nitride 410；And a part is protruded from
The top of compound medium layer 420.The source electrode 431 and/or drain electrode 432 are made up of the first metal, first metal component
Structure is as shown in above-mentioned embodiment.Using the source electrode 431 of the first metal material formation, drain electrode 432, it can be annealed in higher device temperature
During reacted with the aluminum gallium nitride layer 414 in the epitaxial layer of gallium nitride 410, generate alloy so that source electrode
431st, 432 contacts with the contact surface of aluminum gallium nitride of drain electrode are good, can effectively reduce source electrode 431, drain electrode 432 and nitrogen
Change the contact resistance of gallium aluminium layer；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, the grid 433 is down extended into the aluminum gallium nitride 414, the bottom of grid 433 to institute
State the bottom of aluminum gallium nitride 414 is preferably the half of the whole aluminum gallium nitride 414 apart from H.Grid 433 is by the second metal
Composition, second metal is Ni, Au alloy.
Preferably, include several grid field plates 460, at least one described grid field plate 460 correspond to the grid 433,
It is arranged on the insulating barrier 440, and is connected through the insulating barrier 440 with the top of grid 433.Remaining grid field plate
460 may be disposed at the top of insulating barrier 440.
Insulating barrier 440 is arranged at drain electrode 432, grid 433 and the top of a part of source electrode 431, and exposes the whole come
On compound medium layer 420, the material of the insulating barrier 440 is silica.Wherein, insulating barrier 440 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 431, drain electrode 432, the presence of grid 433, so that in source electrode
Insulating barrier 440 between 431 and grid 433, the insulating barrier 440 between grid 433 and drain electrode 432 be to lower recess, can
The technique that polishes in subsequent step is allowed to smooth.
It can also for example include field plate metal layer 450, it is arranged on the insulating barrier 440.The field plate metal layer 450
It is connected through the insulating barrier 440 with the source electrode 431.Preferably, the material of the field plate metal layer 450 is aluminium copper silicon gold
Belong to layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 2 b, specific steps include：
Step 401：Gallium nitride layer 413 and aluminum gallium nitride 414 are sequentially depositing on silicon substrate 412, is formed outside gallium nitride
Prolong layer 410.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 410
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 420.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 402, dry etching is carried out to the compound medium layer 420, forms the He of source contact openings 421 being oppositely arranged
Drain contact hole 122.
In order that the source contact openings 421, the few impurity of the cleaning of drain contact hole 422 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 420, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
At the alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then acidic mixed solution using hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Step 403, in the present embodiment, in source contact openings 421 and drain contact hole 422 and compound medium layer
The first metal 421 is deposited on 420 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound is situated between
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of metal level may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 419 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 419；Through Ohm contact electrode window 419, it can be seen that the portion of compound medium layer 420
Divide surface.In this way, the first metal on source contact openings 421 constitutes on the source electrode 431 of device, drain contact hole 422
One metal constitutes the drain electrode 432 of device.Now, in order to be able to clear expression process of the present invention, the device that name is now obtained is
First assembly.
Step 404, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 414.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 414 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 414 can be reduced.That is, reduction source electrode 431, drain electrode 432 and aluminium nitride
Contact resistance between gallium layer 414.
Step 405, by Ohm contact electrode window 419, compound medium layer 420 and aluminum gallium nitride 414 are done
Method is etched, and forms gate contact hole 423, wherein, the bottom in gate contact hole 423 has pre- with the bottom of aluminum gallium nitride 414
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 419, to compound medium layer
420 and partial aluminum gallium nitride 414, dry etching is carried out, and then form on the first device a gate contact hole
423.Wherein, gate contact hole 423 is complete breaks through compound medium layer 420, and through the aluminum gallium nitride 414 of part, makes
The bottom of bottom and the aluminum gallium nitride 414 in gate contact hole 423 be preferably apart from H aluminum gallium nitride 414 half.
In the present embodiment, formed after a gate contact hole 423, can there is impurity, particle in gate contact hole 423
And the impurity thing such as ion, will be miscellaneous in gate contact hole 420 so as to using hydrochloric acid solution cleaning gate contact hole 420
Matter thing is got rid of.
The present embodiment is by after dry etching is carried out to compound medium layer 420, using DHF+SC1+SC2 method
Impurity thing in removal devices；And formed after gate contact hole 423, will be miscellaneous in gate contact hole 423 using hydrochloric acid solution
Matter thing is got rid of.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 423 of compound medium layer, and then
It ensure that the performance of gallium nitride semiconductor device.
Step 406, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 423 and grid
The outward flange deposition Ni/Au of pole contact hole 423 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 433.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 407, a layer insulating 440 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 440.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 431, drain electrode 432 and the presence of grid 433, so that in source electrode 431 and grid
Insulating barrier 440 between pole 433, the insulating barrier 440 between grid 433 and drain electrode 432 are to lower recess, using polishing
Technique is allowed to smooth.
Step 408, after to the progress dry etching of insulating barrier 440 of the top of source contact openings 431, perforate 441 is formed.Institute
Stating grid 433 has the protuberance 433a protruded from outside the gate contact hole 423, and the width of the perforate 441 is less than described
Protuberance 433a width.
Step 409, the insulation of the top of gate contact hole 423 is extended in perforate 441 and from source contact openings 431
Field plate metal 450 is deposited on layer 440, field plate metal layer 450 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 441 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 421 above outer peripheral first metal in gate contact hole 423
Field plate metal is deposited on 420, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 450.The thickness of field plate metal layer 450
Degree be it is uniform, field plate metal layer 450 at the position of perforate 441 and source contact openings 421 and gate contact hole 423 it
Between position at be to lower recess.It can be allowed to smooth by polishing operation in the later stage.
Step 4010, the second opening step of increase grid field plate 460.I.e. using the method similar with step 408 in grid
The second perforate 442 of formation of insulating barrier 440 of 433 tops.
Step 4020, using the similar method of such as step 409, the insulating barrier in perforate 442 and around perforate 442
The corresponding region of insulating barrier 440 between 440, and source electrode 431, drain electrode 432, respectively deposited metal AlSiCu form several
Grid field plate 460.
Beneficial effect：
The present embodiment combines grid field plate and compound medium layer, and grid field plate improves device breakdown by suppressing current collapse
Characteristic；High-k media more effectively transmit or extracted electric flux from semiconductor surface, reduce device surface electric field, are changed with this
Kind device performance.The gallium nitride semiconductor device that the present embodiment is obtained can be applied to power electronic element, wave filter, radio and lead to
In the technical fields such as cell part, have a good application prospect.
As shown in Figure 3 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 810, compound medium layer 820, source electrode 831 and drain electrode 832, grid 833, insulating barrier 840.
Wherein, epitaxial layer of gallium nitride 810 is by silicon (Si) substrate 812, gallium nitride (GaN) layer 813 and aluminium gallium nitride alloy (AlGaN)
Layer 814 is constituted, wherein, silicon substrate 812, gallium nitride layer 813 and aluminum gallium nitride 814 are from bottom to top set gradually.
Compound medium layer 820 is arranged on the epitaxial layer of gallium nitride 810；The compound medium layer 820 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 831, drain electrode 832 and grid 833 are arranged on the compound medium layer 820.Specifically, source electrode 831, drain electrode
832 and the outer image " nail " of grid 833 as a part be inserted into the compound medium layer 820, the source electrode 831, drain electrode
832 and grid 833 extend through the compound medium layer 820 and be connected with the epitaxial layer of gallium nitride 810；And a part is protruded from
The top of compound medium layer 820.The source electrode 831 and/or drain electrode 832 by the first metal constitute and above-described embodiment shown in.
Using the first metal material formation source electrode 831, drain electrode 832, can in higher device temperature annealing process with outside the gallium nitride
The aluminum gallium nitride layer 814 prolonged in layer 810 reacts, and generates alloy, so that source electrode 831, drain electrode 832 and aluminium gallium nitride alloy
The contact of the contact surface of layer is good, can effectively reduce source electrode 831, drain electrode 832 and the contact resistance of aluminum gallium nitride；Avoid
The problem of there is the electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, with reference to shown in Fig. 3 b, the grid 833 of the present embodiment includes two connected side by side parts：Shorter is
It is enhanced first grid portion 833a, longer for depletion type second gate portion 833b.The first grid portion 833a and the aluminium gallium nitride alloy
814 surface of layer connection, the second gate portion 833b is stretched into the aluminum gallium nitride 814.What this long and short two part was constituted
Grid is different from existing grid, and " abnormal shape " is presented.
Further, the width D 1 of the first grid portion 833a is preferably not less than second gate portion 833b width D 2.When
So, in other embodiments, first grid portion 833a and second gate portion 833b right position can also be exchanged.
The grid 833b can be extended into down in the aluminum gallium nitride 314, and the grid 833b bottoms are described in
The bottom of aluminum gallium nitride 814 be preferably apart from H the whole aluminum gallium nitride 814 half.Whole grid 833 is by the second gold medal
Category composition, second metal is Ni, Au alloy.
Further, including several floating field plates 829 for being arranged on the compound medium layer 820, the floating
Plate 829 is connected through the compound medium layer 820 with the epitaxial layer of gallium nitride 810, and the floating field plate 829 is independently arranged
Between the source electrode 831, drain electrode 832 and it is presented ring-type.
The height of each floating field plate 829 is preferably 0.25~6 micron.
Insulating barrier 840 is arranged at drain electrode 832, grid 833 and the top of a part of source electrode 831, and exposes the whole come
On compound medium layer 820, the material of the insulating barrier 840 is silica.Wherein, insulating barrier 840 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 831, drain electrode 832, the presence of grid 833, so that in source electrode
Insulating barrier 840 between 831 and grid 833, the insulating barrier 840 between grid 833 and drain electrode 832 be to lower recess, can
It is allowed to smooth using technique is polished.
It can also for example include field plate metal layer 850, it is arranged on the insulating barrier 840.The field plate metal layer 850
It is connected through the insulating barrier 840 with the source electrode 831.Preferably, the material of the field plate metal layer 850 is aluminium copper silicon metal
Layer.
The gallium nitride semiconductor device of the present embodiment is using mixing grid structure, including short belongs to enhanced first grid portion
With the long second gate portion for belonging to depletion type.Under the conditions of OFF state, the shut-off of first grid portion, and second gate portion can be in drain voltage
There is provided high blocking ability for lower pinning groove potential；During ON state, enhancement type channel and deplection type channel provide low raceway groove electricity
Resistance, it is ensured that high conducting electric current and low conducting resistance.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 3 c, specific steps include：
Step 801：Gallium nitride layer 813 and aluminum gallium nitride 814 are sequentially depositing on silicon substrate 812, is formed outside gallium nitride
Prolong layer 810.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 810
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 820.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 802, dry etching is carried out to the compound medium layer 820, forms the He of source contact openings 821 being oppositely arranged
Drain contact hole 822 and multiple floating field plate contact holes 825；Again the pole contact hole 821 and drain contact hole 822,
And the first metal of deposition forms corresponding electrode in multiple floating field plate contact holes 825.
First, drain contact hole 822 is first opened up on compound medium layer 820；Then magnetron sputtering plating work can be used
Skill, in drain contact hole and on the surface of compound medium layer, is sequentially depositing the first titanium coating, aluminum metal layer, the second titanium
Metal level and titanium nitride layer, to form the first metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, aluminum metal layer
Thickness may be, for example, 1200 angstroms, the thickness of the second titanium coating may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example,
200 angstroms.Form drain electrode.
Step 8031, then in source contact openings 821 and the table of the compound medium layer 820 of multiple floating field plate contact holes 825
The first metal is deposited on face.
Similarly, magnetron sputtering membrane process can be used, in source contact openings and multiple floating field plate contact holes
825th, on the surface of part compound medium layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride are sequentially depositing
Layer, to form the first metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer can be such as
For 1200 angstroms, the thickness of the second titanium coating may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.Thus, obtain
Obtain source electrode 831 and floating field plate 835.
Wherein, the length of each floating field plate 835 may be, for example, 0.25~6 micron.
In order that obtaining the source contact openings 821, drain contact hole 822, the cleaning of multiple floating field plate contact holes 825 less
Impurity, in addition to removal step.Specifically, after dry etching is carried out to compound medium layer 820, can first use " DHF
(dilute hydrofluoric acid)+chemical SC-1+ chemicals SC-2 " method, for example, can be first using the hydrogen fluorine after dilution
Acid solution processing apparatus, then using hydrogen peroxide and the alkaline mixed solution processing apparatus of aqua ammonia, then using peroxidating
The acidic mixed solution processed device of hydrogen and hydrogen chloride, and then the impurity thing on the surface of whole device can be removed.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 819 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 819；Through Ohm contact electrode window 819, it can be seen that the portion of compound medium layer 820
Divide surface.In this way, the first metal on source contact openings 821 constitutes on the source electrode 831 of device, drain contact hole 822
One metal constitutes the drain electrode 832 of device.Now, in order to be able to clear expression process of the present invention, the device that name is now obtained is
First assembly.
Step 804, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 814.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 814 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 814 can be reduced.That is, reduction source electrode 831, drain electrode 832 and aluminium nitride
Contact resistance between gallium layer 14.
Step 805, by Ohm contact electrode window 819, compound medium layer 820 and aluminum gallium nitride 814 are done
Method is etched, and forms gate contact hole 823, wherein, the bottom in gate contact hole 823 has pre- with the bottom of aluminum gallium nitride 814
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 819, to compound medium layer
820 and partial aluminum gallium nitride 814, dry etching is carried out, and then form on the first device a gate contact hole
823.Wherein, gate contact hole 823 is complete breaks through compound medium layer 820, and through the aluminum gallium nitride 814 of part, makes
The bottom of bottom and the aluminum gallium nitride 814 in gate contact hole 823 be preferably apart from H aluminum gallium nitride 814 half.Enter
One step, cause gate contact hole 823 is presented one wide at the top and narrow at the bottom, inverted trapezoidal during etching.In the present embodiment, formed
After one gate contact hole 823, there can be the impurity things such as impurity, particle and ion in gate contact hole 823, so as to
So that using hydrochloric acid solution cleaning gate contact hole 820, the impurity thing in gate contact hole 820 to be got rid of.
The present embodiment is by after dry etching is carried out to compound medium layer 820, using DHF+SC1+SC2 method
Impurity thing in removal devices；And formed after gate contact hole 823, will be miscellaneous in gate contact hole 823 using hydrochloric acid solution
Matter thing is got rid of.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 823 of compound medium layer, and then
It ensure that the performance of gallium nitride semiconductor device.
Step 806, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 823 and grid
The outward flange deposition Ni/Au of pole contact hole 823 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 833.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 808, a layer insulating 840 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 840.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 831, drain electrode 832 and the presence of grid 833, so that in source electrode 831 and grid
Insulating barrier 840 between pole 833, the insulating barrier 840 between grid 833 and drain electrode 832 are to lower recess, using polishing
Technique is allowed to smooth.
Step 808, after to the progress dry etching of insulating barrier 840 of the top of source contact openings 831, perforate 841 is formed.Institute
Stating grid 833 has the protuberance 833a protruded from outside the gate contact hole 823, and the width of the perforate 841 is less than described
Protuberance 833a width.
Step 809, the insulation of the top of gate contact hole 823 is extended in perforate 841 and from source contact openings 831
Field plate metal 850 is deposited on layer 840, field plate metal layer 850 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 841 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 821 above outer peripheral first metal in gate contact hole 823
Field plate metal is deposited on 820, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 850.The thickness of field plate metal layer 850
Degree be it is uniform, field plate metal layer 850 at the position of perforate 841 and source contact openings 821 and gate contact hole 823 it
Between position at be, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
The gallium nitride semiconductor device of the present embodiment is using mixing grid structure, including short belongs to enhanced first grid portion
With the long second gate portion for belonging to depletion type.Under the conditions of OFF state, the shut-off of first grid portion, and second gate portion can be in drain voltage
There is provided high blocking ability for lower pinning groove potential；During ON state, enhancement type channel and deplection type channel provide low raceway groove electricity
Resistance, it is ensured that high conducting electric current and low conducting resistance.With reference to the becket of floating, pass through the becket of this floating, extension
The depletion region of power device, reduces the electric-field intensity of main schottky junction, so that it is pressure-resistant to improve device.What the present embodiment was obtained
Gallium nitride semiconductor device can be applied in the technical fields such as power electronic element, wave filter, radio communication element, with good
Good application prospect.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
1. a kind of gallium nitride semiconductor device, it is characterised in that including：Epitaxial layer of gallium nitride；And,
The compound medium layer on the epitaxial layer of gallium nitride is arranged at, the compound medium layer material is silicon nitride and plasma
Strengthen tetraethoxysilance；
Source electrode, drain and gate on the compound medium layer are arranged at, the source electrode, drain and gate extend through described multiple
Dielectric layer is closed to be connected with the epitaxial layer of gallium nitride；
The insulating barrier on the source electrode, drain and gate and the compound medium layer is arranged at, the material of the insulating barrier is
Silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer is through the insulating barrier and the source
Pole is connected.
Also include several grid field plates, at least one described grid field plate is arranged on the insulating barrier, and through the insulation
Layer is connected with the grid.
2. gallium nitride semiconductor device according to claim 1, it is characterised in that the epitaxial layer of gallium nitride includes silicon lining
Bottom, and be arranged at the gallium nitride layer of the surface of silicon, be arranged at the aluminum gallium nitride on the gallium nitride layer surface.
3. gallium nitride semiconductor device according to claim 1, it is characterised in that the grid down extends into the nitridation
In gallium aluminium layer.
4. gallium nitride semiconductor device according to claim 3, it is characterised in that the grid bottom to the aluminium gallium nitride alloy
The distance of layer bottom is the half of the whole aluminum gallium nitride.
5. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the thickness of the compound medium layer
Spend for 2000 angstroms.
6. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the grid field plate is AlSiCu
Grid field plate.
7. a kind of preparation method of gallium nitride semiconductor device, it is characterised in that comprise the following steps：
One epitaxial layer of gallium nitride is provided, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, the nitrogen from bottom to top set gradually
Change gallium layer and aluminum gallium nitride；
In the epitaxy of gallium nitride layer surface deposited silicon nitride and plasma enhancing tetraethoxysilance, compound medium layer is formed；
The acquisition of source contact openings and drain contact hole：The compound medium layer is etched, to form separate source contact
Hole and drain contact hole, the source contact openings, the drain contact hole reach the aluminium nitride through the compound medium layer
Gallium layer；In the source contact openings and the drain contact hole and on the surface of the compound medium layer, the first gold medal is deposited
Category, to obtain source electrode, drain electrode；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, to be contained in the source contact openings and the drain contact hole
Interior first metal forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the compound medium layer and the aluminium gallium nitride alloy
Layer carries out dry etching, forms gate contact hole, wherein, the bottom in the gate contact hole and the bottom of the aluminum gallium nitride
Between have pre-determined distance；
In the gate contact hole, outward flange second metalwork of deposition in the gate contact hole, to obtain grid, now obtain
Obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source electrode；The perforate with
And depositing field plate metal layer on the insulating barrier, the projection of field plate metal layer at least covers the perforate and from described
Source contact openings are to the region between the gate contact hole.
Dry etching is carried out on the insulating barrier, to form the second perforate, the second perforate connection corresponding with the grid；
Insulating barrier in second perforate and around the second perforate, and insulating barrier area corresponding between source electrode, drain electrode
Domain, respectively deposited metal AlSiCu form several grid field plates.
8. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the width of the perforate is small
The protuberance width above the gate contact hole is protruded from the grid.
9. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the high temperature anneal
Step is：Under protection atmosphere, kept for 30~60 seconds at a temperature of 840~850 DEG C.
10. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the pre-determined distance is
The half of the thickness of the aluminum gallium nitride.
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