CN107316895A - Gallium nitride semiconductor device and preparation method thereof - Google Patents
Gallium nitride semiconductor device and preparation method thereof Download PDFInfo
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- CN107316895A CN107316895A CN201710488429.3A CN201710488429A CN107316895A CN 107316895 A CN107316895 A CN 107316895A CN 201710488429 A CN201710488429 A CN 201710488429A CN 107316895 A CN107316895 A CN 107316895A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 227
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 146
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000002360 preparation method Methods 0.000 title claims description 16
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 84
- 230000004888 barrier function Effects 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 101
- 239000002184 metal Substances 0.000 claims description 101
- 238000007667 floating Methods 0.000 claims description 31
- 229910045601 alloy Inorganic materials 0.000 claims description 26
- 239000000956 alloy Substances 0.000 claims description 26
- 238000001312 dry etching Methods 0.000 claims description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052733 gallium Inorganic materials 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- 239000004411 aluminium Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 10
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 10
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 238000000407 epitaxy Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- 230000008859 change Effects 0.000 claims description 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 39
- 239000000377 silicon dioxide Substances 0.000 abstract description 18
- 238000000034 method Methods 0.000 description 44
- 238000000151 deposition Methods 0.000 description 22
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 21
- 239000010936 titanium Substances 0.000 description 21
- 229910052719 titanium Inorganic materials 0.000 description 21
- 239000012535 impurity Substances 0.000 description 20
- 239000011248 coating agent Substances 0.000 description 18
- 238000000576 coating method Methods 0.000 description 18
- 230000008569 process Effects 0.000 description 17
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical group Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 15
- 230000008021 deposition Effects 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 230000005684 electric field Effects 0.000 description 11
- 238000001755 magnetron sputter deposition Methods 0.000 description 10
- 239000012528 membrane Substances 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 9
- 238000004140 cleaning Methods 0.000 description 9
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical group O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 6
- 239000011259 mixed solution Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 5
- 238000010129 solution processing Methods 0.000 description 5
- 229910017083 AlN Inorganic materials 0.000 description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 230000002378 acidificating effect Effects 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- -1 aluminium copper silicon gold Chemical compound 0.000 description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 239000012895 dilution Substances 0.000 description 3
- 238000010790 dilution Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000012459 cleaning agent Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
Include the present invention relates to technical field of semiconductor there is provided a kind of gallium nitride semiconductor device：Epitaxial layer of gallium nitride；And, it is arranged at the dielectric layer on the epitaxial layer of gallium nitride；Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain and gate extend through the dielectric layer and be connected with the epitaxial layer of gallium nitride；The insulating barrier on the source electrode, drain and gate and the dielectric layer is arranged at, the material of the insulating barrier is silica.The gallium nitride semiconductor device of the present invention is less prone to the phenomenon for puncturing aluminum gallium nitride; and then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture; gallium nitride semiconductor device is effectively protected, the reliability of gallium nitride semiconductor device is enhanced.
Description
Technical field
The present invention relates to field of semiconductor technology, more particularly to a kind of gallium nitride semiconductor device and preparation method thereof.
Background technology
Gallium nitride have big energy gap, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, it is corrosion-resistant and
The advantages of radiation resistance, so as to make semi-conducting material using gallium nitride, and obtain gallium nitride semiconductor device.
In the prior art, the preparation method of gallium nitride semiconductor device is：Nitrogen is formed on the surface of epitaxial layer of gallium nitride
SiClx layer, etches on silicon nitride layer and is deposited in source contact openings and drain contact hole, source contact openings and drain contact hole
Metal, so as to form source electrode and drain electrode；The aluminum gallium nitride in etch nitride silicon layer and epitaxial layer of gallium nitride, forms one again
Groove, in a groove deposited metal layer, so as to form grid；Then deposited silicon dioxide layer and field plate metal layer so that shape
Into gallium nitride semiconductor device.
But in the prior art, because electric field density is larger, thus can cause gallium nitride semiconductor device electric leakage and
The problem of puncturing, and then gallium nitride semiconductor device can be damaged, reduce the reliability of gallium nitride semiconductor device.Further,
Gallium nitride power device is after Hi-pot test repeatedly, and the breakdown voltage of device can drift about, this nonsteady behavior and electric charge
Trap is relevant, and the reliability to device can cause harm, it should be suppressed.
The content of the invention
To solve the above problems, the present invention provides a kind of gallium nitride semiconductor device, including：Epitaxial layer of gallium nitride；And,
The dielectric layer on the epitaxial layer of gallium nitride is arranged at, the material of the dielectric layer is hafnium oxide；
Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain and gate, which are extended through, to be given an account of
Matter layer is connected with the epitaxial layer of gallium nitride；Wherein, the grid in the gate contact hole is in inverted trapezoidal；
The insulating barrier on the source electrode, drain and gate and the dielectric layer is arranged at, the material of the insulating barrier is
Silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer runs through the insulating barrier and institute
State source electrode connection.
Also include being arranged on several floating field plates on the dielectric layer, the floating field plate through the dielectric layer with
The epitaxial layer of gallium nitride connection.
There is provided a nitridation for the preparation method of the invention for also providing this gallium nitride semiconductor device with inverted trapezoidal grid
Gallium epitaxial layer, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, gallium nitride layer and the aluminium nitride from bottom to top set gradually
Gallium layer；
In the epitaxy of gallium nitride layer surface deposit hafnium oxides, dielectric layer is formed；
The acquisition of drain contact hole：The dielectric layer is etched to form drain contact hole, the drain contact hole runs through institute
State dielectric layer and reach the aluminum gallium nitride；In the source contact openings and on the surface of the dielectric layer, deposition first
Metal, to be drained；
Source contact openings, the acquisition in floating field plate hole：The dielectric layer is etched to form source contact openings, floating field plate
Hole, the source contact openings, floating field plate hole reach the aluminum gallium nitride through the dielectric layer；In the source contact
In hole, floating field plate hole and on the surface of the dielectric layer, the first metal is deposited, to obtain source electrode, floating field plate；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, connect with to be contained in the source contact openings and the drain electrode
First metal in contact hole forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the dielectric layer and the aluminium gallium nitride alloy
Layer carries out dry etching, forms the gate contact hole of inverted trapezoidal, wherein, bottom and the aluminium gallium nitride alloy in the gate contact hole
There is pre-determined distance between the bottom of layer；
The second metalwork is deposited in the outward flange in the gate contact hole and the gate contact hole, to obtain grid, this
When obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer is at least
Cover the perforate and from the source contact openings to the region between the gate contact hole.
Beneficial effect：
The present invention applies a variety of novel materials by the dielectric layer on the surface of epitaxial layer of gallium nitride, also passes through deposition the
One metal is carrying out the high temperature anneal, to be reacted by the first metal after the etching contacted with each other with aluminum gallium nitride
Alloy is formed afterwards, to reduce the contact resistance of the first metal and aluminum gallium nitride after etching；
The invention enables electric leakage, also, aluminum gallium nitride are difficult on the contact surface in the middle of dielectric layer and aluminum gallium nitride
Field strength peak value is higher, is less prone to the phenomenon for puncturing aluminum gallium nitride, and then avoids the leakage for gallium nitride semiconductor device occur
Electricity and the problem of puncture, is effectively protected gallium nitride semiconductor device, enhances the reliability of gallium nitride semiconductor device.
The present embodiment combination floating field plate, extends the depletion region of power device, reduces the electric-field strength of main schottky junction
Degree, so that it is pressure-resistant to improve device.So as to be effectively protected gallium nitride semiconductor device, gallium nitride semiconductor device is enhanced
Reliability.
Brief description of the drawings
Fig. 1 a are the structural representation of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 b are the first metal structure schematic diagram of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 c are the grid structure schematic diagram of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 d are another structural representation of grid of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 e are the another structural representation of grid of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 f are the preparation flow schematic diagram of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 2 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 2 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 a are the structural representation of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 b are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 c are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 d are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 e are the preparation flow schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in Figure 1a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 110, dielectric layer 120, source electrode 131 and drain electrode 132, grid 133, insulating barrier 140, field plate metal layer 150.
Wherein, epitaxial layer of gallium nitride 110 is by silicon (Si) substrate 112, gallium nitride (GaN) layer 113 and aluminium gallium nitride alloy (AlGaN)
Layer 114 is constituted, wherein, silicon substrate 112, gallium nitride layer 113 and aluminum gallium nitride 114 are from bottom to top set gradually.
Dielectric layer 120 is arranged on the epitaxial layer of gallium nitride 110；The material of the dielectric layer 120 of the present embodiment can example
Such as it is hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 131, drain electrode 132 and grid 133 are arranged on the dielectric layer 120.Specifically, source electrode 131, drain electrode 132
It is inserted into a part as the outer image " nail " of grid 133 in the dielectric layer 120, the source electrode 131, drain electrode 132 and grid
133 extend through the dielectric layer 120 is connected with the epitaxial layer of gallium nitride 110；And a part protrudes from the dielectric layer 120
Top.The source electrode 131 and/or drain electrode 132 are made up of the first metal；First metal (referring to Fig. 1 b) from bottom to up according to
It is secondary including：First titanium coating 134, aluminum metal layer 135, the second titanium coating 136 and titanium nitride layer 137.Wherein, described first
The thickness of titanium coating 134 is 200 angstroms, and the thickness of the aluminum metal layer 135 is 1200 angstroms, second titanium coating 136
Thickness is 200 angstroms, and the thickness of the titanium nitride layer 137 is 200 angstroms.Using the source electrode 131 of the first metal material formation, drain electrode
132, it can be reacted in higher device temperature annealing process with the aluminum gallium nitride layer 114 in the epitaxial layer of gallium nitride 110, it is raw
Into alloy, so that source electrode 131,132 contacts with the contact surface of aluminum gallium nitride of drain electrode are well, it can effectively reduce
Source electrode 131, drain electrode 132 and the contact resistance of aluminum gallium nitride；Avoid the occurrence of the electric leakage of gallium nitride semiconductor device and soft hit
The problem of wearing.
Preferably, the grid 133 is down extended into the aluminum gallium nitride 114, the bottom of grid 133 to institute
State the bottom of aluminum gallium nitride 114 is preferably the half of the whole aluminum gallium nitride 114 apart from H.Grid 133 is by the second metal
Composition, second metal is Ni, Au alloy.
Preferably, the grid 133 has special configuration.With reference to shown in Fig. 1 c, Fig. 1 d and Fig. 1 e, the grid of the present embodiment
Pole 133 can also have various deformation.Seen according to the observation sequence of gallium nitride semiconductor device from bottom to up, the transverse direction of grid 133
Width gradually increases, and the structure of one " upside-down trapezoid " is presented.Further, the part of " upside-down trapezoid " of grid 133 can be
The shape (as illustrated in figure 1 c) uniformly broadened from bottom to up is just presented from gate contact hole 123, has being higher by dielectric layer 120
There is protuberance 133a then to increase width suddenly so that gate contact hole 123 is completely covered；Or can be in aluminum gallium nitride 114
In the part of grid 133 still keep rectangular configuration, aluminum gallium nitride 114 with the part at the top of up to gate contact hole 114 then
Uniformly broaden from bottom to up (as shown in Figure 1 d)；It can also be that composition can be just presented from bottom to up from gate contact hole 123
The shape (as shown in fig. le) uniformly broadened, being higher by the protuberance 133a of dielectric layer 120, then width keeps constant, only increases thick
Degree.
Insulating barrier 140 is arranged at drain electrode 132, grid 133 and the top of a part of source electrode 131, and exposes the whole come
On dielectric layer 120, the material of the insulating barrier 140 is silica.Wherein, insulating barrier 140 is carried out on the surface of whole device
Uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 131, drain electrode 132, the presence of grid 133, so that in source electrode 131
Insulating barrier 140 between grid 133, the insulating barrier 140 between grid 133 and drain electrode 132 be to lower recess, can profit
It is allowed to smooth with technique is polished.
It can also for example include field plate metal layer 150, it is arranged on the insulating barrier 140.The field plate metal layer 150
It is connected through the insulating barrier 140 with the source electrode 131.Preferably, the material of the field plate metal layer 150 is aluminium copper silicon gold
Belong to layer.
The section of grid 133 in above-mentioned gallium nitride semiconductor device is different from " T-shaped " structure of existing grid, but is in
The construction of existing " upside-down trapezoid " wide at the top and narrow at the bottom, the high electric field at suppressor grid edge is effectively guaranteed gallium nitride high tension apparatus
Stable blocking characteristics, make device after high pressure repeatedly, still can keep good reliability.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 1 f, specific steps include：
Step 101：Gallium nitride layer 113 and aluminum gallium nitride 114 are sequentially depositing on silicon substrate 112, is formed outside gallium nitride
Prolong layer 110.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 110
One layer of hafnium oxide (HfO2) of product, forms dielectric layer 120.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms.
Step 102, dry etching is carried out to the dielectric layer 120, forms the source contact openings 21 being oppositely arranged and drain electrode
Contact hole 122.
In order that the source contact openings 121, the few impurity of the cleaning of drain contact hole 122 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to dielectric layer 120, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-1+ization
The method for learning cleaning agent SC-2 ", for example, can be first using the hydrofluoric acid solution processing apparatus after dilution, then using peroxidating
The alkaline mixed solution processing apparatus of hydrogen and aqua ammonia, then using hydrogen peroxide and the acidic mixed solution processor of hydrogen chloride
Part, and then the impurity thing on the surface of whole device can be removed.
Step 103, in the present embodiment, it is interior and dielectric layer 120 in source contact openings 121 and drain contact hole 122
The first metal 121 is deposited on surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and dielectric layer
Surface on, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form the first metal；
Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of layer may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 119 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 119；Through Ohm contact electrode window 119, it can be seen that the part table of dielectric layer 120
Face.In this way, the first metal on source contact openings 121 constitutes the first gold medal on the source electrode 131 of device, drain contact hole 122
Category constitutes the drain electrode 132 of device.Now, in order to be able to clear expression process of the present invention, it is first to name the device now obtained
Component.
Step 104, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 114.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 114 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 114 can be reduced.That is, reduction source electrode 131, drain electrode 132 and aluminium nitride
Contact resistance between gallium layer 14.
Step 105, by Ohm contact electrode window 119, is carried out to dielectric layer 120 and aluminum gallium nitride 114 dry method quarter
Erosion, forms gate contact hole 123, wherein, the bottom in gate contact hole 123 and the bottom of aluminum gallium nitride 114 have it is default away from
From.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 119, to dielectric layer 120 with
And partial aluminum gallium nitride 114, carry out dry etching, and then one gate contact hole 123 of formation on the first device.Its
In, gate contact hole 123 completely breaks through dielectric layer 120, and passes through the aluminum gallium nitride 114 of part so that gate contact
The bottom in hole 123 and the bottom of aluminum gallium nitride 114 be preferably apart from H aluminum gallium nitride 114 half.Further, carve
Cause gate contact hole 123 is presented one wide at the top and narrow at the bottom, inverted trapezoidal during erosion.In the present embodiment, a grid is formed to connect
After contact hole 123, there can be the impurity things such as impurity, particle and ion in gate contact hole 123, so as to molten using hydrochloric acid
Liquid cleaning gate contact hole 120, the impurity thing in gate contact hole 120 is got rid of.
The present embodiment is by after dry etching is carried out to dielectric layer 120, using DHF+SC1+SC2 method remover
Impurity thing on part；And formed after gate contact hole 123, the impurity thing in gate contact hole 123 is gone using hydrochloric acid solution
Remove.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 123 of dielectric layer, and then it ensure that nitridation
The performance of gallium semiconductor devices.
Step 106, in the present embodiment, specifically, using magnetron sputtering membrane process or electron beam evaporation process,
The outward flange deposition Ni/Au in gate contact hole 123 and gate contact hole 123 as the second metal, metal thickness is 0.01~
0.04 μm/0.08~0.4 μm；So as to form the grid 133 of upside-down trapezoid structure.Now, it is interior in order to become apparent from the expression present invention
Hold, it is the second component to name the device now obtained.
Step 107, a layer insulating 140 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO2) of whole second component, thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 140.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 131, drain electrode 132 and the presence of grid 133, so that in source electrode 131 and grid
Insulating barrier 140 between pole 133, the insulating barrier 140 between grid 133 and drain electrode 132 are to lower recess, using polishing
Technique is allowed to smooth.
Step 108, after to the progress dry etching of insulating barrier 140 of the top of source contact openings 131, perforate 141 is formed.Institute
Stating grid 33 has the protuberance 133a protruded from outside the gate contact hole 123, and the width of the perforate 141 is less than described convex
Go out portion 133a width.
Step 109, the insulation of the top of gate contact hole 123 is extended in perforate 141 and from source contact openings 131
Field plate metal 150 is deposited on layer 140, field plate metal layer 150 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 141 and from source electrode
Outer peripheral first metal of contact hole 121 is until on dielectric layer 120 above outer peripheral first metal in gate contact hole 123
Field plate metal is deposited, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 150.Field plate metal layer 150 thickness be
Uniformly, field plate metal layer 150 is at the position of perforate 141 and between source contact openings 121 and gate contact hole 123
At position is, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
The present embodiment by the surface of epitaxy of gallium nitride substrate metallization medium layer be used as instead of existing silicon oxide layer
Dielectric layer；The high temperature anneal technique is recycled, the aluminum gallium nitride in source electrode, drain electrode and epitaxial layer of gallium nitride is reacted
Alloy is formed afterwards, so that source electrode, drain electrode contact with the contact surface of aluminum gallium nitride are well, can effectively reduce source
The contact resistance of pole, drain electrode and aluminum gallium nitride；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Further, the field plate metal layer of formation, makes to be difficult electric leakage on the contact surface in the middle of dielectric layer and aluminum gallium nitride, also, nitrogen
The field strength peak value for changing gallium aluminium layer is higher, is less prone to the phenomenon for puncturing aluminum gallium nitride, and then avoids and gallium nitride occur and partly lead
The electric leakage of body device and the problem of puncture, is effectively protected gallium nitride semiconductor device, enhances gallium nitride semiconductor device
The reliability of part.The gallium nitride semiconductor device that the present embodiment is obtained can be applied to power electronic element, wave filter, radio and lead to
In the technical fields such as cell part, have a good application prospect.
As shown in Figure 2 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 610, dielectric layer 620, source electrode 631 and drain electrode 632, grid 633, insulating barrier 640, field plate metal layer 650.
Wherein, epitaxial layer of gallium nitride 610 is by silicon (Si) substrate 612, gallium nitride (GaN) layer 613 and aluminium gallium nitride alloy (AlGaN)
Layer 614 is constituted, wherein, silicon substrate 612, gallium nitride layer 613 and aluminum gallium nitride 614 are from bottom to top set gradually.
Dielectric layer 620 is arranged on the epitaxial layer of gallium nitride 610；The material of the dielectric layer 620 of the present embodiment can example
Such as it is hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 631, drain electrode 632 and grid 633 are arranged on the dielectric layer 620.Specifically, source electrode 631, drain electrode 632
It is inserted into a part as the outer image " nail " of grid 633 in the dielectric layer 620, the source electrode 631, drain electrode 632 and grid
633 extend through the dielectric layer 620 is connected with the epitaxial layer of gallium nitride 610；And a part protrudes from the dielectric layer 620
Top.The source electrode 631 and/or drain electrode 632 by the first metal constitute and above-described embodiment shown in.Using the first metal material
The source electrode 631 of formation, drain electrode 632, can in higher device temperature annealing process with the nitridation in the epitaxial layer of gallium nitride 610
Gallium aluminium lamination 614 reacts, and generates alloy, so that source electrode 631,632 contacts with the contact surface of aluminum gallium nitride of drain electrode
Well, source electrode 631, drain electrode 632 and the contact resistance of aluminum gallium nitride can be effectively reduced；Avoid the occurrence of gallium nitride semiconductor
The problem of electric leakage and soft breakdown of device.
Preferably, the grid 633 is down extended into the aluminum gallium nitride 614 and gone directly to the aluminium gallium nitride alloy
614 bottom of layer, obtain one " penetrating type grid ".Grid 633 is made up of the second metal, and second metal is Ni, Au alloy.
Insulating barrier 640 is arranged at drain electrode 632, grid 633 and the top of a part of source electrode 631, and exposes the whole come
On dielectric layer 620, the material of the insulating barrier 640 is silica.Wherein, insulating barrier 640 is carried out on the surface of whole device
Uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 631, drain electrode 632, the presence of grid 633, so that in source electrode 631
Insulating barrier 640 between grid 633, the insulating barrier 640 between grid 633 and drain electrode 632 be to lower recess, can profit
It is allowed to smooth with technique is polished.
It can also for example include field plate metal layer 650, it is arranged on the insulating barrier 640.The field plate metal layer 650
It is connected through the insulating barrier 640 with the source electrode 631.Preferably, the material of the field plate metal layer 650 is aluminium copper silicon gold
Belong to layer.
Grid 633 in above-mentioned gallium nitride semiconductor device penetrates whole aluminum gallium nitride and reaches gallium nitride layer, can suppress
The high electric field of gate edge, is effectively guaranteed the stable blocking characteristics of gallium nitride high tension apparatus, makes device by repeatedly high
After pressure, still good reliability can be kept.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 2 b, specific steps include：
Step 601：Gallium nitride layer 613 and aluminum gallium nitride 614 are sequentially depositing on silicon substrate 612, is formed outside gallium nitride
Prolong layer 610.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 610
One layer of hafnium oxide (HfO2) of product, forms dielectric layer 620.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms.
Step 602, dry etching is carried out to the dielectric layer 620, forms the source contact openings 21 being oppositely arranged and drain electrode
Contact hole 622.
In order that the source contact openings 621, the few impurity of the cleaning of drain contact hole 622 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to dielectric layer 620, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-1+ization
The method for learning cleaning agent SC-2 ", for example, can be first using the hydrofluoric acid solution processing apparatus after dilution, then using peroxidating
The alkaline mixed solution processing apparatus of hydrogen and aqua ammonia, then using hydrogen peroxide and the acidic mixed solution processor of hydrogen chloride
Part, and then the impurity thing on the surface of whole device can be removed.
Step 603, in the present embodiment, it is interior and dielectric layer 620 in source contact openings 621 and drain contact hole 622
The first metal 621 is deposited on surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and dielectric layer
Surface on, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form the first metal；
Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 6200 angstroms, the second titanium
The thickness of layer may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 619 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 619；Through Ohm contact electrode window 619, it can be seen that the part table of dielectric layer 620
Face.In this way, the first metal on source contact openings 621 constitutes the first gold medal on the source electrode 631 of device, drain contact hole 622
Category constitutes the drain electrode 632 of device.Now, in order to be able to clear expression process of the present invention, it is first to name the device now obtained
Component.
Step 604, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 614.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 614 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 614 can be reduced.That is, reduction source electrode 631, drain electrode 632 and aluminium nitride
Contact resistance between gallium layer 14.
Step 605, by Ohm contact electrode window 619, is carried out to dielectric layer 620 and aluminum gallium nitride 614 dry method quarter
Erosion, forms gate contact hole 623, wherein, the bottom in gate contact hole 623 and the bottom of aluminum gallium nitride 614 have it is default away from
From.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 619, to dielectric layer 620 with
And partial aluminum gallium nitride 614, carry out dry etching, and then one gate contact hole 623 of formation on the first device.Its
In, gate contact hole 623 completely breaks through dielectric layer 620, and passes through the aluminum gallium nitride 614 of part so that gate contact
The bottom in hole 623 and the bottom of aluminum gallium nitride 614 be preferably apart from H aluminum gallium nitride 614 half.
In the present embodiment, formed after a gate contact hole 623, can there is impurity, particle in gate contact hole 623
And the impurity thing such as ion, will be miscellaneous in gate contact hole 620 so as to using hydrochloric acid solution cleaning gate contact hole 620
Matter thing is got rid of.
The present embodiment is by after dry etching is carried out to dielectric layer 620, using DHF+SC1+SC2 method remover
Impurity thing on part；And formed after gate contact hole 623, the impurity thing in gate contact hole 623 is gone using hydrochloric acid solution
Remove.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 623 of dielectric layer, and then it ensure that nitridation
The performance of gallium semiconductor devices.
Step 606, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 623 and grid
The outward flange deposition Ni/Au of pole contact hole 623 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 633.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 607, a layer insulating 640 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO2) of whole second component, thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 640.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 631, drain electrode 632 and the presence of grid 633, so that in source electrode 631 and grid
Insulating barrier 640 between pole 633, the insulating barrier 640 between grid 633 and drain electrode 632 are to lower recess, using polishing
Technique is allowed to smooth.
Step 608, after to the progress dry etching of insulating barrier 640 of the top of source contact openings 631, perforate 641 is formed.Institute
Stating grid 33 has the protuberance 633a protruded from outside the gate contact hole 623, and the width of the perforate 641 is less than described convex
Go out portion 633a width.
Step 609, the insulation of the top of gate contact hole 623 is extended in perforate 641 and from source contact openings 631
Field plate metal 650 is deposited on layer 640, field plate metal layer 650 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 641 and from source electrode
Outer peripheral first metal of contact hole 621 is until on dielectric layer 620 above outer peripheral first metal in gate contact hole 623
Field plate metal is deposited, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 650.Field plate metal layer 650 thickness be
Uniformly, field plate metal layer 650 is at the position of perforate 641 and between source contact openings 621 and gate contact hole 623
At position is, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
The present embodiment by the surface of epitaxy of gallium nitride substrate metallization medium layer be used as instead of existing silicon oxide layer
Dielectric layer；The high temperature anneal technique is recycled, the aluminum gallium nitride in source electrode, drain electrode and epitaxial layer of gallium nitride is reacted
Alloy is formed afterwards, so that source electrode, drain electrode contact with the contact surface of aluminum gallium nitride are well, can effectively reduce source
The contact resistance of pole, drain electrode and aluminum gallium nitride；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Further, the structure of optimization grid causes grid to penetrate whole aluminum gallium nitride, compatible with CMOS technology line, adjustment electric field point
Cloth, improves the pressure-resistant of device with this.The gallium nitride semiconductor device that the present embodiment is obtained can be applied to power electronic element, filter
In the technical fields such as ripple device, radio communication element, have a good application prospect.
As shown in Figure 3 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 710, dielectric layer 720, source electrode 731 and drain electrode 732, grid 733, floating plate 729, insulating barrier 740, field plate metal layer
750。
Wherein, epitaxial layer of gallium nitride 710 is by silicon (Si) substrate 712, gallium nitride (GaN) layer 713 and aluminium gallium nitride alloy (AlGaN)
Layer 714 is constituted, wherein, silicon substrate 712, gallium nitride layer 713 and aluminum gallium nitride 714 are from bottom to top set gradually.
Dielectric layer 720 is arranged on the epitaxial layer of gallium nitride 710；The material of the dielectric layer 720 of the present embodiment can example
Such as it is hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 731, drain electrode 732 and grid 733 are arranged on the dielectric layer 720.Specifically, source electrode 731, drain electrode 732
It is inserted into a part as the outer image " nail " of grid 733 in the dielectric layer 720, the source electrode 731, drain electrode 732 and grid
733 extend through the dielectric layer 720 is connected with the epitaxial layer of gallium nitride 710；And a part protrudes from the dielectric layer 720
Top.The source electrode 731 and/or drain electrode 732 by the first metal constitute and above-described embodiment shown in.Using the first metal material
The source electrode 731 of formation, drain electrode 732, can in higher device temperature annealing process with the nitridation in the epitaxial layer of gallium nitride 710
Gallium aluminium lamination 714 reacts, and generates alloy, so that source electrode 731,732 contacts with the contact surface of aluminum gallium nitride of drain electrode
Well, source electrode 731, drain electrode 732 and the contact resistance of aluminum gallium nitride can be effectively reduced；Avoid the occurrence of gallium nitride semiconductor
The problem of electric leakage and soft breakdown of device.
Preferably, the grid 733 is down extended into the aluminum gallium nitride 714, the bottom of grid 733 to institute
State the bottom of aluminum gallium nitride 714 is preferably the half of the whole aluminum gallium nitride 714 apart from H.Grid 733 is by the second metal
Composition, second metal is Ni, Au alloy.
Preferably, the grid 733 has special configuration.With reference to shown in Fig. 3 b, Fig. 3 c and Fig. 3 d, the grid of the present embodiment
Pole 733 can also have various deformation.Seen according to the observation sequence of gallium nitride semiconductor device from bottom to up, the transverse direction of grid 733
Width gradually increases, and one " upside-down trapezoid " is presented.Further, the part of " upside-down trapezoid " of grid 733 can be from grid
Just the shape (as shown in Figure 3 b) uniformly broadened from bottom to up is presented in contact hole 723, there is protrusion being higher by dielectric layer 720
Then increase width causes gate contact hole 723 is completely covered portion 733a suddenly；Or can be the grid in aluminum gallium nitride 714
733 parts still keep rectangular configuration, aluminum gallium nitride 714 with the part at the top of up to gate contact hole 714 then from bottom to up
Uniformly broaden (as shown in Figure 3 c)；It can also be that composition can be just presented from gate contact hole 723 uniformly to broaden from bottom to up
Shape (as shown in Figure 3 d), be higher by the protuberance 733a of dielectric layer 720 then width keep it is constant, only increase thickness.
Further, including several floating field plates 729 for being arranged on the dielectric layer 720, the floating field plate 729
It is connected through the dielectric layer 720 with the epitaxial layer of gallium nitride 710, and the floating field plate 729 is independently disposed to the source
Between pole 731, drain electrode 732 and it is presented ring-type.
The height of each floating field plate 729 is preferably 0.25~6 micron.
Insulating barrier 740 is arranged at drain electrode 732, grid 733 and the top of a part of source electrode 731, and exposes the whole come
On dielectric layer 720, the material of the insulating barrier 740 is silica.Wherein, insulating barrier 740 is carried out on the surface of whole device
Uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 731, drain electrode 732, the presence of grid 733, so that in source electrode 731
Insulating barrier 740 between grid 733, the insulating barrier 740 between grid 733 and drain electrode 732 be to lower recess, can profit
It is allowed to smooth with technique is polished.
It can also for example include field plate metal layer 750, it is arranged on the insulating barrier 740.The field plate metal layer 750
It is connected through the insulating barrier 740 with the source electrode 731.Preferably, the material of the field plate metal layer 750 is aluminium copper silicon gold
Belong to layer.
The section of grid 733 in above-mentioned gallium nitride semiconductor device is different from " T-shaped " structure of existing grid, but is in
Existing " trapezoidal " construction of inversion wide at the top and narrow at the bottom, the high electric field at suppressor grid edge is effectively guaranteed gallium nitride high tension apparatus steady
Fixed blocking characteristics, make device after high pressure repeatedly, still can keep good reliability.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 3 e, specific steps include：
Step 701：Gallium nitride layer 713 and aluminum gallium nitride 714 are sequentially depositing on silicon substrate 712, is formed outside gallium nitride
Prolong layer 710.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 710
One layer of hafnium oxide (HfO2) of product, forms dielectric layer 720.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms.
Step 702, dry etching is carried out to the dielectric layer 720, forms the source contact openings 721 being oppositely arranged and leakage
Pole contact hole 722 and multiple floating field plate contact holes 725；Again the pole contact hole 721 and drain contact hole 722, with
And the first metal of deposition forms corresponding electrode in multiple floating field plate contact holes 725.
First, drain contact hole 722 is first opened up on dielectric layer 720；Then magnetron sputtering membrane process can be used,
In drain contact hole and on the surface of dielectric layer, the first titanium coating, aluminum metal layer, the second titanium coating and nitrogen are sequentially depositing
Change titanium layer, to form the first metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer can example
It it is such as 1200 angstroms, the thickness of the second titanium coating may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.Form leakage
Pole.
Step 7031, then on the surface of source contact openings 721 and the dielectric layer 720 of multiple floating field plate contact holes 725
Deposit the first metal.
Similarly, magnetron sputtering membrane process can be used, in source contact openings and multiple floating field plate contact holes
725th, on the surface of certain media layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing,
To form the first metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example,
1200 angstroms, the thickness of the second titanium coating may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.Thus, obtain
Source electrode 731 and floating field plate 735.
Wherein, the length of each floating field plate 735 may be, for example, 0.25~6 micron.
In order that obtaining the source contact openings 721, drain contact hole 722, the cleaning of multiple floating field plate contact holes 725 less
Impurity, in addition to removal step.Specifically, after dry etching is carried out to dielectric layer 720, can first use that " DHF is (dilute
Hydrofluoric acid)+chemical SC-1+ chemicals SC-2 " method, for example, can first using dilution after hydrofluoric acid it is molten
Liquid processing apparatus, then using hydrogen peroxide and the alkaline mixed solution processing apparatus of aqua ammonia, then using hydrogen peroxide with
The acidic mixed solution processed device of hydrogen chloride, and then the impurity thing on the surface of whole device can be removed.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 719 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 719；Through Ohm contact electrode window 719, it can be seen that the part table of dielectric layer 720
Face.In this way, the first metal on source contact openings 721 constitutes the first gold medal on the source electrode 731 of device, drain contact hole 722
Category constitutes the drain electrode 732 of device.Now, in order to be able to clear expression process of the present invention, it is first to name the device now obtained
Component.
Step 704, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 714.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 714 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 714 can be reduced.That is, reduction source electrode 731, drain electrode 732 and aluminium nitride
Contact resistance between gallium layer 14.
Step 705, by Ohm contact electrode window 719, is carried out to dielectric layer 720 and aluminum gallium nitride 714 dry method quarter
Erosion, forms gate contact hole 723, wherein, the bottom in gate contact hole 723 and the bottom of aluminum gallium nitride 714 have it is default away from
From.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 719, to dielectric layer 720 with
And partial aluminum gallium nitride 714, carry out dry etching, and then one gate contact hole 723 of formation on the first device.Its
In, gate contact hole 723 completely breaks through dielectric layer 720, and passes through the aluminum gallium nitride 714 of part so that gate contact
The bottom in hole 723 and the bottom of aluminum gallium nitride 714 be preferably apart from H aluminum gallium nitride 714 half.Further, carve
Cause gate contact hole 723 is presented one wide at the top and narrow at the bottom, inverted trapezoidal during erosion.In the present embodiment, a grid is formed to connect
After contact hole 723, there can be the impurity things such as impurity, particle and ion in gate contact hole 723, so as to molten using hydrochloric acid
Liquid cleaning gate contact hole 720, the impurity thing in gate contact hole 720 is got rid of.
The present embodiment is by after dry etching is carried out to dielectric layer 720, using DHF+SC1+SC2 method remover
Impurity thing on part；And formed after gate contact hole 723, the impurity thing in gate contact hole 723 is gone using hydrochloric acid solution
Remove.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 723 of dielectric layer, and then it ensure that nitridation
The performance of gallium semiconductor devices.
Step 706, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 723 and grid
The outward flange deposition Ni/Au of pole contact hole 723 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 733.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 707, a layer insulating 740 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO2) of whole second component, thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 740.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 731, drain electrode 732 and the presence of grid 733, so that in source electrode 731 and grid
Insulating barrier 740 between pole 733, the insulating barrier 740 between grid 733 and drain electrode 732 are to lower recess, using polishing
Technique is allowed to smooth.
Step 708, after to the progress dry etching of insulating barrier 740 of the top of source contact openings 731, perforate 741 is formed.Institute
Stating grid 33 has the protuberance 733a protruded from outside the gate contact hole 723, and the width of the perforate 741 is less than described convex
Go out portion 733a width.
Step 709, the insulation of the top of gate contact hole 723 is extended in perforate 741 and from source contact openings 731
Field plate metal 750 is deposited on layer 740, field plate metal layer 750 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 741 and from source electrode
Outer peripheral first metal of contact hole 721 is until on dielectric layer 720 above outer peripheral first metal in gate contact hole 723
Field plate metal is deposited, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 750.Field plate metal layer 750 thickness be
Uniformly, field plate metal layer 750 is at the position of perforate 741 and between source contact openings 721 and gate contact hole 723
At position is, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
The present embodiment by the surface of epitaxy of gallium nitride substrate metallization medium layer be used as instead of existing silicon oxide layer
Dielectric layer；The high temperature anneal technique is recycled, the aluminum gallium nitride in source electrode, drain electrode and epitaxial layer of gallium nitride is reacted
Alloy is formed afterwards, so that source electrode, drain electrode contact with the contact surface of aluminum gallium nitride are well, can effectively reduce source
The contact resistance of pole, drain electrode and aluminum gallium nitride；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Further, with reference to the becket of floating, by the becket of this floating, the depletion region of power device is extended, is reduced
The electric-field intensity of main schottky junction, so that it is pressure-resistant to improve device.The gallium nitride semiconductor device that the present embodiment is obtained can be applied to
In the technical fields such as power electronic element, wave filter, radio communication element, have a good application prospect.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (11)
1. a kind of gallium nitride semiconductor device, it is characterised in that including：Epitaxial layer of gallium nitride；And,
The dielectric layer on the epitaxial layer of gallium nitride is arranged at, the dielectric layer material is hafnium oxide；
Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain electrode, grid extend through the dielectric layer
It is connected with the epitaxial layer of gallium nitride；Wherein, the grid is in inverted trapezoidal；
The insulating barrier on the source electrode, drain and gate and the dielectric layer is arranged at, the material of the insulating barrier is dioxy
SiClx；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer is through the insulating barrier and the source
Pole is connected；
Also include being arranged on several floating field plates on the dielectric layer, the floating field plate through the dielectric layer with it is described
Epitaxial layer of gallium nitride is connected.
2. gallium nitride semiconductor device according to claim 1, it is characterised in that the epitaxial layer of gallium nitride includes silicon lining
Bottom, and be arranged at the gallium nitride layer of the surface of silicon, be arranged at the aluminum gallium nitride on the gallium nitride layer surface.
3. gallium nitride semiconductor device according to claim 2, it is characterised in that the grid stretches to the aluminium gallium nitride alloy
In layer.
4. gallium nitride semiconductor device according to claim 2, it is characterised in that the gate bottom to the aluminium gallium nitride alloy
The distance of layer bottom is the half of the aluminum gallium nitride.
5. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the thickness of the dielectric layer is
2000 angstroms.
6. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the height of each floating field plate
For 0.25~6 micron.
7. a kind of preparation method of gallium nitride semiconductor device, it is characterised in that comprise the following steps：
One epitaxial layer of gallium nitride is provided, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, the nitrogen from bottom to top set gradually
Change gallium layer and aluminum gallium nitride；
In the epitaxy of gallium nitride layer surface deposit hafnium oxides, dielectric layer is formed；
The acquisition of drain contact hole：The dielectric layer is etched to form drain contact hole, the drain contact hole, which runs through, to be given an account of
Matter layer reaches the aluminum gallium nitride；In the source contact openings and on the surface of the dielectric layer, the first gold medal is deposited
Category, to be drained；
Source contact openings, the acquisition in floating field plate hole：The dielectric layer is etched to form source contact openings, floating field plate hole, institute
State source contact openings, floating field plate hole and reach the aluminum gallium nitride through the dielectric layer；In the source contact openings, floating
In field plate hole and on the surface of the dielectric layer, the first metal is deposited, to obtain source electrode, floating field plate；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, to be contained in the source contact openings and the drain contact hole
Interior first metal forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, the dielectric layer and the aluminum gallium nitride are entered
Row dry etching, forms the gate contact hole in upside-down trapezoid, the gate contact hole is through the dielectric layer and stretches into described
In aluminum gallium nitride；
The second metalwork is deposited in the outward flange in the gate contact hole and the gate contact hole, to obtain grid, is now obtained
Obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer at least covers described
Perforate and from the source contact openings to the region between the gate contact hole.
8. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the width of the perforate is small
The protuberance width above the gate contact hole is protruded from the grid.
9. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the high temperature anneal
Step is：Under protection atmosphere, kept for 30~60 seconds at a temperature of 840~850 DEG C.
10. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the gate bottom is arrived
The distance of the aluminum gallium nitride bottom is the half of the aluminum gallium nitride.
11. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that each floating
The height of plate is 0.25~6 micron.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101414635A (en) * | 2008-12-01 | 2009-04-22 | 西安电子科技大学 | Groove insulated gate type gate-leakage composite field plate power device and preparation method thereof |
| US20110221011A1 (en) * | 2007-02-22 | 2011-09-15 | Eldat Bahat-Treidel | Semiconductor component and method for producing the same |
| CN103000673A (en) * | 2011-09-09 | 2013-03-27 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
| CN104934476A (en) * | 2014-03-19 | 2015-09-23 | 株式会社东芝 | Semiconductor device and manufacturing method for the same |
| CN105720097A (en) * | 2016-04-28 | 2016-06-29 | 中国科学院半导体研究所 | Enhanced-mode high electron mobility transistor, preparation method thereof, and semiconductor device |
| CN106601809A (en) * | 2015-10-15 | 2017-04-26 | 北京大学 | Gallium-nitride field effect transistor and manufacturing method therefor |
-
2017
- 2017-06-23 CN CN201710488429.3A patent/CN107316895A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110221011A1 (en) * | 2007-02-22 | 2011-09-15 | Eldat Bahat-Treidel | Semiconductor component and method for producing the same |
| CN101414635A (en) * | 2008-12-01 | 2009-04-22 | 西安电子科技大学 | Groove insulated gate type gate-leakage composite field plate power device and preparation method thereof |
| CN103000673A (en) * | 2011-09-09 | 2013-03-27 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
| CN104934476A (en) * | 2014-03-19 | 2015-09-23 | 株式会社东芝 | Semiconductor device and manufacturing method for the same |
| CN106601809A (en) * | 2015-10-15 | 2017-04-26 | 北京大学 | Gallium-nitride field effect transistor and manufacturing method therefor |
| CN105720097A (en) * | 2016-04-28 | 2016-06-29 | 中国科学院半导体研究所 | Enhanced-mode high electron mobility transistor, preparation method thereof, and semiconductor device |
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Application publication date: 20171103 |