CN107331697A - Gallium nitride semiconductor device and preparation method thereof - Google Patents

Gallium nitride semiconductor device and preparation method thereof Download PDF

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Publication number
CN107331697A
CN107331697A CN201710488978.0A CN201710488978A CN107331697A CN 107331697 A CN107331697 A CN 107331697A CN 201710488978 A CN201710488978 A CN 201710488978A CN 107331697 A CN107331697 A CN 107331697A
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gallium nitride
layer
contact hole
dielectric layer
semiconductor device
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刘美华
林信南
刘岩军
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Shenzhen Crystal Phase Technology Co Ltd
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Shenzhen Crystal Phase Technology Co Ltd
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Priority to CN201710488978.0A priority Critical patent/CN107331697A/en
Publication of CN107331697A publication Critical patent/CN107331697A/en
Priority to PCT/CN2018/092141 priority patent/WO2018233660A1/en
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract

Include the present invention relates to technical field of semiconductor there is provided a kind of gallium nitride semiconductor device：Epitaxial layer of gallium nitride；And, it is arranged at the dielectric layer on the epitaxial layer of gallium nitride；Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain and gate extend through the dielectric layer and be connected with the epitaxial layer of gallium nitride；The insulating barrier on the source electrode, drain and gate and the dielectric layer is arranged at, the material of the insulating barrier is silica.The gallium nitride semiconductor device of the present invention is less prone to the phenomenon for puncturing aluminum gallium nitride; and then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture; gallium nitride semiconductor device is effectively protected, the reliability of gallium nitride semiconductor device is enhanced.

Description

Gallium nitride semiconductor device and preparation method thereof
Technical field
The present invention relates to field of semiconductor technology, more particularly to a kind of gallium nitride semiconductor device and preparation method thereof.
Background technology
Gallium nitride have big energy gap, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, it is corrosion-resistant and The advantages of radiation resistance, so as to make semi-conducting material using gallium nitride, and obtain gallium nitride semiconductor device.
In the prior art, the preparation method of gallium nitride semiconductor device is：Nitrogen is formed on the surface of epitaxial layer of gallium nitride SiClx layer, etches on silicon nitride layer and is deposited in source contact openings and drain contact hole, source contact openings and drain contact hole Metal, so as to form source electrode and drain electrode；The aluminum gallium nitride in etch nitride silicon layer and epitaxial layer of gallium nitride, forms one again Groove, in a groove deposited metal layer, so as to form grid；Then deposited silicon dioxide layer and field plate metal layer so that shape Into gallium nitride semiconductor device.
But in the prior art, because electric field density is larger, thus can cause gallium nitride semiconductor device electric leakage and The problem of puncturing, and then gallium nitride semiconductor device can be damaged, reduce the reliability of gallium nitride semiconductor device.Further, Gallium nitride power device is after Hi-pot test repeatedly, and the breakdown voltage of device can drift about, this nonsteady behavior and electric charge Trap is relevant, and the reliability to device can cause harm, it should be suppressed.
The content of the invention
To solve the above problems, the present invention provides a kind of gallium nitride semiconductor device, it is characterised in that including：Gallium nitride Epitaxial layer；And,
The dielectric layer on the epitaxial layer of gallium nitride is arranged at, the material of the dielectric layer is hafnium oxide；
Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain and gate, which are extended through, to be given an account of Matter layer is connected with the epitaxial layer of gallium nitride；The drain electrode includes the first drain electrode being connected with each other and the second drain electrode；
The insulating barrier on the source electrode, drain and gate and the dielectric layer is arranged at, the material of the insulating barrier is Silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer runs through the insulating barrier and institute State source electrode connection.
There is provided a nitridation for the preparation method of the invention for also providing this gallium nitride semiconductor device with inverted trapezoidal grid Gallium epitaxial layer, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, gallium nitride layer and the aluminium nitride from bottom to top set gradually Gallium layer；
In the epitaxy of gallium nitride layer surface deposit hafnium oxides, dielectric layer is formed；
The acquisition of p-type silicon nitride layer；In epitaxy of gallium nitride layer surface deposited silicon dioxide layer, then in the silica The second drain contact hole is used as using dry etching formation deposition hole on layer；P-type gallium nitride layer is deposited in the deposition hole, is gone Except the silicon dioxide layer, obtain being formed the p-type gallium nitride layer on epitaxial layer of gallium nitride；
Source contact openings, the acquisition of the first drain contact hole：The dielectric layer is etched, is connect with the source electrode for forming separate Contact hole and the first drain contact hole, the source contact openings, first drain contact hole reach described through the dielectric layer Aluminum gallium nitride；
In the source contact openings and first drain contact hole and on the p-type silicon nitride layer, the medium On the surface of layer, the first metal is deposited, to obtain source electrode, the first drain electrode, the second drain electrode；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, connect with to be contained in the source contact openings and the drain electrode First metal in contact hole forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the dielectric layer and the aluminium gallium nitride alloy Layer carries out dry etching, forms gate contact hole, wherein, the bottom in the gate contact hole and the bottom of the aluminum gallium nitride Between have pre-determined distance；
The second metalwork is deposited in the outward flange in the gate contact hole and the gate contact hole, to obtain grid, this When obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer is at least covered The perforate and from the source contact openings to the region between the gate contact hole.
Beneficial effect：
The present invention applies a variety of novel materials by the dielectric layer on the surface of epitaxial layer of gallium nitride, also passes through deposition the One metal is carrying out the high temperature anneal, to be reacted by the first metal after the etching contacted with each other with aluminum gallium nitride Alloy is formed afterwards, to reduce the contact resistance of the first metal and aluminum gallium nitride after etching；
This embodiment introduces first drain electrode, second drain electrode structure, i.e., first drain electrode beside introduce one additionally P-GaN areas (the second drain electrode), p-GaN areas are connected with drain electrode.In OFF state, from p-GaN areas, injected holes is effectively released Electronics in trap, so as to completely eliminate current collapse effect.
Brief description of the drawings
Fig. 1 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 1 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 2 a are the structural representation of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 2 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 b are the grid structure schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 c are the grid structure schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 d are the grid structure schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 e are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in Figure 1a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride Epitaxial layer 210, dielectric layer 220, source electrode 231 and drain electrode 232, grid 233, insulating barrier 240, field plate metal layer 250.
Wherein, epitaxial layer of gallium nitride 210 is by silicon (Si) substrate 212, gallium nitride (GaN) layer 213 and aluminium gallium nitride alloy (AlGaN) Layer 214 is constituted, wherein, silicon substrate 212, gallium nitride layer 213 and aluminum gallium nitride 214 are from bottom to top set gradually.
Dielectric layer 220 is arranged on the epitaxial layer of gallium nitride 210；The material of the dielectric layer 220 of the present embodiment can example Such as it is hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 231, drain electrode 232 and grid 233 are arranged on the dielectric layer 220.Specifically, source electrode 231, drain electrode 232 It is inserted into a part as the outer image " nail " of grid 233 in the dielectric layer 220, the source electrode 231, drain electrode 232 and grid 233 extend through the dielectric layer 220 is connected with the epitaxial layer of gallium nitride 210；And a part protrudes from the dielectric layer 220 Top.The source electrode 231 and/or drain electrode 232 are made up of the first metal；First metal composition is same as the previously described embodiments.Adopt With the first metal material formation source electrode 231, drain electrode 232, can in higher device temperature annealing process with the epitaxy of gallium nitride Aluminum gallium nitride layer 214 in layer 210 reacts, and generates alloy, so that source electrode 231, drain electrode 232 and aluminum gallium nitride The contact of contact surface is good, can effectively reduce source electrode 231, drain electrode 232 and the contact resistance of aluminum gallium nitride；Avoid the occurrence of The problem of electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, the grid 233 is down extended into the aluminum gallium nitride 214, the bottom of grid 233 to institute State the bottom of aluminum gallium nitride 214 is preferably the half of the whole aluminum gallium nitride 214 apart from H.Grid 233 is by the second metal Composition, second metal is Ni, Au alloy.
Preferably, a gate dielectric layer 234 is also included between the grid 233 and the epitaxial layer of gallium nitride 210, this The material of gate dielectric layer 234 may be, for example, silicon nitride in embodiment.
Insulating barrier 240 is arranged at drain electrode 232, grid 233 and the top of a part of source electrode 231, and exposes the whole come On dielectric layer 220, the material of the insulating barrier 240 is silica.Wherein, insulating barrier 240 is carried out on the surface of whole device Uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 231, drain electrode 232, the presence of grid 233, so that in source electrode 231 Insulating barrier 240 between grid 233, the insulating barrier 240 between grid 233 and drain electrode 232 are, to lower recess, to pass through Technique is polished in subsequent step so that smooth.
It can also for example include field plate metal layer 250, it is arranged on the insulating barrier 240.The field plate metal layer 250 It is connected through the insulating barrier 240 with the source electrode 231.Preferably, the material of the field plate metal layer 250 is aluminium copper silicon gold Belong to layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 1 b, specific steps include：
Step 201：Gallium nitride layer 213 and aluminum gallium nitride 214 are sequentially depositing on silicon substrate 212, is formed outside gallium nitride Prolong layer 210.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10 ~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 110 One layer of hafnium oxide (HfO of product2), form dielectric layer 120.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms.
Step 202, dry etching is carried out to the dielectric layer 120, forms the source contact openings 221 being oppositely arranged and leakage Pole contact hole 222.
In order that the source contact openings 221, the few impurity of the cleaning of drain contact hole 222 are obtained, in addition to removal step.Specifically , after dry etching is carried out to dielectric layer 220, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-1+ization The method for learning cleaning agent SC-2 ", for example, can be first using the hydrofluoric acid solution processing apparatus after dilution, then using peroxidating The alkaline mixed solution processing apparatus of hydrogen and aqua ammonia, then using hydrogen peroxide and the acidic mixed solution processor of hydrogen chloride Part, and then the impurity thing on the surface of whole device can be removed.
Step 203, in the present embodiment, it is interior and dielectric layer 220 in source contact openings 221 and drain contact hole 222 The first metal is deposited on surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and dielectric layer Surface on, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form the first metal； Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium The thickness of layer may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 219 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to Form an Ohm contact electrode window 219；Through Ohm contact electrode window 219, it can be seen that the part table of dielectric layer 220 Face.In this way, the first metal on source contact openings 121 constitutes the first gold medal on the source electrode 231 of device, drain contact hole 222 Category constitutes the drain electrode 232 of device.Now, in order to be able to clear expression process of the present invention, it is first to name the device now obtained Component.
Step 204, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other Category forms alloy after being reacted with aluminum gallium nitride 214.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 214 on its contact surface, so that The contact resistance between the first metal and aluminum gallium nitride 214 can be reduced.That is, reduction source electrode 231, drain electrode 232 and aluminium nitride Contact resistance between gallium layer 214.
Step 205, by Ohm contact electrode window 219, is carried out to dielectric layer 220 and aluminum gallium nitride 214 dry method quarter Erosion, forms gate contact hole 223, wherein, the bottom in gate contact hole 223 and the bottom of aluminum gallium nitride 214 have it is default away from From.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 219, to dielectric layer 220 with And partial aluminum gallium nitride 214, carry out dry etching, and then one gate contact hole 223 of formation on the first device.Its In, gate contact hole 223 completely breaks through dielectric layer 220, and passes through the aluminum gallium nitride 214 of part so that gate contact The bottom in hole 223 and the bottom of aluminum gallium nitride 214 be preferably apart from H aluminum gallium nitride 214 half.
In the present embodiment, formed after a gate contact hole 223, can there is impurity, particle in gate contact hole 223 And the impurity thing such as ion, will be miscellaneous in gate contact hole 220 so as to using hydrochloric acid solution cleaning gate contact hole 220 Matter thing is got rid of.
The present embodiment is by after dry etching is carried out to dielectric layer 220, using DHF+SC1+SC2 method remover Impurity thing on part；And formed after gate contact hole 223, the impurity thing in gate contact hole 223 is gone using hydrochloric acid solution Remove.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 223 of dielectric layer, and then it ensure that nitridation The performance of gallium semiconductor devices.
Step 206, in the present embodiment, specifically, using magnetron sputtering membrane process, being sunk in gate contact hole 223 One layer of silicon nitride layer of product, the silicon nitride layer is not higher than the gate contact hole 223；Then again on the silicon nitride layer, with And the outward flange deposition Ni/Au in gate contact hole 223, as the second metal, metal thickness is 0.01~0.04 μm/0.08~0.4 μm；So as to constitute grid 233.So, the grid 233 is a kind of composite construction with multiple material.
Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 207, a layer insulating 240 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 240.Wherein, silica enters on the surface of whole device Row uniform deposition, thickness is identical everywhere, due to source electrode 231, drain electrode 232 and the presence of grid 233, so that in source electrode 231 and grid Insulating barrier 240 between pole 233, the insulating barrier 240 between grid 233 and drain electrode 232 are to lower recess, using polishing Technique is allowed to smooth.
Step 208, after to the progress dry etching of insulating barrier 140 of the top of source contact openings 231, perforate 241 is formed.Institute Stating grid 233 has the protuberance 233a protruded from outside the gate contact hole 223, and the width of the perforate 241 is less than described Protuberance 233a width.
Step 209, the insulation of the top of gate contact hole 123 is extended in perforate 241 and from source contact openings 231 Field plate metal 250 is deposited on layer 240, field plate metal layer 250 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 241 and from source electrode Outer peripheral first metal of contact hole 221 is until on dielectric layer 220 above outer peripheral first metal in gate contact hole 223 Field plate metal is deposited, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 250.Field plate metal layer 250 thickness be Uniformly, field plate metal layer 250 is at the position of perforate 241 and between source contact openings 221 and gate contact hole 223 At position is, to lower recess, to be allowed to smooth using technique is polished.
The present embodiment can be with optimised devices manufacture craft, optimised devices technique compatible with CMOS technology line, improves electric conduction Resistance.And then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture, be effectively protected gallium nitride and partly lead Body device, enhances the reliability of gallium nitride semiconductor device.The gallium nitride semiconductor device that the present embodiment is obtained can be applied to In the technical fields such as power electronic element, wave filter, radio communication element, have a good application prospect.
As shown in Figure 2 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride Epitaxial layer 910, dielectric layer 920, source electrode 931 and drain electrode 932, grid 933, insulating barrier 940.
Wherein, epitaxial layer of gallium nitride 910 is by silicon (Si) substrate 912, gallium nitride (GaN) layer 913 and aluminium gallium nitride alloy (AlGaN) Layer 914 is constituted, wherein, silicon substrate 912, gallium nitride layer 913 and aluminum gallium nitride 914 are from bottom to top set gradually.
Dielectric layer 920 is arranged on the epitaxial layer of gallium nitride 910；The material of the dielectric layer 920 of the present embodiment can example Such as it is hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 931, drain electrode 932 and grid 933 are arranged on the dielectric layer 920.Specifically, source electrode 931, drain electrode 932 It is inserted into a part as the outer image " nail " of grid 933 in the dielectric layer 920, the source electrode 931, drain electrode 932 and grid 933 extend through the dielectric layer 920 is connected with the epitaxial layer of gallium nitride 910；And a part protrudes from the dielectric layer 920 Top.Further, as shown in Figure 2 a, the drain electrode 932 includes：The first drain electrode 932a being connected with each other and the second drain electrode 932b, it is described.The source electrode 931 and first drain electrode 932 by the first metal constitute and above-described embodiment shown in.Using the first metal Material formation source electrode 931, drain electrode 932, can in higher device temperature annealing process with the epitaxial layer of gallium nitride 910 Aluminum gallium nitride layer 914 reacts, and generates alloy, so that source electrode 931, drain electrode 932 and the contact surface of aluminum gallium nitride Contact is good, can effectively reduce source electrode 931, drain electrode 932 and the contact resistance of aluminum gallium nitride；Avoid the occurrence of gallium nitride half The problem of electric leakage and soft breakdown of conductor device.Second drain electrode 932b is by gallium nitride layer 935, two kinds of functional layers of the first metal Constitute.
This hole for making drain electrode form in p-type gallium nitride layer, p-type gallium nitride layer of designing can be combined with electronics, So as to eliminate electronics, and then prevent when draining into horizontal high voltage and then produce the phenomenon of current collapse, the electricity prevented The phenomenon of stream avalanche can damage gallium nitride semiconductor device, enhance the reliability of gallium nitride semiconductor device.
T-shape is presented in the section of grid 933 of the present embodiment, and the grid 933 can down extend into the aluminium gallium nitride alloy In layer 914, the bottom of grid 933 to the bottom of aluminum gallium nitride 914 is preferably the whole aluminum gallium nitride apart from H 914 half.Whole grid 933 is made up of the second metal, and second metal is Ni, Au alloy.
Insulating barrier 940 is arranged at drain electrode 932, grid 933 and the top of a part of source electrode 931, and exposes the whole come On dielectric layer 920, the material of the insulating barrier 940 is silica.Wherein, insulating barrier 940 is carried out on the surface of whole device Uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 931, drain electrode 932, the presence of grid 933, so that in source electrode 931 Insulating barrier 940 between grid 933, the insulating barrier 940 between grid 933 and drain electrode 932 be to lower recess, can profit It is allowed to smooth with technique is polished.
It can also for example include field plate metal layer 950, it is arranged on the insulating barrier 940.The field plate metal layer 950 It is connected through the insulating barrier 940 with the source electrode 931.Preferably, the material of the field plate metal layer 950 is aluminium copper silicon gold Belong to layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 2 b, specific steps include：
Step 901：Gallium nitride layer 913 and aluminum gallium nitride 914 are sequentially depositing on silicon substrate 912, is formed outside gallium nitride Prolong layer 910.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10 ~-3e10 volts per cm.
Step 902, p-type gallium nitride layer 935 is then deposited on the epitaxial layer of gallium nitride 910.Specifically, in gallium nitride The surface of epitaxial layer 910 deposits a silicon dioxide layer, is then made in the silicon dioxide layer using dry etching formation deposition hole For the second drain contact hole 922b；P-type gallium nitride layer is deposited in the deposition hole, the silicon dioxide layer is removed, obtains shape Into the p-type gallium nitride layer 935 on epitaxial layer of gallium nitride 910.
903, then chemical gaseous phase electrodeposition method can be strengthened with using plasma, in epitaxial layer of gallium nitride 910, p-type nitrogen Change and one layer of hafnium oxide (HfO is deposited on the surface of gallium layer2), form dielectric layer 920.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms, its thickness needs the thickness more than the p-type gallium nitride layer 935.
Step 904：Dry etching is carried out to the dielectric layer 920, the source contact openings 921 that are oppositely arranged and the is formed One drain contact hole 922a；The p-type gallium nitride layer 935 is located between the drain contact hole 922a of source contact openings 921 and first, Deposition hole is opened up in the top of p-type gallium nitride layer 935 corresponding to former second drain contact hole 922b position again.
Step 9041, magnetron sputtering membrane process then can be used, in the drain contact hole of source contact openings 921 and first In 922a and on the top of p-type gallium nitride layer 935, the surface of dielectric layer 920, the first titanium coating, aluminum metal are sequentially depositing Layer, the second titanium coating and titanium nitride layer, to form the first metal；Wherein, the thickness of the first titanium coating may be, for example, 200 Angstrom, the thickness of aluminum metal layer may be, for example, 1200 angstroms, and the thickness of the second titanium coating may be, for example, 200 angstroms, the thickness of titanium nitride layer Degree may be, for example, 200 angstroms.It is derived from the drain electrodes of drain electrode 932a and second of source electrode 931, first 932b.
In order that the source contact openings 921, drain contact hole, the few impurity of cleaning are obtained, in addition to removal step.Specifically , after dry etching is carried out to dielectric layer 920, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-1+ Chemical SC-2 " method, for example, can be first using the hydrofluoric acid solution processing apparatus after dilution, then using peroxide Change the alkaline mixed solution processing apparatus of hydrogen and aqua ammonia, then handled using the acidic mixed solution of hydrogen peroxide and hydrogen chloride Device, and then the impurity thing on the surface of whole device can be removed.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 919 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to Form an Ohm contact electrode window 919；Through Ohm contact electrode window 919, it can be seen that the part table of dielectric layer 920 Face.In this way, the first metal on source contact openings 921 constitutes the first gold medal on the source electrode 931 of device, drain contact hole 922 Category constitutes the drain electrode 932 of device.Now, in order to be able to clear expression process of the present invention, it is first to name the device now obtained Component.
Step 905, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other Category forms alloy after being reacted with aluminum gallium nitride 914.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 914 on its contact surface, so that The contact resistance between the first metal and aluminum gallium nitride 914 can be reduced.That is, reduction source electrode 931, drain electrode 932 and aluminium nitride Contact resistance between gallium layer 914.
Step 906, by Ohm contact electrode window 919, is carried out to dielectric layer 920 and aluminum gallium nitride 914 dry method quarter Erosion, forms gate contact hole 923, wherein, the bottom in gate contact hole 923 and the bottom of aluminum gallium nitride 914 have it is default away from From.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 919, to dielectric layer 920 with And partial aluminum gallium nitride 914, carry out dry etching, and then one gate contact hole 923 of formation on the first device.Its In, gate contact hole 923 completely breaks through dielectric layer 920, and passes through the aluminum gallium nitride 914 of part so that gate contact The bottom in hole 923 and the bottom of aluminum gallium nitride 914 be preferably apart from H aluminum gallium nitride 914 half.Further, carve Cause gate contact hole 923 is presented one wide at the top and narrow at the bottom, inverted trapezoidal during erosion.In the present embodiment, a grid is formed to connect After contact hole 923, there can be the impurity things such as impurity, particle and ion in gate contact hole 923, so as to molten using hydrochloric acid Liquid cleaning gate contact hole 920, the impurity thing in gate contact hole 920 is got rid of.
The present embodiment is by after dry etching is carried out to dielectric layer 920, using DHF+SC1+SC2 method remover Impurity thing on part；And formed after gate contact hole 923, the impurity thing in gate contact hole 923 is gone using hydrochloric acid solution Remove.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 923 of dielectric layer, and then it ensure that nitridation The performance of gallium semiconductor devices.
Step 907, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 923 and grid The outward flange deposition Ni/Au of pole contact hole 923 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm； So as to constitute grid 933.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 908, a layer insulating 940 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 940.Wherein, silica enters on the surface of whole device Row uniform deposition, thickness is identical everywhere, due to source electrode 931, drain electrode 932 and the presence of grid 933, so that in source electrode 931 and grid Insulating barrier 940 between pole 933, the insulating barrier 940 between grid 933 and drain electrode 932 are to lower recess, using polishing Technique is allowed to smooth.
Step 909, after to the progress dry etching of insulating barrier 940 of the top of source contact openings 931, perforate 941 is formed.Institute Stating grid 933 has the protuberance 933a protruded from outside the gate contact hole 923, and the width of the perforate 941 is less than described Protuberance 933a width.
Step 9010, the exhausted of the top of gate contact hole 923 is extended in perforate 941 and from source contact openings 931 Field plate metal 950 is deposited in edge layer 940, field plate metal layer 950 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 941 and from source electrode Outer peripheral first metal of contact hole 921 is until on dielectric layer 920 above outer peripheral first metal in gate contact hole 923 Field plate metal is deposited, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 950.Field plate metal layer 950 thickness be Uniformly, field plate metal layer 950 is at the position of perforate 941 and between source contact openings 921 and gate contact hole 923 At position is, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
This embodiment introduces first drain electrode, second drain electrode structure, i.e., first drain electrode beside introduce one additionally P-GaN areas (the second drain electrode), p-GaN areas are connected with drain electrode.In OFF state, from p-GaN areas, injected holes is effectively released Electronics in trap, so as to completely eliminate current collapse effect.The gallium nitride semiconductor device that the present embodiment is obtained can be applied In the technical fields such as power electronic element, wave filter, radio communication element, have a good application prospect.
As shown in Figure 3 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride Epitaxial layer 1010, dielectric layer 1020, source electrode 1031 and drain electrode 1032, grid 1033, insulating barrier 1040, field plate metal layer 1050, Protective layer 1060.
Wherein, epitaxial layer of gallium nitride 1010 is by silicon (Si) substrate 1012, gallium nitride (GaN) layer 1013 and aluminium gallium nitride alloy (AlGaN) layer 1014 is constituted, wherein, silicon substrate 1012, gallium nitride layer 1013 and aluminum gallium nitride 1014 are from bottom to top set successively Put.
Dielectric layer 1020 is arranged on the epitaxial layer of gallium nitride 1010；The material of the dielectric layer 1020 of the present embodiment May be, for example, hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 1031, drain electrode 1032 and grid 1033 are arranged on the dielectric layer 1020.Specifically, source electrode 1031, leakage A part as pole 1032 and the outer image " nail " of grid 1033 is inserted into the dielectric layer 1020, the source electrode 1031, drain electrode 1032 and grid 1033 extend through the dielectric layer 1020 and be connected with the epitaxial layer of gallium nitride 1010；And a part is protruded from The top of dielectric layer 1020.The source electrode 1031 and/or drain electrode 1032 are made up of the first metal；The group of first metal Part is referring to shown in above-described embodiment.Using the source electrode 1031 of the first metal material formation, drain electrode 1032, it can be moved back in higher device temperature Reacted during fire with the aluminum gallium nitride layer 1014 in the epitaxial layer of gallium nitride 1010, alloy is generated, so that source Pole 1031,1032 contacts with the contact surface of aluminum gallium nitride of drain electrode are good, can effectively reduce source electrode 1031, drain electrode 1032 with the contact resistance of aluminum gallium nitride；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, the grid 1033 is down extended into the aluminum gallium nitride 1014, and the bottom of grid 1033 is arrived The bottom of aluminum gallium nitride 1014 be preferably apart from H the whole aluminum gallium nitride 1014 half.Grid 1033 is by Two metals are constituted, and second metal is Ni, Au alloy.
Preferably, the grid 1033 has special configuration.With reference to shown in Fig. 3 b, Fig. 3 c and Fig. 3 d, the present embodiment Grid 1033 can also have various deformation.Seen according to the observation sequence of gallium nitride semiconductor device from bottom to up, grid 1033 Transverse width gradually increases, and one " upside-down trapezoid " is presented.Further, the part of " upside-down trapezoid " of grid 1033 can be from Just the shape (as shown in Figure 3 b) uniformly broadened from bottom to up is presented in gate contact hole 1023, has being higher by dielectric layer 1020 There is protuberance 1033a then to increase width suddenly so that gate contact hole 1023 is completely covered；Or can be in aluminum gallium nitride The part of grid 1033 in 1014 still keeps rectangular configuration, in aluminum gallium nitride 1014 with the up to top of gate contact hole 1014 Part then uniformly broadens (as shown in Figure 3 c) from bottom to up；It can also be that composition can be just presented from gate contact hole 1023 The shape (as shown in Figure 3 d) uniformly broadened from bottom to up, being higher by the protuberance 1033a of dielectric layer 1020, then width keeps constant, Only increase thickness.
Insulating barrier 1040 is arranged at drain electrode 1032, grid 1033 and the top of a part of source electrode 1031, and exposes what is come On whole dielectric layers 1020, the material of the insulating barrier 1040 is silica.Wherein, table of the insulating barrier 1040 in whole device Face carries out uniform deposition, and the thickness precipitated everywhere is identical.Due to source electrode 1031, drain electrode 1032, the presence of grid 1033, so that Insulating barrier 1040 between source electrode 1031 and grid 1033, the insulating barrier 1040 between grid 1033 and drain electrode 1032 are downward Depression, it is allowed to smooth using technique is polished.
It can also for example include field plate metal layer 1050, it is arranged on the insulating barrier 1040.The field plate metal layer 1050 are connected through the insulating barrier 1040 with the source electrode 1031.Preferably, the material of the field plate metal layer 1050 is aluminium Copper silicon metal level.
Also include matcoveredn 1060, specifically, in field plate metal layer 1050, and the table of the insulating barrier 1040 There is a protective layer 1060 in face, also deposition.The protective layer 1060 includes Si setting up and down3N4Passivation layer and PETEOS oxide layers. After the structure for increasing protective layer, impurity absorption and electrostatic can be reduced with impurity electrostatic in air-isolation and coarse sheath surface Effect, reduces surface leakage, so that it is pressure-resistant to improve device.
The section of grid 1033 in above-mentioned gallium nitride semiconductor device is different from " T-shaped " structure of existing grid, but " trapezoidal " construction of inversion wide at the top and narrow at the bottom is presented, the high electric field at suppressor grid edge is effectively guaranteed gallium nitride high tension apparatus Stable blocking characteristics, make device after high pressure repeatedly, still can keep good reliability.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 3 e, specific steps include：
Step 1001：Gallium nitride layer 1013 and aluminum gallium nitride 1014 are sequentially depositing on silicon substrate 1012, nitridation is formed Gallium epitaxial layer 110.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high strike Wear the characteristics such as electric field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and anti-spoke According to having stronger advantage under environmental condition, so as to be to study shortwave opto-electronic device and high voltagehigh frequency rate high power device most Good material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 110 One layer of hafnium oxide (HfO2) of product, forms dielectric layer 1020.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms.
Step 1002, dry etching is carried out to the dielectric layer 1020, forms the source contact openings 21 being oppositely arranged and leakage Pole contact hole 1022.
In order that the source contact openings 1021, the few impurity of the cleaning of drain contact hole 1022 are obtained, in addition to removal step.Tool Body, after dry etching is carried out to dielectric layer 1020, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-1 + chemical SC-2 " method, for example, can be first using the hydrofluoric acid solution processing apparatus after dilution, then using peroxide Change the alkaline mixed solution processing apparatus of hydrogen and aqua ammonia, then handled using the acidic mixed solution of hydrogen peroxide and hydrogen chloride Device, and then the impurity thing on the surface of whole device can be removed.
Step 1003, in the present embodiment, in source contact openings 1021 and drain contact hole 1022 and dielectric layer The first metal 1021 is deposited on 1020 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and dielectric layer Surface on, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form the first metal； Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 10200 angstroms, the second titanium The thickness of layer may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 1019 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to Form an Ohm contact electrode window 1019；Through Ohm contact electrode window 1019, it can be seen that the portion of dielectric layer 1020 Divide surface.In this way, the first metal on source contact openings 1021 is constituted on the source electrode 1031 of device, drain contact hole 1022 First metal constitutes the drain electrode 1032 of device.Now, in order to be able to clear expression process of the present invention, the device now obtained is named For first assembly.
Step 1004, the high temperature anneal is carried out to whole first assembly, to pass through first after the etching contacted with each other Metal forms alloy after being reacted with aluminum gallium nitride 1014.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 1014 on its contact surface, so that The contact resistance between the first metal and aluminum gallium nitride 1014 can be reduced.That is, reduction source electrode 1031, drain electrode 1032 and nitridation Contact resistance between gallium aluminium layer 14.
Step 1005, by Ohm contact electrode window 1019, dielectric layer 1020 and aluminum gallium nitride 1014 are done Method is etched, and forms gate contact hole 1023, wherein, the bottom and the bottom of aluminum gallium nitride 1014 in gate contact hole 1023 have Pre-determined distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 1019, to dielectric layer 1020 And partial aluminum gallium nitride 1014, carry out dry etching, and then one gate contact hole 1023 of formation on the first device. Wherein, gate contact hole 1023 is complete breaks through dielectric layer 1020, and passes through the aluminum gallium nitride 1014 of part so that grid The bottom of contact hole 1023 and the bottom of aluminum gallium nitride 1014 be preferably apart from H aluminum gallium nitride 1014 half.Enter one Step ground, causes gate contact hole 1023 is presented one wide at the top and narrow at the bottom, inverted trapezoidal during etching.In the present embodiment, one is formed After individual gate contact hole 1023, there can be the impurity things such as impurity, particle and ion in gate contact hole 1023, so as to Using hydrochloric acid solution cleaning gate contact hole 1020, the impurity thing in gate contact hole 1020 is got rid of.
The present embodiment using DHF+SC1+SC2 method by after dry etching is carried out to dielectric layer 1020, being removed Impurity thing on device；And formed after gate contact hole 1023, using hydrochloric acid solution by the impurity in gate contact hole 1023 Thing is got rid of.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 1023 of dielectric layer, and then ensure The performance of gallium nitride semiconductor device.
Step 1006, in the present embodiment, specifically, using magnetron sputtering membrane process, in the He of gate contact hole 1023 The outward flange deposition Ni/Au in gate contact hole 1023 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm；So as to constitute grid 1033.Now, in order to become apparent from expressing present invention, it is second to name the device now obtained Component.
Step 1007, a layer insulating 1040 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO2) of whole second component, thickness can For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 1040.Wherein, silica enters on the surface of whole device Row uniform deposition, thickness is identical everywhere, due to source electrode 1031, drain electrode 1032 and the presence of grid 1033, so that in source electrode 1031 Insulating barrier 1040 between grid 1033, the insulating barrier 1040 between grid 1033 and drain electrode 1032 be to lower recess, It is allowed to smooth using technique is polished.
Step 1008, after to the progress dry etching of insulating barrier 1040 of the top of source contact openings 1031, perforate is formed 1041.The grid 1033 has the protuberance 1033a protruded from outside the gate contact hole 1023, the width of the perforate 1041 Width of the degree less than the protuberance 1033a.
Step 1009, the top of gate contact hole 1023 is extended in perforate 1041 and from source contact openings 1031 Field plate metal 1050 is deposited on insulating barrier 1040, field plate metal layer 1050 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, in the perforate 1041 and from source electrode Dielectric layer of outer peripheral first metal of contact hole 1021 above outer peripheral first metal in gate contact hole 1023 Field plate metal is deposited on 1020, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 1050.Field plate metal layer 1050 Thickness be uniform, field plate metal layer 1050 is at the position of perforate 1041 and source contact openings 1021 and gate contact At position between hole 1023 is, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
Step 1010, using magnetron sputtering membrane process field plate metal layer 1050, the surface of insulating barrier 1040 according to One silicon nitride layer of secondary deposition and PETEOS oxide layers.
After the structure of the present embodiment increase protective layer, it can be subtracted with impurity electrostatic in air-isolation and coarse sheath surface Few impurity absorption and electrostatic interaction, reduce surface leakage, so that it is pressure-resistant to improve device.The gallium nitride semiconductor that the present embodiment is obtained Device can be applied in the technical fields such as power electronic element, wave filter, radio communication element, before good application Scape.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic； And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and Scope.

Claims (10)

1. a kind of gallium nitride semiconductor device, it is characterised in that including：Epitaxial layer of gallium nitride；And,
The dielectric layer on the epitaxial layer of gallium nitride is arranged at, the dielectric layer material is hafnium oxide；
Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain electrode, grid extend through the dielectric layer It is connected with the epitaxial layer of gallium nitride；Wherein, the drain electrode includes the first drain electrode being connected with each other and the second drain electrode；
The insulating barrier on the source electrode, drain and gate and the dielectric layer is arranged at, the material of the insulating barrier is dioxy SiClx；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer is through the insulating barrier and the source Pole is connected.
2. gallium nitride semiconductor device according to claim 1, it is characterised in that the epitaxial layer of gallium nitride includes silicon lining Bottom, and be arranged at the gallium nitride layer of the surface of silicon, be arranged at the aluminum gallium nitride on the gallium nitride layer surface.
3. gallium nitride semiconductor device according to claim 2, it is characterised in that second drain electrode includes and the nitridation The p-type silicon nitride layer of gallium aluminium layer connection.
4. gallium nitride semiconductor device according to claim 2, it is characterised in that the gate bottom to the aluminium gallium nitride alloy The distance of layer bottom is the half of the aluminum gallium nitride.
5. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the thickness of the dielectric layer is 2000 angstroms.
6. a kind of preparation method of gallium nitride semiconductor device, it is characterised in that comprise the following steps：
One epitaxial layer of gallium nitride is provided, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, the nitrogen from bottom to top set gradually Change gallium layer and aluminum gallium nitride；
In the epitaxy of gallium nitride layer surface deposit hafnium oxides, dielectric layer is formed；
The acquisition of p-type silicon nitride layer；In epitaxy of gallium nitride layer surface deposited silicon dioxide layer, then in the silicon dioxide layer Second drain contact hole is used as using dry etching formation deposition hole；P-type gallium nitride layer is deposited in the deposition hole, institute is removed Silicon dioxide layer is stated, obtains being formed the p-type gallium nitride layer on epitaxial layer of gallium nitride；
Source contact openings, the acquisition of the first drain contact hole：The dielectric layer is etched, to form separate source contact openings With the first drain contact hole, the source contact openings, first drain contact hole reach the nitridation through the dielectric layer Gallium aluminium layer；
In the source contact openings and first drain contact hole and on the p-type silicon nitride layer, the dielectric layer On surface, the first metal is deposited, to obtain source electrode, the first drain electrode, the second drain electrode；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, to be contained in the source contact openings and the drain contact hole Interior first metal forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, the dielectric layer and the aluminum gallium nitride are entered Row dry etching, forms gate contact hole, wherein, the gate contact hole is through the dielectric layer and stretches into the aluminium gallium nitride alloy In layer；
The second metalwork is deposited in the outward flange in the gate contact hole and the gate contact hole, to obtain grid, is now obtained Obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer at least covers described Perforate and from the source contact openings to the region between the gate contact hole.
7. the preparation method of gallium nitride semiconductor device according to claim 6, it is characterised in that the width of the perforate is small The protuberance width above the gate contact hole is protruded from the grid.
8. the preparation method of gallium nitride semiconductor device according to claim 6, it is characterised in that the high temperature anneal Step is：Under protection atmosphere, kept for 30~60 seconds at a temperature of 840~850 DEG C.
9. the preparation method of gallium nitride semiconductor device according to claim 6, it is characterised in that the gate bottom to institute The distance for stating aluminum gallium nitride bottom is the half of the aluminum gallium nitride.
10. the preparation method of gallium nitride semiconductor device according to claim 6, it is characterised in that the grid is by second Metal is constituted, and second metal is Ni, Au alloy.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018233660A1 (en) * 2017-06-23 2018-12-27 深圳市晶相技术有限公司 Gallium nitride semiconductor device and manufacturing method thereof
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