CN107316890A - Gallium nitride semiconductor device and preparation method thereof - Google Patents
Gallium nitride semiconductor device and preparation method thereof Download PDFInfo
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- CN107316890A CN107316890A CN201710487762.2A CN201710487762A CN107316890A CN 107316890 A CN107316890 A CN 107316890A CN 201710487762 A CN201710487762 A CN 201710487762A CN 107316890 A CN107316890 A CN 107316890A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 207
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 141
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000002360 preparation method Methods 0.000 title claims description 15
- 150000001875 compounds Chemical class 0.000 claims abstract description 86
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 66
- 230000004888 barrier function Effects 0.000 claims abstract description 50
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 25
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 273
- 229910052751 metal Inorganic materials 0.000 claims description 106
- 239000002184 metal Substances 0.000 claims description 106
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 26
- 229910045601 alloy Inorganic materials 0.000 claims description 24
- 239000000956 alloy Substances 0.000 claims description 24
- 238000001312 dry etching Methods 0.000 claims description 24
- 230000008021 deposition Effects 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 230000002708 enhancing effect Effects 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052733 gallium Inorganic materials 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 7
- 229910017083 AlN Inorganic materials 0.000 claims description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 150000002632 lipids Chemical class 0.000 claims 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 description 40
- 239000012535 impurity Substances 0.000 description 24
- 230000008569 process Effects 0.000 description 16
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- 229910052719 titanium Inorganic materials 0.000 description 12
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 10
- 238000001755 magnetron sputter deposition Methods 0.000 description 10
- 239000012528 membrane Substances 0.000 description 10
- 238000004140 cleaning Methods 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- 239000000243 solution Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000011259 mixed solution Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000010129 solution processing Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- -1 aluminium copper silicon gold Chemical compound 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000002378 acidificating effect Effects 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 239000012895 dilution Substances 0.000 description 3
- 238000010790 dilution Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 3
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000009881 electrostatic interaction Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 125000004494 ethyl ester group Chemical group 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000000108 ultra-filtration Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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Abstract
Include the present invention relates to technical field of semiconductor there is provided a kind of gallium nitride semiconductor device：Epitaxial layer of gallium nitride；And, it is arranged at the compound medium layer on the epitaxial layer of gallium nitride；Source electrode, drain and gate on the compound medium layer are arranged at, the source electrode, drain and gate extend through the compound medium layer and be connected with the epitaxial layer of gallium nitride；The insulating barrier on the source electrode, drain and gate and the compound medium layer is arranged at, the material of the insulating barrier is silica.The gallium nitride semiconductor device of the present invention is less prone to the phenomenon for puncturing aluminum gallium nitride; and then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture; gallium nitride semiconductor device is effectively protected, the reliability of gallium nitride semiconductor device is enhanced.
Description
Technical field
The present invention relates to field of semiconductor technology, more particularly to a kind of gallium nitride semiconductor device and preparation method thereof.
Background technology
Gallium nitride have big energy gap, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, it is corrosion-resistant and
The advantages of radiation resistance, so as to make semi-conducting material using gallium nitride, and obtain gallium nitride semiconductor device.
In the prior art, the preparation method of gallium nitride semiconductor device is：Nitrogen is formed on the surface of epitaxial layer of gallium nitride
SiClx layer, etches on silicon nitride layer and is deposited in source contact openings and drain contact hole, source contact openings and drain contact hole
Metal, so as to form source electrode and drain electrode；The aluminum gallium nitride in etch nitride silicon layer and epitaxial layer of gallium nitride, forms one again
Groove, in a groove deposited metal layer, so as to form grid；Then deposited silicon dioxide layer and field plate metal layer so that shape
Into gallium nitride semiconductor device.
But in the prior art, because electric field density is larger, thus can cause gallium nitride semiconductor device electric leakage and
The problem of puncturing, and then gallium nitride semiconductor device can be damaged, reduce the reliability of gallium nitride semiconductor device.Further,
Gallium nitride power device is after Hi-pot test repeatedly, and the breakdown voltage of device can drift about, this nonsteady behavior and electric charge
Trap is relevant, and the reliability to device can cause harm, it should be suppressed.
The content of the invention
To solve the above problems, the present invention provides a kind of gallium nitride semiconductor device, it is characterised in that including：Gallium nitride
Epitaxial layer；And,
The compound medium layer on the epitaxial layer of gallium nitride is arranged at, the material of the compound medium layer is silicon nitride and waited
Gas ions strengthen tetraethoxysilance；
Source electrode, drain and gate on the compound medium layer are arranged at, the source electrode, drain and gate extend through institute
Compound medium layer is stated to be connected with the epitaxial layer of gallium nitride；Wherein, the grid in the gate contact hole is in inverted trapezoidal；
It is arranged at the insulating barrier on the source electrode, drain and gate and the compound medium layer, the material of the insulating barrier
Matter is silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer runs through the insulating barrier and institute
State source electrode connection.
In field plate metal layer and the surface of insulating layer, also deposition has a protective layer, above and below the protection includes
The silicon nitride layer and oxide layer of stacking.
The present invention also provides the preparation method of this gallium nitride semiconductor device there is provided an epitaxial layer of gallium nitride, wherein, institute
State layer-of-substrate silicon, gallium nitride layer and aluminum gallium nitride that epitaxial layer of gallium nitride includes from bottom to top setting gradually；
In the epitaxy of gallium nitride layer surface deposited silicon nitride and plasma enhancing tetraethoxysilance, complex media is formed
Layer；
The acquisition of source contact openings and drain contact hole：The compound medium layer is etched, to form separate source electrode
Contact hole and drain contact hole, the source contact openings, the drain contact hole reach the nitrogen through the compound medium layer
Change gallium aluminium layer；
In the source contact openings and the drain contact hole and on the surface of the compound medium layer, deposition the
One metal, to obtain source electrode, drain electrode；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, connect with to be contained in the source contact openings and the drain electrode
First metal in contact hole forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the compound medium layer and the nitridation
Gallium aluminium layer carries out dry etching, forms gate contact hole, wherein, bottom and the aluminum gallium nitride in the gate contact hole
There is pre-determined distance between bottom；
The second metalwork is deposited in the outward flange in the gate contact hole and the gate contact hole, to obtain grid, this
When obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer is at least covered
The perforate and from the source contact openings to the region between the gate contact hole；
In field plate metal layer and the surface of insulating layer, successively deposited silicon nitride layer and the positive silicon of plasma enhancing
Sour ethyl ester layer, obtains protective layer.
Beneficial effect：
The present invention applies a variety of novel materials by the compound medium layer on the surface of epitaxial layer of gallium nitride, also by heavy
The first metal of product is carrying out the high temperature anneal, to be carried out by the first metal after the etching contacted with each other and aluminum gallium nitride
Alloy is formed after reaction, to reduce the contact resistance of the first metal and aluminum gallium nitride after etching；
The invention enables electric leakage, also, aluminium gallium nitride alloy are difficult on the contact surface in the middle of compound medium layer and aluminum gallium nitride
The field strength peak value of layer is higher, is less prone to the phenomenon for puncturing aluminum gallium nitride, and then avoids and gallium nitride semiconductor device occur
Electric leakage and the problem of puncture, be effectively protected gallium nitride semiconductor device, enhance gallium nitride semiconductor device can
By property.
After the structure of the present embodiment increase protective layer, it can be subtracted with impurity electrostatic in air-isolation and coarse sheath surface
Few impurity absorption and electrostatic interaction, reduce surface leakage, so that it is pressure-resistant to improve device.
Brief description of the drawings
Fig. 1 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 1 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 2 a are the structural representation of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 2 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 b are the grid structure schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 c are the grid structure schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 d are the grid structure schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 e are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in Figure 1a, a kind of gallium nitride semiconductor device is provided in one embodiment, and it includes from bottom to up：Gallium nitride
Epitaxial layer 210, compound medium layer 220, source electrode 231 and drain electrode 232, grid 233, insulating barrier 240, field plate metal layer 250.
Wherein, epitaxial layer of gallium nitride 210 is by silicon (Si) substrate 212, gallium nitride (GaN) layer 213 and aluminium gallium nitride alloy (AlGaN)
Layer 214 is constituted, wherein, silicon substrate 212, gallium nitride layer 213 and aluminum gallium nitride 214 are from bottom to top set gradually.
Compound medium layer 220 is arranged on the epitaxial layer of gallium nitride 210；The compound medium layer 220 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 231, drain electrode 232 and grid 233 are arranged on the compound medium layer 220.Specifically, source electrode 231, drain electrode
232 and the outer image " nail " of grid 233 as a part be inserted into the compound medium layer 220, the source electrode 231, drain electrode
232 and grid 233 extend through the compound medium layer 220 and be connected with the epitaxial layer of gallium nitride 210；And a part is protruded from
The top of compound medium layer 220.The source electrode 231 and/or drain electrode 232 are made up of the first metal；First metal constitute with
Above-described embodiment is identical., can be in higher device temperature annealing process using the source electrode 231 of the first metal material formation, drain electrode 232
Reacted with the aluminum gallium nitride layer 214 in the epitaxial layer of gallium nitride 210, generate alloy, so that source electrode 231, drain electrode
232 contacts with the contact surface of aluminum gallium nitride are good, can effectively reduce source electrode 231, drain electrode 232 and aluminum gallium nitride
Contact resistance；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, a gate dielectric layer 234 is also included between the grid 233 and the epitaxial layer of gallium nitride 210, this
The material of gate dielectric layer 234 may be, for example, silicon nitride in embodiment.Grid 233 is made up of the second metal, second metal be Ni,
Au alloys.
Preferably, the grid 233 is down extended into the aluminum gallium nitride 214, the bottom of grid 233 to institute
State the bottom of aluminum gallium nitride 214 is preferably the half of the whole aluminum gallium nitride 214 apart from H.
Insulating barrier 240 is arranged at drain electrode 232, grid 233 and the top of a part of source electrode 231, and exposes the whole come
On compound medium layer 220, the material of the insulating barrier 240 is silica.Wherein, insulating barrier 240 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 231, drain electrode 232, the presence of grid 233, so that in source electrode
Insulating barrier 240 between 231 and grid 233, the insulating barrier 240 between grid 233 and drain electrode 232 are, to lower recess, to lead to
Cross in subsequent step and polish technique so that smooth.
It can also for example include field plate metal layer 250, it is arranged on the insulating barrier 240.The field plate metal layer 250
It is connected through the insulating barrier 240 with the source electrode 231.Preferably, the material of the field plate metal layer 250 is aluminium copper silicon gold
Belong to layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 1 b, specific steps include：
Step 201：Gallium nitride layer 213 and aluminum gallium nitride 214 are sequentially depositing on silicon substrate 212, is formed outside gallium nitride
Prolong layer 210.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 110
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 120.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 202, dry etching is carried out to the compound medium layer 120, forms the He of source contact openings 221 being oppositely arranged
Drain contact hole 222.
In order that the source contact openings 221, the few impurity of the cleaning of drain contact hole 222 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 220, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
At the alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then acidic mixed solution using hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Step 203, in the present embodiment, in source contact openings 221 and drain contact hole 222 and compound medium layer
The first metal is deposited on 220 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound is situated between
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of metal level may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 219 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 219；Through Ohm contact electrode window 219, it can be seen that the portion of compound medium layer 220
Divide surface.In this way, the first metal on source contact openings 121 constitutes on the source electrode 231 of device, drain contact hole 222
One metal constitutes the drain electrode 232 of device.Now, in order to be able to clear expression process of the present invention, the device that name is now obtained is
First assembly.
Step 204, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 214.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 214 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 214 can be reduced.That is, reduction source electrode 231, drain electrode 232 and aluminium nitride
Contact resistance between gallium layer 214.
Step 205, by Ohm contact electrode window 219, compound medium layer 220 and aluminum gallium nitride 214 are done
Method is etched, and forms gate contact hole 223, wherein, the bottom in gate contact hole 223 has pre- with the bottom of aluminum gallium nitride 214
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 219, to compound medium layer
220 and partial aluminum gallium nitride 214, dry etching is carried out, and then form on the first device a gate contact hole
223.Wherein, gate contact hole 223 is complete breaks through compound medium layer 220, and through the aluminum gallium nitride 214 of part, makes
The bottom of bottom and the aluminum gallium nitride 214 in gate contact hole 223 be preferably apart from H aluminum gallium nitride 214 half.
In the present embodiment, formed after a gate contact hole 223, can there is impurity, particle in gate contact hole 223
And the impurity thing such as ion, will be miscellaneous in gate contact hole 220 so as to using hydrochloric acid solution cleaning gate contact hole 220
Matter thing is got rid of.
The present embodiment is by after dry etching is carried out to compound medium layer 220, using DHF+SC1+SC2 method
Impurity thing in removal devices；And formed after gate contact hole 223, will be miscellaneous in gate contact hole 223 using hydrochloric acid solution
Matter thing is got rid of.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 223 of compound medium layer, and then
It ensure that the performance of gallium nitride semiconductor device.
Step 206, in the present embodiment, specifically, using magnetron sputtering membrane process, being sunk in gate contact hole 223
One layer of silicon nitride layer of product is as gate dielectric layer, and the silicon nitride layer is not higher than the gate contact hole 223；Then again described
The outward flange deposition Ni/Au on silicon nitride layer and gate contact hole 223 as the second metal, metal thickness is 0.01~
0.04 μm/0.08~0.4 μm；So as to constitute grid 233.So, the grid 233 is a kind of composite junction with multiple material
Structure.
Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 207, a layer insulating 240 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 240.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 231, drain electrode 232 and the presence of grid 233, so that in source electrode 231 and grid
Insulating barrier 240 between pole 233, the insulating barrier 240 between grid 233 and drain electrode 232 are to lower recess, using polishing
Technique is allowed to smooth.
Step 208, after to the progress dry etching of insulating barrier 140 of the top of source contact openings 231, perforate 241 is formed.Institute
Stating grid 233 has the protuberance 233a protruded from outside the gate contact hole 223, and the width of the perforate 241 is less than described
Protuberance 233a width.
Step 209, the insulation of the top of gate contact hole 123 is extended in perforate 241 and from source contact openings 231
Field plate metal 250 is deposited on layer 240, field plate metal layer 250 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 241 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 221 above outer peripheral first metal in gate contact hole 223
Field plate metal is deposited on 220, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 250.The thickness of field plate metal layer 250
Degree be it is uniform, field plate metal layer 250 at the position of perforate 241 and source contact openings 221 and gate contact hole 223 it
Between position at be, to lower recess, to be allowed to smooth using polishing technique.
The present embodiment can be with optimised devices manufacture craft, optimised devices technique compatible with CMOS technology line, improves electric conduction
Resistance.And then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture, be effectively protected gallium nitride and partly lead
Body device, enhances the reliability of gallium nitride semiconductor device.The gallium nitride semiconductor device that the present embodiment is obtained can be applied to
In the technical fields such as power electronic element, wave filter, radio communication element, have a good application prospect.
As shown in Figure 2 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 910, compound medium layer 920, source electrode 931 and drain electrode 932, grid 933, insulating barrier 940.
Wherein, epitaxial layer of gallium nitride 910 is by silicon (Si) substrate 912, gallium nitride (GaN) layer 913 and aluminium gallium nitride alloy (AlGaN)
Layer 914 is constituted, wherein, silicon substrate 912, gallium nitride layer 913 and aluminum gallium nitride 914 are from bottom to top set gradually.
Compound medium layer 920 is arranged on the epitaxial layer of gallium nitride 910；The compound medium layer 920 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 931, drain electrode 932 and grid 933 are arranged on the compound medium layer 920.Specifically, source electrode 931, drain electrode
932 and the outer image " nail " of grid 933 as a part be inserted into the compound medium layer 920, the source electrode 931, drain electrode
932 and grid 933 extend through the compound medium layer 920 and be connected with the epitaxial layer of gallium nitride 910；And a part is protruded from
The top of compound medium layer 920.Further, as shown in Figure 2 a, the drain electrode 932 includes：The first drain electrode being connected with each other
932a and second drain electrode 932b, it is described.The drain electrode of source electrode 931 and first 932 is made up of and above-described embodiment institute the first metal
Show.Using the first metal material formation source electrode 931, drain electrode 932, can in higher device temperature annealing process with the gallium nitride
Aluminum gallium nitride layer 914 in epitaxial layer 910 reacts, and generates alloy, so that source electrode 931, drain electrode 932 and aluminium nitride
The contact of the contact surface of gallium layer is good, can effectively reduce source electrode 931, drain electrode 932 and the contact resistance of aluminum gallium nitride；Keep away
Exempt from the problem of electric leakage and soft breakdown that gallium nitride semiconductor device occur.Second drain electrode 932b is by gallium nitride layer 935, the first gold medal
Two kinds of functional layers of category are constituted.
This hole for making drain electrode form in p-type gallium nitride layer, p-type gallium nitride layer of designing can be combined with electronics,
So as to eliminate electronics, and then prevent when draining into horizontal high voltage and then produce the phenomenon of current collapse, the electricity prevented
The phenomenon of stream avalanche can damage gallium nitride semiconductor device, enhance the reliability of gallium nitride semiconductor device.
T-shape is presented in the section of grid 933 of the present embodiment, and the grid 933 can down extend into the aluminium gallium nitride alloy
In layer 914, the bottom of grid 933 to the bottom of aluminum gallium nitride 914 is preferably the whole aluminum gallium nitride apart from H
914 half.Whole grid 933 is made up of the second metal, and second metal is Ni, Au alloy.
Insulating barrier 940 is arranged at drain electrode 932, grid 933 and the top of a part of source electrode 931, and exposes the whole come
On compound medium layer 920, the material of the insulating barrier 940 is silica.Wherein, insulating barrier 940 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 931, drain electrode 932, the presence of grid 933, so that in source electrode
Insulating barrier 940 between 931 and grid 933, the insulating barrier 940 between grid 933 and drain electrode 932 be to lower recess, can
It is allowed to smooth using technique is polished.
It can also for example include field plate metal layer 950, it is arranged on the insulating barrier 940.The field plate metal layer 950
It is connected through the insulating barrier 940 with the source electrode 931.Preferably, the material of the field plate metal layer 950 is aluminium copper silicon gold
Belong to layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 2 b, specific steps include：
Step 901：Gallium nitride layer 913 and aluminum gallium nitride 914 are sequentially depositing on silicon substrate 912, is formed outside gallium nitride
Prolong layer 910.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Step 902, p-type gallium nitride layer 935 is then deposited on the epitaxial layer of gallium nitride 910.Specifically, in gallium nitride
The surface of epitaxial layer 910 deposits a silicon dioxide layer, is then made in the silicon dioxide layer using dry etching formation deposition hole
For the second drain contact hole 922b；P-type gallium nitride layer is deposited in the deposition hole, the silicon dioxide layer is removed, obtains shape
Into the p-type gallium nitride layer 935 on epitaxial layer of gallium nitride 910.
903, then chemical gaseous phase electrodeposition method can be strengthened with using plasma, in epitaxial layer of gallium nitride 910, p-type nitrogen
Change one layer of silicon nitride of deposition and plasma enhancing tetraethoxysilance (PETEOS) on the surface of gallium layer, form compound medium layer
920.Wherein, the thickness of silicon nitride and plasma enhancing tetraethoxysilance for example can be 2000 angstroms, and its thickness needs to be more than institute
State the thickness of p-type gallium nitride layer 935.
Step 904：Dry etching is carried out to the compound medium layer 920, the He of source contact openings 921 being oppositely arranged is formed
First drain contact hole 922a；The p-type gallium nitride layer 935 be located at the drain contact hole 922a of source contact openings 921 and first it
Between, open up deposition hole corresponding to former second drain contact hole 922b position again in the top of p-type gallium nitride layer 935.
Step 9041, magnetron sputtering membrane process then can be used, in the drain contact hole of source contact openings 921 and first
In 922a and on the top of p-type gallium nitride layer 935, the surface of compound medium layer 920, the first titanium coating, aluminium gold are sequentially depositing
Belong to layer, the second titanium coating and titanium nitride layer, to form the first metal；Wherein, the thickness of the first titanium coating may be, for example, 200
Angstrom, the thickness of aluminum metal layer may be, for example, 1200 angstroms, and the thickness of the second titanium coating may be, for example, 200 angstroms, the thickness of titanium nitride layer
Degree may be, for example, 200 angstroms.It is derived from the drain electrodes of drain electrode 932a and second of source electrode 931, first 932b.
In order that the source contact openings 921, drain contact hole, the few impurity of cleaning are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 920, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
At the alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then acidic mixed solution using hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 919 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 919；Through Ohm contact electrode window 919, it can be seen that the portion of compound medium layer 920
Divide surface.In this way, the first metal on source contact openings 921 constitutes on the source electrode 931 of device, drain contact hole 922
One metal constitutes the drain electrode 932 of device.Now, in order to be able to clear expression process of the present invention, the device that name is now obtained is
First assembly.
Step 905, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 914.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 914 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 914 can be reduced.That is, reduction source electrode 931, drain electrode 932 and aluminium nitride
Contact resistance between gallium layer 914.
Step 906, by Ohm contact electrode window 919, compound medium layer 920 and aluminum gallium nitride 914 are done
Method is etched, and forms gate contact hole 923, wherein, the bottom in gate contact hole 923 has pre- with the bottom of aluminum gallium nitride 914
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 919, to compound medium layer
920 and partial aluminum gallium nitride 914, dry etching is carried out, and then form on the first device a gate contact hole
923.Wherein, gate contact hole 923 is complete breaks through compound medium layer 920, and through the aluminum gallium nitride 914 of part, makes
The bottom of bottom and the aluminum gallium nitride 914 in gate contact hole 923 be preferably apart from H aluminum gallium nitride 914 half.Enter
One step, cause gate contact hole 923 is presented one wide at the top and narrow at the bottom, inverted trapezoidal during etching.In the present embodiment, formed
After one gate contact hole 923, there can be the impurity things such as impurity, particle and ion in gate contact hole 923, so as to
So that using hydrochloric acid solution cleaning gate contact hole 920, the impurity thing in gate contact hole 920 to be got rid of.
The present embodiment is by after dry etching is carried out to compound medium layer 920, using DHF+SC1+SC2 method
Impurity thing in removal devices；And formed after gate contact hole 923, will be miscellaneous in gate contact hole 923 using hydrochloric acid solution
Matter thing is got rid of.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 923 of compound medium layer, and then
It ensure that the performance of gallium nitride semiconductor device.
Step 907, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 923 and grid
The outward flange deposition Ni/Au of pole contact hole 923 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 933.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 908, a layer insulating 940 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 940.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 931, drain electrode 932 and the presence of grid 933, so that in source electrode 931 and grid
Insulating barrier 940 between pole 933, the insulating barrier 940 between grid 933 and drain electrode 932 are to lower recess, using polishing
Technique is allowed to smooth.
Step 909, after to the progress dry etching of insulating barrier 940 of the top of source contact openings 931, perforate 941 is formed.Institute
Stating grid 933 has the protuberance 933a protruded from outside the gate contact hole 923, and the width of the perforate 941 is less than described
Protuberance 933a width.
Step 9010, the exhausted of the top of gate contact hole 923 is extended in perforate 941 and from source contact openings 931
Field plate metal 950 is deposited in edge layer 940, field plate metal layer 950 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 941 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 921 above outer peripheral first metal in gate contact hole 923
Field plate metal is deposited on 920, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 950.The thickness of field plate metal layer 950
Degree be it is uniform, field plate metal layer 950 at the position of perforate 941 and source contact openings 921 and gate contact hole 923 it
Between position at be, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
This embodiment introduces first drain electrode, second drain electrode structure, i.e., first drain electrode beside introduce one additionally
P-GaN areas (the second drain electrode), p-GaN areas are connected with drain electrode.In OFF state, from p-GaN areas, injected holes is effectively released
Electronics in trap, so as to completely eliminate current collapse effect.The gallium nitride semiconductor device that the present embodiment is obtained can be applied
In the technical fields such as power electronic element, wave filter, radio communication element, have a good application prospect.
As shown in Figure 3 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 1010, compound medium layer 1020, source electrode 1031 and drain electrode 1032, grid 1033, insulating barrier 1040, field plate metal layer
1050th, protective layer 1060.
Wherein, epitaxial layer of gallium nitride 1010 is by silicon (Si) substrate 1012, gallium nitride (GaN) layer 1013 and aluminium gallium nitride alloy
(AlGaN) layer 1014 is constituted, wherein, silicon substrate 1012, gallium nitride layer 1013 and aluminum gallium nitride 1014 are from bottom to top set successively
Put.
Compound medium layer 1020 is arranged on the epitaxial layer of gallium nitride 1010；The compound medium layer of the present embodiment
1020 materials may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and plasma enhancing
Tetraethoxysilance belongs to a kind of high-k (high-k) medium.
Source electrode 1031, drain electrode 1032 and grid 1033 are arranged on the compound medium layer 1020.Specifically, source electrode
1031st, the part as 1032 and the outer image " nail " of grid 1033 that drains is inserted into the compound medium layer 1020, the source
Pole 1031, drain electrode 1032 and grid 1033 extend through the compound medium layer 1020 and connected with the epitaxial layer of gallium nitride 1010
Connect；And a part protrudes from the top of compound medium layer 1020.The source electrode 1031 and/or drain electrode 1032 are by the first metal group
Into；The component of first metal is referring to shown in above-described embodiment.Using the source electrode 1031 of the first metal material formation, drain electrode
1032, can occur instead with the aluminum gallium nitride layer 1014 in the epitaxial layer of gallium nitride 1010 in higher device temperature annealing process
Should, alloy is generated, so that source electrode 1031,1032 contacts with the contact surface of aluminum gallium nitride of drain electrode are well, can be effective
Reduction source electrode 1031, drain electrode 1032 and the contact resistance of aluminum gallium nitride；Avoid the occurrence of the electric leakage of gallium nitride semiconductor device
And the problem of soft breakdown.
Preferably, the grid 1033 is down extended into the aluminum gallium nitride 1014, and the bottom of grid 1033 is arrived
The bottom of aluminum gallium nitride 1014 be preferably apart from H the whole aluminum gallium nitride 1014 half.Grid 1033 is by
Two metals are constituted, and second metal is Ni, Au alloy.
Preferably, the grid 1033 has special configuration.With reference to shown in Fig. 3 b, Fig. 3 c and Fig. 3 d, the present embodiment
Grid 1033 can also have various deformation.Seen according to the observation sequence of gallium nitride semiconductor device from bottom to up, grid 1033
Transverse width gradually increases, and one " upside-down trapezoid " is presented.Further, the part of " upside-down trapezoid " of grid 1033 can be from
Just the shape (as shown in Figure 3 b) uniformly broadened from bottom to up is presented in gate contact hole 1023, compound medium layer 1020 is being higher by
Place has protuberance 1033a, and then increase width causes gate contact hole 1023 is completely covered suddenly；Or can be in aluminium gallium nitride alloy
The part of grid 1033 in layer 1014 still keeps rectangular configuration, is pushed up in aluminum gallium nitride 1014 with up to gate contact hole 1014
The part in portion then uniformly broadens (as shown in Figure 3 c) from bottom to up；Can also be composition can just be in from gate contact hole 1023
The shape (as shown in Figure 3 d) now uniformly broadened from bottom to up, being higher by the protuberance 1033a of compound medium layer 1020, then width is protected
Hold constant, only increase thickness.
Insulating barrier 1040 is arranged at drain electrode 1032, grid 1033 and the top of a part of source electrode 1031, and exposes what is come
On whole compound medium layers 1020, the material of the insulating barrier 1040 is silica.Wherein, insulating barrier 1040 is in whole device
Surface carry out uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 1031, drain electrode 1032, the presence of grid 1033,
Insulating barrier 1040 so as to the insulating barrier 1040 between source electrode 1031 and grid 1033, between grid 1033 and drain electrode 1032
It is, to lower recess, to be allowed to smooth using technique is polished.
It can also for example include field plate metal layer 1050, it is arranged on the insulating barrier 1040.The field plate metal layer
1050 are connected through the insulating barrier 1040 with the source electrode 1031.Preferably, the material of the field plate metal layer 1050 is aluminium
Copper silicon metal level.
Also include matcoveredn 1060, specifically, in field plate metal layer 1050, and the table of the insulating barrier 1040
There is a protective layer 1060 in face, also deposition.The protective layer 1060 includes Si3N4 passivation layers setting up and down and PETEOS is aoxidized
Layer.After the structure for increasing protective layer, impurity absorption can be reduced and quiet with impurity electrostatic in air-isolation and coarse sheath surface
Electro ultrafiltration, reduces surface leakage, so that it is pressure-resistant to improve device.
The section of grid 1033 in above-mentioned gallium nitride semiconductor device is different from " T-shaped " structure of existing grid, but
" trapezoidal " construction of inversion wide at the top and narrow at the bottom is presented, the high electric field at suppressor grid edge is effectively guaranteed gallium nitride high tension apparatus
Stable blocking characteristics, make device after high pressure repeatedly, still can keep good reliability.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 3 e, specific steps include：
Step 1001：Gallium nitride layer 1013 and aluminum gallium nitride 1014 are sequentially depositing on silicon substrate 1012, nitridation is formed
Gallium epitaxial layer 110.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high strike
Wear the characteristics such as electric field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and anti-spoke
According to having stronger advantage under environmental condition, so as to be to study shortwave opto-electronic device and high voltagehigh frequency rate high power device most
Good material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is
1e10~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 110
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 1020.Wherein, silicon nitride
Thickness with plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 1002, dry etching is carried out to the compound medium layer 1020, forms the source contact openings 21 being oppositely arranged
With drain contact hole 1022.
In order that the source contact openings 1021, the few impurity of the cleaning of drain contact hole 1022 are obtained, in addition to removal step.Tool
Body, after dry etching is carried out to compound medium layer 1020, it can first use " DHF (dilute hydrofluoric acid)+chemical
SC-1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
The alkaline mixed solution processing apparatus of hydrogen peroxide and aqua ammonia, then using hydrogen peroxide and the acidic mixed solution of hydrogen chloride
Processing apparatus, and then the impurity thing on the surface of whole device can be removed.
Step 1003, in the present embodiment, in source contact openings 1021 and drain contact hole 1022 and complex media
The first metal 1021 is deposited on the surface of layer 1020.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound is situated between
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 10200 angstroms, second
The thickness of titanium coating may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 1019 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 1019；Through Ohm contact electrode window 1019, it can be seen that compound medium layer 1020
Part surface.In this way, the first metal on source contact openings 1021 constitutes the source electrode 1031 of device, drain contact hole 1022
On the first metal constitute the drain electrode 1032 of device.Now, in order to be able to clear expression process of the present invention, what name was now obtained
Device is first assembly.
Step 1004, the high temperature anneal is carried out to whole first assembly, to pass through first after the etching contacted with each other
Metal forms alloy after being reacted with aluminum gallium nitride 1014.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 1014 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 1014 can be reduced.That is, reduction source electrode 1031, drain electrode 1032 and nitridation
Contact resistance between gallium aluminium layer 14.
Step 1005, by Ohm contact electrode window 1019, compound medium layer 1020 and aluminum gallium nitride 1014 are entered
Row dry etching, forms gate contact hole 1023, wherein, the bottom in gate contact hole 1023 and the bottom of aluminum gallium nitride 1014
With pre-determined distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 1019, to compound medium layer
1020 and partial aluminum gallium nitride 1014, dry etching is carried out, and then form on the first device a gate contact hole
1023.Wherein, gate contact hole 1023 is complete breaks through compound medium layer 1020, and passes through the aluminum gallium nitride of part
1014 so that the bottom in gate contact hole 1023 is preferably aluminum gallium nitride apart from H with the bottom of aluminum gallium nitride 1014
1014 half.Further, cause gate contact hole 1023 is presented one wide at the top and narrow at the bottom, inverted trapezoidal during etching.At this
In embodiment, formed after a gate contact hole 1023, can there is impurity, particle and ion etc. in gate contact hole 1023
Impurity thing, so as to which using hydrochloric acid solution cleaning gate contact hole 1020, the impurity thing in gate contact hole 1020 is removed
Fall.
The present embodiment is by after dry etching is carried out to compound medium layer 1020, using DHF+SC1+SC2 method
Impurity thing in removal devices；And formed after gate contact hole 1023, using hydrochloric acid solution by gate contact hole 1023
Impurity thing is got rid of.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 1023 of compound medium layer,
And then ensure that the performance of gallium nitride semiconductor device.
Step 1006, in the present embodiment, specifically, using magnetron sputtering membrane process, in the He of gate contact hole 1023
The outward flange deposition Ni/Au in gate contact hole 1023 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4
μm；So as to constitute grid 1033.Now, in order to become apparent from expressing present invention, it is second to name the device now obtained
Component.
Step 1007, a layer insulating 1040 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO2) of whole second component, thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 1040.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 1031, drain electrode 1032 and the presence of grid 1033, so that in source electrode 1031
Insulating barrier 1040 between grid 1033, the insulating barrier 1040 between grid 1033 and drain electrode 1032 be to lower recess,
It is allowed to smooth using technique is polished.
Step 1008, after to the progress dry etching of insulating barrier 1040 of the top of source contact openings 1031, perforate is formed
1041.The grid 1033 has the protuberance 1033a protruded from outside the gate contact hole 1023, the width of the perforate 1041
Width of the degree less than the protuberance 1033a.
Step 1009, the top of gate contact hole 1023 is extended in perforate 1041 and from source contact openings 1031
Field plate metal 1050 is deposited on insulating barrier 1040, field plate metal layer 1050 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, in the perforate 1041 and from source electrode
Compound Jie of outer peripheral first metal of contact hole 1021 above outer peripheral first metal in gate contact hole 1023
Field plate metal is deposited on matter layer 1020, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 1050.Field plate metal layer
1050 thickness is uniform, and field plate metal layer 1050 is at the position of perforate 1041 and source contact openings 1021 and grid
At position between contact hole 1023 is, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
Step 1010, using magnetron sputtering membrane process field plate metal layer 1050, the surface of insulating barrier 1040 according to
One silicon nitride layer of secondary deposition and PETEOS oxide layers.
After the structure of the present embodiment increase protective layer, it can be subtracted with impurity electrostatic in air-isolation and coarse sheath surface
Few impurity absorption and electrostatic interaction, reduce surface leakage, so that it is pressure-resistant to improve device.The gallium nitride semiconductor that the present embodiment is obtained
Device can be applied in the technical fields such as power electronic element, wave filter, radio communication element, before good application
Scape.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
1. a kind of gallium nitride semiconductor device, it is characterised in that including：Epitaxial layer of gallium nitride；And,
The compound medium layer on the epitaxial layer of gallium nitride is arranged at, the compound medium layer material is silicon nitride and plasma
Strengthen tetraethoxysilance；
It is arranged at source electrode, drain and gate on the compound medium layer, the source electrode, drain electrode, grid extend through described multiple
Dielectric layer is closed to be connected with the epitaxial layer of gallium nitride；
The insulating barrier on the source electrode, drain and gate and the compound medium layer is arranged at, the material of the insulating barrier is
Silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer is through the insulating barrier and the source
Pole is connected.
In field plate metal layer and the surface of insulating layer, also deposition has a protective layer, and the protection includes stacked on top of one another
Silicon nitride layer and oxide layer.
2. gallium nitride semiconductor device according to claim 1, it is characterised in that the epitaxial layer of gallium nitride includes silicon lining
Bottom, and be arranged at the gallium nitride layer of the surface of silicon, be arranged at the aluminum gallium nitride on the gallium nitride layer surface.
3. gallium nitride semiconductor device according to claim 2, it is characterised in that the grid stretches to the aluminium gallium nitride alloy
In layer.
4. gallium nitride semiconductor device according to claim 2, it is characterised in that the gate bottom to the aluminium gallium nitride alloy
The distance of layer bottom is the half of the aluminum gallium nitride.
5. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the thickness of the compound medium layer
Spend for 2000 angstroms.
6. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the oxide layer is plasma
Body strengthens tetraethoxysilance oxide layer.
7. a kind of preparation method of gallium nitride semiconductor device, it is characterised in that comprise the following steps：
One epitaxial layer of gallium nitride is provided, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, the nitrogen from bottom to top set gradually
Change gallium layer and aluminum gallium nitride；
In the epitaxy of gallium nitride layer surface deposited silicon nitride and plasma enhancing tetraethoxysilance, compound medium layer is formed；
The acquisition of source contact openings and drain contact hole：The compound medium layer is etched, to form separate source contact
Hole and drain contact hole, the source contact openings, the drain contact hole reach the aluminium nitride through the compound medium layer
Gallium layer；In the source contact openings and the drain contact hole and on the surface of the compound medium layer, the first gold medal is deposited
Category, to obtain source electrode, drain electrode；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, to be contained in the source contact openings and the drain contact hole
Interior first metal forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the compound medium layer and the aluminium gallium nitride alloy
Layer carries out dry etching, forms gate contact hole, wherein, the gate contact hole is through the compound medium layer and stretches into described
In aluminum gallium nitride；
The second metalwork is deposited in the outward flange in the gate contact hole and the gate contact hole, to obtain grid, is now obtained
Obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer at least covers described
Perforate and from the source contact openings to the region between the gate contact hole；
In field plate metal layer and the surface of insulating layer, successively deposited silicon nitride layer and the positive silicic acid second of plasma enhancing
Lipid layer, obtains protective layer.
8. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the width of the perforate is small
The protuberance width above the gate contact hole is protruded from the grid.
9. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the high temperature anneal
Step is：Under protection atmosphere, kept for 30~60 seconds at a temperature of 840~850 DEG C.
10. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the gate bottom is arrived
The distance of the aluminum gallium nitride bottom is the half of the aluminum gallium nitride.
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Application publication date: 20171103 |