CN107393962A - Gallium nitride semiconductor device and preparation method thereof - Google Patents
Gallium nitride semiconductor device and preparation method thereof Download PDFInfo
- Publication number
- CN107393962A CN107393962A CN201710488423.6A CN201710488423A CN107393962A CN 107393962 A CN107393962 A CN 107393962A CN 201710488423 A CN201710488423 A CN 201710488423A CN 107393962 A CN107393962 A CN 107393962A
- Authority
- CN
- China
- Prior art keywords
- gallium nitride
- layer
- contact hole
- semiconductor device
- compound medium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 224
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 145
- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000002360 preparation method Methods 0.000 title claims description 16
- 150000001875 compounds Chemical class 0.000 claims abstract description 101
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 82
- 230000004888 barrier function Effects 0.000 claims abstract description 47
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims description 106
- 239000002184 metal Substances 0.000 claims description 106
- 229910045601 alloy Inorganic materials 0.000 claims description 27
- 239000000956 alloy Substances 0.000 claims description 27
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 22
- 238000001312 dry etching Methods 0.000 claims description 22
- 239000010936 titanium Substances 0.000 claims description 22
- 229910052719 titanium Inorganic materials 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 230000002708 enhancing effect Effects 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- 239000004411 aluminium Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 11
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 238000000407 epitaxy Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910017083 AlN Inorganic materials 0.000 claims description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 18
- 238000000034 method Methods 0.000 description 43
- 238000000151 deposition Methods 0.000 description 24
- 239000012535 impurity Substances 0.000 description 17
- 230000008569 process Effects 0.000 description 16
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 15
- 230000008021 deposition Effects 0.000 description 14
- 238000007667 floating Methods 0.000 description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 230000005684 electric field Effects 0.000 description 10
- 238000001755 magnetron sputter deposition Methods 0.000 description 10
- 239000012528 membrane Substances 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 239000011259 mixed solution Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 238000010129 solution processing Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 3
- 230000002378 acidificating effect Effects 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- -1 aluminium copper silicon gold Chemical compound 0.000 description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 239000012895 dilution Substances 0.000 description 3
- 238000010790 dilution Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 3
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/296—Organo-silicon compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention relates to technical field of semiconductor, there is provided a kind of gallium nitride semiconductor device includes：Epitaxial layer of gallium nitride；And it is arranged at the compound medium layer on the epitaxial layer of gallium nitride；Source electrode, the drain and gate being arranged on the compound medium layer, the source electrode, drain and gate extend through the compound medium layer and are connected with the epitaxial layer of gallium nitride；The insulating barrier being arranged on the source electrode, drain and gate and the compound medium layer, the material of the insulating barrier is silica.The gallium nitride semiconductor device of the present invention is less prone to the phenomenon of breakdown aluminum gallium nitride; and then the problem of avoiding the electric leakage and breakdown for gallium nitride semiconductor device occur; gallium nitride semiconductor device is effectively protected, enhances the reliability of gallium nitride semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor technology, more particularly to a kind of gallium nitride semiconductor device and preparation method thereof.
Background technology
Gallium nitride have big energy gap, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, it is corrosion-resistant and
The advantages that radiation resistance, so as to make semi-conducting material using gallium nitride, and obtain gallium nitride semiconductor device.
In the prior art, the preparation method of gallium nitride semiconductor device is：Nitrogen is formed on the surface of epitaxial layer of gallium nitride
SiClx layer, source contact openings and drain contact hole are etched on silicon nitride layer, are deposited in source contact openings and drain contact hole
Metal, so as to form source electrode and drain electrode；Aluminum gallium nitride in etch nitride silicon layer and epitaxial layer of gallium nitride again, form one
Groove, deposited metal layer in a groove, so as to form grid；Then deposited silicon dioxide layer and field plate metal layer, so as to shape
Into gallium nitride semiconductor device.
But in the prior art, because electric field density is larger, so as to can cause gallium nitride semiconductor device electric leakage and
The problem of breakdown, and then gallium nitride semiconductor device can be damaged, reduce the reliability of gallium nitride semiconductor device.Further,
After Hi-pot test repeatedly, the breakdown voltage of device can drift about gallium nitride power device, this nonsteady behavior and electric charge
Trap is relevant, and the reliability of device can be damaged, it should is suppressed.
The content of the invention
To solve the above problems, the present invention provides a kind of gallium nitride semiconductor device, it is characterised in that including：Gallium nitride
Epitaxial layer；And
The compound medium layer being arranged on the epitaxial layer of gallium nitride, the material of the compound medium layer for silicon nitride and wait
Gas ions strengthen tetraethoxysilance；
Source electrode, the drain and gate being arranged on the compound medium layer, the source electrode, drain and gate extend through institute
Compound medium layer is stated to be connected with the epitaxial layer of gallium nitride；Wherein, the grid in the gate contact hole is in inverted trapezoidal；
The insulating barrier being arranged on the source electrode, drain and gate and the compound medium layer, the material of the insulating barrier
Matter is silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer runs through the insulating barrier and institute
State source electrode connection.
The present invention also provides the preparation method of the gallium nitride semiconductor device of this grid with upside-down trapezoid structure, carries
For an epitaxial layer of gallium nitride, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, the gallium nitride layer from bottom to top set gradually
And aluminum gallium nitride；
In the epitaxy of gallium nitride layer surface deposited silicon nitride and plasma enhancing tetraethoxysilance, complex media is formed
Layer；
The acquisition of source contact openings and drain contact hole：The compound medium layer is etched, to form separate source electrode
Contact hole and drain contact hole, the source contact openings, the drain contact hole reach the nitrogen through the compound medium layer
Change gallium aluminium layer；
In the source contact openings and the drain contact hole and on the surface of the compound medium layer, deposition the
One metal, to obtain source electrode, drain electrode；
Photoetching and etching are carried out to first metal, form Ohm contact electrode window；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, connect with to be contained in the source contact openings and the drain electrode
First metal in contact hole forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the compound medium layer and the nitridation
Gallium aluminium layer carries out dry etching, forms gate contact hole, wherein, bottom and the aluminum gallium nitride in the gate contact hole
There is pre-determined distance between bottom；
The second metalwork is deposited in the outward flange in the gate contact hole and the gate contact hole, to obtain grid, this
When obtain the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer at least covers
The perforate and from the source contact openings to the region between the gate contact hole.
Beneficial effect：
The present invention applies a variety of novel materials by the compound medium layer on the surface of epitaxial layer of gallium nitride, also by heavy
The first metal of product is carrying out the high temperature anneal, to be carried out by the first metal after the etching to contact with each other and aluminum gallium nitride
Alloy is formed after reaction, to reduce the contact resistance of the first metal and aluminum gallium nitride after etching；
The invention enables being not easy to leak electricity on the contact surface among compound medium layer and aluminum gallium nitride, also, aluminium gallium nitride alloy
The field strength peak value of layer is higher, is less prone to the phenomenon of breakdown aluminum gallium nitride, and then avoids and gallium nitride semiconductor device occur
Electric leakage and breakdown the problem of, be effectively protected gallium nitride semiconductor device, enhance gallium nitride semiconductor device can
By property.
Brief description of the drawings
Fig. 1 a are the structural representation of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 b are the first metal structure schematic diagram of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 c are the grid structure schematic diagram of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 d are another structural representation of grid of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 e are the another structural representation of grid of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 1 f are the preparation flow schematic diagram of the gallium nitride semiconductor device of the embodiment of the present invention.
Fig. 2 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 2 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 a are the structural representation of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 b are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 c are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 d are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 e are the preparation flow schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in Figure 1a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 110, compound medium layer 120, source electrode 131 and drain electrode 132, grid 133, insulating barrier 140, field plate metal layer 150.
Wherein, epitaxial layer of gallium nitride 110 is by silicon (Si) substrate 112, gallium nitride (GaN) layer 113 and aluminium gallium nitride alloy (AlGaN)
Layer 114 is formed, wherein, silicon substrate 112, gallium nitride layer 113 and aluminum gallium nitride 114 are from bottom to top set gradually.
Compound medium layer 120 is arranged on the epitaxial layer of gallium nitride 110；The compound medium layer 120 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 131, drain electrode 132 and grid 133 are arranged on the compound medium layer 120.Specifically, source electrode 131, drain electrode
132 and the outer image " nail " of grid 133 as a part be inserted into the compound medium layer 120, the source electrode 131, drain electrode
132 and grid 133 extend through the compound medium layer 120 and be connected with the epitaxial layer of gallium nitride 110；And a part protrudes from
The top of compound medium layer 120.The source electrode 131 and/or drain electrode 132 are made up of the first metal；First metal (referring to
Fig. 1 b) include successively from bottom to up：First titanium coating 134, aluminum metal layer 135, the second titanium coating 136 and titanium nitride layer
137.Wherein, the thickness of first titanium coating 134 is 200 angstroms, and the thickness of the aluminum metal layer 135 is 1200 angstroms, described
The thickness of second titanium coating 136 is 200 angstroms, and the thickness of the titanium nitride layer 137 is 200 angstroms.Using the first metal material shape
Into source electrode 131, drain electrode 132, can in higher device temperature annealing process with the aluminum gallium nitride in the epitaxial layer of gallium nitride 110
Layer 114 reacts, and generates alloy, so that source electrode 131, drain electrode 132 are good with the contact of the contact surface of aluminum gallium nitride,
Source electrode 131, drain electrode 132 and the contact resistance of aluminum gallium nitride can be effectively reduced；Avoid the occurrence of gallium nitride semiconductor device
Electric leakage and soft breakdown the problem of.
Preferably, the grid 133 is down extended into the aluminum gallium nitride 114, the bottom of grid 133 to institute
The distance H for stating the bottom of aluminum gallium nitride 114 is preferably the half of the whole aluminum gallium nitride 114.Grid 133 is by the second metal
Composition, second metal is Ni, Au alloy.
Preferably, the grid 133 has special configuration.With reference to shown in Fig. 1 c, Fig. 1 d and Fig. 1 e, the grid of the present embodiment
Pole 133 can also have various deformation.Seen according to the observation sequence of gallium nitride semiconductor device from bottom to up, the transverse direction of grid 133
Width gradually increases, and one " upside-down trapezoid " is presented.Further, the part of " upside-down trapezoid " of grid 133 can be from grid
Just the shape (as illustrated in figure 1 c) uniformly to broaden from bottom to up is presented in contact hole 123, has being higher by compound medium layer 120
Then increase width causes gate contact hole 123 is completely covered protuberance 133a suddenly；Or can be in aluminum gallium nitride 114
The part of grid 133 still keeps rectangular configuration, aluminum gallium nitride 114 with the part at the top of up to gate contact hole 114 then under
It is supreme uniformly to broaden (as shown in Figure 1 d)；It is uniform from bottom to up to can also be that composition can be just presented from gate contact hole 123
The shape (as shown in fig. le) to broaden, being higher by the protuberance 133a of compound medium layer 120, then width keeps constant, only increases thick
Degree.
Insulating barrier 140 is arranged at drain electrode 132, grid 133 and the top of a part of source electrode 131, and exposes the whole come
On compound medium layer 120, the material of the insulating barrier 140 is silica.Wherein, insulating barrier 140 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 131, drain electrode 132, the presence of grid 133, so as in source electrode
Insulating barrier 140 between 131 and grid 133, the insulating barrier 140 between grid 133 and drain electrode 132 be to lower recess, can
It is allowed to smooth using technique is polished.
It can also for example include field plate metal layer 150, it is arranged on the insulating barrier 140.The field plate metal layer 150
It is connected through the insulating barrier 140 with the source electrode 131.Preferably, the material of the field plate metal layer 150 is aluminium copper silicon gold
Belong to layer.
The section of grid 133 in above-mentioned gallium nitride semiconductor device is different from " T-shaped " structure of existing grid, but is in
Existing " trapezoidal " construction of inversion wide at the top and narrow at the bottom, the high electric field at suppressor grid edge, it is steady to be effectively guaranteed gallium nitride high tension apparatus
Fixed blocking characteristics, device is set still to keep good reliability after high pressure repeatedly.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 1 f, specific steps include：
Step 101：Gallium nitride layer 113 and aluminum gallium nitride 114 are sequentially depositing on silicon substrate 112, is formed outside gallium nitride
Prolong layer 110.Gallium nitride is third generation semiconductor material with wide forbidden band, has big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts are per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 110
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 120.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 102, dry etching is carried out to the compound medium layer 120, forms the He of source contact openings 21 being oppositely arranged
Drain contact hole 122.
In order that the source contact openings 121, the few impurity of the cleaning of drain contact hole 122 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 120, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
The alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then using at the acidic mixed solution of hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Step 103, in the present embodiment, in source contact openings 121 and drain contact hole 122 and compound medium layer
The first metal 121 is deposited on 120 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound Jie
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of metal level may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, form Ohm contact electrode window 119.
Carrying out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 119；Through Ohm contact electrode window 119, it can be seen that the portion of compound medium layer 120
Divide surface.In this way, the first metal on source contact openings 121 constitutes the source electrode 131 of device, on drain contact hole 122
One metal constitutes the drain electrode 132 of device.Now, in order to clear expression process of the present invention, the device that name now obtains is
First assembly.
Step 104, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching to contact with each other
Category forms alloy after being reacted with aluminum gallium nitride 114.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so as to which the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 114 on its contact surface, so as to
The contact resistance between the first metal and aluminum gallium nitride 114 can be reduced.That is, source electrode 131, drain electrode 132 and aluminium nitride are reduced
Contact resistance between gallium layer 14.
Step 105, by Ohm contact electrode window 119, compound medium layer 120 and aluminum gallium nitride 114 are done
Method etches, and forms gate contact hole 123, wherein, the bottom in gate contact hole 123 has pre- with the bottom of aluminum gallium nitride 114
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 119, to compound medium layer
120 and partial aluminum gallium nitride 114, dry etching is carried out, and then a gate contact hole is formed on the first device
123.Wherein, gate contact hole 123 completely breaks through compound medium layer 120, and through the aluminum gallium nitride 114 of part, makes
The bottom of bottom and the aluminum gallium nitride 114 in gate contact hole 123 distance H be preferably aluminum gallium nitride 114 half.Enter
One step, it is wide at the top and narrow at the bottom, inverted trapezoidal make it that gate contact hole 123 is presented one during etching.In the present embodiment, formed
After one gate contact hole 123, there can be the impurity things such as impurity, particle and ion in gate contact hole 123, so as to
So that using hydrochloric acid solution cleaning gate contact hole 120, the impurity thing in gate contact hole 120 to be got rid of.
The present embodiment by compound medium layer 120 carry out dry etching after, using DHF+SC1+SC2 method
Impurity thing in removal devices；And formed after gate contact hole 123, will be miscellaneous in gate contact hole 123 using hydrochloric acid solution
Matter thing is got rid of.So as to the cleaning being effectively guaranteed in the surface of compound medium layer and gate contact hole 123, and then
It ensure that the performance of gallium nitride semiconductor device.
Step 106, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 123 and grid
For the outward flange deposition Ni/Au of pole contact hole 123 as the second metal, metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 133.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 107, a layer insulating 140 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface of whole second component deposition layer of silicon dioxide (SiO2), thickness can
For example, 5000 angstroms, silicon dioxide layer is formed as a layer insulating 140.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 131, drain electrode 132 and the presence of grid 133, so as in source electrode 131 and grid
Insulating barrier 140 between pole 133, the insulating barrier 140 between grid 133 and drain electrode 132 are to lower recess, using polishing
Technique is allowed to smooth.
Step 108, after the insulating barrier 140 above source contact openings 131 carries out dry etching, perforate 141 is formed.Institute
Stating grid 33 has the protuberance 133a protruded from outside the gate contact hole 123, and the width of the perforate 141 is less than described convex
Go out portion 133a width.
Step 109, in the insulation that perforate 141 is interior and is extended to from source contact openings 131 above gate contact hole 123
Field plate metal 150 is deposited on layer 140, forms field plate metal layer 150.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 141 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 121 above outer peripheral first metal in gate contact hole 123
Field plate metal is deposited on 120, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 150.The thickness of field plate metal layer 150
Degree be it is uniform, field plate metal layer 150 opening position and source contact openings 121 and the gate contact hole 123 of perforate 141 it
Between opening position be to lower recess, pass through polishing technique and can be allowed to smooth in subsequent step.
The present embodiment replaces existing silicon oxide layer by depositing compound medium layer on the surface of epitaxy of gallium nitride substrate
As compound medium layer；The high temperature anneal technique is recycled, makes the aluminum gallium nitride in source electrode, drain electrode and epitaxial layer of gallium nitride
Alloy is formed after being reacted, so that source electrode, drain electrode contact with the contact surface of aluminum gallium nitride are good, can be effective
The contact resistance for reducing source electrode, drain electrode and aluminum gallium nitride；Avoid the occurrence of the electric leakage of gallium nitride semiconductor device and soft hit
The problem of wearing.Further, the field plate metal layer of formation, make to be not easy on the contact surface among compound medium layer and aluminum gallium nitride
Electric leakage, also, the field strength peak value of aluminum gallium nitride is higher, is less prone to the phenomenon of breakdown aluminum gallium nitride, and then avoid out
The problem of electric leakage and breakdown of existing gallium nitride semiconductor device, gallium nitride semiconductor device is effectively protected, enhances nitrogen
Change the reliability of gallium semiconductor devices.The gallium nitride semiconductor device that the present embodiment obtains can be applied to power electronic element, filter
In the technical fields such as ripple device, radio communication element, have a good application prospect.
As shown in Figure 2 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 610, compound medium layer 620, source electrode 631 and drain electrode 632, grid 633, insulating barrier 640, field plate metal layer 650.
Wherein, epitaxial layer of gallium nitride 610 is by silicon (Si) substrate 612, gallium nitride (GaN) layer 613 and aluminium gallium nitride alloy (AlGaN)
Layer 614 is formed, wherein, silicon substrate 612, gallium nitride layer 613 and aluminum gallium nitride 614 are from bottom to top set gradually.
Compound medium layer 620 is arranged on the epitaxial layer of gallium nitride 610；The compound medium layer 620 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 631, drain electrode 632 and grid 633 are arranged on the compound medium layer 620.Specifically, source electrode 631, drain electrode
632 and the outer image " nail " of grid 633 as a part be inserted into the compound medium layer 620, the source electrode 631, drain electrode
632 and grid 633 extend through the compound medium layer 620 and be connected with the epitaxial layer of gallium nitride 610；And a part protrudes from
The top of compound medium layer 620.The source electrode 631 and/or drain electrode 632 by the first metal form and above-described embodiment shown in.
Using the first metal material formed source electrode 631, drain electrode 632, can in higher device temperature annealing process with outside the gallium nitride
The aluminum gallium nitride layer 614 prolonged in layer 610 reacts, and generates alloy, so that source electrode 631, drain electrode 632 and aluminium gallium nitride alloy
The contact of the contact surface of layer is good, can effectively reduce source electrode 631, drain electrode 632 and the contact resistance of aluminum gallium nitride；Avoid
There is the problem of electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, the grid 633 is down extended into the aluminum gallium nitride 614 and gone directly to the aluminium gallium nitride alloy
614 bottom of layer, obtain one " penetrating type grid ".Grid 633 is made up of the second metal, and second metal is Ni, Au alloy.
Insulating barrier 640 is arranged at drain electrode 632, grid 633 and the top of a part of source electrode 631, and exposes the whole come
On compound medium layer 620, the material of the insulating barrier 640 is silica.Wherein, insulating barrier 640 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 631, drain electrode 632, the presence of grid 633, so as in source electrode
Insulating barrier 640 between 631 and grid 633, the insulating barrier 640 between grid 633 and drain electrode 632 be to lower recess, can
It is allowed to smooth using technique is polished.
It can also for example include field plate metal layer 650, it is arranged on the insulating barrier 640.The field plate metal layer 650
It is connected through the insulating barrier 640 with the source electrode 631.Preferably, the material of the field plate metal layer 650 is aluminium copper silicon gold
Belong to layer.
Grid 633 in above-mentioned gallium nitride semiconductor device penetrates whole aluminum gallium nitride and reaches gallium nitride layer, can suppress
The high electric field of gate edge, the stable blocking characteristics of gallium nitride high tension apparatus are effectively guaranteed, make device repeatedly high in process
After pressure, good reliability can be still kept.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 2 b, specific steps include：
Step 601：Gallium nitride layer 613 and aluminum gallium nitride 614 are sequentially depositing on silicon substrate 612, is formed outside gallium nitride
Prolong layer 610.Gallium nitride is third generation semiconductor material with wide forbidden band, has big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts are per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 610
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 620.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 602, dry etching is carried out to the compound medium layer 620, forms the He of source contact openings 21 being oppositely arranged
Drain contact hole 622.
In order that the source contact openings 621, the few impurity of the cleaning of drain contact hole 622 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 620, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
The alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then using at the acidic mixed solution of hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Step 603, in the present embodiment, in source contact openings 621 and drain contact hole 622 and compound medium layer
The first metal 621 is deposited on 620 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound Jie
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 6200 angstroms, the second titanium
The thickness of metal level may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, form Ohm contact electrode window 619.
Carrying out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 619；Through Ohm contact electrode window 619, it can be seen that the portion of compound medium layer 620
Divide surface.In this way, the first metal on source contact openings 621 constitutes the source electrode 631 of device, on drain contact hole 622
One metal constitutes the drain electrode 632 of device.Now, in order to clear expression process of the present invention, the device that name now obtains is
First assembly.
Step 604, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching to contact with each other
Category forms alloy after being reacted with aluminum gallium nitride 614.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so as to which the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 614 on its contact surface, so as to
The contact resistance between the first metal and aluminum gallium nitride 614 can be reduced.That is, source electrode 631, drain electrode 632 and aluminium nitride are reduced
Contact resistance between gallium layer 14.
Step 605, by Ohm contact electrode window 619, compound medium layer 620 and aluminum gallium nitride 614 are done
Method etches, and forms gate contact hole 623, wherein, the bottom in gate contact hole 623 has pre- with the bottom of aluminum gallium nitride 614
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 619, to compound medium layer
620 and partial aluminum gallium nitride 614, dry etching is carried out, and then a gate contact hole is formed on the first device
623.Wherein, gate contact hole 623 completely breaks through compound medium layer 620, and through the aluminum gallium nitride 614 of part, makes
The bottom of bottom and the aluminum gallium nitride 614 in gate contact hole 623 distance H be preferably aluminum gallium nitride 614 half.
In the present embodiment, formed after a gate contact hole 623, can there is impurity, particle in gate contact hole 623
And the impurity thing such as ion, will be miscellaneous in gate contact hole 620 so as to clean gate contact hole 620 using hydrochloric acid solution
Matter thing is got rid of.
The present embodiment by compound medium layer 620 carry out dry etching after, using DHF+SC1+SC2 method
Impurity thing in removal devices；And formed after gate contact hole 623, will be miscellaneous in gate contact hole 623 using hydrochloric acid solution
Matter thing is got rid of.So as to the cleaning being effectively guaranteed in the surface of compound medium layer and gate contact hole 623, and then
It ensure that the performance of gallium nitride semiconductor device.
Step 606, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 623 and grid
For the outward flange deposition Ni/Au of pole contact hole 623 as the second metal, metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 633.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 607, a layer insulating 640 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface of whole second component deposition layer of silicon dioxide (SiO2), thickness can
For example, 5000 angstroms, silicon dioxide layer is formed as a layer insulating 640.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 631, drain electrode 632 and the presence of grid 633, so as in source electrode 631 and grid
Insulating barrier 640 between pole 633, the insulating barrier 640 between grid 633 and drain electrode 632 are to lower recess, using polishing
Technique is allowed to smooth.
Step 608, after the insulating barrier 640 above source contact openings 631 carries out dry etching, perforate 641 is formed.Institute
Stating grid 33 has the protuberance 633a protruded from outside the gate contact hole 623, and the width of the perforate 641 is less than described convex
Go out portion 633a width.
Step 609, in the insulation that perforate 641 is interior and is extended to from source contact openings 631 above gate contact hole 623
Field plate metal 650 is deposited on layer 640, forms field plate metal layer 650.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 641 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 621 above outer peripheral first metal in gate contact hole 623
Field plate metal is deposited on 620, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 650.The thickness of field plate metal layer 650
Degree be it is uniform, field plate metal layer 650 opening position and source contact openings 621 and the gate contact hole 623 of perforate 641 it
Between opening position be to lower recess, pass through polishing technique and can be allowed to smooth in subsequent step.
The present embodiment replaces existing silicon oxide layer by depositing compound medium layer on the surface of epitaxy of gallium nitride substrate
As compound medium layer；The high temperature anneal technique is recycled, makes the aluminum gallium nitride in source electrode, drain electrode and epitaxial layer of gallium nitride
Alloy is formed after being reacted, so that source electrode, drain electrode contact with the contact surface of aluminum gallium nitride are good, can be effective
The contact resistance for reducing source electrode, drain electrode and aluminum gallium nitride；Avoid the occurrence of the electric leakage of gallium nitride semiconductor device and soft hit
The problem of wearing.Further, the structure of grid is optimized so that grid penetrates whole aluminum gallium nitride, it is compatible with CMOS technology line,
Electric Field Distribution is adjusted, the pressure-resistant of device is improved with this.The gallium nitride semiconductor device that the present embodiment obtains can be applied to electric power
In the technical fields such as electronic component, wave filter, radio communication element, have a good application prospect.
As shown in Figure 3 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 710, compound medium layer 720, source electrode 731 and drain electrode 732, grid 733, floating plate 729, insulating barrier 740, field plate gold
Belong to layer 750.
Wherein, epitaxial layer of gallium nitride 710 is by silicon (Si) substrate 712, gallium nitride (GaN) layer 713 and aluminium gallium nitride alloy (AlGaN)
Layer 714 is formed, wherein, silicon substrate 712, gallium nitride layer 713 and aluminum gallium nitride 714 are from bottom to top set gradually.
Compound medium layer 720 is arranged on the epitaxial layer of gallium nitride 710；The compound medium layer 720 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 731, drain electrode 732 and grid 733 are arranged on the compound medium layer 720.Specifically, source electrode 731, drain electrode
732 and the outer image " nail " of grid 733 as a part be inserted into the compound medium layer 720, the source electrode 731, drain electrode 732
The compound medium layer 720 is extended through with grid 733 to be connected with the epitaxial layer of gallium nitride 710；And a part protrudes from institute
State the top of compound medium layer 720.The source electrode 731 and/or drain electrode 732 by the first metal form and above-described embodiment shown in.Adopt
With the first metal material formed source electrode 731, drain electrode 732, can in higher device temperature annealing process with the epitaxy of gallium nitride
Aluminum gallium nitride layer 714 in layer 710 reacts, and generates alloy, so that source electrode 731, drain electrode 732 and aluminum gallium nitride
Contact surface contact it is good, source electrode 731, drain electrode 732 and the contact resistances of aluminum gallium nitride can be effectively reduced；Avoid out
The problem of electric leakage and soft breakdown of existing gallium nitride semiconductor device.
Preferably, the grid 733 is down extended into the aluminum gallium nitride 714, the bottom of grid 733 to institute
The distance H for stating the bottom of aluminum gallium nitride 714 is preferably the half of the whole aluminum gallium nitride 714.Grid 733 is by the second metal
Composition, second metal is Ni, Au alloy.
Preferably, the grid 733 has special configuration.With reference to shown in Fig. 3 b, Fig. 3 c and Fig. 3 d, the grid of the present embodiment
Pole 733 can also have various deformation.Seen according to the observation sequence of gallium nitride semiconductor device from bottom to up, the transverse direction of grid 733
Width gradually increases, and one " upside-down trapezoid " is presented.Further, the part of " upside-down trapezoid " of grid 733 can be from grid
Just the shape (as shown in Figure 3 b) uniformly to broaden from bottom to up is presented in contact hole 723, has being higher by compound medium layer 720
Then increase width causes gate contact hole 723 is completely covered protuberance 733a suddenly；Or can be in aluminum gallium nitride 714
The part of grid 733 still keeps rectangular configuration, aluminum gallium nitride 714 with the part at the top of up to gate contact hole 714 then under
It is supreme uniformly to broaden (as shown in Figure 3 c)；It is uniform from bottom to up to can also be that composition can be just presented from gate contact hole 723
The shape (as shown in Figure 3 d) to broaden, being higher by the protuberance 733a of compound medium layer 720, then width keeps constant, only increases thick
Degree.
Further, including several floating field plates 729 for being arranged on the compound medium layer 720, the floating field
Plate 729 is connected through the compound medium layer 720 with the epitaxial layer of gallium nitride 710, and the floating field plate 729 is independently arranged
Between the source electrode 731, drain electrode 732 and it is presented ring-type.
The height of each floating field plate 729 is preferably 0.25~6 micron.
Insulating barrier 740 is arranged at drain electrode 732, grid 733 and the top of a part of source electrode 731, and exposes the whole come
On compound medium layer 720, the material of the insulating barrier 740 is silica.Wherein, insulating barrier 740 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 731, drain electrode 732, the presence of grid 733, so as in source electrode
Insulating barrier 740 between 731 and grid 733, the insulating barrier 740 between grid 733 and drain electrode 732 be to lower recess, can
It is allowed to smooth using technique is polished.
It can also for example include field plate metal layer 750, it is arranged on the insulating barrier 740.The field plate metal layer 750
It is connected through the insulating barrier 740 with the source electrode 731.Preferably, the material of the field plate metal layer 750 is aluminium copper silicon gold
Belong to layer.
The section of grid 733 in above-mentioned gallium nitride semiconductor device is different from " T-shaped " structure of existing grid, but is in
Existing " trapezoidal " construction of inversion wide at the top and narrow at the bottom, the high electric field at suppressor grid edge, it is steady to be effectively guaranteed gallium nitride high tension apparatus
Fixed blocking characteristics, device is set still to keep good reliability after high pressure repeatedly.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 3 e, specific steps include：
Step 701：Gallium nitride layer 713 and aluminum gallium nitride 714 are sequentially depositing on silicon substrate 712, is formed outside gallium nitride
Prolong layer 710.Gallium nitride is third generation semiconductor material with wide forbidden band, has big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts are per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 710
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 720.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 702, dry etching is carried out to the compound medium layer 720, forms the He of source contact openings 721 being oppositely arranged
Drain contact hole 722 and multiple floating field plate contact holes 725；Again the pole contact hole 721 and drain contact hole 722,
And the first metal of deposition forms corresponding electrode in multiple floating field plate contact holes 725.
First, drain contact hole 722 is first opened up on compound medium layer 720；Then magnetron sputtering plating work can be used
Skill, in drain contact hole and on the surface of compound medium layer, it is sequentially depositing the first titanium coating, aluminum metal layer, the second titanium
Metal level and titanium nitride layer, to form the first metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, aluminum metal layer
Thickness may be, for example, 1200 angstroms, the thickness of the second titanium coating may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example,
200 angstroms.Form drain electrode.
Step 7031, then in source contact openings 721 and the table of the compound medium layer 720 of multiple floating field plate contact holes 725
The first metal is deposited on face.
Similarly, magnetron sputtering membrane process can be used, in source contact openings and multiple floating field plate contact holes
725th, on the surface of part compound medium layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride are sequentially depositing
Layer, to form the first metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer can be such as
For 1200 angstroms, the thickness of the second titanium coating may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.Thus, obtain
Obtain source electrode 731 and floating field plate 735.
Wherein, the length of each floating field plate 735 may be, for example, 0.25~6 micron.
In order that obtain the source contact openings 721, drain contact hole 722, the cleaning of multiple floating field plate contact holes 725 less
Impurity, in addition to removal step.Specifically, after dry etching is carried out to compound medium layer 720, " DHF can be first used
(dilute hydrofluoric acid)+chemical SC-1+ chemicals SC-2 " method, for example, can be first using the hydrogen fluorine after dilution
Acid solution processing apparatus, then using hydrogen peroxide and the alkaline mixed solution processing apparatus of aqua ammonia, then using peroxidating
The acidic mixed solution processed device of hydrogen and hydrogen chloride, and then the impurity thing on the surface of whole device can be removed.
Photoetching and etching are carried out to the first metal, form Ohm contact electrode window 719.
Carrying out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 719；Through Ohm contact electrode window 719, it can be seen that the portion of compound medium layer 720
Divide surface.In this way, the first metal on source contact openings 721 constitutes the source electrode 731 of device, on drain contact hole 722
One metal constitutes the drain electrode 732 of device.Now, in order to clear expression process of the present invention, the device that name now obtains is
First assembly.
Step 704, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching to contact with each other
Category forms alloy after being reacted with aluminum gallium nitride 714.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so as to which the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 714 on its contact surface, so as to
The contact resistance between the first metal and aluminum gallium nitride 714 can be reduced.That is, source electrode 731, drain electrode 732 and aluminium nitride are reduced
Contact resistance between gallium layer 14.
Step 705, by Ohm contact electrode window 719, compound medium layer 720 and aluminum gallium nitride 714 are done
Method etches, and forms gate contact hole 723, wherein, the bottom in gate contact hole 723 has pre- with the bottom of aluminum gallium nitride 714
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 719, to compound medium layer
720 and partial aluminum gallium nitride 714, dry etching is carried out, and then a gate contact hole is formed on the first device
723.Wherein, gate contact hole 723 completely breaks through compound medium layer 720, and through the aluminum gallium nitride 714 of part, makes
The bottom of bottom and the aluminum gallium nitride 714 in gate contact hole 723 distance H be preferably aluminum gallium nitride 714 half.Enter
One step, it is wide at the top and narrow at the bottom, inverted trapezoidal make it that gate contact hole 723 is presented one during etching.In the present embodiment, formed
After one gate contact hole 723, there can be the impurity things such as impurity, particle and ion in gate contact hole 723, so as to
So that using hydrochloric acid solution cleaning gate contact hole 720, the impurity thing in gate contact hole 720 to be got rid of.
The present embodiment by compound medium layer 720 carry out dry etching after, using DHF+SC1+SC2 method
Impurity thing in removal devices；And formed after gate contact hole 723, will be miscellaneous in gate contact hole 723 using hydrochloric acid solution
Matter thing is got rid of.So as to the cleaning being effectively guaranteed in the surface of compound medium layer and gate contact hole 723, and then
It ensure that the performance of gallium nitride semiconductor device.
Step 706, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 723 and grid
For the outward flange deposition Ni/Au of pole contact hole 723 as the second metal, metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 733.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 707, a layer insulating 740 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface of whole second component deposition layer of silicon dioxide (SiO2), thickness can
For example, 5000 angstroms, silicon dioxide layer is formed as a layer insulating 740.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 731, drain electrode 732 and the presence of grid 733, so as in source electrode 731 and grid
Insulating barrier 740 between pole 733, the insulating barrier 740 between grid 733 and drain electrode 732 are to lower recess, using polishing
Technique is allowed to smooth.
Step 708, after the insulating barrier 740 above source contact openings 731 carries out dry etching, perforate 741 is formed.Institute
Stating grid 33 has the protuberance 733a protruded from outside the gate contact hole 723, and the width of the perforate 741 is less than described convex
Go out portion 733a width.
Step 709, in the insulation that perforate 741 is interior and is extended to from source contact openings 731 above gate contact hole 723
Field plate metal 750 is deposited on layer 740, forms field plate metal layer 750.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 741 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 721 above outer peripheral first metal in gate contact hole 723
Field plate metal is deposited on 720, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 750.The thickness of field plate metal layer 750
Degree be it is uniform, field plate metal layer 750 opening position and source contact openings 721 and the gate contact hole 723 of perforate 741 it
Between opening position be to lower recess, pass through polishing technique and can be allowed to smooth in subsequent step.
The present embodiment replaces existing silicon oxide layer by depositing compound medium layer on the surface of epitaxy of gallium nitride substrate
As compound medium layer；The high temperature anneal technique is recycled, makes the aluminum gallium nitride in source electrode, drain electrode and epitaxial layer of gallium nitride
Alloy is formed after being reacted, so that source electrode, drain electrode contact with the contact surface of aluminum gallium nitride are good, can be effective
The contact resistance for reducing source electrode, drain electrode and aluminum gallium nitride；Avoid the occurrence of the electric leakage of gallium nitride semiconductor device and soft hit
The problem of wearing.Further, with reference to the becket of floating, by the becket of this floating, exhausting for power device is extended
Area, the electric-field intensity of main schottky junction is reduced, it is pressure-resistant so as to improve device.The gallium nitride semiconductor device that the present embodiment obtains
It can be applied in the technical fields such as power electronic element, wave filter, radio communication element, have a good application prospect.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
- A kind of 1. gallium nitride semiconductor device, it is characterised in that including：Epitaxial layer of gallium nitride；AndThe compound medium layer being arranged on the epitaxial layer of gallium nitride, the compound medium layer material are silicon nitride and plasma Strengthen tetraethoxysilance；Source electrode, the drain and gate being arranged on the compound medium layer, the source electrode, drain electrode, grid extend through described multiple Dielectric layer is closed to be connected with the epitaxial layer of gallium nitride；Wherein, institute's grid is upside-down trapezoid structure；The insulating barrier being arranged on the source electrode, drain and gate and the compound medium layer, the material of the insulating barrier are Silica；Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer is through the insulating barrier and the source Pole connects.
- 2. gallium nitride semiconductor device according to claim 1, it is characterised in that the epitaxial layer of gallium nitride serves as a contrast including silicon Bottom, and be arranged at the gallium nitride layer of the surface of silicon, be arranged at the aluminum gallium nitride on the gallium nitride layer surface.
- 3. gallium nitride semiconductor device according to claim 2, it is characterised in that the grid stretches to the aluminium gallium nitride alloy In layer.
- 4. gallium nitride semiconductor device according to claim 2, it is characterised in that the gate bottom to the aluminium gallium nitride alloy The distance of layer bottom is the half of the aluminum gallium nitride.
- 5. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the thickness of the compound medium layer Spend for 2000 angstroms.
- 6. a kind of preparation method of gallium nitride semiconductor device, it is characterised in that comprise the following steps：One epitaxial layer of gallium nitride is provided, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, the nitrogen from bottom to top set gradually Change gallium layer and aluminum gallium nitride；In the epitaxy of gallium nitride layer surface deposited silicon nitride and plasma enhancing tetraethoxysilance, compound medium layer is formed；The acquisition of source contact openings and drain contact hole：The compound medium layer is etched, to form separate source contact Hole and drain contact hole, the source contact openings, the drain contact hole reach the aluminium nitride through the compound medium layer Gallium layer；In the source contact openings and the drain contact hole and on the surface of the compound medium layer, the first gold medal is deposited Category, to obtain source electrode, drain electrode；Photoetching and etching are carried out to first metal, form Ohm contact electrode window；Now obtain first assembly；The high temperature anneal is carried out to the first assembly, to be contained in the source contact openings and the drain contact hole Interior first metal forms alloy and reacted with the aluminum gallium nitride；The acquisition in gate contact hole：By the Ohm contact electrode window, to the compound medium layer and the aluminium gallium nitride alloy Layer carries out dry etching, forms gate contact hole, wherein, the gate contact hole is through the compound medium layer and stretches into described In aluminum gallium nitride；The second metalwork is deposited in the outward flange in the gate contact hole and the gate contact hole, to obtain grid, is now obtained Obtain the second component；A layer insulating is deposited on the surface of second component；Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer at least covers described Perforate and from the source contact openings to the region between the gate contact hole.
- 7. the preparation method of gallium nitride semiconductor device according to claim 6, it is characterised in that the width of the perforate is small In the protuberance width that the grid is protruded from above the gate contact hole.
- 8. the preparation method of gallium nitride semiconductor device according to claim 6, it is characterised in that the high temperature anneal Step is：In the case where protecting atmosphere, kept for 30~60 seconds at a temperature of 840~850 DEG C.
- 9. the preparation method of gallium nitride semiconductor device according to claim 6, it is characterised in that the gate bottom to institute The distance for stating aluminum gallium nitride bottom is the half of the aluminum gallium nitride.
- 10. the preparation method of gallium nitride semiconductor device according to claim 6, it is characterised in that the source electrode and/or leakage Pole is made up of the first metal；First metal includes successively from bottom to up：First titanium coating, aluminum metal layer, the second titanium Belong to layer and titanium nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710488423.6A CN107393962A (en) | 2017-06-23 | 2017-06-23 | Gallium nitride semiconductor device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710488423.6A CN107393962A (en) | 2017-06-23 | 2017-06-23 | Gallium nitride semiconductor device and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107393962A true CN107393962A (en) | 2017-11-24 |
Family
ID=60333665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710488423.6A Pending CN107393962A (en) | 2017-06-23 | 2017-06-23 | Gallium nitride semiconductor device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107393962A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019109747A1 (en) * | 2017-12-07 | 2019-06-13 | 华南理工大学 | Ohmic contact preparation method for gallium nitride electronic device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040144991A1 (en) * | 2003-01-15 | 2004-07-29 | Fujitsu Limited | Compound semiconductor device and method for fabricating the same |
| CN103000673A (en) * | 2011-09-09 | 2013-03-27 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
| CN104934476A (en) * | 2014-03-19 | 2015-09-23 | 株式会社东芝 | Semiconductor device and manufacturing method for the same |
| CN105720097A (en) * | 2016-04-28 | 2016-06-29 | 中国科学院半导体研究所 | Enhanced-mode high electron mobility transistor, preparation method thereof, and semiconductor device |
| CN106601809A (en) * | 2015-10-15 | 2017-04-26 | 北京大学 | Gallium-nitride field effect transistor and manufacturing method therefor |
| CN106601806A (en) * | 2015-10-15 | 2017-04-26 | 北京大学 | Semiconductor device and manufacture method thereof |
-
2017
- 2017-06-23 CN CN201710488423.6A patent/CN107393962A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040144991A1 (en) * | 2003-01-15 | 2004-07-29 | Fujitsu Limited | Compound semiconductor device and method for fabricating the same |
| CN103000673A (en) * | 2011-09-09 | 2013-03-27 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
| CN104934476A (en) * | 2014-03-19 | 2015-09-23 | 株式会社东芝 | Semiconductor device and manufacturing method for the same |
| CN106601809A (en) * | 2015-10-15 | 2017-04-26 | 北京大学 | Gallium-nitride field effect transistor and manufacturing method therefor |
| CN106601806A (en) * | 2015-10-15 | 2017-04-26 | 北京大学 | Semiconductor device and manufacture method thereof |
| CN105720097A (en) * | 2016-04-28 | 2016-06-29 | 中国科学院半导体研究所 | Enhanced-mode high electron mobility transistor, preparation method thereof, and semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019109747A1 (en) * | 2017-12-07 | 2019-06-13 | 华南理工大学 | Ohmic contact preparation method for gallium nitride electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106601809A (en) | Gallium-nitride field effect transistor and manufacturing method therefor | |
| US20210384339A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN107331697A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107230625A (en) | Gallium nitride transistor and its manufacture method | |
| CN107275385A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107316892A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107393962A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107331696A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN207116436U (en) | Gallium nitride semiconductor device | |
| CN107316891A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107293578A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107316894A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107275386A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107293577A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107293576B (en) | Gallium nitride semiconductor device and method for manufacturing same | |
| CN107437560A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107316893A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107316895A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN108831923A (en) | A kind of enhancement type high electron mobility transistor and preparation method thereof | |
| CN107275384A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107248524A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107230614A (en) | The preparation method of gallium nitride semiconductor device | |
| CN107316890A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107248526A (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN107393963A (en) | Gallium nitride semiconductor device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171124 |
|
| RJ01 | Rejection of invention patent application after publication |