CN107248525A - Gallium nitride semiconductor device and preparation method thereof - Google Patents
Gallium nitride semiconductor device and preparation method thereof Download PDFInfo
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- CN107248525A CN107248525A CN201710488399.6A CN201710488399A CN107248525A CN 107248525 A CN107248525 A CN 107248525A CN 201710488399 A CN201710488399 A CN 201710488399A CN 107248525 A CN107248525 A CN 107248525A
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- gallium nitride
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- dielectric layer
- contact hole
- gate
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 190
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 123
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000002360 preparation method Methods 0.000 title claims description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 95
- 239000002184 metal Substances 0.000 claims abstract description 95
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 70
- 230000004888 barrier function Effects 0.000 claims abstract description 47
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910000449 hafnium oxide Inorganic materials 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 25
- 238000001312 dry etching Methods 0.000 claims description 23
- 229910045601 alloy Inorganic materials 0.000 claims description 22
- 239000000956 alloy Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 13
- 229910052733 gallium Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- 239000004411 aluminium Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- 230000008859 change Effects 0.000 claims description 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 238000000034 method Methods 0.000 description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 31
- 238000000151 deposition Methods 0.000 description 18
- 239000012535 impurity Substances 0.000 description 18
- 230000008569 process Effects 0.000 description 16
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical group Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 15
- 239000000377 silicon dioxide Substances 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 12
- 239000010931 gold Substances 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- 229910052719 titanium Inorganic materials 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 11
- 230000008021 deposition Effects 0.000 description 11
- 238000004140 cleaning Methods 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 238000001755 magnetron sputter deposition Methods 0.000 description 8
- 239000012528 membrane Substances 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000005684 electric field Effects 0.000 description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 239000011259 mixed solution Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000010129 solution processing Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical group O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 229910017083 AlN Inorganic materials 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 230000002378 acidificating effect Effects 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- -1 aluminium copper silicon gold Chemical compound 0.000 description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000012459 cleaning agent Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 239000012895 dilution Substances 0.000 description 3
- 238000010790 dilution Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
Include the present invention relates to technical field of semiconductor there is provided a kind of gallium nitride semiconductor device：Epitaxial layer of gallium nitride；And, it is arranged at the hafnium oxide dielectric layer on the epitaxial layer of gallium nitride；Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain and gate extend through the dielectric layer and be connected with the epitaxial layer of gallium nitride；It is arranged at the insulating barrier on the source electrode, drain and gate and the dielectric layer, and the field plate metal layer being arranged on the insulating barrier.The gallium nitride semiconductor device of the present invention is less prone to the phenomenon for puncturing aluminum gallium nitride; and then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture; gallium nitride semiconductor device is effectively protected, the reliability of gallium nitride semiconductor device is enhanced.
Description
Technical field
The present invention relates to field of semiconductor technology, more particularly to a kind of gallium nitride semiconductor device and preparation method thereof.
Background technology
Gallium nitride have big energy gap, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, it is corrosion-resistant and
The advantages of radiation resistance, so as to make semi-conducting material using gallium nitride, and obtain gallium nitride semiconductor device.
In the prior art, the preparation method of gallium nitride semiconductor device is：Nitrogen is formed on the surface of epitaxial layer of gallium nitride
SiClx layer, etches on silicon nitride layer and is deposited in source contact openings and drain contact hole, source contact openings and drain contact hole
Metal, so as to form source electrode and drain electrode；The aluminum gallium nitride in etch nitride silicon layer and epitaxial layer of gallium nitride, forms one again
Groove, in a groove deposited metal layer, so as to form grid；Then deposited silicon dioxide layer and field plate metal layer so that shape
Into gallium nitride semiconductor device.
But in the prior art, because electric field density is larger, thus can cause gallium nitride semiconductor device electric leakage and
The problem of puncturing, and then gallium nitride semiconductor device can be damaged, reduce the reliability of gallium nitride semiconductor device.Further,
In order to obtain high performance gallium nitride transistor, the improvement of conducting resistance is very important.In total conducting resistance, 80%
Resistance is non-grid region and grid region resistance, and 20% resistance is Ohmic contact and the resistance being indirectly connected with.
The content of the invention
To solve the above problems, the present invention provides a kind of gallium nitride semiconductor device with gate dielectric layer, including：Nitridation
Gallium epitaxial layer；And,
It is arranged at the dielectric layer on the epitaxial layer of gallium nitride；
Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain and gate, which are extended through, to be given an account of
Matter layer is connected with the epitaxial layer of gallium nitride；Wherein, there is gate dielectric layer between the grid and the epitaxial layer of gallium nitride；
The insulating barrier on the source electrode, drain and gate and the dielectric layer is arranged at, the material of the insulating barrier is
Silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer runs through the insulating barrier and institute
State source electrode connection.
The present invention also provides the preparation method of this gallium nitride semiconductor device there is provided an epitaxial layer of gallium nitride, wherein, institute
State layer-of-substrate silicon, gallium nitride layer and aluminum gallium nitride that epitaxial layer of gallium nitride includes from bottom to top setting gradually；
In the epitaxy of gallium nitride layer surface deposit hafnium oxides, dielectric layer is formed, the dielectric layer material is hafnium oxide；
The acquisition of source contact openings and drain contact hole：The dielectric layer is etched, to form separate source contact
Hole and drain contact hole, the source contact openings, the drain contact hole reach the aluminum gallium nitride through the dielectric layer；
In the source contact openings and the drain contact hole and on the surface of the dielectric layer, the first gold medal is deposited
Category, to obtain source electrode, drain electrode；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, connect with to be contained in the source contact openings and the drain electrode
First metal in contact hole forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the dielectric layer and the aluminium gallium nitride alloy
Layer carries out dry etching, forms gate contact hole, wherein, the bottom in the gate contact hole and the bottom of the aluminum gallium nitride
Between have pre-determined distance；
First deposited silicon nitride is used as gate dielectric layer in the gate contact hole；Then again on the gate dielectric layer, institute
The outward flange for stating gate contact hole deposits the second metalwork, to obtain grid, now obtains the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer is at least covered
The perforate and from the source contact openings to the region between the gate contact hole.
Beneficial effect：
The present invention applies novel materials by the dielectric layer on the surface of epitaxial layer of gallium nitride, also by depositing the first gold medal
Category is carrying out the high temperature anneal, after being reacted by the first metal after the etching contacted with each other and aluminum gallium nitride
Alloy is formed, to reduce the contact resistance of the first metal and aluminum gallium nitride after etching；
The present embodiment introduces gate dielectric layer can be with optimised devices manufacture craft, optimised devices work compatible with CMOS technology line
Skill, improves conducting resistance.And then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture, be effectively protected
Gallium nitride semiconductor device, enhances the reliability of gallium nitride semiconductor device.
Brief description of the drawings
Fig. 1 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 1 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 2 a are the structural representation of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 2 b are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 2 c are the preparation flow schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in Figure 1a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 210, dielectric layer 220, source electrode 231 and drain electrode 232, grid 233, insulating barrier 240, field plate metal layer 250.
Wherein, epitaxial layer of gallium nitride 210 is by silicon (Si) substrate 212, gallium nitride (GaN) layer 213 and aluminium gallium nitride alloy (AlGaN)
Layer 214 is constituted, wherein, silicon substrate 212, gallium nitride layer 213 and aluminum gallium nitride 214 are from bottom to top set gradually.
Dielectric layer 220 is arranged on the epitaxial layer of gallium nitride 210；The material of the dielectric layer 220 of the present embodiment can example
Such as it is hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 231, drain electrode 232 and grid 233 are arranged on the dielectric layer 220.Specifically, source electrode 231, drain electrode 232
It is inserted into a part as the outer image " nail " of grid 233 in the dielectric layer 220, the source electrode 231, drain electrode 232 and grid
233 extend through the dielectric layer 220 is connected with the epitaxial layer of gallium nitride 210；And a part protrudes from the dielectric layer 220
Top.The source electrode 231 and/or drain electrode 232 are made up of the first metal；First metal composition is same as the previously described embodiments.Adopt
With the first metal material formation source electrode 231, drain electrode 232, can in higher device temperature annealing process with the epitaxy of gallium nitride
Aluminum gallium nitride layer 214 in layer 210 reacts, and generates alloy, so that source electrode 231, drain electrode 232 and aluminum gallium nitride
The contact of contact surface is good, can effectively reduce source electrode 231, drain electrode 232 and the contact resistance of aluminum gallium nitride；Avoid the occurrence of
The problem of electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, the grid 233 is down extended into the aluminum gallium nitride 214, the bottom of grid 233 to institute
State the bottom of aluminum gallium nitride 214 is preferably the half of the whole aluminum gallium nitride 214 apart from H.Grid 233 is by the second metal
Composition, second metal is Ni, Au alloy.
Preferably, a gate dielectric layer 234 is also included between the grid 233 and the epitaxial layer of gallium nitride 210, this
The material of gate dielectric layer 234 may be, for example, silicon nitride in embodiment.
Insulating barrier 240 is arranged at drain electrode 232, grid 233 and the top of a part of source electrode 231, and exposes the whole come
On dielectric layer 220, the material of the insulating barrier 240 is silica.Wherein, insulating barrier 240 is carried out on the surface of whole device
Uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 231, drain electrode 232, the presence of grid 233, so that in source electrode 231
Insulating barrier 240 between grid 233, the insulating barrier 240 between grid 233 and drain electrode 232 are, to lower recess, to pass through
Technique is polished in subsequent step so that smooth.
It can also for example include field plate metal layer 250, it is arranged on the insulating barrier 240.The field plate metal layer 250
It is connected through the insulating barrier 240 with the source electrode 231.Preferably, the material of the field plate metal layer 250 is aluminium copper silicon gold
Belong to layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 1 b, specific steps include：
Step 201：Gallium nitride layer 213 and aluminum gallium nitride 214 are sequentially depositing on silicon substrate 212, is formed outside gallium nitride
Prolong layer 210.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 110
One layer of hafnium oxide (HfO of product2), form dielectric layer 120.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms.
Step 202, dry etching is carried out to the dielectric layer 120, forms the source contact openings 221 being oppositely arranged and leakage
Pole contact hole 222.
In order that the source contact openings 221, the few impurity of the cleaning of drain contact hole 222 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to dielectric layer 220, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-1+ization
The method for learning cleaning agent SC-2 ", for example, can be first using the hydrofluoric acid solution processing apparatus after dilution, then using peroxidating
The alkaline mixed solution processing apparatus of hydrogen and aqua ammonia, then using hydrogen peroxide and the acidic mixed solution processor of hydrogen chloride
Part, and then the impurity thing on the surface of whole device can be removed.
Step 203, in the present embodiment, it is interior and dielectric layer 220 in source contact openings 221 and drain contact hole 222
The first metal is deposited on surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and dielectric layer
Surface on, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form the first metal；
Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of layer may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 219 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 219；Through Ohm contact electrode window 219, it can be seen that the part table of dielectric layer 220
Face.In this way, the first metal on source contact openings 121 constitutes the first gold medal on the source electrode 231 of device, drain contact hole 222
Category constitutes the drain electrode 232 of device.Now, in order to be able to clear expression process of the present invention, it is first to name the device now obtained
Component.
Step 204, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 214.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 214 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 214 can be reduced.That is, reduction source electrode 231, drain electrode 232 and aluminium nitride
Contact resistance between gallium layer 214.
Step 205, by Ohm contact electrode window 219, is carried out to dielectric layer 220 and aluminum gallium nitride 214 dry method quarter
Erosion, forms gate contact hole 223, wherein, the bottom in gate contact hole 223 and the bottom of aluminum gallium nitride 214 have it is default away from
From.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 219, to dielectric layer 220 with
And partial aluminum gallium nitride 214, carry out dry etching, and then one gate contact hole 223 of formation on the first device.Its
In, gate contact hole 223 completely breaks through dielectric layer 220, and passes through the aluminum gallium nitride 214 of part so that gate contact
The bottom in hole 223 and the bottom of aluminum gallium nitride 214 be preferably apart from H aluminum gallium nitride 214 half.
In the present embodiment, formed after a gate contact hole 223, can there is impurity, particle in gate contact hole 223
And the impurity thing such as ion, will be miscellaneous in gate contact hole 220 so as to using hydrochloric acid solution cleaning gate contact hole 220
Matter thing is got rid of.
The present embodiment is by after dry etching is carried out to dielectric layer 220, using DHF+SC1+SC2 method remover
Impurity thing on part；And formed after gate contact hole 223, the impurity thing in gate contact hole 223 is gone using hydrochloric acid solution
Remove.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 223 of dielectric layer, and then it ensure that nitridation
The performance of gallium semiconductor devices.
Step 206, in the present embodiment, specifically, using magnetron sputtering membrane process, being sunk in gate contact hole 223
One layer of silicon nitride layer of product, the silicon nitride layer is not higher than the gate contact hole 223；Then again on the silicon nitride layer, with
And the outward flange deposition Ni/Au in gate contact hole 223, as the second metal, metal thickness is 0.01~0.04 μm/0.08~0.4
μm；So as to constitute grid 233.So, the grid 233 is a kind of composite construction with multiple material.
Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 207, a layer insulating 240 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 240.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 231, drain electrode 232 and the presence of grid 233, so that in source electrode 231 and grid
Insulating barrier 240 between pole 233, the insulating barrier 240 between grid 233 and drain electrode 232 are to lower recess, using polishing
Technique is allowed to smooth.
Step 208, after to the progress dry etching of insulating barrier 140 of the top of source contact openings 231, perforate 241 is formed.Institute
Stating grid 233 has the protuberance 233a protruded from outside the gate contact hole 223, and the width of the perforate 241 is less than described
Protuberance 233a width.
Step 209, the insulation of the top of gate contact hole 123 is extended in perforate 241 and from source contact openings 231
Field plate metal 250 is deposited on layer 240, field plate metal layer 250 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 241 and from source electrode
Outer peripheral first metal of contact hole 221 is until on dielectric layer 220 above outer peripheral first metal in gate contact hole 223
Field plate metal is deposited, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 250.Field plate metal layer 250 thickness be
Uniformly, field plate metal layer 250 is at the position of perforate 241 and between source contact openings 221 and gate contact hole 223
At position is, to lower recess, to be allowed to smooth using technique is polished.
The present embodiment can be with optimised devices manufacture craft, optimised devices technique compatible with CMOS technology line, improves electric conduction
Resistance.And then the problem of avoid the electric leakage for gallium nitride semiconductor device occur and puncture, be effectively protected gallium nitride and partly lead
Body device, enhances the reliability of gallium nitride semiconductor device.The gallium nitride semiconductor device that the present embodiment is obtained can be applied to
In the technical fields such as power electronic element, wave filter, radio communication element, have a good application prospect.
It refer to shown in Fig. 2 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Nitrogen
Change gallium epitaxial layer 310, dielectric layer 320, source electrode 331 and drain electrode 332, grid 333, insulating barrier 340, field plate metal layer 350.
Wherein, epitaxial layer of gallium nitride 310 is by silicon (Si) substrate 312, gallium nitride (GaN) layer 313 and aluminium gallium nitride alloy (AlGaN)
Layer 314 is constituted, wherein, silicon substrate 312, gallium nitride layer 313 and aluminum gallium nitride 314 are from bottom to top set gradually.
Dielectric layer 320 is arranged on the epitaxial layer of gallium nitride 310；The material of the dielectric layer 320 of the present embodiment can example
Such as it is hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 331, drain electrode 332 and grid 333 are arranged on the dielectric layer 320.Specifically, source electrode 331, drain electrode 332
It is inserted into a part as the outer image " nail " of grid 333 in the dielectric layer 320, the source electrode 331, drain electrode 332 and grid
333 extend through the dielectric layer 320 is connected with the epitaxial layer of gallium nitride 310；And a part protrudes from the dielectric layer 320
Top.The source electrode 331 and/or drain electrode 332 are made up of the first metal.The wherein component structure of the first metal and above-mentioned implementation
Example is identical.Using the first metal material formation source electrode 331, drain electrode 332, can in higher device temperature annealing process with the nitrogen
The aluminum gallium nitride layer 314 changed in gallium epitaxial layer 310 reacts, and generates alloy, so that source electrode 331, drain electrode 332 and nitrogen
The contact for changing the contact surface of gallium aluminium layer is good, can effectively reduce the contact electricity of source electrode 331, drain electrode 332 with aluminum gallium nitride
Resistance；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, with reference to shown in Fig. 2 b, the grid 333 of the present embodiment includes two connected side by side parts：Shorter is
It is enhanced first grid portion 333a, longer for depletion type second gate portion 333b.The first grid portion 333a and the aluminium gallium nitride alloy
314 surface of layer connection, the second gate portion 333b is stretched into the aluminum gallium nitride 314.What this long and short two part was constituted
Grid is different from existing grid, and " abnormal shape " is presented.
Further, the width D 1 of the first grid portion 333a is preferably not less than second gate portion 333b width D 2.When
So, in other embodiments, first grid portion 333a and second gate portion 333b right position can also be exchanged.
The grid 333b can be extended into down in the aluminum gallium nitride 314, and the grid 333b bottoms are described in
The bottom of aluminum gallium nitride 314 be preferably apart from H the whole aluminum gallium nitride 314 half.Whole grid 333 is by the second gold medal
Category composition, second metal is Ni, Au alloy.
Insulating barrier 340 is arranged at drain electrode 332, grid 333 and the top of a part of source electrode 331, and exposes the whole come
On dielectric layer 320, the material of the insulating barrier 340 is silica.Wherein, insulating barrier 340 is carried out on the surface of whole device
Uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 331, drain electrode 332, the presence of grid 333, so that in source electrode 331
Insulating barrier 340 between grid 333, the insulating barrier 340 between grid 33 and drain electrode 332 are, to lower recess, can to pass through
Follow-up lapping process is allowed to smooth.
It can also for example include field plate metal layer 350, it is arranged on the insulating barrier 340.The field plate metal layer 350
It is connected through the insulating barrier 340 with the source electrode 331.Preferably, the material of the field plate metal layer 350 is aluminium copper silicon gold
Belong to layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 2 c, specific steps include：
Step 301：Gallium nitride layer 313 and aluminum gallium nitride 314 are sequentially depositing on silicon substrate 312, is formed outside gallium nitride
Prolong layer 310.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 310
One layer of hafnium oxide (HfO of product2), form dielectric layer 120.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms.
Step 302, dry etching is carried out to the dielectric layer 320, forms the source contact openings 321 being oppositely arranged and leakage
Pole contact hole 322.
In order that the source contact openings 321, the few impurity of the cleaning of drain contact hole 322 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to dielectric layer 320, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-1+ization
The method for learning cleaning agent SC-2 ", for example, can be first using the hydrofluoric acid solution processing apparatus after dilution, then using peroxidating
The alkaline mixed solution processing apparatus of hydrogen and aqua ammonia, then using hydrogen peroxide and the acidic mixed solution processor of hydrogen chloride
Part, and then the impurity thing on the surface of whole device can be removed.
Step 303, in the present embodiment, it is interior and dielectric layer 120 in source contact openings 321 and drain contact hole 322
The first metal is deposited on surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and dielectric layer
Surface on, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form the first metal；
Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of layer may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 319 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 319；Through Ohm contact electrode window 319, it can be seen that the part table of dielectric layer 320
Face.In this way, the first metal on source contact openings 121 constitutes the first gold medal on the source electrode 331 of device, drain contact hole 322
Category constitutes the drain electrode 332 of device.Now, in order to be able to clear expression process of the present invention, it is first to name the device now obtained
Component.
Step 104, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category and aluminum gallium nitride, 314 reacted after formation alloy.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 314 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 314 can be reduced.That is, reduction source electrode 331, drain electrode 332 and aluminium nitride
Contact resistance between gallium layer 314.
Step 305, by Ohm contact electrode window, 319, dry method quarter is carried out to dielectric layer 320 and aluminum gallium nitride 314
Erosion, forms gate contact hole 323, wherein, the bottom in gate contact hole 323 and the bottom of aluminum gallium nitride 314 have it is default away from
From.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 319, to dielectric layer 320 with
And partial aluminum gallium nitride 314, carry out dry etching, and then one gate contact hole 323 of formation on the first device.
Wherein, when etching for the first time, only carried out in the part of dielectric layer 320, obtain the first shallower contact hole 323a；
It is amesiality among the first obtained contact hole 323a of first time etching during second of dry etching to carry out, and etching runs through
Deeply carried out again into partial nitridation gallium aluminium layer 314 after whole dielectric layer 320, form deeper second contact hole 323b；So
Obtain overall gate contact hole 323.By controlling etch process parameters to adjust gate contact hole 323b width, to control the
The proportionate relationship of the width D 1 in one grid portion, the width D 2 in second gate portion.Then in the gate contact hole 323a, gate contact hole
323b and certain media layer 320 deposit Ni/Au, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm；Obtain grid
333.It follows that actually interconnected between two gate contact holes, first grid portion 333a, second gate portion 333b
Preparation is also integrally formed.
Preferably, the second contact hole 323b completely breaks through dielectric layer 320, and through the aluminum gallium nitride 314 of part,
So that the bottom of the second contact hole 323b bottom and aluminum gallium nitride 314 is preferably the one of aluminum gallium nitride 314 apart from H
Half.
In the present embodiment, formed after a gate contact hole 323, can there is impurity, particle in gate contact hole 323
And the impurity thing such as ion, will be miscellaneous in gate contact hole 320 so as to using hydrochloric acid solution cleaning gate contact hole 320
Matter thing is got rid of.
Specifically, the present embodiment is by after dry etching is carried out to dielectric layer 320, using DHF+SC1+SC2 side
Impurity thing in method removal devices；And formed after gate contact hole 323, using hydrochloric acid solution by gate contact hole 323
Impurity thing is got rid of.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 323 of dielectric layer, Jin Erbao
The performance of gallium nitride semiconductor device is demonstrate,proved.
Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 307, a layer insulating, 340 are deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO of whole second component2), thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 340.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 331, drain electrode 332 and the presence of grid 333, so that in source electrode 331 and grid
Insulating barrier 340 between pole 333, the insulating barrier 340 between grid 333 and drain electrode 332 are to lower recess, using polishing
Technique is allowed to smooth.
Step 308, after to the progress dry etching of insulating barrier 340 of the top of source contact openings 331, perforate 341 is formed.Institute
Stating grid 333 has the protuberance 333a protruded from outside the gate contact hole 323, and the width of the perforate 341 is less than described
Protuberance 333a width.
Step 309, the insulation of the top of gate contact hole 323 is extended in perforate 341 and from source contact openings 331
Field plate metal 350 is deposited on layer 340, field plate metal layer 350 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 341 and from source electrode
Outer peripheral first metal of contact hole 321 is until on dielectric layer 320 above outer peripheral first metal in gate contact hole 323
Field plate metal is deposited, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 350.Field plate metal layer 350 thickness be
Uniformly, field plate metal layer 350 is at the position of perforate 341 and between source contact openings 221 and gate contact hole 223
At position is that, to lower recess, can be allowed to smooth by the technique that polishes in subsequent step.
Beneficial effect：
The gallium nitride semiconductor device of the present embodiment is using mixing grid structure, including short belongs to enhanced first grid portion
The 333a and long second gate portion 333b for belonging to depletion type.Under the conditions of OFF state, first grid portion 333a shut-offs, and second gate portion
333b can pin groove potential under drain voltage, and there is provided high blocking ability；During ON state, enhancement type channel and depletion type ditch
Road provides low channel resistance, it is ensured that high conducting electric current and low conducting resistance.The gallium nitride semiconductor that the present embodiment is obtained
Device can be applied in the technical fields such as power electronic element, wave filter, radio communication element, before good application
Scape.
As shown in Figure 3 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 610, dielectric layer 620, source electrode 631 and drain electrode 632, grid 633, insulating barrier 640, field plate metal layer 650.
Wherein, epitaxial layer of gallium nitride 610 is by silicon (Si) substrate 612, gallium nitride (GaN) layer 613 and aluminium gallium nitride alloy (AlGaN)
Layer 614 is constituted, wherein, silicon substrate 612, gallium nitride layer 613 and aluminum gallium nitride 614 are from bottom to top set gradually.
Dielectric layer 620 is arranged on the epitaxial layer of gallium nitride 610；The material of the dielectric layer 620 of the present embodiment can example
Such as it is hafnium oxide (HfO2).The hafnium oxide belongs to a kind of high-k (high-k) medium.
Source electrode 631, drain electrode 632 and grid 633 are arranged on the dielectric layer 620.Specifically, source electrode 631, drain electrode 632
It is inserted into a part as the outer image " nail " of grid 633 in the dielectric layer 620, the source electrode 631, drain electrode 632 and grid
633 extend through the dielectric layer 620 is connected with the epitaxial layer of gallium nitride 610；And a part protrudes from the dielectric layer 620
Top.The source electrode 631 and/or drain electrode 632 by the first metal constitute and above-described embodiment shown in.Using the first metal material
The source electrode 631 of formation, drain electrode 632, can in higher device temperature annealing process with the nitridation in the epitaxial layer of gallium nitride 610
Gallium aluminium lamination 614 reacts, and generates alloy, so that source electrode 631,632 contacts with the contact surface of aluminum gallium nitride of drain electrode
Well, source electrode 631, drain electrode 632 and the contact resistance of aluminum gallium nitride can be effectively reduced；Avoid the occurrence of gallium nitride semiconductor
The problem of electric leakage and soft breakdown of device.
Preferably, the grid 633 is down extended into the aluminum gallium nitride 614 and gone directly to the aluminium gallium nitride alloy
614 bottom of layer, obtain one " penetrating type grid ".Grid 633 is made up of the second metal, and second metal is Ni, Au alloy.
Insulating barrier 640 is arranged at drain electrode 632, grid 633 and the top of a part of source electrode 631, and exposes the whole come
On dielectric layer 620, the material of the insulating barrier 640 is silica.Wherein, insulating barrier 640 is carried out on the surface of whole device
Uniform deposition, the thickness precipitated everywhere is identical.Due to source electrode 631, drain electrode 632, the presence of grid 633, so that in source electrode 631
Insulating barrier 640 between grid 633, the insulating barrier 640 between grid 633 and drain electrode 632 be to lower recess, it is available
Polish technique and be allowed to smooth.
It can also for example include field plate metal layer 650, it is arranged on the insulating barrier 640.The field plate metal layer 650
It is connected through the insulating barrier 640 with the source electrode 631.Preferably, the material of the field plate metal layer 650 is aluminium copper silicon metal
Layer.
Grid 633 in above-mentioned gallium nitride semiconductor device penetrates whole aluminum gallium nitride and reaches gallium nitride layer, can suppress
The high electric field of gate edge, is effectively guaranteed the stable blocking characteristics of gallium nitride high tension apparatus, makes device by repeatedly high
After pressure, still good reliability can be kept.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 3 b, specific steps include：
Step 601：Gallium nitride layer 613 and aluminum gallium nitride 614 are sequentially depositing on silicon substrate 612, is formed outside gallium nitride
Prolong layer 610.Gallium nitride is third generation semiconductor material with wide forbidden band, with big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 610
One layer of hafnium oxide (HfO2) of product, forms dielectric layer 620.Wherein, the thickness of hafnium oxide for example can be 2000 angstroms.
Step 602, dry etching is carried out to the dielectric layer 620, forms the source contact openings 21 being oppositely arranged and drain electrode
Contact hole 622.
In order that the source contact openings 621, the few impurity of the cleaning of drain contact hole 622 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to dielectric layer 620, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-1+ization
The method for learning cleaning agent SC-2 ", for example, can be first using the hydrofluoric acid solution processing apparatus after dilution, then using peroxidating
The alkaline mixed solution processing apparatus of hydrogen and aqua ammonia, then using hydrogen peroxide and the acidic mixed solution processor of hydrogen chloride
Part, and then the impurity thing on the surface of whole device can be removed.
Step 603, in the present embodiment, it is interior and dielectric layer 620 in source contact openings 621 and drain contact hole 622
The first metal 621 is deposited on surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and dielectric layer
Surface on, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form the first metal；
Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 6200 angstroms, the second titanium
The thickness of layer may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, Ohm contact electrode window 619 is formed.
Carry out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 619；Through Ohm contact electrode window 619, it can be seen that the part table of dielectric layer 620
Face.In this way, the first metal on source contact openings 621 constitutes the first gold medal on the source electrode 631 of device, drain contact hole 622
Category constitutes the drain electrode 632 of device.Now, in order to be able to clear expression process of the present invention, it is first to name the device now obtained
Component.
Step 604, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching contacted with each other
Category forms alloy after being reacted with aluminum gallium nitride 614.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so that the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 614 on its contact surface, so that
The contact resistance between the first metal and aluminum gallium nitride 614 can be reduced.That is, reduction source electrode 631, drain electrode 632 and aluminium nitride
Contact resistance between gallium layer 14.
Step 605, by Ohm contact electrode window 619, is carried out to dielectric layer 620 and aluminum gallium nitride 614 dry method quarter
Erosion, forms gate contact hole 623, wherein, the bottom in gate contact hole 623 and the bottom of aluminum gallium nitride 614 have it is default away from
From.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 619, to dielectric layer 620 with
And partial aluminum gallium nitride 614, carry out dry etching, and then one gate contact hole 623 of formation on the first device.Its
In, gate contact hole 623 completely breaks through dielectric layer 620, and passes through the aluminum gallium nitride 614 of part so that gate contact
The bottom in hole 623 and the bottom of aluminum gallium nitride 614 be preferably apart from H aluminum gallium nitride 614 half.
In the present embodiment, formed after a gate contact hole 623, can there is impurity, particle in gate contact hole 623
And the impurity thing such as ion, will be miscellaneous in gate contact hole 620 so as to using hydrochloric acid solution cleaning gate contact hole 620
Matter thing is got rid of.
The present embodiment is by after dry etching is carried out to dielectric layer 620, using DHF+SC1+SC2 method remover
Impurity thing on part；And formed after gate contact hole 623, the impurity thing in gate contact hole 623 is gone using hydrochloric acid solution
Remove.So as to the cleaning being effectively guaranteed in the surface and gate contact hole 623 of dielectric layer, and then it ensure that nitridation
The performance of gallium semiconductor devices.
Step 606, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 623 and grid
The outward flange deposition Ni/Au of pole contact hole 623 is as the second metal, and metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 633.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 607, a layer insulating 640 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface deposition layer of silicon dioxide (SiO2) of whole second component, thickness can
For example, 5000 angstroms, form silicon dioxide layer and be used as a layer insulating 640.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 631, drain electrode 632 and the presence of grid 633, so that in source electrode 631 and grid
Insulating barrier 640 between pole 633, the insulating barrier 640 between grid 633 and drain electrode 632 are to lower recess, using polishing
Technique is allowed to smooth.
Step 608, after to the progress dry etching of insulating barrier 640 of the top of source contact openings 631, perforate 641 is formed.Institute
Stating grid 33 has the protuberance 633a protruded from outside the gate contact hole 623, and the width of the perforate 641 is less than described convex
Go out portion 633a width.
Step 609, the insulation of the top of gate contact hole 623 is extended in perforate 641 and from source contact openings 631
Field plate metal 650 is deposited on layer 640, field plate metal layer 650 is formed.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 641 and from source electrode
Outer peripheral first metal of contact hole 621 is until on dielectric layer 620 above outer peripheral first metal in gate contact hole 623
Field plate metal is deposited, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 650.Field plate metal layer 650 thickness be
Uniformly, field plate metal layer 650 is at the position of perforate 641 and between source contact openings 621 and gate contact hole 623
At position is, to lower recess, to pass through polishing technique and can be allowed to smooth in subsequent step.
The present embodiment by the surface of epitaxy of gallium nitride substrate metallization medium layer be used as instead of existing silicon oxide layer
Dielectric layer；The high temperature anneal technique is recycled, the aluminum gallium nitride in source electrode, drain electrode and epitaxial layer of gallium nitride is reacted
Alloy is formed afterwards, so that source electrode, drain electrode contact with the contact surface of aluminum gallium nitride are well, can effectively reduce source
The contact resistance of pole, drain electrode and aluminum gallium nitride；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Further, the structure of optimization grid causes grid to penetrate whole aluminum gallium nitride, compatible with CMOS technology line, adjustment electric field point
Cloth, improves the pressure-resistant of device with this.The gallium nitride semiconductor device that the present embodiment is obtained can be applied to power electronic element, filter
In the technical fields such as ripple device, radio communication element, have a good application prospect.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
1. a kind of gallium nitride semiconductor device, it is characterised in that including：Epitaxial layer of gallium nitride；And,
The dielectric layer on the epitaxial layer of gallium nitride is arranged at, the dielectric layer material is hafnium oxide；
Source electrode, drain and gate on the dielectric layer are arranged at, the source electrode, drain and gate extend through the dielectric layer
It is connected with the epitaxial layer of gallium nitride；Wherein, there is gate dielectric layer between the grid and the epitaxial layer of gallium nitride；
The insulating barrier on the source electrode, drain and gate and the dielectric layer is arranged at, the material of the insulating barrier is dioxy
SiClx；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer is through the insulating barrier and the source
Pole is connected.
2. gallium nitride semiconductor device according to claim 1, it is characterised in that the epitaxial layer of gallium nitride includes silicon lining
Bottom, and be arranged at the gallium nitride layer of the surface of silicon, be arranged at the aluminum gallium nitride on the gallium nitride layer surface.
3. gallium nitride semiconductor device according to claim 1, it is characterised in that the gate dielectric layer down extends into described
In aluminum gallium nitride.
4. gallium nitride semiconductor device according to claim 3, it is characterised in that the gate dielectric layer bottom to the nitridation
The distance of gallium aluminium layer bottom is the half of the whole aluminum gallium nitride.
5. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the thickness of the dielectric layer is
2000 angstroms.
6. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the gate dielectric layer is nitridation
Silicon.
7. a kind of preparation method of gallium nitride semiconductor device, it is characterised in that comprise the following steps：
One epitaxial layer of gallium nitride is provided, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, the nitrogen from bottom to top set gradually
Change gallium layer and aluminum gallium nitride；
In the epitaxy of gallium nitride layer surface deposit hafnium oxides, dielectric layer is formed；
The acquisition of source contact openings and drain contact hole：Etch the dielectric layer, with formed separate source contact openings and
Drain contact hole, the source contact openings, the drain contact hole reach the aluminum gallium nitride through the dielectric layer；Institute
State in source contact openings and the drain contact hole and on the surface of the dielectric layer, the first metal is deposited, to obtain source
Pole, drain electrode；
Photoetching and etching are carried out to first metal, Ohm contact electrode window is formed；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, to be contained in the source contact openings and the drain contact hole
Interior first metal forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, the dielectric layer and the aluminum gallium nitride are entered
Row dry etching, forms gate contact hole, wherein, between the bottom in the gate contact hole and the bottom of the aluminum gallium nitride
With pre-determined distance；
First deposited silicon nitride is used as gate dielectric layer in the gate contact hole；Then again on the gate dielectric layer, the grid
The outward flange of pole contact hole deposits the second metalwork, to obtain grid, now obtains the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer at least covers described
Perforate and from the source contact openings to the region between the gate contact hole.
8. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the width of the perforate is small
The protuberance width above the gate contact hole is protruded from the grid.
9. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the high temperature anneal
Step is：Under protection atmosphere, kept for 30~60 seconds at a temperature of 840~850 DEG C.
10. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the pre-determined distance is
The half of the thickness of the aluminum gallium nitride.
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