CN107393963A - Gallium nitride semiconductor device and preparation method thereof - Google Patents
Gallium nitride semiconductor device and preparation method thereof Download PDFInfo
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- CN107393963A CN107393963A CN201710488430.6A CN201710488430A CN107393963A CN 107393963 A CN107393963 A CN 107393963A CN 201710488430 A CN201710488430 A CN 201710488430A CN 107393963 A CN107393963 A CN 107393963A
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- gallium nitride
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 190
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 127
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000002360 preparation method Methods 0.000 title claims description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 104
- 239000002184 metal Substances 0.000 claims abstract description 104
- 150000001875 compounds Chemical class 0.000 claims abstract description 89
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 66
- 230000004888 barrier function Effects 0.000 claims abstract description 47
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 230000002708 enhancing effect Effects 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 25
- 229910045601 alloy Inorganic materials 0.000 claims description 23
- 239000000956 alloy Substances 0.000 claims description 23
- 238000001312 dry etching Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 13
- 229910052733 gallium Inorganic materials 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 8
- 229910017083 AlN Inorganic materials 0.000 claims description 5
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 238000000034 method Methods 0.000 description 41
- 238000000151 deposition Methods 0.000 description 19
- 239000012535 impurity Substances 0.000 description 18
- 230000008569 process Effects 0.000 description 16
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 12
- 230000008021 deposition Effects 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- 229910052719 titanium Inorganic materials 0.000 description 12
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- 238000001755 magnetron sputter deposition Methods 0.000 description 8
- 239000012528 membrane Substances 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 239000011259 mixed solution Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000010129 solution processing Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 230000002378 acidificating effect Effects 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- -1 aluminium copper silicon Chemical compound 0.000 description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 239000012895 dilution Substances 0.000 description 3
- 238000010790 dilution Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 3
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
The present invention relates to technical field of semiconductor, there is provided a kind of gallium nitride semiconductor device includes：Epitaxial layer of gallium nitride；And it is arranged at silicon nitride and plasma enhancing tetraethoxysilance compound medium layer on the epitaxial layer of gallium nitride；Source electrode, the drain and gate being arranged on the compound medium layer, the source electrode, drain and gate extend through the compound medium layer and are connected with the epitaxial layer of gallium nitride；The insulating barrier being arranged on the source electrode, drain and gate and the compound medium layer, and the field plate metal layer being arranged on the insulating barrier.The gallium nitride semiconductor device of the present invention is less prone to the phenomenon of breakdown aluminum gallium nitride; and then the problem of avoiding the electric leakage and breakdown for gallium nitride semiconductor device occur; gallium nitride semiconductor device is effectively protected, enhances the reliability of gallium nitride semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor technology, more particularly to a kind of gallium nitride semiconductor device and preparation method thereof.
Background technology
Gallium nitride have big energy gap, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, it is corrosion-resistant and
The advantages that radiation resistance, so as to make semi-conducting material using gallium nitride, and obtain gallium nitride semiconductor device.
In the prior art, the preparation method of gallium nitride semiconductor device is：Nitrogen is formed on the surface of epitaxial layer of gallium nitride
SiClx layer, source contact openings and drain contact hole are etched on silicon nitride layer, are deposited in source contact openings and drain contact hole
Metal, so as to form source electrode and drain electrode；Aluminum gallium nitride in etch nitride silicon layer and epitaxial layer of gallium nitride again, form one
Groove, deposited metal layer in a groove, so as to form grid；Then deposited silicon dioxide layer and field plate metal layer, so as to shape
Into gallium nitride semiconductor device.
But in the prior art, because electric field density is larger, so as to can cause gallium nitride semiconductor device electric leakage and
The problem of breakdown, and then gallium nitride semiconductor device can be damaged, reduce the reliability of gallium nitride semiconductor device.Further,
In order to obtain high performance gallium nitride transistor, the improvement of conducting resistance is very important.In total conducting resistance, 80%
Resistance is non-grid region and grid region resistance, and 20% resistance is Ohmic contact and the resistance being indirectly connected with.
The content of the invention
To solve the above problems, the present invention provides a kind of gallium nitride semiconductor device with gate dielectric layer, including：Nitridation
Gallium epitaxial layer；And
The compound medium layer being arranged on the epitaxial layer of gallium nitride；
Source electrode, the drain and gate being arranged on the compound medium layer, the source electrode, drain and gate extend through institute
Compound medium layer is stated to be connected with the epitaxial layer of gallium nitride；Wherein, there are grid between the grid and the epitaxial layer of gallium nitride
Dielectric layer；
The insulating barrier being arranged on the source electrode, drain and gate and the compound medium layer, the material of the insulating barrier
Matter is silica；
Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer runs through the insulating barrier and institute
State source electrode connection.
The present invention also provides the preparation method of this gallium nitride semiconductor device with inverted trapezoidal grid, there is provided a nitridation
Gallium epitaxial layer, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, gallium nitride layer and the aluminium nitride from bottom to top set gradually
Gallium layer；
In the epitaxy of gallium nitride layer surface deposited silicon nitride and plasma enhancing tetraethoxysilance, complex media is formed
Layer, the compound medium layer material is silicon nitride and plasma enhancing tetraethoxysilance；
The acquisition of source contact openings and drain contact hole：The compound medium layer is etched, to form separate source electrode
Contact hole and drain contact hole, the source contact openings, the drain contact hole reach the nitrogen through the compound medium layer
Change gallium aluminium layer；
In the source contact openings and the drain contact hole and on the surface of the compound medium layer, deposition the
One metal, to obtain source electrode, drain electrode；
Photoetching and etching are carried out to first metal, form Ohm contact electrode window；Now obtain first assembly；
The high temperature anneal is carried out to the first assembly, connect with to be contained in the source contact openings and the drain electrode
First metal in contact hole forms alloy and reacted with the aluminum gallium nitride；
The acquisition in gate contact hole：By the Ohm contact electrode window, to the compound medium layer and the nitridation
Gallium aluminium layer carries out dry etching, forms gate contact hole, wherein, bottom and the aluminum gallium nitride in the gate contact hole
There is pre-determined distance between bottom；
First deposited silicon nitride is as gate dielectric layer in the gate contact hole；Then again on the gate dielectric layer, institute
The outward flange for stating gate contact hole deposits the second metalwork, to obtain grid, now obtains the second component；
A layer insulating is deposited on the surface of second component；
Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；
Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer at least covers
The perforate and from the source contact openings to the region between the gate contact hole.
Beneficial effect：
The present invention by the compound medium layer on the surface of epitaxial layer of gallium nitride applies novel materials, also passes through deposition the
One metal is carrying out the high temperature anneal, to be reacted by the first metal after the etching to contact with each other with aluminum gallium nitride
Alloy is formed afterwards, to reduce the contact resistance of the first metal and aluminum gallium nitride after etching；
The present embodiment introduces gate dielectric layer can be with optimised devices manufacture craft, optimised devices work compatible with CMOS technology line
Skill, improve conducting resistance.And then the problem of avoiding the electric leakage and breakdown for gallium nitride semiconductor device occur, it is effectively protected
Gallium nitride semiconductor device, enhance the reliability of gallium nitride semiconductor device.
Brief description of the drawings
Fig. 1 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 1 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 2 a are the structural representation of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 2 b are the grid structure schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 2 c are the preparation flow schematic diagram of the gallium nitride semiconductor device of further embodiment of this invention.
Fig. 3 a are the structural representation of the gallium nitride semiconductor device of another embodiment of the present invention.
Fig. 3 b are the preparation flow schematic diagram of the gallium nitride semiconductor device of another embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in Figure 1a, a kind of gallium nitride semiconductor device is provided in one embodiment, and it includes from bottom to up：Gallium nitride
Epitaxial layer 210, compound medium layer 220, source electrode 231 and drain electrode 232, grid 233, insulating barrier 240, field plate metal layer 250.
Wherein, epitaxial layer of gallium nitride 210 is by silicon (Si) substrate 212, gallium nitride (GaN) layer 213 and aluminium gallium nitride alloy (AlGaN)
Layer 214 is formed, wherein, silicon substrate 212, gallium nitride layer 213 and aluminum gallium nitride 214 are from bottom to top set gradually.
Compound medium layer 220 is arranged on the epitaxial layer of gallium nitride 210；The compound medium layer 220 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 231, drain electrode 232 and grid 233 are arranged on the compound medium layer 220.Specifically, source electrode 231, drain electrode
232 and the outer image " nail " of grid 233 as a part be inserted into the compound medium layer 220, the source electrode 231, drain electrode 232
The compound medium layer 220 is extended through with grid 233 to be connected with the epitaxial layer of gallium nitride 210；And a part protrudes from institute
State the top of compound medium layer 220.The source electrode 231 and/or drain electrode 232 are made up of the first metal；First metal form with it is upper
It is identical to state embodiment.Using the first metal material formed source electrode 231, drain electrode 232, can in higher device temperature annealing process with
Aluminum gallium nitride layer 214 in the epitaxial layer of gallium nitride 210 reacts, and generates alloy, so that source electrode 231, drain electrode 232
It is good with the contact of the contact surface of aluminum gallium nitride, source electrode 231 can be effectively reduced, drain electrode 232 connects with aluminum gallium nitride
Get an electric shock and hinder；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, a gate dielectric layer 234, this reality are also included between the grid 233 and the epitaxial layer of gallium nitride 210
It may be, for example, silicon nitride to apply the material of gate dielectric layer 234 in example.Grid 233 is made up of the second metal, and second metal is Ni, Au
Alloy.
Preferably, the grid 233 is down extended into the aluminum gallium nitride 214, and the bottom of grid 233 is described in
The distance H of the bottom of aluminum gallium nitride 214 is preferably the half of the whole aluminum gallium nitride 214.
Insulating barrier 240 is arranged at drain electrode 232, grid 233 and the top of a part of source electrode 231, and exposes the whole come
On compound medium layer 220, the material of the insulating barrier 240 is silica.Wherein, insulating barrier 240 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 231, drain electrode 232, the presence of grid 233, so as in source electrode
Insulating barrier 240 between 231 and grid 233, the insulating barrier 240 between grid 233 and drain electrode 232 are to lower recess, are led to
Cross in subsequent step polish technique cause it is smooth.
It can also for example include field plate metal layer 250, it is arranged on the insulating barrier 240.The field plate metal layer 250
It is connected through the insulating barrier 240 with the source electrode 231.Preferably, the material of the field plate metal layer 250 is aluminium copper silicon metal
Layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 1 b, specific steps include：
Step 201：Gallium nitride layer 213 and aluminum gallium nitride 214 are sequentially depositing on silicon substrate 212, is formed outside gallium nitride
Prolong layer 210.Gallium nitride is third generation semiconductor material with wide forbidden band, has big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts are per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 110
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 120.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 202, dry etching is carried out to the compound medium layer 120, forms the He of source contact openings 221 being oppositely arranged
Drain contact hole 222.
In order that the source contact openings 221, the few impurity of the cleaning of drain contact hole 222 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 220, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
The alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then using at the acidic mixed solution of hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Step 203, in the present embodiment, in source contact openings 221 and drain contact hole 222 and compound medium layer
The first metal is deposited on 220 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound Jie
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of metal level may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, form Ohm contact electrode window 219.
Carrying out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 219；Through Ohm contact electrode window 219, it can be seen that the portion of compound medium layer 220
Divide surface.In this way, the first metal on source contact openings 121 constitutes the source electrode 231 of device, on drain contact hole 222
One metal constitutes the drain electrode 232 of device.Now, in order to clear expression process of the present invention, the device that name now obtains is
First assembly.
Step 204, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching to contact with each other
Category forms alloy after being reacted with aluminum gallium nitride 214.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so as to which the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 214 on its contact surface, so as to
The contact resistance between the first metal and aluminum gallium nitride 214 can be reduced.That is, source electrode 231, drain electrode 232 and aluminium nitride are reduced
Contact resistance between gallium layer 214.
Step 205, by Ohm contact electrode window 219, compound medium layer 220 and aluminum gallium nitride 214 are done
Method etches, and forms gate contact hole 223, wherein, the bottom in gate contact hole 223 has pre- with the bottom of aluminum gallium nitride 214
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 219, to compound medium layer
220 and partial aluminum gallium nitride 214, dry etching is carried out, and then a gate contact hole is formed on the first device
223.Wherein, gate contact hole 223 completely breaks through compound medium layer 220, and through the aluminum gallium nitride 214 of part, makes
The bottom of bottom and the aluminum gallium nitride 214 in gate contact hole 223 distance H be preferably aluminum gallium nitride 214 half.
In the present embodiment, formed after a gate contact hole 223, can there is impurity, particle in gate contact hole 223
And the impurity thing such as ion, will be miscellaneous in gate contact hole 220 so as to clean gate contact hole 220 using hydrochloric acid solution
Matter thing is got rid of.
The present embodiment using DHF+SC1+SC2 method by after dry etching is carried out to compound medium layer 220, being gone
Except the impurity thing on device；And formed after gate contact hole 223, using hydrochloric acid solution by the impurity in gate contact hole 223
Thing is got rid of.So as to the cleaning being effectively guaranteed in the surface of compound medium layer and gate contact hole 223, Jin Erbao
The performance of gallium nitride semiconductor device is demonstrate,proved.
Step 206, in the present embodiment, specifically, using magnetron sputtering membrane process, sunk in gate contact hole 223
One layer of silicon nitride layer of product is not higher than the gate contact hole 223 as gate dielectric layer, the silicon nitride layer；Then again in the nitrogen
The outward flange on SiClx layer and gate contact hole 223 deposits Ni/Au as the second metal, and metal thickness is 0.01~0.04 μ
M/0.08~0.4 μm；So as to constitute grid 233.So the grid 233 is a kind of composite construction with multiple material.
Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 207, a layer insulating 240 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface of whole second component deposition layer of silicon dioxide (SiO2), thickness can
For example, 5000 angstroms, silicon dioxide layer is formed as a layer insulating 240.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 231, drain electrode 232 and the presence of grid 233, so as in source electrode 231 and grid
Insulating barrier 240 between pole 233, the insulating barrier 240 between grid 233 and drain electrode 232 are to lower recess, using polishing
Technique is allowed to smooth.
Step 208, after the insulating barrier 140 above source contact openings 231 carries out dry etching, perforate 241 is formed.Institute
Stating grid 233 has the protuberance 233a protruded from outside the gate contact hole 223, and the width of the perforate 241 is less than described
Protuberance 233a width.
Step 209, in the insulation that perforate 241 is interior and is extended to from source contact openings 231 above gate contact hole 123
Field plate metal 250 is deposited on layer 240, forms field plate metal layer 250.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 241 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 221 above outer peripheral first metal in gate contact hole 223
Field plate metal is deposited on 220, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 250.The thickness of field plate metal layer 250
Degree be it is uniform, field plate metal layer 250 opening position and source contact openings 221 and the gate contact hole 223 of perforate 241 it
Between opening position be to lower recess, be allowed to smooth using polishing technique.
The present embodiment can improve electric conduction with optimised devices manufacture craft, optimised devices technique compatible with CMOS technology line
Resistance.And then the problem of avoiding the electric leakage and breakdown for gallium nitride semiconductor device occur, it is effectively protected gallium nitride and partly leads
Body device, enhance the reliability of gallium nitride semiconductor device.The gallium nitride semiconductor device that the present embodiment obtains can be applied to
In the technical fields such as power electronic element, wave filter, radio communication element, have a good application prospect.
It refer to shown in Fig. 2 a, a kind of gallium nitride semiconductor device be provided in embodiments of the present invention, it is wrapped from bottom to up
Include：Epitaxial layer of gallium nitride 310, compound medium layer 320, source electrode 331 and drain electrode 332, grid 333, insulating barrier 340, field plate metal
Layer 350.
Wherein, epitaxial layer of gallium nitride 310 is by silicon (Si) substrate 312, gallium nitride (GaN) layer 313 and aluminium gallium nitride alloy (AlGaN)
Layer 314 is formed, wherein, silicon substrate 312, gallium nitride layer 313 and aluminum gallium nitride 314 are from bottom to top set gradually.
Compound medium layer 320 is arranged on the epitaxial layer of gallium nitride 310；The compound medium layer 320 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 331, drain electrode 332 and grid 333 are arranged on the compound medium layer 320.Specifically, source electrode 331, drain electrode
332 and the outer image " nail " of grid 333 as a part be inserted into the compound medium layer 320, the source electrode 331, drain electrode 332
The compound medium layer 320 is extended through with grid 333 to be connected with the epitaxial layer of gallium nitride 310；And a part protrudes from institute
State the top of compound medium layer 320.The source electrode 331 and/or drain electrode 332 are made up of the first metal.The wherein component of the first metal
Structure is same as the previously described embodiments.Using the source electrode 331 of the first metal material formation, drain electrode 332, can be annealed in higher device temperature
During reacted with the aluminum gallium nitride layer 314 in the epitaxial layer of gallium nitride 310, generate alloy so that source electrode
331st, drain electrode 332 is good with the contact of the contact surface of aluminum gallium nitride, can effectively reduce source electrode 331, drain electrode 332 and nitridation
The contact resistance of gallium aluminium layer；The problem of avoiding the occurrence of the electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, with reference to shown in Fig. 2 b, the grid 333 of the present embodiment includes two connected side by side parts：Shorter is
It is enhanced first grid portion 333a, longer for depletion type second gate portion 333b.The first grid portion 333a and the aluminium gallium nitride alloy
The connection of 314 surface of layer, the second gate portion 333b are stretched into the aluminum gallium nitride 314.What this long and short two part was formed
Grid is different from existing grid, and " abnormal shape " is presented.
Further, the width D 1 of the first grid portion 333a is preferably not less than second gate portion 333b width D 2.Certainly,
In other embodiments, first grid portion 333a and second gate portion 333b right position can also exchange.
The grid 333b can be extended into down in the aluminum gallium nitride 314, and the grid 333b bottoms are described in
The distance H of the bottom of aluminum gallium nitride 314 is preferably the half of the whole aluminum gallium nitride 314.Whole grid 333 is by the second gold medal
Category composition, second metal is Ni, Au alloy.
Insulating barrier 340 is arranged at drain electrode 332, grid 333 and the top of a part of source electrode 331, and exposes the whole come
On compound medium layer 320, the material of the insulating barrier 340 is silica.Wherein, insulating barrier 340 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 331, drain electrode 332, the presence of grid 333, so as in source electrode
Insulating barrier 340 between 331 and grid 333, the insulating barrier 340 between grid 33 and drain electrode 332 are to lower recess, can be led to
Later continuous lapping process is allowed to smooth.
It can also for example include field plate metal layer 350, it is arranged on the insulating barrier 340.The field plate metal layer 350
It is connected through the insulating barrier 340 with the source electrode 331.Preferably, the material of the field plate metal layer 350 is aluminium copper silicon metal
Layer.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 2 c, specific steps include：
Step 301：Gallium nitride layer 313 and aluminum gallium nitride 314 are sequentially depositing on silicon substrate 312, is formed outside gallium nitride
Prolong layer 310.Gallium nitride is third generation semiconductor material with wide forbidden band, has big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts are per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 310
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 120.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 302, dry etching is carried out to the compound medium layer 320, forms the He of source contact openings 321 being oppositely arranged
Drain contact hole 322.
In order that the source contact openings 321, the few impurity of the cleaning of drain contact hole 322 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 320, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
The alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then using at the acidic mixed solution of hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Step 303, in the present embodiment, in source contact openings 321 and drain contact hole 322 and compound medium layer
The first metal is deposited on 120 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound Jie
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 1200 angstroms, the second titanium
The thickness of metal level may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, form Ohm contact electrode window 319.
Carrying out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 319；Through Ohm contact electrode window 319, it can be seen that the portion of compound medium layer 320
Divide surface.In this way, the first metal on source contact openings 121 constitutes the source electrode 331 of device, on drain contact hole 322
One metal constitutes the drain electrode 332 of device.Now, in order to clear expression process of the present invention, the device that name now obtains is
First assembly.
Step 104, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching to contact with each other
Category and aluminum gallium nitride, 314 reacted after formation alloy.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so as to which the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 314 on its contact surface, so as to
The contact resistance between the first metal and aluminum gallium nitride 314 can be reduced.That is, source electrode 331, drain electrode 332 and aluminium nitride are reduced
Contact resistance between gallium layer 314.
Step 305, by Ohm contact electrode window, 319, compound medium layer 320 and aluminum gallium nitride 314 are done
Method etches, and forms gate contact hole 323, wherein, the bottom in gate contact hole 323 has pre- with the bottom of aluminum gallium nitride 314
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 319, to compound medium layer
320 and partial aluminum gallium nitride 314, dry etching is carried out, and then a gate contact hole is formed on the first device
323。
Wherein, when etching for the first time, only carried out in the part of compound medium layer 320, obtain the first shallower contact hole
323a；The amesiality progress among the first obtained contact hole 323a of first time etching during second of dry etching, and carve
Erosion runs through after whole compound medium layer 320 deeply to be carried out into partial nitridation gallium aluminium layer 314 again, forms deeper second contact hole
323b；So obtain overall gate contact hole 323.By controlling etch process parameters to adjust gate contact hole 323b width
Degree, to control the width D 1 in first grid portion, the proportionate relationship of the width D 2 in second gate portion.Then in the gate contact hole
323a, gate contact hole 323b and part compound medium layer 320 deposit Ni/Au, and metal thickness is 0.01~0.04 μm/
0.08~0.4 μm；Obtain grid 333.It follows that be actually interconnected between two gate contact holes, first grid portion
333a, second gate portion 333b preparation are also integrally formed.
Preferably, the second contact hole 323b completely breaks through compound medium layer 320, and passes through the aluminum gallium nitride of part
314 so that the distance H of the second contact hole 323b bottom and the bottom of aluminum gallium nitride 314 is preferably aluminum gallium nitride 314
Half.
In the present embodiment, formed after a gate contact hole 323, can there is impurity, particle in gate contact hole 323
And the impurity thing such as ion, will be miscellaneous in gate contact hole 320 so as to clean gate contact hole 320 using hydrochloric acid solution
Matter thing is got rid of.
Specifically, the present embodiment by compound medium layer 320 carry out dry etching after, using DHF+SC1+SC2
Method removal devices on impurity thing；And formed after gate contact hole 323, using hydrochloric acid solution by gate contact hole 323
Interior impurity thing is got rid of.It is clear in the surface of compound medium layer and gate contact hole 323 so as to be effectively guaranteed
It is clean, and then ensure that the performance of gallium nitride semiconductor device.
Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 307, whole second component surface deposit a layer insulating, 340.
In the present embodiment, specifically, in the surface of whole second component deposition layer of silicon dioxide (SiO2), thickness can
For example, 5000 angstroms, silicon dioxide layer is formed as a layer insulating 340.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 331, drain electrode 332 and the presence of grid 333, so as in source electrode 331 and grid
Insulating barrier 340 between pole 333, the insulating barrier 340 between grid 333 and drain electrode 332 are to lower recess, using polishing
Technique is allowed to smooth.
Step 308, after the insulating barrier 340 above source contact openings 331 carries out dry etching, perforate 341 is formed.Institute
Stating grid 333 has the protuberance 333a protruded from outside the gate contact hole 323, and the width of the perforate 341 is less than described
Protuberance 333a width.
Step 309, in the insulation that perforate 341 is interior and is extended to from source contact openings 331 above gate contact hole 323
Field plate metal 350 is deposited on layer 340, forms field plate metal layer 350.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 341 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 321 above outer peripheral first metal in gate contact hole 323
Field plate metal is deposited on 320, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 350.The thickness of field plate metal layer 350
Degree be it is uniform, field plate metal layer 350 opening position and source contact openings 221 and the gate contact hole 223 of perforate 341 it
Between opening position be to lower recess, can be allowed to smooth by the technique that polishes in subsequent step.
Beneficial effect：
The gallium nitride semiconductor device of the present embodiment is using mixing grid structure, including short belongs to enhanced first grid portion
The 333a and long second gate portion 333b for belonging to depletion type.Under the conditions of OFF state, first grid portion 333a shut-offs, and second gate portion
333b can pin groove potential under drain voltage, there is provided high blocking ability；During ON state, enhancement type channel and depletion type ditch
Road provides low channel resistance, ensures high conducting electric current and low conducting resistance.The gallium nitride semiconductor that the present embodiment obtains
Device can be applied in the technical fields such as power electronic element, wave filter, radio communication element, before having good application
Scape.
As shown in Figure 3 a, the embodiment of the present invention provides a kind of gallium nitride semiconductor device, and it includes from bottom to up：Gallium nitride
Epitaxial layer 610, compound medium layer 620, source electrode 631 and drain electrode 632, grid 633, insulating barrier 640, field plate metal layer 650.
Wherein, epitaxial layer of gallium nitride 610 is by silicon (Si) substrate 612, gallium nitride (GaN) layer 613 and aluminium gallium nitride alloy (AlGaN)
Layer 614 is formed, wherein, silicon substrate 612, gallium nitride layer 613 and aluminum gallium nitride 614 are from bottom to top set gradually.
Compound medium layer 620 is arranged on the epitaxial layer of gallium nitride 610；The compound medium layer 620 of the present embodiment
Material may be, for example, silicon nitride and plasma enhancing tetraethoxysilance (PETEOS).The silicon nitride and the positive silicon of plasma enhancing
Sour second fat belongs to a kind of high-k (high-k) medium.
Source electrode 631, drain electrode 632 and grid 633 are arranged on the compound medium layer 620.Specifically, source electrode 631, drain electrode
632 and the outer image " nail " of grid 633 as a part be inserted into the compound medium layer 620, the source electrode 631, drain electrode 632
The compound medium layer 620 is extended through with grid 633 to be connected with the epitaxial layer of gallium nitride 610；And a part protrudes from institute
State the top of compound medium layer 620.The source electrode 631 and/or drain electrode 632 by the first metal form and above-described embodiment shown in.Adopt
With the first metal material formed source electrode 631, drain electrode 632, can in higher device temperature annealing process with the epitaxy of gallium nitride
Aluminum gallium nitride layer 614 in layer 610 reacts, and generates alloy, so that source electrode 631, drain electrode 632 and aluminum gallium nitride
The contact of contact surface is good, can effectively reduce source electrode 631, drain electrode 632 and the contact resistance of aluminum gallium nitride；Avoid the occurrence of
The problem of electric leakage and soft breakdown of gallium nitride semiconductor device.
Preferably, the grid 633 is down extended into the aluminum gallium nitride 614 and gone directly to the aluminium gallium nitride alloy
614 bottom of layer, obtain one " penetrating type grid ".Grid 633 is made up of the second metal, and second metal is Ni, Au alloy.
Insulating barrier 640 is arranged at drain electrode 632, grid 633 and the top of a part of source electrode 631, and exposes the whole come
On compound medium layer 620, the material of the insulating barrier 640 is silica.Wherein, insulating barrier 640 is on the surface of whole device
Uniform deposition is carried out, the thickness precipitated everywhere is identical.Due to source electrode 631, drain electrode 632, the presence of grid 633, so as in source electrode
Insulating barrier 640 between 631 and grid 633, the insulating barrier 640 between grid 633 and drain electrode 632 be to lower recess, can
It is allowed to smooth using technique is polished.
It can also for example include field plate metal layer 650, it is arranged on the insulating barrier 640.The field plate metal layer 650
It is connected through the insulating barrier 640 with the source electrode 631.Preferably, the material of the field plate metal layer 650 is aluminium copper silicon metal
Layer.
Grid 633 in above-mentioned gallium nitride semiconductor device penetrates whole aluminum gallium nitride and reaches gallium nitride layer, can suppress
The high electric field of gate edge, the stable blocking characteristics of gallium nitride high tension apparatus are effectively guaranteed, make device repeatedly high in process
After pressure, good reliability can be still kept.
The present invention also provides the preparation method of above-mentioned gallium nitride semiconductor device.As shown in Figure 3 b, specific steps include：
Step 601：Gallium nitride layer 613 and aluminum gallium nitride 614 are sequentially depositing on silicon substrate 612, is formed outside gallium nitride
Prolong layer 610.Gallium nitride is third generation semiconductor material with wide forbidden band, has big energy gap, high electron saturation velocities, high breakdown potential
Characteristics such as field, higher heat-conductivity, corrosion-resistant and radiation resistance and in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase ring
There is stronger advantage, so as to be the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device under the conditions of border
Material；Wherein, big energy gap is 3.4 electron-volts, and high electron saturation velocities are 2e7 centimeters per seconds, and high breakdown electric field is 1e10
~-3e10 volts are per cm.
Then chemical gaseous phase electrodeposition method can be strengthened with using plasma, is sunk on the surface of epitaxial layer of gallium nitride 610
One layer of silicon nitride of product and plasma enhancing tetraethoxysilance (PETEOS), form compound medium layer 620.Wherein, silicon nitride and
The thickness of plasma enhancing tetraethoxysilance for example can be 2000 angstroms.
Step 602, dry etching is carried out to the compound medium layer 620, forms the He of source contact openings 21 being oppositely arranged
Drain contact hole 622.
In order that the source contact openings 621, the few impurity of the cleaning of drain contact hole 622 are obtained, in addition to removal step.Specifically
, after dry etching is carried out to compound medium layer 620, it can first use " DHF (dilute hydrofluoric acid)+chemical SC-
1+ chemicals SC-2 " method, for example, can then be used first using the hydrofluoric acid solution processing apparatus after dilution
The alkaline mixed solution processing apparatus of hydrogen oxide and aqua ammonia, then using at the acidic mixed solution of hydrogen peroxide and hydrogen chloride
Device is managed, and then the impurity thing on the surface of whole device can be removed.
Step 603, in the present embodiment, in source contact openings 621 and drain contact hole 622 and compound medium layer
The first metal 621 is deposited on 620 surface.
Specifically, magnetron sputtering membrane process can be used, in source contact openings and drain contact hole and compound Jie
On the surface of matter layer, the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer are sequentially depositing, to form first
Metal；Wherein, the thickness of the first titanium coating may be, for example, 200 angstroms, and the thickness of aluminum metal layer may be, for example, 6200 angstroms, the second titanium
The thickness of metal level may be, for example, 200 angstroms, and the thickness of titanium nitride layer may be, for example, 200 angstroms.
Photoetching and etching are carried out to the first metal, form Ohm contact electrode window 619.
Carrying out photoetching and etching to the first metal, the program of wherein photoetching includes gluing, exposed and developed, so as to
Form an Ohm contact electrode window 619；Through Ohm contact electrode window 619, it can be seen that the portion of compound medium layer 620
Divide surface.In this way, the first metal on source contact openings 621 constitutes the source electrode 631 of device, on drain contact hole 622
One metal constitutes the drain electrode 632 of device.Now, in order to clear expression process of the present invention, the device that name now obtains is
First assembly.
Step 604, the high temperature anneal is carried out to whole first assembly, to pass through the first gold medal after the etching to contact with each other
Category forms alloy after being reacted with aluminum gallium nitride 614.
In the present embodiment, specifically, being passed through nitrogen gas in reacting furnace, to whole in the environment of 840~850 DEG C
First assembly carries out the high temperature anneal of 30 seconds, so as to which the first metal after etching can turn into alloy, and contact with each other
The first metal after etching can also also form alloy after being reacted with aluminum gallium nitride 614 on its contact surface, so as to
The contact resistance between the first metal and aluminum gallium nitride 614 can be reduced.That is, source electrode 631, drain electrode 632 and aluminium nitride are reduced
Contact resistance between gallium layer 14.
Step 605, by Ohm contact electrode window 619, compound medium layer 620 and aluminum gallium nitride 614 are done
Method etches, and forms gate contact hole 623, wherein, the bottom in gate contact hole 623 has pre- with the bottom of aluminum gallium nitride 614
If distance.
In the present embodiment, using the method for dry etching, by Ohm contact electrode window 619, to compound medium layer
620 and partial aluminum gallium nitride 614, dry etching is carried out, and then a gate contact hole is formed on the first device
623.Wherein, gate contact hole 623 completely breaks through compound medium layer 620, and through the aluminum gallium nitride 614 of part, makes
The bottom of bottom and the aluminum gallium nitride 614 in gate contact hole 623 distance H be preferably aluminum gallium nitride 614 half.
In the present embodiment, formed after a gate contact hole 623, can there is impurity, particle in gate contact hole 623
And the impurity thing such as ion, will be miscellaneous in gate contact hole 620 so as to clean gate contact hole 620 using hydrochloric acid solution
Matter thing is got rid of.
The present embodiment using DHF+SC1+SC2 method by after dry etching is carried out to compound medium layer 620, being gone
Except the impurity thing on device；And formed after gate contact hole 623, using hydrochloric acid solution by the impurity in gate contact hole 623
Thing is got rid of.So as to the cleaning being effectively guaranteed in the surface of compound medium layer and gate contact hole 623, Jin Erbao
The performance of gallium nitride semiconductor device is demonstrate,proved.
Step 606, in the present embodiment, specifically, using magnetron sputtering membrane process, in gate contact hole 623 and grid
For the outward flange deposition Ni/Au of pole contact hole 623 as the second metal, metal thickness is 0.01~0.04 μm/0.08~0.4 μm；
So as to constitute grid 633.Now, in order to become apparent from expressing present invention, it is the second component to name the device now obtained.
Step 607, a layer insulating 640 is deposited on the surface of whole second component.
In the present embodiment, specifically, in the surface of whole second component deposition layer of silicon dioxide (SiO2), thickness can
For example, 5000 angstroms, silicon dioxide layer is formed as a layer insulating 640.Wherein, silica enters on the surface of whole device
Row uniform deposition, thickness is identical everywhere, due to source electrode 631, drain electrode 632 and the presence of grid 633, so as in source electrode 631 and grid
Insulating barrier 640 between pole 633, the insulating barrier 640 between grid 633 and drain electrode 632 are to lower recess, using polishing
Technique is allowed to smooth.
Step 608, after the insulating barrier 640 above source contact openings 631 carries out dry etching, perforate 641 is formed.Institute
Stating grid 33 has the protuberance 633a protruded from outside the gate contact hole 623, and the width of the perforate 641 is less than described convex
Go out portion 633a width.
Step 609, in the insulation that perforate 641 is interior and is extended to from source contact openings 631 above gate contact hole 623
Field plate metal 650 is deposited on layer 640, forms field plate metal layer 650.
In the present embodiment, specifically, magnetron sputtering membrane process can be used, connect in perforate 641 and from source electrode
Compound medium layer of outer peripheral first metal of contact hole 621 above outer peripheral first metal in gate contact hole 623
Field plate metal is deposited on 620, thickness may be, for example, 10000 angstroms, so as to form field plate metal layer 650.The thickness of field plate metal layer 650
Degree be it is uniform, field plate metal layer 650 opening position and source contact openings 621 and the gate contact hole 623 of perforate 641 it
Between opening position be to lower recess, pass through polishing technique and can be allowed to smooth in subsequent step.
The present embodiment replaces existing silicon oxide layer by depositing compound medium layer on the surface of epitaxy of gallium nitride substrate
As compound medium layer；The high temperature anneal technique is recycled, makes the aluminum gallium nitride in source electrode, drain electrode and epitaxial layer of gallium nitride
Alloy is formed after being reacted, so that source electrode, drain electrode contact with the contact surface of aluminum gallium nitride are good, can be effective
The contact resistance for reducing source electrode, drain electrode and aluminum gallium nitride；Avoid the occurrence of the electric leakage of gallium nitride semiconductor device and soft hit
The problem of wearing.Further, the structure of grid is optimized so that grid penetrates whole aluminum gallium nitride, it is compatible with CMOS technology line,
Electric Field Distribution is adjusted, the pressure-resistant of device is improved with this.The gallium nitride semiconductor device that the present embodiment obtains can be applied to electric power
In the technical fields such as electronic component, wave filter, radio communication element, have a good application prospect.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
- A kind of 1. gallium nitride semiconductor device, it is characterised in that including：Epitaxial layer of gallium nitride；AndThe compound medium layer being arranged on the epitaxial layer of gallium nitride, the compound medium layer material are silicon nitride and plasma Strengthen tetraethoxysilance；Source electrode, the drain and gate being arranged on the compound medium layer, the source electrode, drain and gate extend through described multiple Dielectric layer is closed to be connected with the epitaxial layer of gallium nitride；Wherein, there is gate medium between the grid and the epitaxial layer of gallium nitride Layer；The insulating barrier being arranged on the source electrode, drain and gate and the compound medium layer, the material of the insulating barrier are Silica；Also include the field plate metal layer being arranged on the insulating barrier, the field plate metal layer is through the insulating barrier and the source Pole connects.
- 2. gallium nitride semiconductor device according to claim 1, it is characterised in that the epitaxial layer of gallium nitride serves as a contrast including silicon Bottom, and be arranged at the gallium nitride layer of the surface of silicon, be arranged at the aluminum gallium nitride on the gallium nitride layer surface.
- 3. gallium nitride semiconductor device according to claim 1, it is characterised in that the grid down extends into the nitridation In gallium aluminium layer.
- 4. gallium nitride semiconductor device according to claim 3, it is characterised in that the grid bottom to the aluminium gallium nitride alloy The distance of layer bottom is the half of the whole aluminum gallium nitride.
- 5. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the thickness of the compound medium layer Spend for 2000 angstroms.
- 6. according to the gallium nitride semiconductor device of claim 1 or 2 or 3 or described, it is characterised in that the gate dielectric layer is nitridation Silicon.
- 7. a kind of preparation method of gallium nitride semiconductor device, it is characterised in that comprise the following steps：One epitaxial layer of gallium nitride is provided, wherein, the epitaxial layer of gallium nitride includes layer-of-substrate silicon, the nitrogen from bottom to top set gradually Change gallium layer and aluminum gallium nitride；In the epitaxy of gallium nitride layer surface deposited silicon nitride and plasma enhancing tetraethoxysilance, compound medium layer is formed；The acquisition of source contact openings and drain contact hole：The compound medium layer is etched, to form separate source contact Hole and drain contact hole, the source contact openings, the drain contact hole reach the aluminium nitride through the compound medium layer Gallium layer；In the source contact openings and the drain contact hole and on the surface of the compound medium layer, the first gold medal is deposited Category, to obtain source electrode, drain electrode；Photoetching and etching are carried out to first metal, form Ohm contact electrode window；Now obtain first assembly；The high temperature anneal is carried out to the first assembly, to be contained in the source contact openings and the drain contact hole Interior first metal forms alloy and reacted with the aluminum gallium nitride；The acquisition in gate contact hole：By the Ohm contact electrode window, to the compound medium layer and the aluminium gallium nitride alloy Layer carries out dry etching, forms gate contact hole, wherein, the bottom in the gate contact hole and the bottom of the aluminum gallium nitride Between there is pre-determined distance；First deposited silicon nitride is as gate dielectric layer in the gate contact hole；Then again on the gate dielectric layer, the grid The outward flange of pole contact hole deposits the second metalwork, to obtain grid, now obtains the second component；A layer insulating is deposited on the surface of second component；Dry etching is carried out on the insulating barrier, to form perforate, the perforate is corresponding with the source contact openings；Field plate metal layer is deposited in the perforate and the insulating barrier, the projection of the field plate metal layer at least covers described Perforate and from the source contact openings to the region between the gate contact hole.
- 8. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the width of the perforate is small In the protuberance width that the grid is protruded from above the gate contact hole.
- 9. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the high temperature anneal Step is：In the case where protecting atmosphere, kept for 30~60 seconds at a temperature of 840~850 DEG C.
- 10. the preparation method of gallium nitride semiconductor device according to claim 7, it is characterised in that the pre-determined distance is The half of the thickness of the aluminum gallium nitride.
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