CN109980007A - 一种提高横向耐压的大功率埋层结构 - Google Patents

一种提高横向耐压的大功率埋层结构 Download PDF

Info

Publication number
CN109980007A
CN109980007A CN201711454894.1A CN201711454894A CN109980007A CN 109980007 A CN109980007 A CN 109980007A CN 201711454894 A CN201711454894 A CN 201711454894A CN 109980007 A CN109980007 A CN 109980007A
Authority
CN
China
Prior art keywords
oxide layer
buried oxide
drain terminal
shaped
breakdown voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711454894.1A
Other languages
English (en)
Inventor
陆宇
沈立
周润宝
沈金龙
程玉华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Core Microelectronics Polytron Technologies Inc
Shanghai Zhuo Micro System Technology Co Ltd
Shanghai Research Institute of Microelectronics of Peking University
Original Assignee
Shanghai Core Microelectronics Polytron Technologies Inc
Shanghai Zhuo Micro System Technology Co Ltd
Shanghai Research Institute of Microelectronics of Peking University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Core Microelectronics Polytron Technologies Inc, Shanghai Zhuo Micro System Technology Co Ltd, Shanghai Research Institute of Microelectronics of Peking University filed Critical Shanghai Core Microelectronics Polytron Technologies Inc
Priority to CN201711454894.1A priority Critical patent/CN109980007A/zh
Publication of CN109980007A publication Critical patent/CN109980007A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

本文公开了一种提高SOI器件击穿电压的器件新结构,其中主要包括埋层结构,埋氧层在源端和漏端成U型。利用U型埋氧层在大的漏端电压时正电荷不易被抽走提高击穿电压;源端U型介质埋氧层在漏端电压较大时保证击穿不会发生在p阱和漂移区形成的耗尽区,漏端U型介质埋层通过积累大量正电荷来提高击穿电压。

Description

一种提高横向耐压的大功率埋层结构
技术领域
本发明涉及半导体器件领域,更具体的涉及一种绝缘体上硅高压器件结构。
背景技术
SOI高压器件是SOI SPIC的重要组成部分,以其寄生效应小,功耗小,速度高,集成度高,抗辐射能力强,消除了闭锁效应等受到了广泛关注。SOI器件的耐压由横向耐压和纵向耐压来决定。SOI器件的横向耐压和体硅器件的横向耐压相似,可以将比较成熟的体硅结终端技术应用到SOI器件上来。而对S01器件的纵向耐压,则与体硅器件有较大的差别,是决定SOI器件耐压的主要因素。
先前提高击穿电压的方法有(1)在SI层和SiO2界面加一层N+缓冲层来提高埋氧层承担的电压。(2)Si02上加一薄层高阻SIPOS层来屏蔽衬底偏压的影响。(3)漂移区线性掺杂结构。(4)屏蔽槽结构。(5)阶梯型埋氧层结构。(6)复合型埋氧层结构。
下面以屏蔽槽结构为例阐述现有的SOI高压器件结构。
图2是现有技术中SOI高压器件的结构示意图。主要特点在埋氧层上由源到漏有排列均匀的绝缘屏蔽槽,通过绝缘屏蔽槽阻挡产生的正电荷被抽走,从而在埋氧层上形成一层附加的正电荷,产生附加电场增强埋层电场以提高器件纵向耐压,源极下的硅窗口在提高耐压的同时缓解了器件的自热效应。
发明内容
本发明在于提供一种SOI器件新结构,以提高其纵向击穿电压,实现高压,高速,低导通电阻的SOI器件。
可选的,埋氧层可以是U型或是V型。
本发明提供一种SOI器件新结构在原有的基础上提出了U型埋氧层新结构。
本发明SOI器件新结构,源端和漏端都是U型的埋氧层结构。
漏端下的U型的埋氧层结构主要用于改善器件的击穿电压。
源端下的埋氧层开有槽,使衬底和顶层硅连接,在提高击穿电压的同时,降低自热效应。
本发明实施例与传统的高压器件相比,U型埋氧层使得源端的击穿电压增加,不会使击穿发生在p阱和漂移区接触处,并且由于U型埋氧层致使导通电阻降低。漏端下的U型埋氧层使得漏端形成附加的正电荷层,提高氧化层所承担的电压,从而提高了器件的击穿电压,氧化层结构使得工艺更加简单。
附图说明
图1是现有技术中高压SOI器件的结构示意图;
图2是改进后的高压SOI器件的结构示意图;
图3是改进后的高压SOI器件界面处电荷分布示意图;
具体实施方式
图2是本发明实施例中高压SOI器件侧视视结构示意图,该结构将埋氧层改变成源端和漏端都是U型埋氧层。
图1是现有技术中高压SOI器件的结构示意图,该结构埋氧层埋氧层上由源到漏有排列均匀的绝缘屏蔽槽。
U型埋氧层使源端p阱下方厚度足够大,在漏端加足够大的电压时,源端耗尽区可以承受更多的电压,不会使击穿发生在源端p阱与漂移区界面处。同时由于U型结构,衬底与氧化层界面处引起负电荷集聚,集聚的负电荷可以对上层硅与氧化层界面的电场分布调制,使电场线分布更加均匀进一步增加击穿电压。
在漏端加足够大的电压时,U型埋氧层阻止正电荷被大的正漏电压抽走,形成一层正电荷层,积累在漏端下的氧化层表面,屏蔽氧化层表面内的电场,使纵向击穿电压增大。
上述实施例仅以U型埋氧层为例来说明本发明,实际上,只要使漏端和源端形成的正电荷在大的正向电压时不会被抽走,例如V型埋氧层,使漏端的氧化层可以承担更高电压的埋氧层结构都会比原有的SOI器件击穿电压要高。

Claims (6)

1.一种SOI高压器件新结构,包括漂移区,埋氧层,衬底,其特征是影响击穿电压主要因素是漏端纵向击穿电压,并且埋氧层结构可以提SOI器件的击穿电压。
2.根据权利要求1所术的SOI高压器件,其特征是源端p阱和漂移区形成的耗尽区不会在漏端击穿前击穿。
3.根据权利要求1所术的SOI高压器件,其特征是源端p阱下的漂移区足够厚。
4.根据权利要求1所术的SOI高压器件,其特征是漏端埋氧层结构可以提高氧化层承担的电压。
5.根据权利要求3所术的SOI高压器件,其特征是源端下方将是U型埋氧层。
6.根据权利要求4所术的SOI高压器件,其特征是漏端埋氧层也将是U型埋氧层。
CN201711454894.1A 2017-12-28 2017-12-28 一种提高横向耐压的大功率埋层结构 Pending CN109980007A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711454894.1A CN109980007A (zh) 2017-12-28 2017-12-28 一种提高横向耐压的大功率埋层结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711454894.1A CN109980007A (zh) 2017-12-28 2017-12-28 一种提高横向耐压的大功率埋层结构

Publications (1)

Publication Number Publication Date
CN109980007A true CN109980007A (zh) 2019-07-05

Family

ID=67074148

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711454894.1A Pending CN109980007A (zh) 2017-12-28 2017-12-28 一种提高横向耐压的大功率埋层结构

Country Status (1)

Country Link
CN (1) CN109980007A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024012428A1 (zh) * 2022-07-12 2024-01-18 无锡华润上华科技有限公司 半导体器件及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024012428A1 (zh) * 2022-07-12 2024-01-18 无锡华润上华科技有限公司 半导体器件及其制备方法

Similar Documents

Publication Publication Date Title
TWI550858B (zh) 半導體裝置及其製造方法
CN104347698B (zh) 半导体装置
CN109920854A (zh) Mosfet器件
JP6588340B2 (ja) 窒化物パワーデバイスおよびその製造方法
CN103928522B (zh) 一种槽型积累层mosfet器件
US9627519B2 (en) Semiconductor device
CN102403349B (zh) Ⅲ族氮化物mishemt器件
US20140320193A1 (en) Semiconductor device
US20160118488A1 (en) Field effect transistor
US9263560B2 (en) Power semiconductor device having reduced gate-collector capacitance
CN105322020A (zh) 高压金属氧化物半导体器件及其形成方法
CN102832213B (zh) 一种具有esd保护功能的ligbt器件
CN103560145B (zh) 一种具有界面栅的soi功率器件结构
CN109980007A (zh) 一种提高横向耐压的大功率埋层结构
CN102420247B (zh) Ⅲ族氮化物hemt器件
KR101685572B1 (ko) 바닥 산화막의 전계를 감소시키는 실리콘 카바이드 모스펫 소자 및 그의 제조 방법
CN104201204A (zh) 横向对称dmos管及其制造方法
CN102790090A (zh) 一种基于高k材料的ldmos器件
CN110047931A (zh) 碳化硅平面垂直型场效应晶体管及其制作方法
CN108054194B (zh) 一种具有三维横向变掺杂的半导体器件耐压层
CN105097928A (zh) Soi器件新结构
CN106601800B (zh) 一种沟槽绝缘栅双极型晶体管
CN109979985A (zh) 一种提高击穿电压的大功率器件模块结构
CN106252404B (zh) 一种具有高k介质槽的纵向增强型mis hemt器件
CN105990437A (zh) 半导体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190705

WD01 Invention patent application deemed withdrawn after publication