CN109979810B - Self-aligned gate structure and manufacturing method thereof, and self-aligned gate width structure and manufacturing method thereof - Google Patents
Self-aligned gate structure and manufacturing method thereof, and self-aligned gate width structure and manufacturing method thereof Download PDFInfo
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- CN109979810B CN109979810B CN201910175487.XA CN201910175487A CN109979810B CN 109979810 B CN109979810 B CN 109979810B CN 201910175487 A CN201910175487 A CN 201910175487A CN 109979810 B CN109979810 B CN 109979810B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 238000001883 metal evaporation Methods 0.000 claims abstract description 4
- 238000010992 reflux Methods 0.000 claims description 10
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention provides a method for manufacturing a self-aligned gate structure, which comprises the following steps: 1) coating a first photoresist on the upper surface of the epitaxial layer; 2) forming a gate groove on the upper surface of the epitaxial layer through a first photomask, exposure, development and etching; 3) reflowing the first photoresist left after etching to the gate groove by a reflow process to form a T-shaped gate width; 4) coating a second photoresist on the upper surface of the first photoresist, forming the appearance of a T-shaped gate cap through a second photomask and exposure development, and etching to form the appearance of a T-shaped gate on the basis, wherein the T-shaped gate cap is communicated with the width of the T-shaped gate; 5) and after metal evaporation is carried out on the appearance of the T-shaped gate, the first photoresist and the second photoresist are stripped to form a T-shaped gate structure. According to the self-aligned gate structure and the manufacturing method thereof, extremely high alignment is achieved between the gate structure and the epitaxial resistor.
Description
Technical Field
The present invention relates to electronic components, and particularly to transistors.
Background
In the prior art, when a gate structure is manufactured, the following steps are generally sampled:
recessed EPI Recesses (gate Recess): using RE mask to complete RE PH (PH: yellow light) process, then performing RE etching and RE photoresist removal to form processed EPI process;
t-gate stem (T-gate width): coating GS (GS: Gate stem Gate width) photoresist, exposing with GS mask, and reducing GS line width into T-Gate stem by using photoresist reflux;
t-gate Top (T-type gate cap): coating GT (GT: Gate Top) photoresist, and using GT mask to make T-Gate Top
The prior art has the following defects: and (5) completing the T-shaped gate process by utilizing three layers of light masks and two times of exposure alignment operation. The two-exposure alignment refers to the exposure alignment of GS and RE, and the exposure alignment of GT and GS is performed for a large number of times.
Disclosure of Invention
The invention aims to provide a self-aligned gate structure and a manufacturing method thereof, and improve the alignment between the gate structure and a resistor.
In order to solve the above technical problem, the present invention provides a method for manufacturing a self-aligned gate structure, comprising the following steps:
1) coating a first photoresist on the upper surface of the epitaxial layer;
2) forming a gate groove on the upper surface of the epitaxial layer through a first photomask, exposure, development and etching;
3) reflowing the first photoresist left after etching to the gate groove by a reflow process to form a T-shaped gate width;
4) coating a second photoresist on the upper surface of the first photoresist, forming a T-shaped gate morphology through a second photomask, exposure development and etching, wherein a T-shaped gate cap is formed on the second photoresist, and the T-shaped gate cap is communicated with the T-shaped gate width;
5) and stripping the first photoresist and the second photoresist after metal evaporation is carried out on the T-shaped gate cap and the T-shaped gate width.
In a preferred embodiment: the time interval between the coating of the second photoresist and the exposure and development of the second photoresist is not more than 4 hours.
In a preferred embodiment: the temperature of the first photoresist is between 100 and 160 ℃, and the refluxing time is between 30 and 90 minutes.
The invention also provides a self-aligned gate structure comprising: the T-shaped gate structure stands on the gate groove of the epitaxial layer;
the T-shaped gate structure comprises a gate width and a gate cap, wherein the bottom of the gate width is positioned in the gate groove, and the top of the gate width is provided with the gate cap.
In a preferred embodiment: the side wall of the grid width and the inner wall of the grid groove are spaced at a certain distance.
The invention also provides a manufacturing method of the self-aligned gate width structure, which comprises the following steps: and reflowing the photoresist for manufacturing the resistor into the gate groove by a photoresist reflowing process, wherein the gap of the photoresist in the gate groove determines the gate width dimension.
In a preferred embodiment: the reflux temperature of the photoresist is 100-160 ℃, and the reflux time is 30-90 minutes
The invention also provides a self-aligned gate width feature structure, comprising: an epitaxial layer and photoresist; compared with the prior art, the gate groove formed on the epitaxial layer is characterized in that the first photoresist extends from the outside to the gate groove, and the gate width morphology is formed in the photoresist gap after the first photoresist extends in the gate groove, the technical scheme of the invention has the following beneficial effects:
1. only two sets of light shields are needed, so that the cost of the light shields is saved;
2. after the gate groove is finished, the photoresist is not required to be stripped, and the gate width appearance is made after direct reflux;
3. because the grating groove and the grating width use the same light resistance structure, the grating width is ensured to be positioned at the right middle position of the grating groove, and the grating width is prevented from deviating leftwards or rightwards in the grating groove. The gate recess has a very high alignment with the gate width.
Drawings
Fig. 1-6 are flow charts of methods for fabricating self-aligned gate structures in accordance with preferred embodiments of the present invention.
Detailed Description
In order to make the technical solution of the present invention clearer, the present invention will now be described in further detail with reference to the following embodiments and accompanying drawings:
the embodiment provides a manufacturing method of a self-aligned gate width structure, which comprises the following steps: and refluxing the photoresist for manufacturing the epitaxial resistor into the gate groove by a photoresist reflux process, wherein the gap of the photoresist in the concave part is the gate width morphology.
The self-aligned gate width structure obtained by the method comprises the following steps: epitaxial layer resistor and photoresist; and the first photoresist extends from the outside to the resistor concave part, and the gap of the first photoresist after being reduced forms a grid width appearance.
Because the grating groove and the grating width use the same basic photoresist appearance, the epitaxial resistor and the grating structure have extremely high alignment.
Through the above method for fabricating a self-aligned gate width structure, the present embodiment further provides a method for fabricating a self-aligned gate width structure, as shown in fig. 1 to 6, including the following steps:
1) coating a first photoresist RE PR on the upper surface of the epitaxial layer EPI as shown in FIG. 1;
2) forming a gate groove on the upper surface of the epitaxial layer EPI by a first photomask, exposure development and etching, as shown in fig. 2;
3) reflowing the first photoresist RE PR remained after etching into the concave part through a reflow process to form a T-shaped gate width morphology, as shown in FIG. 3;
the temperature of the first photoresist is between 100 and 160 ℃, and the refluxing time is between 30 and 90 minutes.
4) Coating a second photoresist GT PR on the upper surface of the first photoresist RE PR, and forming a T-shaped gate morphology on the second photoresist GT PR through a second photomask, exposure development and etching, wherein the morphology on the second photoresist is the morphology of a T-shaped gate cap which is communicated to the width of the T-shaped gate, as shown in FIG. 4;
the time interval between the coating of the second photoresist and the exposure and development of the second photoresist is not more than 4 hours.
5) And after metal evaporation is carried out on the T-shaped gate cap and the T-shaped gate width, the first photoresist RE PR and the second photoresist GT PR are stripped to form the T-shaped gate, as shown in the figures 5 and 6.
By the method, the self-aligned gate structure is prepared, and comprises the following steps: an epitaxial resistor and a T-shaped gate structure;
the T-shaped gate structure comprises a gate width and a gate cap, the bottom of the gate width is located in the resistor concave part and extends along the direction of the resistor concave part, and the top of the gate width is provided with the gate cap.
The manufacturing method of the self-aligned grid width structure only needs two sets of light masks, so that the cost of the light masks is saved; after the resistance concave part is finished, the photoresistance is not required to be stripped, and a gate cap is made after direct reflux; because the grating groove and the grating width use the same light resistance structure, the grating width is ensured to be positioned at the right middle position of the grating groove, and the grating width is prevented from deviating leftwards or rightwards in the grating groove. The gate recess has a very high alignment with the gate width.
The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and variations or technical scopes disclosed by the present invention can be easily conceived by those skilled in the art. Alternatives are intended to be included within the scope of the invention. Therefore, the protection scope of the present invention should be determined by the scope of the claims.
Claims (8)
1. A method for manufacturing a self-aligned gate structure is characterized by comprising the following steps:
1) coating a first photoresist on the upper surface of the epitaxial layer;
2) forming a gate groove on the upper surface of the epitaxial layer through a first photomask, exposure, development and etching;
3) reflowing the first photoresist left after etching to the gate groove by a reflow process to form a T-shaped gate width;
4) coating a second photoresist on the upper surface of the first photoresist, forming a T-shaped gate morphology through a second photomask, exposure development and etching, wherein a T-shaped gate cap is formed on the second photoresist, and the T-shaped gate cap is communicated with the T-shaped gate width;
5) and stripping the first photoresist and the second photoresist after metal evaporation is carried out on the T-shaped gate cap and the T-shaped gate width.
2. The method of claim 1, wherein: the time interval between the coating of the second photoresist and the exposure and development of the second photoresist is not more than 4 hours.
3. The method of claim 1, wherein: the temperature of the first photoresist is between 100 and 160 ℃, and the refluxing time is between 30 and 90 minutes.
4. A self-aligned gate structure prepared by the method of claim 1, 2 or 3, comprising: the T-shaped gate structure stands on the gate groove of the epitaxial layer;
the T-shaped gate structure comprises a gate width and a gate cap, wherein the bottom of the gate width is positioned in the gate groove, and the top of the gate width is provided with the gate cap.
5. A self-aligned gate structure according to claim 4, wherein: the side wall of the grid width and the inner wall of the grid groove are spaced at a certain distance.
6. A method for manufacturing a self-aligned gate width structure is characterized by comprising the following steps:
1) coating a first photoresist on the upper surface of the epitaxial layer;
2) forming a gate groove on the upper surface of the epitaxial layer through a first photomask, exposure, development and etching;
3) and reflowing the first photoresist remained after etching into the gate groove by a photoresist reflowing process, wherein the gap of the photoresist in the gate groove determines the gate width dimension.
7. The method of claim 6, wherein: the photoresist reflowing temperature is 100-160 ℃, and the reflowing time is 30-90 minutes.
8. A self-aligned gate width structure prepared by the method of claim 6 or 7, comprising: an epitaxial layer and photoresist; and the first photoresist extends from the outside to the gate groove, and the gate width morphology is formed in the photoresist gap after the first photoresist extends in the gate groove.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910175487.XA CN109979810B (en) | 2019-03-08 | 2019-03-08 | Self-aligned gate structure and manufacturing method thereof, and self-aligned gate width structure and manufacturing method thereof |
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| CN201910175487.XA CN109979810B (en) | 2019-03-08 | 2019-03-08 | Self-aligned gate structure and manufacturing method thereof, and self-aligned gate width structure and manufacturing method thereof |
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| CN109979810B true CN109979810B (en) | 2021-06-25 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330010A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院微电子研究所 | Method for manufacturing T-shaped HBT emitter/HEMT grid |
| CN103715077A (en) * | 2014-01-06 | 2014-04-09 | 中国科学院微电子研究所 | Manufacturing method of deep submicron U-shaped gate groove |
| CN104882373A (en) * | 2015-04-24 | 2015-09-02 | 石以瑄 | Method for manufacturing transistor T-shaped gate |
| CN108962726A (en) * | 2017-05-17 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100578763B1 (en) * | 2004-10-12 | 2006-05-12 | 한국전자통신연구원 | Fabrication method for T-type gate |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330010A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院微电子研究所 | Method for manufacturing T-shaped HBT emitter/HEMT grid |
| CN103715077A (en) * | 2014-01-06 | 2014-04-09 | 中国科学院微电子研究所 | Manufacturing method of deep submicron U-shaped gate groove |
| CN104882373A (en) * | 2015-04-24 | 2015-09-02 | 石以瑄 | Method for manufacturing transistor T-shaped gate |
| CN108962726A (en) * | 2017-05-17 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
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