CN106783746B - Array substrate manufacturing method - Google Patents
Array substrate manufacturing method Download PDFInfo
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- CN106783746B CN106783746B CN201611214086.3A CN201611214086A CN106783746B CN 106783746 B CN106783746 B CN 106783746B CN 201611214086 A CN201611214086 A CN 201611214086A CN 106783746 B CN106783746 B CN 106783746B
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- 239000000758 substrate Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 100
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 38
- 238000001312 dry etching Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000004380 ashing Methods 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 36
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 3
- 238000005286 illumination Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a manufacturing method of an array substrate, which comprises the steps of sequentially forming an insulating layer, a semiconductor base layer, an ohmic contact base layer and a second metal layer on a substrate; forming a light resistance layer on the second metal layer, and patterning the light resistance layer to form a first light resistance area and a second light resistance area; performing first half-dry etching on the semiconductor base layer and the ohmic contact base layer according to the patterned photoresist layer; performing first ashing treatment on the patterned photoresist layer, and performing second half-dry etching on the semiconductor base layer and the ohmic contact base layer after the first half-dry etching according to the first photoresist region after the first ashing treatment; ashing the first photoresist area of the photoresist layer for the second time to expose part of the semiconductor layer and the ohmic contact base layer; and forming a data line, a drain line and an ohmic contact layer by etching the patterned second metal layer and the ohmic contact base layer twice.
Description
Technical Field
The invention relates to the technical field of liquid crystal panel manufacturing, in particular to a manufacturing method of an array substrate.
Background
Generally, a TFT-LCD array substrate production process is divided into 4 masks and 5 masks, and in order to improve productivity and reduce cost, the 4mask process is more and more widely used at present, because of the particularity of the 4mask process, a semiconductor base layer is arranged below an array substrate data line, the semiconductor base layer has photoelectric benefit and can generate photocurrent when being irradiated by light, so that the semiconductor layer area of the TFT-LCD array substrate produced by the 4mask process is larger, and the formed photocurrent influences the product stability.
Disclosure of Invention
The invention provides a manufacturing method of an array substrate, which avoids the influence of excessive illumination of a semiconductor layer on the stability of the array substrate.
The invention provides a manufacturing method of an array substrate, comprising the following steps,
sequentially forming an insulating layer, a semiconductor base layer, an ohmic contact base layer and a second metal layer on the substrate;
forming a photoresist layer on the second metal layer, and patterning the photoresist layer; the patterned photoresist layer comprises a first photoresist area and second photoresist areas on two sides of the first photoresist area, and the thickness of the second photoresist areas is thinner than that of the first photoresist areas;
forming a patterned second metal layer covered by the first photoresist region of the photoresist layer;
carrying out first dry etching on the semiconductor basic layer and the ohmic contact basic layer according to the patterned photoresist layer; removing the semiconductor basic layer and the ohmic contact basic layer to expose the patterned photoresist layer;
performing first ashing treatment on the patterned photoresist layer, and removing the second photoresist region to enable two sides of the first photoresist region of the ashed photoresist layer to be flush with two sides of the patterned second metal layer, so that the semiconductor basic layer and the ohmic contact basic layer after the first dry etching are exposed out of two sides of the first photoresist region;
carrying out second dry etching on the semiconductor base layer and the ohmic contact base layer subjected to the first dry etching to form a semiconductor layer and remove the part of the ohmic contact base layer exposed out of the first photoresist region;
ashing the first photoresist area of the photoresist layer for the second time, and removing part of the first photoresist area of the photoresist layer to expose part of the semiconductor layer and the ohmic contact base layer;
forming a data line, a drain line and an ohmic contact layer by etching twice;
and removing the first photoresist region after the second ashing.
And in the step of carrying out second dry etching on the semiconductor basic layer and the ohmic contact basic layer which are subjected to the first dry etching, the pattern edges of the formed semiconductor layer and the ohmic contact basic layer are flush with the pattern edge of the patterned second metal layer.
Wherein the step of forming the semiconductor layer and the ohmic contact layer by two times of etching includes; and wet etching the patterned second metal layer to form the data line and the drain line.
Wherein the step of forming the semiconductor layer and the ohmic contact layer by two times of etching includes; and carrying out dry etching on the ohmic contact basic layer after the second dry etching exposing the data line and the drain line to form the ohmic contact layer.
And forming a passivation layer on the data line, the drain line, the semiconductor layer and the ohmic contact layer.
And patterning the photoresist layer, wherein the photoresist layer comprises forming a photomask above the photoresist layer, the photomask comprises a shading area, a semi-transparent area and a full-transparent area, the semi-transparent area is opposite to the second photoresist area, and the shading area is opposite to the first photoresist area of the photoresist layer.
Wherein the step of forming a patterned second metal layer covered by the first photoresist region of the photoresist layer forms the patterned second metal layer by wet etching the second metal layer.
The first dry etching and the second dry etching are performed twice with an interval of one complete dry etching operation.
The array substrate manufacturing method can modify, optimize and improve the problem that the semiconductor layer under the 4mask process data line generates photocurrent from the TFT array substrate photomask process steps, the photoresist layer is divided into parts with different thicknesses, then the ashing and etching processes are divided into two times, the etching amount on two sides of the semiconductor is large when the oxide semiconductor layer process is formed, the length of the two sides of the semiconductor layer is further reduced, the photocurrent generation is reduced, and the stability of the TFT array substrate is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for manufacturing an array substrate according to the present invention;
FIG. 2 is a schematic process diagram of step S2 of the method for manufacturing an array substrate according to the present invention;
FIG. 3 is a schematic process diagram of step S3 of the method for manufacturing an array substrate according to the present invention;
FIG. 4 is a schematic process diagram of step S4 of the method for manufacturing an array substrate according to the present invention;
FIG. 5 is a schematic process diagram of step S5 of the method for manufacturing an array substrate according to the present invention;
FIG. 6 is a schematic process diagram of step S6 of the method for manufacturing an array substrate according to the present invention;
FIG. 7 is a schematic process diagram of step S7 of the method for manufacturing an array substrate according to the present invention;
fig. 8 and 9 are schematic process views of step S8 of the method for manufacturing an array substrate according to the present invention;
fig. 10 is a schematic process diagram of step S9 of the array substrate manufacturing method according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a method for manufacturing an array substrate includes the following steps:
in step S1, as shown in fig. 2, the insulating layer 10, the semiconductor foundation layer 11, the ohmic contact foundation layer 12, and the second metal layer 13 are sequentially formed on the substrate.
Referring to fig. 2, in step S2, forming a photoresist layer 14 on the second metal layer 13, and patterning the photoresist layer 14; the patterned photoresist layer 14 includes a first photoresist region 141 and a second photoresist region 142 on both sides of the first photoresist region 141, wherein the thickness of the second photoresist region 142 is thinner than that of the first photoresist region 141. Please refer to FIG. 2.
In this step, a photomask (not shown) is used above the photoresist layer 14, the photomask includes a light-shielding region, a semi-transparent region and a full-transparent region, the second photoresist region opposite to the semi-transparent region and the first photoresist region opposite to the light-shielding region on the photoresist layer are illuminated, and then the photomask is removed.
Referring to fig. 3, in step S3, a patterned second metal layer 131 is formed to be covered by the first photoresist region 141 of the photoresist layer. In this step, the second metal layer is etched according to the pattern of the photoresist layer 14 by wet etching to form the patterned second metal layer 131, wherein, preferably, due to the characteristics of wet etching, the amount of lateral etching is larger than the amount of longitudinal ashing during etching, so that the portion of the second metal layer proper to the second photoresist region can be removed during wet etching according to the time required to be designed, so that the widths of both sides of the pattern of the patterned second metal layer 131 are the same as those of both sides of the first photoresist region 141.
Referring to fig. 4, in step S4, a first dry etching is performed on the semiconductor base layer 11 and the ohmic contact base layer 12 according to the patterned photoresist layer 14; the semiconductor base layer 11 and the ohmic contact base layer 12 are removed to expose portions of the patterned photoresist layer 14, specifically, portions on both sides of the second photoresist region 142.
Referring to fig. 5, in step S5, the patterned photoresist layer 14 is subjected to a first ashing process to remove the second photoresist region 142, so that two sides of the first photoresist region 141 of the ashed photoresist layer 14 are flush with two sides of the patterned second metal layer 131, and the semiconductor base layer 11 and the ohmic contact base layer 12 after the first dry etching are exposed at two sides of the first photoresist region 141. At this time, both sides of the semiconductor base layer 11 and the ohmic contact base layer 12 are exposed to both sides of the first photoresist region 141. In this step, since the thickness of the second photoresist region 142 is thinner than that of the first photoresist region 141, the excess portion of the photoresist layer is easily removed, and the processing difficulty is reduced.
Referring to fig. 6, in step S6, the semiconductor base layer 11 and the ohmic contact base layer 12 are dry-etched for the second time to form the semiconductor layer 111, and the ohmic contact base layer 12 is removed to expose the first photoresist region 141. I.e., the excess portions on both sides of the channel semiconductor base layer, the pattern edges of the semiconductor layer 111 and the ohmic contact base layer formed are flush with the pattern edges of the patterned second metal layer. Compared with the manufacturing method in the prior art, the semiconductor layer 111 is formed by etching the side part twice, and the width area of the semiconductor layer is reduced compared with that of the semiconductor layer in the prior art, namely the stepped area of the semiconductor layer, the ohmic contact layer and the data line is reduced, so that the generation of light-induced photocurrent of the semiconductor layer is reduced, and the residual risk is reduced; the influence of the backlight of the array substrate on the quality of the liquid crystal display panel can be reduced, and the quality stability of the array substrate is improved.
Referring to fig. 7, in step S7, the first photoresist region 141 of the photoresist layer 14 is ashed for the second time, and a portion of the first photoresist region 141 of the photoresist layer is removed to expose a portion of the semiconductor layer 111 and the ohmic contact base layer 12. This step exposes the patterned second metal layer 131, both sides of the semiconductor layer 111, and both sides of the ohmic contact base layer 12. In this step, the ashing isotropic etching photoresist is used, so that the portions on both sides of the first photoresist region 141 can be removed in a reasonable time.
Referring to fig. 8 and 9, in step S8, a data line, a drain line and an ohmic contact layer are formed on the second metal layer and the ohmic contact base layer by two etching processes.
The method specifically comprises the following steps; in fig. 8, the patterned second metal layer 131 is wet-etched to form a data line 132 and a drain line. The wet etching lateral etching is larger than the lateral ashing, and thus both sides where the data line 132 is formed are shorter than both sides of the first photoresist region 141.
In fig. 9, the ohmic contact layer 121 is formed by dry etching the ohmic contact base layer 12 after the second dry etching exposing the data line 132 and the drain line. In this step, the vertical etching is performed according to the dry etching, and the metal layer has a barrier effect, so that both sides of the ohmic contact layer 121 protrude from the data line 132.
Referring to fig. 10, in step S9, the photoresist layer is removed, specifically, the first photoresist region after the second ashing is removed. Further comprising the step of forming a passivation layer 15 on the data line 132, the drain line, the semiconductor layer 111, and the ohmic contact layer 121.
The array substrate manufacturing method can improve the problem that a semiconductor layer under a 4mask process data line generates photocurrent through TFT array substrate photomask process modification optimization, does not need to increase cost additionally, creates a larger aperture opening ratio for a manufacturing process, and improves the quality stability of the 4mask process array substrate.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A method for manufacturing an array substrate includes,
sequentially forming an insulating layer, a semiconductor base layer, an ohmic contact base layer and a second metal layer on the substrate;
forming a light resistance layer on the second metal layer, and patterning the light resistance layer to form a first light resistance area and second light resistance areas positioned at two sides of the first light resistance area; wherein, the thickness of the second photoresist area is thinner than that of the first photoresist area;
forming a patterned second metal layer covered by the first photoresist region of the photoresist layer;
carrying out first dry etching on the semiconductor basic layer and the ohmic contact basic layer according to the patterned photoresist layer; removing the semiconductor basic layer and the ohmic contact basic layer to expose the patterned photoresist layer;
performing first ashing treatment on the patterned photoresist layer, and removing the second photoresist region to enable two sides of the first photoresist region of the ashed photoresist layer to be flush with two sides of the patterned second metal layer, so that the semiconductor basic layer and the ohmic contact basic layer after the first dry etching are exposed out of two sides of the first photoresist region;
carrying out second dry etching on the semiconductor base layer and the ohmic contact base layer after the first dry etching to form a semiconductor layer and remove the part of the ohmic contact base layer exposed out of the first photoresist area;
ashing the first photoresist area of the photoresist layer for the second time, and removing part of the first photoresist area to expose part of the semiconductor layer and the ohmic contact base layer;
forming a data line, a drain line and an ohmic contact layer by etching the patterned second metal layer and the ohmic contact base layer twice;
and removing the first photoresist region after the second ashing.
2. The method of claim 1, wherein the step of dry-etching the semiconductor base layer and the ohmic contact base layer for the first time is performed for a second time, and the patterned edges of the semiconductor layer and the ohmic contact base layer are formed to be flush with the patterned edges of the second metal layer.
3. The method for manufacturing an array substrate according to claim 1, wherein the step of forming the data line and the drain line and the ohmic contact layer by etching the patterned second metal layer and the ohmic contact base layer twice includes; and wet etching the patterned second metal layer to form the data line and the drain line.
4. The method for manufacturing an array substrate according to claim 3, wherein the step of forming the data line and the drain line and the ohmic contact layer by etching the patterned second metal layer and the ohmic contact base layer twice further comprises; and carrying out dry etching on the ohmic contact basic layer after the second dry etching exposing the data line and the drain line to form the ohmic contact layer.
5. The method of manufacturing an array substrate of claim 1, further comprising the step of forming a passivation layer on the data line, the drain line, the semiconductor layer, and the ohmic contact layer.
6. The method of claim 1, wherein forming a photoresist layer on the second metal layer and patterning the photoresist layer comprises:
and a photomask is adopted above the photoresist layer, the photomask comprises a shading area, a semi-transparent area and a full-transparent area, a second photoresist area is formed on the photoresist layer at a position opposite to the semi-transparent area through illumination, a first photoresist area is formed at a position opposite to the shading area, and then the photomask is removed.
7. The method of claim 1, wherein the step of forming a patterned second metal layer covered by the first photoresist region of the photoresist layer forms the patterned second metal layer by wet etching the second metal layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611214086.3A CN106783746B (en) | 2016-12-24 | 2016-12-24 | Array substrate manufacturing method |
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| CN201611214086.3A CN106783746B (en) | 2016-12-24 | 2016-12-24 | Array substrate manufacturing method |
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| CN106783746B true CN106783746B (en) | 2020-05-05 |
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| CN110120426B (en) * | 2018-02-07 | 2023-01-10 | 南京京东方显示技术有限公司 | Manufacturing method of thin film transistor and thin film transistor |
| CN109103140B (en) * | 2018-08-03 | 2020-10-16 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of array substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102148259A (en) * | 2010-10-12 | 2011-08-10 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing methods thereof and liquid crystal display |
| CN102455591A (en) * | 2010-10-14 | 2012-05-16 | 京东方科技集团股份有限公司 | Manufacturing method for thin film pattern and array substrate |
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| TWI483344B (en) * | 2011-11-28 | 2015-05-01 | Au Optronics Corp | Array substrate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102148259A (en) * | 2010-10-12 | 2011-08-10 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing methods thereof and liquid crystal display |
| CN102455591A (en) * | 2010-10-14 | 2012-05-16 | 京东方科技集团股份有限公司 | Manufacturing method for thin film pattern and array substrate |
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