CN109979810A - Self aligning grid structure and preparation method thereof, autoregistration grid width structure and preparation method thereof - Google Patents
Self aligning grid structure and preparation method thereof, autoregistration grid width structure and preparation method thereof Download PDFInfo
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- CN109979810A CN109979810A CN201910175487.XA CN201910175487A CN109979810A CN 109979810 A CN109979810 A CN 109979810A CN 201910175487 A CN201910175487 A CN 201910175487A CN 109979810 A CN109979810 A CN 109979810A
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- grid
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 238000010992 reflux Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000001883 metal evaporation Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 abstract 1
- 238000007740 vapor deposition Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Measurement Of Radiation (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention provides a kind of production method of self aligning grid structure, include the following steps: 1) to coat the first photoresist in the upper surface of epitaxial layer；2) pass through the first light shield, exposure development and the upper surface formation grid recess for being etched in epitaxial layer；3) remaining first Photoresist reflow forms T-type grid width into grid recess after being etched by reflux technique；4) the second photoresist is coated in the upper surface of the first photoresist, forms the pattern of T-type grid cover by the second light shield, exposure development, form T-type grid pattern after etching on this basis, T-type grid cover is connected to T-type grid width；5) after the enterprising row metal vapor deposition of the pattern of T-type grid, then the first photoresist and the second photoresist are removed, forms T-type grid structure.Self aligning grid structure provided by the invention and preparation method thereof has high alignment between grid structure and epitaxial electric resistance.
Description
Technical field
The present invention relates to electronic component more particularly to transistors.
Background technique
The prior art generally samples following step when making grid structure:
1.Recessed EPI Recess (grid recess): with RE mask (extension high resistance light shield) finish RE PH (PH:
Yellow light) technique, it then does RE etching and RE photoresist removes to form Recessed EPI Recess (grid recess)；
2.T-gate stem (T-type grid width): coating GS (GS:Gate stem grid width) photoresist is exposed, benefit with GS mask
It is flowed back with photoresist, reducing GS line width becomes T-gate stem；
3.T-gate Top (T-type grid cover): coating GT (GT:Gate top grid cover) photoresist is T-gate using GT mask
Top
Prior art disadvantage: the technique for completing T-type grid using three-layer light cover and double exposure contraposition operation.Double exposure pair
Position refers to that it is more to align number for the exposure aligning of GS and RE, the exposure aligning of GT and GS.
Summary of the invention
The main technical problem to be solved by the present invention is to provide self aligning grid structure and preparation method thereof, improve grid knot
Alignment between structure and resistance.
In order to solve the above technical problems, the present invention provides a kind of production methods of self aligning grid structure, including such as
Lower step:
1) the first photoresist is coated in the upper surface of epitaxial layer；
2) pass through the first light shield, exposure development and the upper surface formation grid recess for being etched in epitaxial layer；
3) remaining first Photoresist reflow forms T-type grid width into grid recess after being etched by reflux technique；
4) the second photoresist is coated in the upper surface of the first photoresist, T is formed by the second light shield, exposure development and etching
Type grid pattern, what is formed on the second photoresist is T-type grid cover, and T-type grid cover is connected to T-type grid width；
5) after to metal evaporation is carried out in T-type grid cover and T-type grid width, the first photoresist and the second photoresist are removed.
In a preferred embodiment: when coating the second photoresist and being exposed the interval between development to the second photoresist
Between be no more than 4 hours.
In a preferred embodiment: the temperature of the first Photoresist reflow is at 100 DEG C -- and 160 DEG C, return time is at 30 points
Clock -- 90 minutes.
The present invention also provides a kind of self aligning grid structures, comprising: epitaxial layer and T-type grid structure, T-type grid structure are stood
On the grid recess of epitaxial layer；
The T-type grid structure includes grid width and grid cover, and the bottom of grid width is located in grid recess, be set as at the top of grid width as
The upper grid cover.
In a preferred embodiment: spaced apart between the side wall of the grid width and the inner wall of grid recess.
The present invention also provides a kind of production method of autoregistration grid width structure, include the following steps: to return by photoresist
Stream technique will be used to make the Photoresist reflow of resistance into grid recess, and gap of the photoresist in grid recess determines grid width
Size.
In a preferred embodiment: the temperature of the Photoresist reflow is at 100 DEG C -- and 160 DEG C, return time is at 30 points
Clock -- 90 minutes
The present invention also provides a kind of autoregistration grid width appearance structures, comprising: epitaxial layer and photoresist；On the epitaxial layer
The grid recess of formation, for first photoresist by extending in export-oriented grid recess, the first photoresist prolongs the light after stretching in grid recess
Photoresist gap forms grid width pattern compared to the prior art, technical solution of the present invention have it is following the utility model has the advantages that
1. two sets of light shields of needs, save light shield cost；
2. not needing photoresist removing after the completion of grid recess, grid width pattern directly is done after reflux；
3. ensure that grid width is located at the middle of grid recess since grid recess and grid width use identical light resistance structure
Position avoids grid width and deviates to the left or to the right in grid recess.So grid recess and grid width have high alignment.
Detailed description of the invention
Fig. 1-Fig. 6 is the production method flow chart of self aligning grid structure in the preferred embodiment of the present invention.
Specific embodiment
In order to keep technical solution of the present invention clearer, now the present invention is done further specifically with attached drawing in conjunction with the embodiments
It is bright:
The production method for present embodiments providing a kind of autoregistration grid width structure includes the following steps: to return by photoresist
Stream technique will be used to make the Photoresist reflow of epitaxial electric resistance into grid recess, and gap of the photoresist in recessed portion is grid
Wide pattern.
Pass through autoregistration grid width structure obtained by the above method, comprising: epilayer resistance and photoresist；On the epitaxial layer
The grid recess of formation, by extending in export-oriented resistance recessed portion, the gap after the first photoresist reduces is formed first photoresist
Grid width pattern.
Due to grid recess and grid width be same foundation photoresist pattern, so epitaxial electric resistance and grid structure have pole
High alignment.
By the production method of above-mentioned autoregistration grid width structure, the present embodiment further provides a kind of sag knot
The production method of structure includes the following steps: as shown in figs 1 to 6
1) the first photoresist RE PR, such as Fig. 1 is coated in the upper surface of epitaxial layer EPI；
2) pass through the first light shield, exposure development and the upper surface formation grid recess for being etched in epitaxial layer EPI, such as Fig. 2；
3) the first photoresist RE PR remaining after etching is back in recessed portion by reflux technique, forms T-type grid width
Pattern, such as Fig. 3；
The temperature of first Photoresist reflow is at 100 DEG C -- and 160 DEG C, return time was at 30 minutes -- and 90 minutes.
4) the second photoresist GT PR is coated in the upper surface of the first photoresist RE PR, passes through the second light shield, exposure development
T-type grid pattern is formed with being etched on the second photoresist GT PR, the pattern on the second photoresist is the pattern of T-type grid cover, T-type
Grid cover is connected to T-type grid width, such as Fig. 4；
The interval time for coating the second photoresist and being exposed between development to the second photoresist is no more than 4 hours.
5) after to metal evaporation is carried out in T-type grid cover and T-type grid width, the first photoresist RE PR and the second photoresist are removed
GT PR forms T-type grid, such as Fig. 5 and Fig. 6.
By above-mentioned method, a kind of self aligning grid structure is made, comprising: epitaxial electric resistance and T-type grid structure；
The T-type grid structure includes grid width and grid cover, and the bottom of grid width is located in resistance recessed portion, and along principle resistance
The direction of recessed portion extends, and the grid cover is arranged in the top of grid width.
The production method of above-mentioned autoregistration grid width structure, it is only necessary to which two sets of light shields save light shield cost；Resistance recessed portion
Photoresist removing is not needed after the completion, directly does grid cover after reflux；Since grid recess and grid width use identical light resistance structure,
It ensure that grid width is located at the middle position of grid recess, avoid grid width and deviated to the left or to the right in grid recess.So grid
Groove and grid width have high alignment.
The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and those skilled in the art can
To readily appreciate that variation disclosed in this invention or technical scope.Alternative solution is intended to cover within the scope of the invention.Cause
This, protection scope of the present invention should be determined by the scope of the claims.
Claims (8)
1. a kind of production method of self aligning grid structure, it is characterised in that include the following steps:
1) the first photoresist is coated in the upper surface of epitaxial layer；
2) pass through the first light shield, exposure development and the upper surface formation grid recess for being etched in epitaxial layer；
3) remaining first Photoresist reflow forms T-type grid width into grid recess after being etched by reflux technique；
4) the second photoresist is coated in the upper surface of the first photoresist, T-type grid is formed by the second light shield, exposure development and etching
Pattern, what is formed on the second photoresist is T-type grid cover, and T-type grid cover is connected to T-type grid width；
5) after to metal evaporation is carried out in T-type grid cover and T-type grid width, the first photoresist and the second photoresist are removed.
2. a kind of production method of self aligning grid structure according to claim 1, it is characterised in that: the second photoresist of coating
It is no more than 4 hours with the interval time being exposed to the second photoresist between development.
3. a kind of production method of self aligning grid structure according to claim 1, it is characterised in that: the first Photoresist reflow
Temperature at 100 DEG C -- 160 DEG C, return time was at 30 minutes -- 90 minutes.
4. a kind of self aligning grid structure, characterized by comprising: epitaxial layer and T-type grid structure, T-type grid structure are stood in epitaxial layer
Grid recess on；
The T-type grid structure includes grid width and grid cover, and the bottom of grid width is located in grid recess, and institute as above is set as at the top of grid width
State grid cover.
5. a kind of self aligning grid structure according to claim 4, it is characterised in that: the side wall of the grid width and grid recess
It is spaced apart between inner wall.
6. a kind of production method of autoregistration grid width structure, it is characterised in that include the following steps: through Photoresist reflow technique,
The Photoresist reflow of resistance will be used to make into grid recess, gap of the photoresist in grid recess to determine grid width size.
7. a kind of production method of autoregistration grid width structure according to claim 6, it is characterised in that: the photoresist returns
The temperature of stream is at 100 DEG C -- and 160 DEG C, return time was at 30 minutes -- and 90 minutes.
8. a kind of autoregistration grid width appearance structure, characterized by comprising: epitaxial layer and photoresist；It is formed on the epitaxial layer
Grid recess, by extending in export-oriented grid recess, the first photoresist prolongs between the photoresist after stretching in grid recess first photoresist
Gap forms grid width pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910175487.XA CN109979810B (en) | 2019-03-08 | 2019-03-08 | Self-aligned gate structure and manufacturing method thereof, and self-aligned gate width structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910175487.XA CN109979810B (en) | 2019-03-08 | 2019-03-08 | Self-aligned gate structure and manufacturing method thereof, and self-aligned gate width structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109979810A true CN109979810A (en) | 2019-07-05 |
| CN109979810B CN109979810B (en) | 2021-06-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910175487.XA Active CN109979810B (en) | 2019-03-08 | 2019-03-08 | Self-aligned gate structure and manufacturing method thereof, and self-aligned gate width structure and manufacturing method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060079030A1 (en) * | 2004-10-12 | 2006-04-13 | Jong Moon Park | Method of fabricating T-type gate |
| CN101330010A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院微电子研究所 | Method for preparing T type HBT emitter electrode/HEMT gate |
| CN103715077A (en) * | 2014-01-06 | 2014-04-09 | 中国科学院微电子研究所 | Method for manufacturing deep submicron U-shaped grating groove |
| CN104882373A (en) * | 2015-04-24 | 2015-09-02 | 石以瑄 | Method for manufacturing transistor T-shaped gate |
| CN108962726A (en) * | 2017-05-17 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
-
2019
- 2019-03-08 CN CN201910175487.XA patent/CN109979810B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060079030A1 (en) * | 2004-10-12 | 2006-04-13 | Jong Moon Park | Method of fabricating T-type gate |
| CN101330010A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院微电子研究所 | Method for preparing T type HBT emitter electrode/HEMT gate |
| CN103715077A (en) * | 2014-01-06 | 2014-04-09 | 中国科学院微电子研究所 | Method for manufacturing deep submicron U-shaped grating groove |
| CN104882373A (en) * | 2015-04-24 | 2015-09-02 | 石以瑄 | Method for manufacturing transistor T-shaped gate |
| CN108962726A (en) * | 2017-05-17 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
Non-Patent Citations (2)
| Title |
|---|
| HONG ZHU; YANG SHEN; YANQING LI; JIANXIN TANG: "Recent advances in flexible and wearable organic optoelectronic devices", 《JOURNAL OF SEMICONDUCTORS》 * |
| 刘文安等: "亚0.1μm栅长CMOS器件和电路的研制 ", 《半导体学报》 * |
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| Publication number | Publication date |
|---|---|
| CN109979810B (en) | 2021-06-25 |
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