CN109952657A - Isolator integrated circuit and manufacturing method with encapsulating structure cavity - Google Patents
Isolator integrated circuit and manufacturing method with encapsulating structure cavity Download PDFInfo
- Publication number
- CN109952657A CN109952657A CN201780068616.4A CN201780068616A CN109952657A CN 109952657 A CN109952657 A CN 109952657A CN 201780068616 A CN201780068616 A CN 201780068616A CN 109952657 A CN109952657 A CN 109952657A
- Authority
- CN
- China
- Prior art keywords
- bare chip
- semiconductor bare
- lead frame
- circuit
- frame structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 230000003287 optical effect Effects 0.000 claims abstract description 87
- 239000000463 material Substances 0.000 claims description 100
- 239000004065 semiconductor Substances 0.000 claims description 53
- 239000004020 conductor Substances 0.000 claims description 42
- 238000010276 construction Methods 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 33
- CWYNVVGOOAEACU-UHFFFAOYSA-N Fe2+ Chemical compound [Fe+2] CWYNVVGOOAEACU-UHFFFAOYSA-N 0.000 claims description 19
- 230000008878 coupling Effects 0.000 claims description 17
- 238000010168 coupling process Methods 0.000 claims description 17
- 238000005859 coupling reaction Methods 0.000 claims description 17
- 238000007789 sealing Methods 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000005538 encapsulation Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 239000011797 cavity material Substances 0.000 claims 13
- 239000000758 substrate Substances 0.000 description 20
- 238000000465 moulding Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 7
- 150000002736 metal compounds Chemical group 0.000 description 7
- 239000007787 solid Substances 0.000 description 7
- 239000011162 core material Substances 0.000 description 6
- 238000004821 distillation Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000002835 absorbance Methods 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000013536 elastomeric material Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 108091008695 photoreceptors Proteins 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000035807 sensation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000005092 sublimation method Methods 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F38/00—Adaptations of transformers or inductances for specific applications or functions
- H01F38/14—Inductive couplings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/11—Devices sensitive to infrared, visible or ultraviolet radiation characterised by two potential barriers or surface barriers, e.g. bipolar phototransistor
- H01L31/1105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by two potential barriers or surface barriers, e.g. bipolar phototransistor the device being a bipolar phototransistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
- H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
- H01L31/167—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by at least one potential or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/80—Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water
- H04B10/801—Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water using optical interconnects, e.g. light coupled isolators, circuit board interconnections
- H04B10/803—Free space interconnects, e.g. between circuit boards or chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/08113—Disposition the whole bonding area protruding from the surface of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48149—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the wire connector connecting to a bonding area protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12043—Photo diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
Abstract
Disclosed example includes a kind of integrated circuit (100), and the integrated circuit includes lead frame structure (104a, 104b)；First circuit structure (106a), it includes be configured to generate the light source (108a) of the optical signal along optical path (114)；Second circuit structure (106b), it includes the optical sensors (108b) that the optical signal is received towards the optical path (114)；And molded encapsulating structure (102), its part for closing the lead frame structure (104a, 104b), the molded encapsulating structure (102) has the cavity (110) limited by the inner surface of the molded encapsulating structure (102), extends between first circuit structure and the second circuit structure (106a, 106b) in the optical path (114) cavity (110).
Description
Background technique
Isolated product is for providing electric isolution between the circuit with different voltages level and/or according to different confessions
Answer the transmission signal between voltage and the circuit for being grounded reference operation.A type of isolator is referred to as photoisolator or light
Electric coupler provides light transmission path may transmit signal between circuit electrically isolated from one.Photoisolator is used
In other systems that data communication, power supply and its mesohigh or high conversion rate common-mode signal occur between input and output
In.Photoisolator is usually configured as the transmitter and receiver that are separated and be packaged together by glass.Glass provides dc electricity
Isolation and optical transport, but by the capacitive coupling between transmitter and receiver and also increase installation cost.Transformer provide by
Being isolated to be total to by high pressure or high conversion rate between the magnetic coupling primary coil and magnetic coupling secondary coil of insulator separation
Data and/or power are transmitted between two circuits of mould Signal separator.Some transformers include coupling material to enhance primary
Magnetic coupling between coil and secondary coil.
Summary of the invention
Disclosed example includes a kind of integrated circuit (IC), and the integrated circuit includes light source, generates optical signal；
Optical sensor receives optical signal；And molded encapsulating structure, have provide between light source and optical sensor without solid
The cavity of optical path.Other example IC are being provided between first coil structure and the second loop construction in encapsulating structure cavity
Magnetic coupling.Example IC manufacturing method includes: semiconductor bare chip being mounted in lead frame structure, bare die and lead frame structure are connected
Between closing line, form expendable material above a part of bare die, above bare die, closing line and lead frame structure with
The upper of expendable material forms molded encapsulating material, and distillation expendable material to form cavity, and the cavity includes
At least part that barrier is isolated between the first circuit associated with semiconductor bare chip and second circuit.
Detailed description of the invention
Fig. 1 is to include in the spaced-apart semiconductor bare die in the internal cavities of molded encapsulating structure according to an embodiment
LED light source and photoreceptor diode-transducer are to provide the integrated circuit that is optically isolated of optical path for electric isolution
Side cross-sectional view.
Fig. 2 is to include the reflectance coating being formed in the concave surface of package cavity with LED light source and bipolar transistor
Another side cross-sectional view for being optically isolated IC embodiment of sensor.
Fig. 3 is the top plan view for being optically isolated IC of Fig. 1.
Fig. 4 is another section for being optically isolated IC embodiment comprising horizontal diode to form optical sensor circuit
Side view.
Fig. 5 is the received fragmentary sectional side view of optics in the embodiment of display diagram 4.
Fig. 6 is another section for being optically isolated IC embodiment comprising vertical diode to form optical sensor circuit
Side view.
Fig. 7 is the received fragmentary sectional side view of optics in the embodiment of display diagram 6.
Fig. 8 is the flow chart according to the method for the production integrated circuit of an embodiment.
Fig. 9 be according to another embodiment include the coil section that extends in the internal cavities of molded encapsulating structure
The fragmentary sectional side view of transformer integrated circuit.
Figure 10 is the section-top plan view of the transformer IC of Fig. 9.
Figure 11 to 16 is the section lateral plan of the IC of Fig. 9 and 10 at each stage of manufacture.
Figure 17 is included in the another of the coil section and ferrous materia extended in the internal cavities of molded encapsulating structure
The side cross-sectional view of transformer IC embodiment.
Figure 18 is the top plan view of the transformer IC embodiment of Figure 17.
Figure 19 is the flow chart of the method for production integrated circuit according to another embodiment.
Specific embodiment
In the drawings, same reference numerals throughout refer to similar elements, and various features are not necessarily drawn to scale.?
In following discussion and claims, term " including (including, includes) ", " having (having, has) " " are had
(with) " or its version is intended in the way of being similar to term " including (comprising) " as inclusive, and therefore
It should be interpreted as meaning " include, but are not limited to ... ".In addition, term " coupling (couple, coupled or couples) "
It is intended to encompass and is directly or indirectly electrically connected or is mechanically connected or combinations thereof.For example, if first device is coupled to the second dress
It sets or is coupled with second device, then the connection can be directly electrical connection or via one or more intervention devices and connection
Electrical connection indirectly.
Show example optics separated set at circuit (IC) 100, such as photoisolator or light referring initially to Fig. 1 to 3, Fig. 1
Electric coupler device.IC 100 includes to be configured to generate the light source 108a along the optical signal of optical path 114.In an example
In, light source is the LED being manufactured in the first semiconductor bare chip or other circuit structure 106a, but laser or other light sources are available
In other embodiments.IC 100 further includes second device or circuit structure 106b, it includes towards optical path 114 with
Receive the optical sensor 108a of optical signal.In an example, optical sensor 108b is the light sensation that meaning property as shown in fig. 1 illustrates
Receiver diode-transducer.Any suitable optical sensor that optical signal is received from source 108a can be used.Fig. 2 illustrates another possibility
Embodiment, wherein second circuit structure 106b includes the bipolar transistor 109 of sensing received optical signal.It is opened up as shown in figure 1
Show, circuit structure 106a and 106b individually include by closing line 124 be connected to lead frame structure correspondence electric conductor 104a,
The joint liner 122 of 104b.In an example shown in Fig. 3, the first circuit structure 106a includes to be separately connected to draw
The first joint liner and the second joint liner 122 of a pair of wire frame structure corresponding first couple of electric conductor 104a-l, 104a-2.?
In one example, conductor 104a-l and 104a-2 are the IC pin or lining that may be welded to host printed circuit board (PCB is not shown)
Pad.In this example, external circuit (not shown) is provided via conductor 104a-l and 104a-2 to the signal of light source 108a, and
In response, light source 108a generates optical signal.In this example, second circuit structure 106b also includes by corresponding closing line
124 are electrically connected to the joint liner 122 of second couple of lead frame electric conductor 104b-l and 104b-2.Conductor in illustrated example
104b-l and 104b-2 provide the liner or pin that may be welded to host PC B of IC 100, with conductor 104a-l and 104a-2
The source signal at place isolator transmits signal from sensor 108b.By this method, the spacing 116 of circuit structure 106a and 106b provides
It is electrically isolated, wherein signal is transmitted via the cavity 110 of IC 100 along path 114.
According to an embodiment, light source 108a and sensor 108b in the internal cavities 110 of molded encapsulating structure 102 with
It is separated from each other to provide electric isolution therebetween.Cavity 110 provides the optical path 114 for being free of solid (that is, without solid).Glass
Or other optical transmissibility solid structures is conventional using the cost for increasing optic isolator device, and increases source/sensor configuration
Capacitor.Using solid transmission media device capacitor especially in terms of high-speed data communication and high common mode conversion rate inhibition
There are problems, and manufacturing cost is excessively high for many applications.In addition, there is also optical properties to drop at any time for solid transmission media
The problem of grade.On the contrary, disclosed photoelectrical coupler IC 100 advantageously reduces coupled capacitor and cost, while helping to appoint
What desired horizontal electric isolution and high-breakdown-voltage.In this regard, air, which has, is significantly less than glass or other transparent materials
Dielectric constant, and disclosed example reduces the capacitive coupling between optical sensor and transmitter.In addition, source bare die 106a
Can be controlled by its structure relative positioning without solid gap 116 between sensor die 106b, to provide along with any institute
Spacing or clearance distance 116 needed for the optical transport in the path 114 for needing voltage rating to be isolated.In an example, clearance distance
116 can be controlled by the sacrifice sublimator material deposited.Gap 116 in certain examples is by the machine on one in bare die 106
Tool character control extends such as between bare die 106 the oxide convex block (not shown) of clearance distance 116 is arranged.Some
In example, gap 116 is controlled by there will be the filler material of particular size to mix with expendable material.In other embodiments
In, ink-jet printing technology can be used that distillation region is formed as unique printing shape, and optical channel can be directly printed.
Optical sensor 108b at least partially faces light source 108a to receive optical signal.In the example of Fig. 1 to 3, first
Circuit structure 106a include light signal output surface or side 107a, and second circuit structure 106b include sensor surface or
Side 107b, wherein signal output surface 107a and sensor surface 107b is in by the distance 116 in cavity 110 and each other
In usual parallel plane spaced apart.In other possible examples, surface 107 is without parallel.Any relative configuration can be used,
Wherein sensor surface 107b at least partially faces light source 108a to receive optical signal.No matter diode 108b or transistor
It is special to modify the electricity of sensor that 109 or other optical sensor structures, sensor surface 107b allow light to enter structure 106b
Property, to generate sensor signal to be output or to be further processed by second circuit structure 106b.Circuit 106 can be wrapped further
(not shown) containing interface circuit is to operate sensor signal.As shown in Fig. 1 and 2, in addition, surface 107a's and 107b is significant
Partial exposure is not all of the strict demand of possible embodiment in cavity 110.
IC 100 in Fig. 1 to 3 also includes molded encapsulating structure 102, closes part and the electricity of lead frame structure 104
The part of line structure 106a and 106b.In other examples, encapsulating structure material 102 without closed circuit structure 106a and
106b.Encapsulating structure 102 exposes the part of electric conductor 104a-l, 104a-2,104b-l and 104b-2 to the open air to allow and the first circuit
The external connection of structure 106a and second circuit structure 106b.In illustrated embodiment, encapsulating structure 102 is comprising cavity
110 molded material structure, and optical signal path 114 is in the light source 108a and optical sensor of circuit structure 106a, 106b
Extend in cavity 110 between 108b, 109.Therefore cavity 110 is provided without Solid-state Optics path 114 to be used for circuit structure
Optical signal between 106a and 106b.Illustrated structure is further included to be extended to outside encapsulating structure 102 from cavity 110
Port 118, and nut cap or sealing structure 120 from sealing cavity 110 outside IC.Port 118 can be at sky as described
In the upper part of chamber 110 or cavity can be equipped with across side or across the port of bottom or combinations thereof.
Cavity 110 is limited by the inner surface of encapsulating structure 102.Inner surface can be any suitable shape and profile.?
In certain examples, inner surface enhances the optical transport in cavity.The inner surface of encapsulating structure 102 includes in the embodiment of Fig. 1 and 2
Concave part.In this example, expendable material such as can be formed as dripping by concave surface by during manufacture using printing technology
Shape object or one or more drops and be arranged.Therefore the expendable material of this deposition forms part convex structure, and the material
It distils or evaporates after the formation of molded encapsulating structure material 102 later, to leave concave inside surface.
In the example of figure 2, the concave part of inner surface includes to make light from light source 108a towards optical sensor 108b, 109
The reflectance coating 200 of reflection.In an example, reflective coating materials 200 are in the mould for forming molded encapsulating structure material 102
It is deposited on before technique processed above the sacrifice sublimator material of convex surface.The distillation of sacrificial material layer leaves at least portion after the molding process
The cavity 110 for dividing ground to be limited by the concave surface of the layer of reflective material 200 retained.Can be used help to be generated by light source 108a it is complete
Portion or part optical signals are towards optical sensor 108b, any suitable non-conducting materials 200 of 109 reflections.As shown in Fig. 2, coming
It can be propagate directly to the sensing surface of sensor die 106b along optical path 114 via cavity 110 from the optical signal of source 108a
107b and/or signal can also be propagated via the reflectance coating 200 in concave surface along reflection path 202.
It laterally extends outwardly in other examples, can be formed and (be shown in the dashed line form in Fig. 2) to expose source to the open air
The concave surface 210,212 of the top section of one or two of circuit structure 106a and sensor circuit structure 106b.One
In a embodiment, concave surface 212 includes reflective coating materials 210.These embodiments may include having towards reflectance coating material
The luminous top of 210 transmitting light of material or the LED or other circuit of light sources 106a of top surface, and optical signal reflection passes one or more times
It is delivered to the side and/or top sensing surface of sensor circuit 106b.As used herein, the sensing surface of circuit 106 is straight
Ground connection or via cavity 110 spill or flat surfaces one or more reflecting surfaces (for example, surface 200,210) at least partly
Ground is to circuit of light sources.In certain embodiments, top and/or side-emission source circuit 106a can feel with top and/or side
Slowdown monitoring circuit 106b is applied in combination for directly or using one or more reflections transmitting optical signalling.
Molding or other suitable techniques can be passed through, it is preferred to use electrical insulator material forms encapsulating structure 102.Institute
Disclosed example provides the inexpensive isolating device using cavity 110 using sublimation process, and the cavity is included in source circuit
At least part that barrier is isolated between structure 106a and sensor circuit structure 106b.Circuit structure 106 is at least partly
It is encapsulated in the sacrifice sublimator material deposited during manufacture, and then further by molded 102 capsule of encapsulating structure material
Envelope.The structure then passes through baking with (for example, evaporation) expendable material that distils, to leave internal cavities 110, wherein bare die
106a and 106b or at least part of it does not contact mold compound 102.In some instances, by 118 Drillings of opening or casting
Make the expendable material that can distil into encapsulating structure 102, and thereafter sealing structure 120 be arranged in opening 118 over top with
Sealing cavity 110.Opening 118 can be casted into encapsulating structure 102 via molding note road, or can before molding process via
Opening 118 is incorporated into encapsulation by deserted plug, or after the moulding using mechanical drilling, laser drill, etching or other
Technology is by the opening Drilling into encapsulation 102.
Disclosed structure advantageously contributes to small package size, mitigate cost and reduce with by glass or other transparent materials
It is difficult that material is embedded in associated manufacture in the optical path of optic isolator device.In addition, disclosed example slows down and photoelectricity
Glass or the associated capacitor of other solid materials and problem of aging in the optical path of isolator, and therefore provide and especially exist
The enhancing performance of high-speed communication application aspect.In addition, can be used conventional mainstream manufacture processing step and equipment disclosed to manufacture
Example.
In a certain example, bare die 106 includes individually substrate, such as silicon, SOI or other semiconductor substrates.It can be used
Semiconductor fabrication process and equipment are known to form light source 108a and optical sensor 108b in associated substrate, 109 and various connect
Mouth circuit.In an example, encapsulating structure 102 is molded structure.Encapsulating structure 102 can be to provide to bare die 106
Any suitable molding material of electrical isolation and mechanicalness protection, and may include low modulus elastomeric material to enhance crushing resistance.This
Outside, bare die 106 can be supported in any suitable manner in cavity 110, be installed in lead frame structure as demonstrated.With
Afterwards, before molding, expendable material is at least partially deposited at 106 top of bare die.In the molding or other shapes of encapsulating material 102
Cheng Hou, heating assembly so that via molding material structure 102 port 118 distil sacrifice encapsulation materials.Suitable system
It makes technique and material explanation and is described in submission on August 26th, 2016 and entitled " floating bare die encapsulation (Floating Die
Package in U.S. Patent Application No. 15/248,151) ", the full content of the application case is hereby with the side of reference
Formula is incorporated to.
Referring also to Figure 4 and 5, Fig. 4 displaying is another to be optically isolated IC embodiment 100.In this example, optical sensor 108a
Diode comprising multiple connections respectively contains the N doped region and P doped region of substrate.In this example, second circuit knot
What structure 108b was connected in parallel in each of two (for example, lower part and top) substrates or bare die 401 and 402 comprising five
Horizontal diode, but one or more any number of such stacked dies can be used.Fig. 5 illustrates in multiple 401 Hes of stacked die
Along the side photonic absorbance of the length of pn-junction in 402.In this embodiment, n-quadrant and the region P are usually along optical path
114 arrangements, wherein n-quadrant or trap, which are formed in p doped substrate to leave, underlies the p region of N trap and is connected in parallel to each other with being formed
Multiple diodes of connection.In this example, circuit structure 108b includes substrate bare die 400, is had comprising any required
The semiconductor substrate of amplifier, filter or other interface circuit (not shown).In an example, bare die 401 and 402 passes through
Backgrind is to have vertical height more smaller than substrate bare die 400.Such as most preferably find out in Fig. 5, substrate bare die 400 also wraps
Containing with one or more inter-metal dielectric (IMD) structures (for example, dielectric layer and conductive metal knot for circuit interconnection
Structure) metal compound structure and upper passivation and one or more die pads, the die pad has and one or more
One or more engagement wire connections 124 of associated lead frame electric conductor 104b.In this example, single bare die 401 and 402 wraps
Containing via being implanted into base substrate 500 (for example, silicon), the metal that corresponding dopant is adulterated in illustrated n-quadrant and the region P
Compound structure 502 and upper passivation 504.Circuit structure 108b include any suitable intervention electric conductor structure (not shown) with
The circuit for making the diode of stacked die 401 and 402 and substrate bare die 400 and connector interconnection via associated lead frame to lead
Body 104b provides sensor or receiver output signal to external circuit.
Optics in the stacked die 401 and 402 of Fig. 5 display diagram 4 receives.It shows at sensing surface 107b into dual
Direct and reflection optical path 114 and 202 the example of horizontal stacked die configuration 401,402.It stacks PN junction and extends side
The use of optical transport (for example, in Fig. 5, from left to right) for optical signal provide it is bigger generated in diode structure 108b it is defeated
The chance of signal out.Therefore, disclosed example facilitates the high output signal performance in the optical coupled isolation IC 100 in side,
And slow down the low signal disadvantage of conventional photo isolator.In an example, single bare die 401 and 402 respectively generates substantially
0.5V voltage signal, and stacked die 401 and 402 can be mutual in parallel and/or series system via metal compound structure interconnection piece
Even with the output signal strength for enhancing.In this regard, have the embodiment greater than 2 stacked dies can be any desired
Series connection and/or parallel configuration interconnection, to reach required level output signal in response to the optical signal from light source 108a.
Fig. 6 and 7 is shown in optical sensor 108b using multiple another isolation IC examples 100 for stacking diode.Fig. 6
In second circuit structure 106b be more nude film structures with vertical diode, the vertical diode forms optical sensor
Circuit 108b.This circuit structure 106b includes four stacked dies, 601,602,603 and being formed on substrate bare die 600
604 to provide circuit structure 106b.Fig. 7 shows other details of sensor circuit 108b, and wherein substrate bare die 600 includes and has
The semiconductor substrate of any desired amplifier, filter or other interface circuit (not shown), and there are one or more IMD
The metal compound structure and upper passivation of structure and one or more die pads 122, the die pad have with it is one or more
One or more engagement wire connections 124 of a associated lead frame electric conductor 104b.Single bare die 601 to 604 includes to have doping
There is the bottom part of P-type dopant (for example, boron, is expressed as P+ in Fig. 7) and doped with N type dopant (for example, phosphorus, indicates
For N-) upper part 702 base substrate 700 (for example, silicon) to form vertically oriented diode.In this example,
The n-quadrant and the region P of bare die 601 to 604 therefore with 114 quadrature arrangement of optical path.Single bare die 601 to 604 is also comprising touching
Point 704 and the IMD/ metal compound structure 706 with any relevant passivation layer.In this example, upper die 604 include by
Closing line 710 is connected to the die pad 708 of the die pad 712 of substrate bare die 600.As examples detailed above, Fig. 6 and 7
In circuit structure 108b include any suitable intervention electric conductor structure (not shown) with by the two of stacked die 601 to 604
Circuit and the connector interconnection of pole pipe and substrate bare die 600 are to provide any desired horizontal output signal.In a reality
In example, single bare die 601 to 604 respectively generates substantially 0.6V voltage signal, and stacked die 601 to 604 can be with any required
Series connection and/or parallel configuration interconnection, to reach required level output signal in response to the optical signal from light source 108a.
Fig. 8 illustrates the instance method or technique for the isolation IC that can be used for manufacturing optic isolator device as described above
800.Method 800 starts from 802, wherein source bare die and sensor die are mounted on lead frame relative to each other with spaced relationship
On.For example, first circuit structure 106a and second circuit structure 106b can be installed to lead frame structure 104 at 802,
Wherein source surface 107a and sensor surface 107b by required clearance distance 116 in figure 1 above be separated from each other.Above
In example, in addition, second semiconductor bare chip 106b is mounted on lead frame structure 104b at 802, so that optical sensor
The sensing surface 107b of 108b at least partially faces optical path to receive optical signal from light source 108a.At 804 in fig. 8
Wire bonding technique is executed, it includes be connected between the lead frame electric conductor 104a and 104b corresponding with Fig. 1 of die pad 122
Closing line 124.Can substrate at 804 by other necessary closing lines (for example, 710) for example from the graph in 4 to 7 example it is naked
Piece 400,600 is attached to one or more stacked dies 401,402,601 to 604.Soldered ball or other IC interconnection techniques also can be used
Carry out substituted or supplemented wire bonding.At 806, expendable material is formed in the intended optical path between source bare die and sensor die
In sub-assembly at least partly top.At 806, in some instances, sacrificial material can be at least partially formed at
A part top of one or two of semiconductor bare die 106a and the second semiconductor bare chip 106b.In certain embodiments
In, in addition, expendable material SL to be formed to have to the drop of nonreentrant surface at 806.In an example, 807 in fig. 8
Reflecting material is formed on the nonreentrant surface of expendable material (for example, reflecting material 200 in figure 2 above) by place.
At 808 in fig. 8, molding process is executed so as to above semiconductor bare chip 106, closing line 124 and in lead
It is molded to be formed that molded encapsulating material (for example, above-mentioned material 102) is formed above the part of mount structure 104 and expendable material
Encapsulating structure 102.Embodiment for using the reflecting material being formed in above all or part of sacrificial material layer,
Encapsulating material is at least partially formed on reflecting material 200 at 808.At 810, the expendable material that distils is tied with being formed by encapsulation
The internal cavities (for example, above-mentioned cavity 110) that the inner surface of structure 102 limits.In above-mentioned IC example 100, at 810, distillation
Technique provides the structure 102 with the cavity 110 comprising at least part optical path 114, to allow optical signal in light source
It is transmitted between 108a and optical sensor 108b.At 812, in some instances, the cavity 110 is sealed.For example, exist
At 812, in the example of fig. 1, sealing structure 120 is mounted on the top of port 118, so as to from the external sealing cavity of IC 100
110。
Referring now to Fig. 9 to 19, magnetic coupling is provided according to other embodiments, IC 900 is isolated.The explanation of Fig. 9 and 10 is included in
The transformer section 906 and secondary coil section 908 extended in the internal cavities 110 of molded encapsulating structure 102
Transformer IC 900.Figure 11 to 16 illustrate the manufacturing process 1900 according to shown in Figure 19 at each stage of manufacture
The IC 900 of Fig. 9 and 10.The substitution that the explanation of Figure 17 and 18 further includes the ferrous materia 1700 in encapsulating structure cavity 110 is real
Apply example.In various possible embodiments, the transformer isolation device comprising two or more loop constructions is provided.Some
In example, loop construction is made of conventional cores.In other examples, etching coil using PC plate technology.In other examples
In, as shown in Fig. 9 and 10, carry out printed coil structure using suitable targeting print deposition techniques.In illustrated example
In, sacrifice sublimator material is used during intermediate fabrication steps, and then using the suitable of those techniques as described above
The technique of conjunction distils.In some instances, powdered ferrite or other core materials include sublimator material to be used for
The magnetic coupling of enhancing between primary coil structure 906 and secondary coil structure 908.Disclosed example is by secondary coil region
It is with advantage situated as the silicon substrate 902 far from semiconductor bare chip structure 901.This reduces eddy-current loss, and by the magnetic in cavity 110
The air core structure that coupling generates helps to reduce capacity loss to enhance high-frequency operation and reduce total from high conversion rate
The coupling of mould signal.It is shown in example as described, in addition, before molding, loop construction 906,908 can be by least
The selective position for being partially overlying on the expendable material of loop construction 906,908 is come at least partly by molded encapsulating structure
102 mechanically support.In other examples, the loop construction at least partly spacer by being formed before deposited sacrificial material
Support to material mechanical.
In the example of Fig. 9, IC 900 includes the lead frame knot with electric conductor 104a and 104b as described above
Structure.In this example, primary circuit is by being electrically connected to the of first couple of lead frame electric conductor 104a-l and 104a-2
The formation of one loop construction 906.First coil structure 906 is partially formed in semiconductor bare chip structure 901 via printing technology,
And also extend above the first expendable material (not shown in Fig. 9 and 10) so that a part of gained first coil structure 906 exists
Extend in expected cavity 110 after distillation processing.In the example of Fig. 9, in addition, at least partly landform of first coil structure 906
It is described above die pad or other conductive structures 122 (that is, being in electrical contact with the die pad or other conductive structures)
Die pad or other conductive structures are formed in the passivation of semiconductor bare chip 901, in IMD/ metal compound structure 904.At this
In example, metal compound structure 904 further includes conductive structure 907 so that the first end of first coil structure 906 to be electrically connected
To external die pad 122, the external die pad wire bonding to corresponding lead frame electric conductor 104a.Loop construction 906
Second end is connected to the second lead frame electric conductor 104a by the second conductive structure 907.As Figure 10 top view in most preferably show,
First coil structure 906 forms the bending section inside the cavity 110 between first end and second end.Loop construction 906 and 908 is also
It can be the spiral with multiple concentric bending sections.
In this example, the second loop construction 908 formed have both ends transformer secondary circuit, the both ends via
Metal compound configuration conductor 909, corresponding die pad 122 and associated splice line 124 are electrically connected to second pair of lead frame electric conductor
104b-l and 104b-2.In this example, the second loop construction 908 is formed by printed deposit technique, and is included in semiconductor
The end partly extended in nude film structure 901 is to form and the electrical connection of corresponding die pad 122.Use its of two bare dies
Its example be it is possible, one for primary coil and one is used for secondary coil.Described technology can also be used in other realities
Apply in example with manufacture inside IC package with air dielectric isolating transformer and without IC bare die to provide separated transformer.
Second loop construction 908 is extended in cavity 110 and is formed at least partly in the first coil structure 906 in cavity 110
The bending section of Fang Yanshen.It is configured by this, first coil structure 906 and the second loop construction 908 are via the air in cavity 110
Or it other gases and is magnetically coupling to one another to form the air core transformer in certain examples.As that described above is optically isolated
As device 100, the cavity 110 in the transformer example 900 of Fig. 9 includes port or opening 118, and the port or opening are by certain
Sealing structure 120 in a little examples covers.IC 900 includes general encapsulating structure 102 as described above, the encapsulating structure
Close lead frame structure 104 part and closing line 124, while expose to the open air lead frame electric conductor 104a-l, 104a-2,104b-l,
The part of 104b-2 is to allow the external connection with first coil structure 906 and the second loop construction 908.
Figure 17 and 18 illustrates substitution transformer IC embodiment 900, and it includes general first coil sections as described above
906 and second coil section 908.The example of Figure 17 and 18 further includes the ferrous iron at least partly extended in cavity 110
Material 1700.As seen in Figure 17, ferrous materia 1700 can be formed in the structure 904 of semiconductor bare chip structure 901, with first
Loop construction 906 is spaced apart with a part of the second loop construction 908 and in the first coil structure and second coil
A part of structure is following.In this example, in addition, ferrous materia 1700 at least partly extends in cavity 110.It is grasping
In work, ferrous materia 1700 facilitates the magnetic coupling of first coil structure 906 and the second loop construction 908.Other possible real
It applies in scheme, ferrous materia 1700 can be formed at least partly at the different location in cavity 110.It may implement at one
In scheme, ferrous materia structure 1700 can be vertically formed between first coil structure 906 and the second loop construction 908, and
It is spaced apart with the first coil structure and second loop construction, to further enhance the magnetic coupling of coil.For example,
Before forming the second loop construction 908, ferrous materia layer 1700 can be formed in corresponding the sacrificing of 906 top of first coil structure
Above material layer, and the second loop construction 908 can be formed in above another sacrificial material layer formed on ferrous materia 1700,
Another sacrificial material layer exposes at least part of the ferrous materia structure 1700 of deposition to the open air.In such example, package material
The distillation of the subsequently molded and sacrificial material layer of material 102 leaves the Asia at least partly mechanically supported by molded material 102
Iron material structure 1700, and the ferrous materia structure between loop construction 906 and 908 vertically extend and with the coil
Spacing structure is opened.Multiple ferrous materia layers can be also used at the identical or different position relative to loop construction.
Illustrate the technique or method of production integrated circuit according to another embodiment referring now to Figure 11 to 19, Figure 19
1900.For example, the transformer IC example of Fig. 9,10,17 and/or 18 can be manufactured using technique 1900 as described previously
900.Method 1900 starts from 1902, wherein one or more semiconductor bare chips are mounted in lead frame structure.For example, scheme
Semiconductor bare chip structure 901 in 9 or Figure 17 may be mounted to the lead frame structure comprising lead frame electric conductor 104, in Figure 11
Finding.In Figure 19 1904 at, execute wire bonding technique closing line 124 is connected to the naked of semiconductor bare chip structure 901
Between piece liner 122 and lead frame electric conductor 104, as shown in fig. 11.In some instances, at 1905, the is being formed
Before one sacrificial material layer, ferrous materia 1700 can be formed above a part of semiconductor bare chip 901 with for transformer core
The heart (for example, as shown in Figure 17).At 1906, the first expendable material is formed in a part top of semiconductor bare chip 901
(for example, directly or above intervention ferrous materia layer 1700).First sacrificial material layer and subsequent sacrificial material layer can be by appointing
What suitable depositing operation is formed.In Figure 11, the first sacrificial layer is shown as a layer SL1.In this example, at 1906,
First sacrificial material layer SL1 is formed in above the middle section of the upper face of nude film structure 901, and the layer SL1 does not cover
The illustrated die pad 122 formed in lid structure 904.
In Figure 19 1908 at, first coil structure (for example, above 906) is at least partially formed at the first sacrifice
On material layer SL1.In the example of Figure 11, loop construction 906 is at least partially formed at the naked of semiconductor bare chip structure 9014
122 top of piece liner, the die pad is by being electrically connected to the first of lead frame structure in the previous wire bonding of 1904 processing
To electric conductor 104a-l, 104a-2.In an example, the first transformer is printed using printed form depositing operation at 1908
Loop construction 906.In Figure 19 1910 at, the second sacrificial material layer SL2 is formed in a part of first coil structure 906
Side.Figure 12 shows an example, and wherein second material layer SL2 is formed in a part top of the first sacrificial material layer SL1 and is formed
In a part top for the first coil structure 906 being previously formed.In Figure 19 1912 at, 908 part of the second loop construction
Ground is formed on the second sacrificial material layer SL2.As demonstrated in Figure 13, in an example, second is formed using printing technology
Loop construction 908 is at least partly naked above the second sacrificial material layer SL2 and in the correspondence of semiconductor bare chip structure 9014
Piece liner 122 top extend, the die pad via closing line 124 be electrically connected to second couple of lead frame electric conductor 104b-l and
104b-2。
Continue to form one or more other sacrificial material layers at 1914 in Figure 19.In the example of Figure 14, third is formed
Sacrificial layer SL3 forms thereafter the 4th sacrificial material layer to limit the upper part of expected cavity 110 (for example, Fig. 9) in order
SL4 is to limit expected port openings 118 (for example, Fig. 9).In various embodiments, it can be formed at 1914 more or less
Sacrificial layer.At 1916, molding process is executed to form semiconductor bare chip 901,124 top of closing line and in lead frame structure
Encapsulating material (for example, 102 in Figure 15) above 104 part and sacrificial material layer is to form molded encapsulating structure
102.As shown in Figure 15, in addition, in some instances, molded encapsulating material 102 is at least partially formed at coil knot
To be used for its subsequent structural support after the sacrificial material layer that distils above one or two of structure 906 and/or 908.1918
Place, the expendable material SL that distils is to form the internal cavities 110 limited by the inner surface of encapsulating structure 102, such as the institute in Figure 16
It shows.Gained internal cavities 110 include electric isolution barrier between first coil structure 906 and the second loop construction 908 extremely
Few a part, and air core is also provided in some instances so that loop construction 906,908 magnetic couplings.In some instances,
In addition, in Figure 19 1920 at for example by rectangular on the port 118 in the transformer IC 900 of figure 9 above, 10,17 and 18
The cavity is sealed at sealing structure 120.
Examples detailed above only illustrates several possible embodiments of the various aspects of the disclosure, wherein in this theory of reading and understanding
Others skilled in the art will envision equivalence changes and/or modification after bright book and attached drawing.In claims
In range, the modification to described embodiment is possible, and other embodiments are possible.
Claims (25)
1. a kind of Integrated circuit IC comprising:
Lead frame structure, it includes multiple electric conductors；
First circuit structure, is electrically connected to first pair of electric conductor of the lead frame structure, and first circuit structure includes
It is configured to generate the light source of optical signal；
Second circuit structure is spaced apart with first circuit structure and is electrically connected to second pair of electricity of the lead frame structure
Conductor, the second circuit structure include at least partially face the light source to receive the optical sensor of the optical signal；With
And
Molded encapsulating structure, closes the part of the lead frame structure, and the molded encapsulating structure exposes described first to the open air
To the part of electric conductor and second pair of electric conductor to allow and first circuit structure and the second circuit structure
External connection, the molded encapsulating structure include the internal cavities limited by the inner surface of the molded encapsulating structure, institute
Cavity is stated to be provided between first circuit structure and the second circuit structure for the optical signal without Solid-state Optics
Path.
2. IC according to claim 1, wherein sealing the cavity.
3. IC according to claim 1, wherein the inner surface of the molded encapsulating structure includes concave part, and
Wherein the concave part of the inner surface includes the reflectance coating for reflecting light from the light source towards the optical sensor.
4. IC according to claim 1, wherein the light source includes Light-emitting diode LED.
5. IC according to claim 1, wherein the optical sensor includes diode.
6. IC according to claim 5, wherein the optical sensor includes multiple diodes.
7. IC according to claim 6, wherein the optical sensor includes the diode of multiple connections, single two pole
Pipe includes the n-quadrant and the region P of the semiconductor bare chip arranged along the optical path.
8. IC according to claim 6, wherein the optical sensor includes the diode of multiple connections, single two pole
Pipe includes the n-quadrant and the region P with the semiconductor bare chip of the optical path quadrature arrangement.
9. IC according to claim 1, wherein the optical sensor includes transistor.
10. IC according to claim 1, wherein the molded encapsulating structure close first circuit structure with it is described
The part of second circuit structure.
11. a kind of integrated circuit comprising:
Lead frame structure, it includes multiple electric conductors；
First coil structure is electrically connected to first pair of electric conductor of the lead frame structure, the first coil structure division
Ground is formed in semiconductor bare chip structure；
Second loop construction is electrically connected to second pair of electric conductor of the lead frame structure, second coil structure portions
Ground is formed in the semiconductor bare chip structure；And
Molded encapsulating structure, closes the part of the lead frame structure, and the molded encapsulating structure exposes described first to the open air
To the part of electric conductor and second pair of electric conductor to allow and the first coil structure and second loop construction
External connection, the molded encapsulating structure include the portion of first coil structure and second loop construction described in magnetic couplings
The cavity divided.
12. IC according to claim 11, wherein sealing the cavity.
13. IC according to claim 11, wherein the part of the first coil structure and second loop construction exists
Extend in the cavity.
14. IC according to claim 13, wherein the molded encapsulating structure closes the first coil structure and institute
State the part of the second loop construction.
15. IC according to claim 14 further comprises the ferrous material at least partly extended in the cavity
Material.
16. IC according to claim 11, wherein the molded encapsulating structure closes the first coil structure and institute
State the part of the second loop construction.
17. IC according to claim 11 further comprises the ferrous material at least partly extended in the cavity
Material.
18. IC according to claim 17, wherein the ferrous materia is formed in the semiconductor bare chip structure.
19. a kind of method for manufacturing Integrated circuit IC, which comprises
At least one semiconductor bare chip is mounted in lead frame structure；
Connect multiple closing lines between the joint liner of the semiconductor bare chip and the corresponding electric conductor of the lead frame structure；
Expendable material is formed above a part of the semiconductor bare chip；
It is formed in the semiconductor bare chip, the closing line and the lead frame structure and the upper of the expendable material
Molded encapsulating material, to form molded encapsulating structure；And
The expendable material distil to form the internal cavities limited by the inner surface of the molded encapsulating structure, the inside
Cavity includes at least one that barrier is isolated between the first circuit associated with the semiconductor bare chip and second circuit
Point.
20. further comprising according to the method for claim 19, sealing the internal cavities.
21. the method according to claim 11, further comprising:
First semiconductor bare chip is mounted in the lead frame structure, first semiconductor bare chip includes to be configured to generate
Along the light source of the optical signal of optical path；
Second semiconductor bare chip is mounted in the lead frame structure, second semiconductor bare chip includes at least partly ground
It is spaced apart to the optical path and with the light source of first semiconductor bare chip to receive the light sensing of the optical signal
Device；
The die pad of first semiconductor bare chip is connected to first pair of electric conductor of the lead frame structure；
The die pad of second semiconductor bare chip is connected to second pair of electric conductor of the lead frame structure；And
At least partly along one of first semiconductor bare chip of the optical path and second semiconductor bare chip
The expendable material is formed above point；
The expendable material that wherein distils forms at least part of internal cavities comprising the optical path, to allow
The optical signal is transmitted between the light source and the optical sensor.
22. described according to the method for claim 21, wherein the expendable material is formed to have the drop of nonreentrant surface
Method further comprises that reflectance coating, and the shape on the reflectance coating are formed on the nonreentrant surface of the expendable material
At the molded encapsulating material.
23. the method according to claim 11, further comprising:
First pair of die pad of the semiconductor bare chip is connected to first pair of electric conductor of the lead frame structure；
Second pair of die pad of the semiconductor bare chip is connected to second pair of electric conductor of the lead frame structure；
The first sacrificial material layer is formed above a part of the semiconductor bare chip；
First coil structure is partly formed in first sacrificial material layer, the first coil structure is electrically connected to described
First pair of electric conductor of lead frame structure；
The second sacrificial material layer is formed above a part of the first coil structure；
The second loop construction is partly formed in second sacrificial material layer, second loop construction is electrically connected to described
Second pair of electric conductor of lead frame structure；
Third sacrificial material layer is formed above a part of second loop construction；And
In the semiconductor bare chip, the closing line and the lead frame structure, the first coil structure and described second
Loop construction and the upper of the sacrificial material layer form the molded encapsulating material, to form the molded encapsulation
Structure；
The expendable material that wherein distils includes to distil the sacrificial material layer to form the internal cavities to provide in institute
State the electric isolution barrier between first coil structure and the part of second loop construction.
24. the method according to claim 11, further comprising:
Before forming the molded encapsulating material, one in the semiconductor bare chip with one in the loop construction
A a part top forms ferrous materia layer.
25. according to the method for claim 23 comprising:
First semiconductor bare chip and the second semiconductor bare chip are mounted in the lead frame structure；
The first coil structure is partly formed on first semiconductor bare chip；And
Second loop construction is partly formed on second semiconductor bare chip.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/395,584 US10074639B2 (en) | 2016-12-30 | 2016-12-30 | Isolator integrated circuits with package structure cavity and fabrication methods |
| US15/395,584 | 2016-12-30 | ||
| PCT/US2017/068983 WO2018126153A1 (en) | 2016-12-30 | 2017-12-29 | Isolator integrated circuits with package structure cavity and fabrication methods |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109952657A true CN109952657A (en) | 2019-06-28 |
| CN109952657B CN109952657B (en) | 2023-01-13 |
Family
ID=62708430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780068616.4A Active CN109952657B (en) | 2016-12-30 | 2017-12-29 | Isolator integrated circuit with package structure cavity and method of manufacture |
Country Status (3)
| Country | Link |
|---|---|
| US (3) | US10074639B2 (en) |
| CN (1) | CN109952657B (en) |
| WO (1) | WO2018126153A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024066277A1 (en) * | 2022-09-27 | 2024-04-04 | 长鑫存储技术有限公司 | Semiconductor structure preparation method and semiconductor structure |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6371725B2 (en) * | 2015-03-13 | 2018-08-08 | 株式会社東芝 | Semiconductor module |
| WO2018142863A1 (en) * | 2017-02-06 | 2018-08-09 | 富士電機株式会社 | Semiconductor module, electric automobile and power control unit |
| EP3685442B1 (en) * | 2017-09-22 | 2024-05-01 | Lawrence Livermore National Security, LLC | Photoconductive charge trapping apparatus |
| US10505456B1 (en) * | 2018-09-07 | 2019-12-10 | International Business Machines Corporation | Fully integrated multi-phase buck converter with coupled air core inductors |
| US11049980B2 (en) | 2018-10-30 | 2021-06-29 | Texas Instruments Incorporated | Integrated MIM diode |
| US10840171B2 (en) * | 2018-11-28 | 2020-11-17 | Texas Instruments Incorporated | Integrated circuit package including inward bent leads |
| US11211515B2 (en) * | 2019-02-27 | 2021-12-28 | Apple Inc. | Edge-mountable semiconductor chip package |
| DE102021210618A1 (en) * | 2021-09-23 | 2023-04-06 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | OPTOELECTRONIC DEVICE |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020172476A1 (en) * | 2001-05-16 | 2002-11-21 | Tohru Nagase | Optical module, optical transmitter and optical receiver |
| US20050218300A1 (en) * | 2004-04-02 | 2005-10-06 | Quinones Maria Clemens Y | Surface mount multi-channel optocoupler |
| US20080227286A1 (en) * | 2007-03-16 | 2008-09-18 | Commissariat A L'energie Atomique | Method for manufacturing an interconnection structure with cavities for an integrated circuit |
| CN103151419A (en) * | 2011-12-07 | 2013-06-12 | 安华高科技通用Ip(新加坡)公司 | An optical coupler |
| CN103727965A (en) * | 2012-10-16 | 2014-04-16 | 安华高科技通用Ip(新加坡)公司 | Proximity sensor device with internal channeling section |
| US20140117383A1 (en) * | 2012-10-30 | 2014-05-01 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Optocoupler Having Lens Layer |
Family Cites Families (140)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3363155A (en) | 1964-08-19 | 1968-01-09 | Philips Corp | Opto-electronic transistor with a base-collector junction spaced from the material heterojunction |
| US4007978A (en) | 1974-01-18 | 1977-02-15 | Texas Instruments Incorporated | Integrated optical circuits |
| US3952265A (en) | 1974-10-29 | 1976-04-20 | Hughes Aircraft Company | Monolithic dual mode emitter-detector terminal for optical waveguide transmission lines |
| US4272753A (en) | 1978-08-16 | 1981-06-09 | Harris Corporation | Integrated circuit fuse |
| US4210923A (en) | 1979-01-02 | 1980-07-01 | Bell Telephone Laboratories, Incorporated | Edge illuminated photodetector with optical fiber alignment |
| US4267484A (en) | 1979-08-28 | 1981-05-12 | The United States Of America As Represented By The Secretary Of The Air Force | Parallel multi-electrode spark gap switch |
| US4303934A (en) | 1979-08-30 | 1981-12-01 | Burr-Brown Research Corp. | Molded lead frame dual in line package including a hybrid circuit |
| US4996577A (en) | 1984-01-23 | 1991-02-26 | International Rectifier Corporation | Photovoltaic isolator and process of manufacture thereof |
| US4757210A (en) | 1987-03-02 | 1988-07-12 | Rockwell International Corporation | Edge illuminated detector arrays for determination of spectral content |
| JPS6457739A (en) | 1987-08-28 | 1989-03-06 | Toshiba Corp | Resin seal type element |
| US4916506A (en) | 1988-11-18 | 1990-04-10 | Sprague Electric Company | Integrated-circuit lead-frame package with low-resistance ground-lead and heat-sink means |
| US4891730A (en) | 1989-05-10 | 1990-01-02 | The United States Of America As Represented By The Secretary Of The Army | Monolithic microwave integrated circuit terminal protection device |
| US5340993A (en) * | 1993-04-30 | 1994-08-23 | Motorola, Inc. | Optocoupler package wth integral voltage isolation barrier |
| JPH0715030A (en) | 1993-06-07 | 1995-01-17 | Motorola Inc | Linear integrated optically-coupled element and preparation thereof |
| US6728113B1 (en) | 1993-06-24 | 2004-04-27 | Polychip, Inc. | Method and apparatus for non-conductively interconnecting integrated circuits |
| US5389578A (en) | 1994-01-04 | 1995-02-14 | Texas Instruments Incorporated | Optical coupler |
| US5514892A (en) | 1994-09-30 | 1996-05-07 | Motorola, Inc. | Electrostatic discharge protection device |
| US5796570A (en) | 1996-09-19 | 1998-08-18 | National Semiconductor Corporation | Electrostatic discharge protection package |
| US6111305A (en) | 1997-10-09 | 2000-08-29 | Nippon Telegraph And Telephone Corporation | P-I-N semiconductor photodetector |
| DE19800459A1 (en) | 1998-01-08 | 1999-07-22 | Siemens Ag | Oscillator structure with at least one oscillator circuit and at least one resonator |
| JPH11274196A (en) | 1998-03-26 | 1999-10-08 | Seiko Epson Corp | Manufacture of semiconductor device, molding system and the semiconductor device |
| US5929514A (en) | 1998-05-26 | 1999-07-27 | Analog Devices, Inc. | Thermally enhanced lead-under-paddle I.C. leadframe |
| CN1118103C (en) | 1998-10-21 | 2003-08-13 | 李韫言 | Thermal radiation infrared sensor for fine machining |
| US5990519A (en) | 1998-11-27 | 1999-11-23 | United Microelectronics Corp. | Electrostatic discharge structure |
| US6351011B1 (en) | 1998-12-08 | 2002-02-26 | Littlefuse, Inc. | Protection of an integrated circuit with voltage variable materials |
| JP2000311959A (en) | 1999-04-27 | 2000-11-07 | Sanyo Electric Co Ltd | Semiconductor device and manufacture of the same |
| RU2169962C2 (en) | 1999-07-13 | 2001-06-27 | Минг-Тунг ШЕН | Module with semiconductor integrated circuits and its manufacturing process |
| US6300632B1 (en) | 1999-10-14 | 2001-10-09 | The Regents Of The University Of Michigan | Uncooled infrared focal plane imager and microelectromechanical infrared detector for use therein |
| KR20010037247A (en) | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | Semiconductor package |
| US6509574B2 (en) | 1999-12-02 | 2003-01-21 | Texas Instruments Incorporated | Optocouplers having integrated organic light-emitting diodes |
| TW466720B (en) | 2000-05-22 | 2001-12-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with flash-prevention structure and manufacture method |
| US6507264B1 (en) | 2000-08-28 | 2003-01-14 | Littelfuse, Inc. | Integral fuse for use in semiconductor packages |
| JP4565727B2 (en) | 2000-10-10 | 2010-10-20 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| RU2201017C2 (en) | 2000-10-26 | 2003-03-20 | Зао "Синтэк" | Optron |
| US7334326B1 (en) | 2001-06-19 | 2008-02-26 | Amkor Technology, Inc. | Method for making an integrated circuit substrate having embedded passive components |
| US6801114B2 (en) | 2002-01-23 | 2004-10-05 | Broadcom Corp. | Integrated radio having on-chip transformer balun |
| US20030141802A1 (en) | 2002-01-28 | 2003-07-31 | John Liebeskind | Electronic device having a getter used as a circuit element |
| JP2003282935A (en) | 2002-03-26 | 2003-10-03 | Sharp Corp | Optically coupled device and method of manufacturing the same, and electronic apparatus |
| US20030183916A1 (en) | 2002-03-27 | 2003-10-02 | John Heck | Packaging microelectromechanical systems |
| US20040080025A1 (en) | 2002-09-17 | 2004-04-29 | Shinko Electric Industries Co., Ltd. | Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same |
| US6879004B2 (en) | 2002-11-05 | 2005-04-12 | Silicon Labs Cp, Inc. | High voltage difference amplifier with spark gap ESD protection |
| US6977468B1 (en) | 2003-02-03 | 2005-12-20 | Auburn University | Integrated spark gap device |
| US7247246B2 (en) | 2003-10-20 | 2007-07-24 | Atmel Corporation | Vertical integration of a MEMS structure with electronics in a hermetically sealed cavity |
| US6921704B1 (en) | 2003-11-05 | 2005-07-26 | Advanced Micro Devices, Inc. | Method for improving MOS mobility |
| RU2263999C1 (en) | 2004-02-02 | 2005-11-10 | ЗАО "Синтез электронных компонентов" | Integrated optocoupler |
| US7180098B2 (en) | 2004-04-05 | 2007-02-20 | Legerity, Inc. | Optical isolator device, and method of making same |
| US7508644B2 (en) | 2004-06-30 | 2009-03-24 | Research In Motion Limited | Spark gap apparatus and method for electrostatic discharge protection |
| US7015587B1 (en) | 2004-09-07 | 2006-03-21 | National Semiconductor Corporation | Stacked die package for semiconductor devices |
| DE102004043663B4 (en) | 2004-09-07 | 2006-06-08 | Infineon Technologies Ag | Semiconductor sensor component with cavity housing and sensor chip and method for producing a semiconductor sensor component with cavity housing and sensor chip |
| JP5011115B2 (en) | 2004-10-18 | 2012-08-29 | スタッツ・チップパック・インコーポレイテッド | Multi-chip lead frame semiconductor package |
| JP2006120953A (en) | 2004-10-22 | 2006-05-11 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US7718967B2 (en) | 2005-01-26 | 2010-05-18 | Analog Devices, Inc. | Die temperature sensors |
| US8487260B2 (en) | 2005-01-26 | 2013-07-16 | Analog Devices, Inc. | Sensor |
| JP4724488B2 (en) | 2005-02-25 | 2011-07-13 | 日立オートモティブシステムズ株式会社 | Integrated microelectromechanical system |
| KR100833017B1 (en) | 2005-05-12 | 2008-05-27 | 주식회사 엘지화학 | Method for preparing a high resolution pattern with direct writing means |
| US7787230B2 (en) | 2005-09-14 | 2010-08-31 | University of Wirwatersrand, Johannesburg | Spark gap protection device |
| JP4594205B2 (en) | 2005-10-05 | 2010-12-08 | 本田技研工業株式会社 | Direction indicator lights for vehicles |
| US7436054B2 (en) | 2006-03-03 | 2008-10-14 | Silicon Matrix, Pte. Ltd. | MEMS microphone with a stacked PCB package and method of producing the same |
| JP5001564B2 (en) | 2006-03-17 | 2012-08-15 | 日本電波工業株式会社 | Surface mount crystal oscillator and manufacturing method thereof |
| JP2007325013A (en) | 2006-06-01 | 2007-12-13 | Alps Electric Co Ltd | Surface acoustic wave device and method for manufacturing the same |
| US7732892B2 (en) | 2006-11-03 | 2010-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fuse structures and integrated circuit devices |
| US7834435B2 (en) | 2006-12-27 | 2010-11-16 | Mediatek Inc. | Leadframe with extended pad segments between leads and die pad, and leadframe package using the same |
| US20080217759A1 (en) | 2007-03-06 | 2008-09-11 | Taiwan Solutions Systems Corp. | Chip package substrate and structure thereof |
| US20080266730A1 (en) | 2007-04-25 | 2008-10-30 | Karsten Viborg | Spark Gaps for ESD Protection |
| US8436460B1 (en) | 2007-05-04 | 2013-05-07 | Cypress Semiconductor Corporation | Multiple die paddle leadframe and semiconductor device package |
| US8049326B2 (en) | 2007-06-07 | 2011-11-01 | The Regents Of The University Of Michigan | Environment-resistant module, micropackage and methods of manufacturing same |
| JP5076725B2 (en) | 2007-08-13 | 2012-11-21 | 富士電機株式会社 | Insulation transformer and power converter |
| JP4912275B2 (en) | 2007-11-06 | 2012-04-11 | 新光電気工業株式会社 | Semiconductor package |
| US7847387B2 (en) | 2007-11-16 | 2010-12-07 | Infineon Technologies Ag | Electrical device and method |
| US8159056B1 (en) | 2008-01-15 | 2012-04-17 | Rf Micro Devices, Inc. | Package for an electronic device |
| JP4636187B2 (en) | 2008-04-22 | 2011-02-23 | 株式会社デンソー | Method for manufacturing mechanical quantity sensor and mechanical quantity sensor |
| US7842542B2 (en) | 2008-07-14 | 2010-11-30 | Stats Chippac, Ltd. | Embedded semiconductor die package and method of making the same using metal frame carrier |
| US8148781B2 (en) | 2008-07-28 | 2012-04-03 | MCube Inc. | Method and structures of monolithically integrated ESD suppression device |
| JP2010071816A (en) | 2008-09-18 | 2010-04-02 | Toshiba Corp | Electronic device |
| US8072770B2 (en) | 2008-10-14 | 2011-12-06 | Texas Instruments Incorporated | Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame |
| JP5590814B2 (en) | 2009-03-30 | 2014-09-17 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and manufacturing method thereof |
| JP2010245337A (en) | 2009-04-07 | 2010-10-28 | Elpida Memory Inc | Semiconductor device and manufacturing method for the same |
| EP2252077B1 (en) | 2009-05-11 | 2012-07-11 | STMicroelectronics Srl | Assembly of a capacitive acoustic transducer of the microelectromechanical type and package thereof |
| US8519481B2 (en) | 2009-10-14 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Voids in STI regions for forming bulk FinFETs |
| US8183593B2 (en) | 2009-10-16 | 2012-05-22 | Oracle America, Inc. | Semiconductor die with integrated electro-static discharge device |
| US8274301B2 (en) | 2009-11-02 | 2012-09-25 | International Business Machines Corporation | On-chip accelerated failure indicator |
| US8410463B2 (en) | 2009-11-12 | 2013-04-02 | Fairchild Semiconductor Corporation | Optocoupler devices |
| JP2011192841A (en) | 2010-03-15 | 2011-09-29 | Toshiba Corp | Semiconductor device |
| US8368232B2 (en) | 2010-03-25 | 2013-02-05 | Qualcomm Incorporated | Sacrificial material to facilitate thin die attach |
| US8941064B2 (en) | 2010-04-12 | 2015-01-27 | Mikrosens Elektronik San. Ve Tic. A.S. | Uncooled infrared detector and methods for manufacturing the same |
| JP5521827B2 (en) | 2010-06-28 | 2014-06-18 | セイコーエプソン株式会社 | Pyroelectric detector, pyroelectric detector and electronic device |
| US8260098B1 (en) | 2011-02-17 | 2012-09-04 | Nxp B.V. | Optocoupler circuit |
| JP5541306B2 (en) | 2011-05-27 | 2014-07-09 | 株式会社デンソー | Mechanical quantity sensor device and manufacturing method thereof |
| US8564004B2 (en) | 2011-11-29 | 2013-10-22 | Cree, Inc. | Complex primary optics with intermediate elements |
| US8587077B2 (en) | 2012-01-02 | 2013-11-19 | Windtop Technology Corp. | Integrated compact MEMS device with deep trench contacts |
| US9154103B2 (en) | 2012-01-30 | 2015-10-06 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Temperature controlled acoustic resonator |
| US9667218B2 (en) | 2012-01-30 | 2017-05-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Temperature controlled acoustic resonator comprising feedback circuit |
| US9466532B2 (en) | 2012-01-31 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Micro-electro mechanical system (MEMS) structures with through substrate vias and methods of forming the same |
| US9279946B2 (en) * | 2012-05-23 | 2016-03-08 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Premolded cavity for optoelectronic device |
| DE102012208730A1 (en) | 2012-05-24 | 2013-11-28 | Osram Opto Semiconductors Gmbh | Optoelectronic component device and method for producing an optoelectronic component device |
| US8674509B2 (en) | 2012-05-31 | 2014-03-18 | Freescale Semiconductor, Inc. | Integrated circuit die assembly with heat spreader |
| US9269609B2 (en) | 2012-06-01 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor isolation structure with air gaps in deep trenches |
| US9011176B2 (en) | 2012-06-09 | 2015-04-21 | Apple Inc. | ESD path for connector receptacle |
| US9310552B2 (en) | 2012-06-15 | 2016-04-12 | Micron Technology, Inc. | Methods and apparatus providing thermal isolation of photonic devices |
| US8633551B1 (en) | 2012-06-29 | 2014-01-21 | Intel Corporation | Semiconductor package with mechanical fuse |
| US8704370B2 (en) | 2012-06-29 | 2014-04-22 | Freescale Semiconductor, Inc. | Semiconductor package structure having an air gap and method for forming |
| JP6084401B2 (en) | 2012-08-30 | 2017-02-22 | 浜松ホトニクス株式会社 | Method for manufacturing side-incident photodiodes |
| US8912890B2 (en) | 2012-10-01 | 2014-12-16 | Thin Film Electronics Asa | Surveillance devices with multiple capacitors |
| US9184012B2 (en) | 2012-12-19 | 2015-11-10 | Allegro Microsystems, Llc | Integrated circuit fuse and method of fabricating the integrated circuit fuse |
| DE102013101262A1 (en) | 2013-02-08 | 2014-08-14 | Osram Opto Semiconductors Gmbh | Optoelectronic light module, optoelectronic light device and vehicle headlights |
| US20150380353A1 (en) | 2013-02-12 | 2015-12-31 | Freescale Semiconductor, Inc. | Method of fabricating an integrated circuit device, and an integrated circuit device therefrom |
| US10002700B2 (en) * | 2013-02-27 | 2018-06-19 | Qualcomm Incorporated | Vertical-coupling transformer with an air-gap structure |
| US9349616B2 (en) | 2013-03-13 | 2016-05-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming WLCSP with semiconductor die embedded within interconnect structure |
| US9184093B2 (en) | 2013-03-15 | 2015-11-10 | Applied Materials, Inc. | Integrated cluster to enable next generation interconnect |
| US9006857B1 (en) | 2013-04-04 | 2015-04-14 | William N. Carr | Platform comprising an infrared sensor |
| EP2790474B1 (en) | 2013-04-09 | 2016-03-16 | Harman Becker Automotive Systems GmbH | Thermoelectric cooler/heater integrated in printed circuit board |
| JP6256933B2 (en) | 2013-05-23 | 2018-01-10 | 木村 光照 | Hydrogen gas sensor having concentration function and hydrogen gas sensor probe used therefor |
| US20150004902A1 (en) * | 2013-06-28 | 2015-01-01 | John M. Pigott | Die-to-die inductive communication devices and methods |
| ITTO20130651A1 (en) | 2013-07-31 | 2015-02-01 | St Microelectronics Srl | PROCESS OF MANUFACTURING AN ENCAPSULATED DEVICE, IN PARTICULAR AN ENCAPSULATED MICRO-ELECTRO-MECHANICAL SENSOR, EQUIPPED WITH AN ACCESSIBLE STRUCTURE, AS A MEMS MICROPHONE AND ENCAPSULATED DEVICE SO OBTAINED |
| US20150069537A1 (en) | 2013-09-08 | 2015-03-12 | Wai Yew Lo | Package-on-package semiconductor sensor device |
| US20150094875A1 (en) | 2013-09-30 | 2015-04-02 | Yacov Duzly | Temperature-Controlled Storage Module that Cools Memory Prior to a Data Burst |
| US9160423B2 (en) * | 2013-12-12 | 2015-10-13 | Freescale Semiconductor, Inc. | Die-to-die inductive communication devices and methods |
| US9630832B2 (en) | 2013-12-19 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing |
| GB2521619A (en) | 2013-12-23 | 2015-07-01 | Nokia Technologies Oy | An apparatus and associated methods for flexible carrier substrates |
| US9287831B2 (en) | 2013-12-23 | 2016-03-15 | Analog Devices Global | Temperature stabilized circuitry |
| DE102014200500A1 (en) | 2014-01-14 | 2015-07-16 | Robert Bosch Gmbh | Micromechanical pressure sensor device and corresponding manufacturing method |
| DE102014210006A1 (en) | 2014-02-18 | 2015-08-20 | Robert Bosch Gmbh | Sensor unit and method for producing a sensor unit |
| US9818665B2 (en) | 2014-02-28 | 2017-11-14 | Infineon Technologies Ag | Method of packaging a semiconductor chip using a 3D printing process and semiconductor package having angled surfaces |
| US9863828B2 (en) | 2014-06-18 | 2018-01-09 | Seiko Epson Corporation | Physical quantity sensor, electronic device, altimeter, electronic apparatus, and mobile object |
| JP2016003977A (en) | 2014-06-18 | 2016-01-12 | セイコーエプソン株式会社 | Physical quantity sensor device, altimeter, electronic apparatus, and mobile body |
| US9281331B2 (en) | 2014-06-19 | 2016-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | High dielectric constant structure for the vertical transfer gates of a complementary metal-oxide semiconductor (CMOS) image sensor |
| TWI691036B (en) | 2014-06-23 | 2020-04-11 | 澳大利亞商西拉娜集團私人有限公司 | Bonded dies with isolation |
| US9472788B2 (en) | 2014-08-27 | 2016-10-18 | 3M Innovative Properties Company | Thermally-assisted self-assembly method of nanoparticles and nanowires within engineered periodic structures |
| US9698256B2 (en) | 2014-09-24 | 2017-07-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Termination of super junction power MOSFET |
| US20160167089A1 (en) | 2014-12-11 | 2016-06-16 | Palo Alto Research Center Incorporation | Forming sacrificial structures using phase-change materials that sublimate |
| US9219028B1 (en) * | 2014-12-17 | 2015-12-22 | Freescale Semiconductor, Inc. | Die-to-die inductive communication devices and methods |
| US20160209285A1 (en) | 2015-01-20 | 2016-07-21 | Seiko Epson Corporation | Pressure sensor, method of manufacturing pressure sensor, altimeter, electronic apparatus, and moving object |
| US9419075B1 (en) | 2015-01-28 | 2016-08-16 | Texas Instruments Incorporated | Wafer substrate removal |
| US20170047271A1 (en) | 2015-08-10 | 2017-02-16 | Freescale Semiconductor, Inc. | Method for making a semiconductor device having an interposer |
| JP2017067463A (en) | 2015-09-28 | 2017-04-06 | セイコーエプソン株式会社 | Pressure sensor, altimeter, electronic apparatus, and movable body |
| JP2017092698A (en) | 2015-11-10 | 2017-05-25 | セイコーエプソン株式会社 | Oscillator, electronic apparatus, and movable body |
| US9957159B2 (en) | 2016-03-28 | 2018-05-01 | Evigia Systems, Inc. | System and method for an ovenized silicon platform using Si/SiO2 hybrid supports |
| US10861796B2 (en) | 2016-05-10 | 2020-12-08 | Texas Instruments Incorporated | Floating die package |
| US9761543B1 (en) * | 2016-12-20 | 2017-09-12 | Texas Instruments Incorporated | Integrated circuits with thermal isolation and temperature regulation |
| US9929110B1 (en) | 2016-12-30 | 2018-03-27 | Texas Instruments Incorporated | Integrated circuit wave device and method |
-
2016
- 2016-12-30 US US15/395,584 patent/US10074639B2/en active Active
-
2017
- 2017-12-29 WO PCT/US2017/068983 patent/WO2018126153A1/en active Application Filing
- 2017-12-29 CN CN201780068616.4A patent/CN109952657B/en active Active
-
2018
- 2018-09-10 US US16/126,577 patent/US10636778B2/en active Active
-
2020
- 2020-04-27 US US16/859,345 patent/US11264369B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020172476A1 (en) * | 2001-05-16 | 2002-11-21 | Tohru Nagase | Optical module, optical transmitter and optical receiver |
| US20050218300A1 (en) * | 2004-04-02 | 2005-10-06 | Quinones Maria Clemens Y | Surface mount multi-channel optocoupler |
| US20080227286A1 (en) * | 2007-03-16 | 2008-09-18 | Commissariat A L'energie Atomique | Method for manufacturing an interconnection structure with cavities for an integrated circuit |
| CN103151419A (en) * | 2011-12-07 | 2013-06-12 | 安华高科技通用Ip(新加坡)公司 | An optical coupler |
| CN103727965A (en) * | 2012-10-16 | 2014-04-16 | 安华高科技通用Ip(新加坡)公司 | Proximity sensor device with internal channeling section |
| US20140117383A1 (en) * | 2012-10-30 | 2014-05-01 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Optocoupler Having Lens Layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024066277A1 (en) * | 2022-09-27 | 2024-04-04 | 长鑫存储技术有限公司 | Semiconductor structure preparation method and semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| US10636778B2 (en) | 2020-04-28 |
| WO2018126153A1 (en) | 2018-07-05 |
| US11264369B2 (en) | 2022-03-01 |
| US10074639B2 (en) | 2018-09-11 |
| US20190006338A1 (en) | 2019-01-03 |
| US20180190628A1 (en) | 2018-07-05 |
| US20200258874A1 (en) | 2020-08-13 |
| CN109952657B (en) | 2023-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109952657A (en) | Isolator integrated circuit and manufacturing method with encapsulating structure cavity | |
| CN100461403C (en) | Semiconductor device | |
| CN105022127B (en) | Active silicon optical bench | |
| CN100452336C (en) | Method for manufacturing optocoupler | |
| CN106024754B (en) | Semiconductor package | |
| CN107409469B (en) | Single layer laminate current isolator assembly | |
| TWI453876B (en) | Chip stack package | |
| CN102237336B (en) | Integrated transformer | |
| US20140055217A1 (en) | Die-to-die electrical isolation in a semiconductor package | |
| CN102110678B (en) | Semiconductor package and manufacturing method thereof | |
| CN105374839A (en) | Wire bond sensor package and method | |
| CN103367334A (en) | Semiconductor package with through silicon via interconnect and method for fabricating the same | |
| CN104882417A (en) | Integrated Passive Flip Chip Package | |
| CN103594440A (en) | Semiconductor substrate | |
| CN104377163A (en) | CMOS compatible wafer bonding layer and process | |
| CN104051436A (en) | Laterally coupled isolator devices | |
| KR20180002044A (en) | Semiconductor die backside device and method of fabrication thereof | |
| CN103101875A (en) | Semiconductor package and method of fabricating the same | |
| TW201322316A (en) | System in package module and manufacturing method thereof | |
| CN206767639U (en) | Integrated-semiconductor device | |
| CN104124212B (en) | Semiconductor package and fabrication method thereof | |
| CN110957302A (en) | Transistor with shielding structure, packaging device and manufacturing method thereof | |
| CN103633551A (en) | Method for encapsulating laser for on-chip optical interconnection | |
| CN105609472B (en) | The encapsulating structure and its manufacture method of pressure sensor | |
| CN107342256A (en) | Semiconductor technology and semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |