CN109873057B - Light emitting diode epitaxial wafer and growth method thereof - Google Patents
Light emitting diode epitaxial wafer and growth method thereof Download PDFInfo
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- CN109873057B CN109873057B CN201910085715.4A CN201910085715A CN109873057B CN 109873057 B CN109873057 B CN 109873057B CN 201910085715 A CN201910085715 A CN 201910085715A CN 109873057 B CN109873057 B CN 109873057B
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Abstract
The invention discloses a light emitting diode epitaxial wafer and a growth method thereof, and belongs to the technical field of semiconductors. The epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the active layer comprises a first laminated structure, a second laminated structure, a third laminated structure and a fourth laminated structure, a quantum barrier of the first laminated structure comprises a first sublayer, a second sublayer and a third sublayer, a quantum barrier of the second laminated structure comprises a fourth sublayer and a fifth sublayer, undoped gallium nitride is adopted as materials of the quantum barriers of the first sublayer, the third sublayer, the fourth sublayer and the fourth laminated structure, and silicon-doped gallium nitride is adopted as materials of the quantum barriers of the second sublayer, the fifth sublayer and the third laminated structure; the average doping concentration of silicon in the quantum barrier of the first laminated structure, the average doping concentration of silicon in the quantum barrier of the second laminated structure and the doping concentration of silicon in the quantum barrier of the third laminated structure are gradually reduced. The invention finally improves the radiation recombination efficiency.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light emitting diode epitaxial wafer and a growth method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. As a novel efficient, environment-friendly and green solid-state illumination light source, LEDs are being rapidly and widely applied in the fields of traffic signal lights, automobile interior and exterior lights, urban landscape lighting, mobile phone backlight sources and the like. The core component of the LED is a chip, and improving the light emitting efficiency of the chip is a goal continuously pursued in the application process of the LED.
The chip comprises an epitaxial wafer and an electrode arranged on the epitaxial wafer. The conventional LED epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate. The active layer includes a plurality of quantum wells and a plurality of quantum barriers, which are alternately stacked. The quantum barrier limits electrons provided by the N-type semiconductor layer and holes provided by the P-type semiconductor layer in the quantum well for composite light emission, the substrate provides an epitaxial growth surface, and the buffer layer provides a nucleation center for epitaxial growth.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the material of the quantum barrier is usually gallium nitride doped with silicon to destroy the line defects in the crystal, and simultaneously, the current injected into the LED is expanded to reduce the working voltage of the LED. If the quantum barrier is doped with high-concentration silicon, although the working voltage of the LED can be greatly reduced, the crystal quality of an epitaxial wafer can be affected, and the luminous brightness of the LED is reduced. If the quantum barrier is doped with low-concentration silicon, the working voltage of the LED is basically unchanged, and the effect of reducing the working voltage of the LED cannot be achieved. Therefore, the doping concentration of silicon in the quantum barrier is difficult to simultaneously consider the crystal quality of the epitaxial wafer and the operating voltage of the LED.
Disclosure of Invention
The embodiment of the invention provides a light-emitting diode epitaxial wafer and a growth method thereof, which can solve the problem that the prior art cannot simultaneously consider the crystal quality of the epitaxial wafer and the LED working voltage. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a light emitting diode epitaxial wafer, where the light emitting diode epitaxial wafer includes a substrate, a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, where the buffer layer, the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are sequentially stacked on the substrate; the active layer comprises a first laminated structure, a second laminated structure, a third laminated structure and a fourth laminated structure which are sequentially laminated, the first laminated structure, the second laminated structure, the third laminated structure and the fourth laminated structure respectively comprise at least one quantum well and at least one quantum barrier, and the quantum wells and the quantum barriers are alternately laminated; the quantum barrier of the first laminated structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated, the quantum barrier of the second laminated structure comprises a fourth sublayer and a fifth sublayer which are sequentially laminated, undoped gallium nitride is adopted as the material of the first sublayer, the material of the third sublayer, the material of the fourth sublayer and the material of the quantum barrier of the fourth laminated structure, and silicon-doped gallium nitride is adopted as the material of the second sublayer, the material of the fifth sublayer and the material of the quantum barrier of the third laminated structure; the average doping concentration of silicon in the quantum barrier of the first laminated structure is greater than that of silicon in the quantum barrier of the second laminated structure, and the average doping concentration of silicon in the quantum barrier of the second laminated structure is greater than that of silicon in the quantum barrier of the third laminated structure.
Optionally, the number of quantum barriers of the first stacked structure is greater than the number of quantum barriers of the second stacked structure, the number of quantum barriers of the second stacked structure is greater than the number of quantum barriers of the third stacked structure, and the number of quantum barriers of the third stacked structure is greater than the number of quantum barriers of the fourth stacked structure.
Further, a difference between the number of quantum barriers of the first stacked structure and the number of quantum barriers of the second stacked structure, a difference between the number of quantum barriers of the second stacked structure and the number of quantum barriers of the third stacked structure, and a difference between the number of quantum barriers of the third stacked structure and the number of quantum barriers of the fourth stacked structure are equal.
Illustratively, the difference between the number of quantum barriers of the third stacked structure and the number of quantum barriers of the fourth stacked structure is 1 to 2.
Illustratively, the number of quantum barriers of the fourth stacked structure is 1 to 2.
Optionally, the ratio of the average doping concentration of silicon in the quantum barrier of the first stacked structure to the average doping concentration of silicon in the quantum barrier of the second stacked structure, and the ratio of the average doping concentration of silicon in the quantum barrier of the second stacked structure to the doping concentration of silicon in the quantum barrier of the third stacked structure are equal.
Further, the average doping concentration of silicon in the quantum barrier of the first stacked structure is 1.5 to 3 times that of silicon in the quantum barrier of the second stacked structure, and the average doping concentration of silicon in the quantum barrier of the second stacked structure is 1.5 to 3 times that of silicon in the quantum barrier of the third stacked structure.
Illustratively, the doping concentration of silicon in the quantum barrier of the third stacked structure is 1 × 1017/cm3～5*1017/cm3。
Optionally, the thickness of the first sub-layer, the thickness of the second sub-layer, the thickness of the third sub-layer, the thickness of the fourth sub-layer, the thickness of the fifth sub-layer, the thickness of the quantum barrier of the third stacked structure, and the thickness of the quantum barrier of the fourth stacked structure are equal.
In another aspect, an embodiment of the present invention provides a growth method of a light emitting diode epitaxial wafer, where the growth method includes:
providing a substrate;
growing a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
the active layer comprises a first laminated structure, a second laminated structure, a third laminated structure and a fourth laminated structure which are sequentially laminated, wherein the first laminated structure, the second laminated structure, the third laminated structure and the fourth laminated structure respectively comprise at least one quantum well and at least one quantum barrier, and the quantum wells and the quantum barriers are alternately laminated; the quantum barrier of the first laminated structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated, the quantum barrier of the second laminated structure comprises a fourth sublayer and a fifth sublayer which are sequentially laminated, undoped gallium nitride is adopted as the material of the first sublayer, the material of the third sublayer, the material of the fourth sublayer and the material of the quantum barrier of the fourth laminated structure, and silicon-doped gallium nitride is adopted as the material of the second sublayer, the material of the fifth sublayer and the material of the quantum barrier of the third laminated structure; the average doping concentration of silicon in the quantum barrier of the first laminated structure is greater than that of silicon in the quantum barrier of the second laminated structure, and the average doping concentration of silicon in the quantum barrier of the second laminated structure is greater than that of silicon in the quantum barrier of the third laminated structure.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the laminated structure formed by alternately laminating the quantum wells and the quantum barriers is divided into four parts, namely a first laminated structure, a second laminated structure, a third laminated structure and a fourth laminated structure, so that the change of the silicon doping concentration in the quantum barriers is realized. The doping concentration of silicon in the quantum barrier of the first laminated structure is highest, and more impurities enable electrons to be easily scattered by the impurities during conduction, multiple scattered waves are mutually interfered, the Anderson localization effect is enhanced, a certain blocking effect can be achieved on the electrons, the movement rate of the electrons is reduced, the transverse expansion of current is facilitated, and the uniform distribution of the electrons is promoted. And the doping concentration of silicon in the quantum barrier of the grown second laminated structure is reduced but still higher, and on the basis of the stress accumulated by the first laminated structure, the growth mode of the crystal is changed, the line defects in the crystal are reduced, so that the quantum well is subjected to spiral growth, a high-density nano island-shaped structure is formed, the light-emitting characteristic is improved, and the band gap fluctuation is inhibited. And then the doping concentration of silicon in the quantum barrier of the grown third laminated structure is lower, so that a buffer effect is achieved between the highly silicon-doped laminated structure and the undoped laminated structure, a certain blocking effect is achieved on electrons, and the phenomenon that the migration rate of the electrons is too high can be avoided. And no silicon is doped in the quantum barrier of the finally grown fourth laminated structure, so that a piezoelectric field caused by stress generated by lattice mismatch can be shielded, the quantum confinement Stark effect is relieved, and the radiation recombination efficiency of electrons and holes is improved.
The first laminated structure is composed of three sublayers, the second laminated structure is composed of two sublayers, and the third laminated structure and the fourth laminated structure are both single-layers, so that the thickness of the quantum barrier can be reduced from the N-type semiconductor layer to the P-type semiconductor layer. Because electrons are injected into the active layer from the N-type semiconductor layer, the quantity of electrons in the quantum barrier close to the N-type semiconductor layer is large, and the migration rate of the electrons is high, the quantum barrier close to the N-type semiconductor layer is thick, the restriction effect on the migration of the electrons is high, the phenomenon that the migration speed of the electrons is too high can be effectively avoided, and the electrons are favorably restricted in a quantum well. And because the quantity of electrons in the quantum barrier close to the P-type semiconductor layer is less and the migration rate of the electrons is slower, the quantum barrier close to the P-type semiconductor layer is thinner, the migration of the electrons is basically not limited, the migration of the electrons is easier, the recombination luminescence in the quantum well with more electron injection holes is facilitated, and meanwhile, the quantum well of the P-type semiconductor layer is considered as a main luminescent well, the quantity of consumed electrons is more, and the overflow of the electrons is not caused.
On the whole, in the direction from the N-type semiconductor layer to the P-type semiconductor layer, the doping concentration of silicon in the quantum barrier is gradually reduced, the thickness of the quantum barrier is gradually reduced, the two are matched with each other, the part close to the N-type semiconductor layer can effectively improve the line defects in the crystal, the current expansion is realized, the part close to the P-type semiconductor layer has better lattice quality, and the radiation recombination efficiency of electrons and holes is finally improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an active layer provided in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a quantum barrier of a first stacked structure provided by an embodiment of the invention;
fig. 4 is a schematic structural diagram of a quantum barrier of a second stacked structure provided by the embodiment of the invention;
fig. 5 is a flowchart of a method for growing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a light-emitting diode epitaxial wafer. Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention. Referring to fig. 1, the light emitting diode epitaxial wafer includes a substrate 1, a buffer layer 2, an N-type semiconductor layer 3, an active layer 4, and a P-type semiconductor layer 5, and the buffer layer 2, the N-type semiconductor layer 3, the active layer 4, and the P-type semiconductor layer 5 are sequentially stacked on the substrate 1.
Fig. 2 is a schematic structural diagram of an active layer according to an embodiment of the present invention. Referring to fig. 2, the active layer 4 includes a first stacked structure 41, a second stacked structure 42, a third stacked structure 43, and a fourth stacked structure 44, which are sequentially stacked, and each of the first stacked structure 41, the second stacked structure 42, the third stacked structure 43, and the fourth stacked structure 44 includes at least one quantum well and at least one quantum barrier, and the quantum wells and the quantum barriers are alternately stacked. In fig. 2, different numbers are used to represent the quantum well and the quantum barrier in different stacked structures, 411 represents the quantum well of the first stacked structure, and 412 represents the quantum barrier of the first stacked structure; 421 denotes a quantum well of the second stacked structure, and 422 denotes a quantum barrier of the second stacked structure; 431 represents a quantum well of the third stacked structure, and 432 represents a quantum barrier of the third stacked structure; 441 denotes a quantum well of the fourth stacked structure, and 442 denotes a quantum barrier of the fourth stacked structure.
Fig. 3 is a schematic structural diagram of a quantum barrier of a first stacked structure according to an embodiment of the present invention. Referring to fig. 3, the quantum barrier 412 of the first stack structure 41 includes a first sub-layer 412a, a second sub-layer 412b, and a third sub-layer 412c, which are sequentially stacked. Fig. 4 is a schematic structural diagram of a quantum barrier of a second stacked structure according to an embodiment of the present invention. Referring to fig. 4, the quantum barrier 422 of the second stacked structure 42 includes a fourth sub-layer 422a and a fifth sub-layer 422b stacked in sequence, the material of the first sub-layer 412a, the material of the third sub-layer 412c, the material of the fourth sub-layer 422a, and the material of the quantum barrier 442 of the fourth stacked structure 44 all adopt undoped gallium nitride, and the material of the second sub-layer 412b, the material of the fifth sub-layer 422b, and the material of the quantum barrier 432 of the third stacked structure 43 all adopt silicon-doped gallium nitride. The average doping concentration of silicon in the quantum barrier 412 of the first stacked structure 41 is greater than the average doping concentration of silicon in the quantum barrier 422 of the second stacked structure 42, and the average doping concentration of silicon in the quantum barrier 422 of the second stacked structure 42 is greater than the doping concentration of silicon in the third stacked structure 43.
In the embodiment of the invention, the laminated structure formed by alternately laminating the quantum well and the quantum barrier is divided into four parts, namely the first laminated structure, the second laminated structure, the third laminated structure and the fourth laminated structure, so that the change of the silicon doping concentration in the quantum barrier is realized. The doping concentration of silicon in the quantum barrier of the first laminated structure is highest, and more impurities enable electrons to be easily scattered by the impurities during conduction, multiple scattered waves are mutually interfered, the Anderson localization effect is enhanced, a certain blocking effect can be achieved on the electrons, the movement rate of the electrons is reduced, the transverse expansion of current is facilitated, and the uniform distribution of the electrons is promoted. And the doping concentration of silicon in the quantum barrier of the grown second laminated structure is reduced but still higher, and on the basis of the stress accumulated by the first laminated structure, the growth mode of the crystal is changed, the line defects in the crystal are reduced, so that the quantum well is subjected to spiral growth, a high-density nano island-shaped structure is formed, the light-emitting characteristic is improved, and the band gap fluctuation is inhibited. And then the doping concentration of silicon in the quantum barrier of the grown third laminated structure is lower, so that a buffer effect is achieved between the highly silicon-doped laminated structure and the undoped laminated structure, a certain blocking effect is achieved on electrons, and the phenomenon that the migration rate of the electrons is too high can be avoided. And no silicon is doped in the quantum barrier of the finally grown fourth laminated structure, so that a piezoelectric field caused by stress generated by lattice mismatch can be shielded, the quantum confinement Stark effect is relieved, and the radiation recombination efficiency of electrons and holes is improved.
The first laminated structure is composed of three sublayers, the second laminated structure is composed of two sublayers, and the third laminated structure and the fourth laminated structure are both single-layers, so that the thickness of the quantum barrier can be reduced from the N-type semiconductor layer to the P-type semiconductor layer. Because electrons are injected into the active layer from the N-type semiconductor layer, the quantity of electrons in the quantum barrier close to the N-type semiconductor layer is large, and the migration rate of the electrons is high, the quantum barrier close to the N-type semiconductor layer is thick, the restriction effect on the migration of the electrons is high, the phenomenon that the migration speed of the electrons is too high can be effectively avoided, and the electrons are favorably restricted in a quantum well. And because the quantity of electrons in the quantum barrier close to the P-type semiconductor layer is less and the migration rate of the electrons is slower, the quantum barrier close to the P-type semiconductor layer is thinner, the migration of the electrons is basically not limited, the migration of the electrons is easier, the recombination luminescence in the quantum well with more electron injection holes is facilitated, and meanwhile, the quantum well of the P-type semiconductor layer is considered as a main luminescent well, the quantity of consumed electrons is more, and the overflow of the electrons is not caused.
On the whole, in the direction from the N-type semiconductor layer to the P-type semiconductor layer, the doping concentration of silicon in the quantum barrier is gradually reduced, meanwhile, the thickness of the quantum barrier is gradually reduced, the two are matched with each other, the part close to the N-type semiconductor layer can effectively improve the line defects in the crystal, the current expansion is realized, meanwhile, the part close to the P-type semiconductor layer has better lattice quality, and finally, the radiation recombination efficiency of electrons and holes is improved.
Alternatively, the number of quantum barriers 412 of the first stacked structure 41 may be greater than the number of quantum barriers 422 of the second stacked structure 42, the number of quantum barriers 422 of the second stacked structure 42 may be greater than the number of quantum barriers 432 of the third stacked structure 43, and the number of quantum barriers 432 of the third stacked structure 43 may be greater than the number of quantum barriers 442 of the fourth stacked structure 44. The number of the quantum barriers with high silicon doping is large, so that the line defects in the crystal can be effectively improved, and the current expansion is realized; the quantum barriers with low or no silicon doping are fewer in number, and can cover the periphery of the main light-emitting well, so that the crystal quality is improved, and the radiation recombination efficiency of electrons and holes is improved finally.
Further, a difference between the number of quantum barriers 412 of the first stacked structure 41 and the number of quantum barriers 422 of the second stacked structure 42, a difference between the number of quantum barriers 422 of the second stacked structure 42 and the number of quantum barriers 432 of the third stacked structure 43, and a difference between the number of quantum barriers 432 of the third stacked structure 43 and the number of quantum barriers 442 of the fourth stacked structure 44 may be equal. The difference of the quantum barriers of two adjacent laminated structures is the same, the number of the quantum barriers of the laminated structures can be gradually changed, and adverse effects on the lattice structure caused by too large change are avoided.
Illustratively, the difference between the number of quantum barriers 432 of the third stacked structure 43 and the number of quantum barriers 442 of the fourth stacked structure 44 may be 1 to 2. The number difference of the quantum barriers is limited within 1-2, the variation amplitude is small, and the integral lattice structure is favorably maintained.
For example, the number of the quantum barriers 442 of the fourth stacked structure 44 may be 1 to 2, the number of the quantum barriers 432 of the third stacked structure 43 may be 2 to 3, the number of the quantum barriers 422 of the second stacked structure 42 may be 3 to 4, and the number of the quantum barriers 412 of the first stacked structure 41 may be 4 to 5, which is advantageous in terms of implementation.
Alternatively, the ratio of the average doping concentration of silicon in the quantum barrier 412 of the first stacked structure 41 to the average doping concentration of silicon in the quantum barrier 422 of the second stacked structure 42, and the ratio of the average doping concentration of silicon in the quantum barrier 422 of the second stacked structure 42 to the doping concentration of silicon in the quantum barrier 432 of the third stacked structure 43 may be equal. The doping concentration ratio of silicon in the quantum barriers of the two adjacent laminated structures is the same, the doping concentration of silicon in the quantum barriers of the laminated structures can be gradually changed, and the adverse effect on the lattice structure caused by too large change is avoided.
Further, the average doping concentration of silicon in the quantum barrier 412 of the first stacked structure 41 may be 1.5 to 3 times the average doping concentration of silicon in the quantum barrier 422 of the second stacked structure 42, and the average doping concentration of silicon in the quantum barrier of the second stacked structure 42 may be 1.5 to 3 times the doping concentration of silicon in the quantum barrier 432 of the third stacked structure 43. The doping concentration ratio of silicon is limited to 1.5-3 times, so that the change of the doping concentration of silicon can be utilized, the crystal quality of an epitaxial wafer and the working voltage of an LED (light-emitting diode) can be considered, and the adverse effect on the lattice structure caused by too large change can be avoided.
Exemplarily, the doping concentration of silicon in the quantum barrier 432 of the third stacked structure 43 may be 1 × 1017/cm3～5*1017/cm3E.g. 3 x 1017/cm3(ii) a The average doping concentration of silicon in the quantum barrier 422 of the second stacked structure 42 may be 6 x 1017/cm3～1*1018/cm3E.g. 8 x 1017/cm3(ii) a The average doping concentration of silicon in the quantum barrier 412 of the first stacked structure 41 may be 1 × 1018/cm3～5*1018/cm3E.g. 3 x 1018/cm3And the overall realization effect is good.
Optionally, the thickness of the first sub-layer 412a, the thickness of the second sub-layer 412b, the thickness of the third sub-layer 412c, the thickness of the fourth sub-layer 422a, the thickness of the fifth sub-layer 422b, the thickness of the quantum barrier 432 of the third stacked structure 43, and the thickness of the quantum barrier 442 of the fourth stacked structure 44 may be equal, which is convenient to implement and has a better effect.
Illustratively, the thickness of the first sub-layer 412a, the thickness of the second sub-layer 412b, the thickness of the third sub-layer 412c, the thickness of the fourth sub-layer 422a, the thickness of the fifth sub-layer 422b, the thickness of the quantum barrier 432 of the third stacked structure 43, and the thickness of the quantum barrier 442 of the fourth stacked structure 44 may each be 6nm to 12nm, such as 9 nm.
Alternatively, the material of the substrate 1 may be sapphire (alumina is a main material), for example, with a crystal orientation of [0001 ]]The sapphire of (4). The buffer layer 2 may be made of undoped gallium nitride or aluminum nitride. The material of the N-type semiconductor layer 3 may be N-type doped (e.g., silicon) gallium nitride. The quantum well material may be indium gallium nitride (InGaN), such as InxGa1-xN, 0 < x < 1. The P-type semiconductor layer 5 may be made of P-type doped (e.g., mg) gan.
Further, the thickness of the buffer layer 2 may be 15nm to 30nm, preferably 25 nm. The thickness of the N-type semiconductor layer 3 may be 2 to 3 μm, preferably 2.5 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer 3 may be 1018cm-3～1019cm-3Preferably 5 x 1018cm-3. The thickness of the quantum well can be 1.5 nm-3.5 nm, preferably 2.5 nm; the thickness of the active layer 4 may be 130nm to 160nm, preferably 145 nm. The thickness of the P-type semiconductor layer 5 may be 50nm to 80nm, preferably 65 nm; p-type semiconductorThe doping concentration of the P-type dopant in layer 6 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an undoped gallium nitride layer 6, where the undoped gallium nitride layer 6 is disposed between the buffer layer 2 and the N-type semiconductor layer 3 to relieve stress and defects caused by lattice mismatch between the substrate material and the gallium nitride, and provide a growth surface with good crystal quality for the epitaxial wafer main body structure.
In a specific implementation, buffer layer 2 is a thin layer of gallium nitride that is first grown at low temperature on a patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer 6 in this embodiment.
Further, the thickness of the undoped gallium nitride layer 6 may be 2 μm to 3.5 μm, preferably 2.75 μm.
Optionally, the light emitting diode epitaxial wafer may further include a stress release layer 7, where the stress release layer 7 is disposed between the N-type semiconductor layer 3 and the active layer 4 to release stress generated by lattice mismatch between sapphire and gallium nitride, so as to improve crystal quality of the active layer, facilitate radiation recombination of electrons and holes in the active layer for light emission, improve internal quantum efficiency of the LED, and further improve light emission efficiency of the LED.
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an electron blocking layer 81, and the electron blocking layer 81 is disposed between the active layer 4 and the P-type semiconductor layer 5 to prevent electrons from jumping into the P-type semiconductor layer to combine with holes in a non-radiative manner, thereby reducing the light emitting efficiency of the LED.
Specifically, the material of the electron blocking layer 81The material can be P-type doped aluminum gallium nitride (AlGaN), such as AlyGa1-yN，0.15＜y＜0.25。
Further, the thickness of the electron blocking layer 81 may be 30nm to 50nm, preferably 40 nm.
Preferably, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a low temperature P-type layer 82, and the low temperature P-type layer 82 is disposed between the active layer 4 and the electron blocking layer 81, so as to prevent indium atoms in the active layer from being precipitated due to a high growth temperature of the electron blocking layer, which affects the light emitting efficiency of the light emitting diode.
Specifically, the material of the low-temperature P-type layer 82 may be the same as that of the P-type semiconductor layer 5. In the present embodiment, the material of the low temperature P-type layer 82 may be P-type doped gan.
Further, the thickness of the low-temperature P-type layer 82 may be 10nm to 50nm, preferably 30 nm; the doping concentration of the P-type dopant in the low temperature P-type layer 82 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a contact layer 9, and the contact layer 9 is disposed on the P-type semiconductor layer 5 to form an ohmic contact with an electrode or a transparent conductive film formed in a chip manufacturing process.
Specifically, the contact layer 9 may be made of P-type doped indium gallium nitride or gallium nitride.
Further, the thickness of the contact layer 9 may be 5nm to 300nm, preferably 100 nm; the doping concentration of the P-type dopant in the contact layer 9 may be 1021/cm3～1022/cm3Preferably 5 x 1021/cm3。
The embodiment of the invention provides a method for growing a light-emitting diode epitaxial wafer, which is suitable for growing the light-emitting diode epitaxial wafer shown in figure 1. Fig. 5 is a flowchart of a method for growing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. Referring to fig. 5, the growing method includes:
step 201: a substrate is provided.
Optionally, the step 201 may include:
the substrate is annealed at a temperature of 1000 to 1100 deg.C (preferably 1050 deg.C) and a pressure of 200to 500torr (preferably 350torr) in a hydrogen atmosphere for 5 to 6 minutes (preferably 5.5 minutes).
The surface of the substrate is cleaned through the steps, impurities are prevented from being doped into the epitaxial wafer, and the growth quality of the epitaxial wafer is improved.
Step 202: a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
In this embodiment, the active layer includes a first stacked structure, a second stacked structure, a third stacked structure and a fourth stacked structure that are sequentially stacked, where the first stacked structure, the second stacked structure, the third stacked structure and the fourth stacked structure each include at least one quantum well and at least one quantum barrier, and the quantum wells and the quantum barriers are alternately stacked; the quantum barrier of the first laminated structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated, the quantum barrier of the second laminated structure comprises a fourth sublayer and a fifth sublayer which are sequentially laminated, undoped gallium nitride is adopted as the material of the first sublayer, the material of the third sublayer, the material of the fourth sublayer and the material of the quantum barrier of the fourth laminated structure, and silicon-doped gallium nitride is adopted as the material of the second sublayer, the material of the fifth sublayer and the material of the quantum barrier of the third laminated structure; the average doping concentration of silicon in the quantum barrier of the first stacked structure is greater than the average doping concentration of silicon in the quantum barrier of the second stacked structure, and the average doping concentration of silicon in the quantum barrier of the second stacked structure is greater than the doping concentration of silicon in the quantum barrier of the third stacked structure.
Optionally, this step 202 may include:
firstly, controlling the temperature to be 530-560 ℃ (preferably 545 ℃) and the pressure to be 200-500 torr (preferably 350torr), and growing a buffer layer on a substrate;
secondly, controlling the temperature to be 1000-1100 ℃ (preferably 1050 ℃), and the pressure to be 100-500 torr (preferably 300torr), and growing an N-type semiconductor layer on the buffer layer;
thirdly, growing an active layer on the N-type semiconductor layer; wherein, the growth temperature of the quantum well is 760 ℃ to 780 ℃ (preferably 770 ℃), and the pressure is 200 torr; the growth temperature of the quantum barrier is 860 ℃ -890 ℃ (preferably 875 ℃), and the pressure is 200 torr;
and fourthly, controlling the temperature to be 940-980 ℃ (preferably 960 ℃) and the pressure to be 200-600 torr (preferably 400torr), and growing the P-type semiconductor layer on the active layer.
Optionally, before the second step, the growing method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
an undoped gallium nitride layer is grown on the buffer layer at a temperature of 1000 ℃ to 1100 ℃ (preferably 1050 ℃) and a pressure of 200torr to 600torr (preferably 400 torr).
Optionally, before the third step, the growing method may further include:
and growing a stress release layer on the N-type semiconductor layer.
Accordingly, an active layer is grown on the stress relieving layer.
Optionally, before the fourth step, the growing method may further include:
an electron blocking layer is grown on the active layer.
Accordingly, a P-type semiconductor layer is grown on the electron blocking layer.
Specifically, growing an electron blocking layer on the active layer may include:
the electron blocking layer is grown on the active layer at a controlled temperature of 930 deg.C to 970 deg.C (preferably 950 deg.C) and a pressure of 100 torr.
Preferably, before growing the electron blocking layer on the active layer, the growth method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 600 ℃ to 850 ℃ (preferably 750 ℃) and the pressure is controlled to be 100torr to 600torr (preferably 300torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after the fourth step, the growing method may further include:
and growing a contact layer on the P-type semiconductor layer.
Specifically, growing a contact layer on the P-type semiconductor layer may include:
the contact layer is grown on the P-type semiconductor layer at a temperature of 850 to 1050 deg.C (preferably 950 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
After the completion of the epitaxial growth, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.
The control of the temperature and the pressure both refer to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically refer to the reaction chamber of a Metal-organic Chemical Vapor Deposition (MOCVD) device, such as Veeco K465i MOCVD or Veeco C4 MOCVD. During implementation, hydrogen or nitrogen or a mixed gas of hydrogen and nitrogen is used as a carrier gas, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as a silicon source, and magnesium diclocide is used as a magnesium source.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. A light emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate; the active layer comprises a first laminated structure, a second laminated structure, a third laminated structure and a fourth laminated structure which are sequentially laminated, wherein the first laminated structure, the second laminated structure, the third laminated structure and the fourth laminated structure respectively comprise at least one quantum well and at least one quantum barrier, and the quantum wells and the quantum barriers are alternately laminated; the quantum barrier of the first laminated structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated, the quantum barrier of the second laminated structure comprises a fourth sublayer and a fifth sublayer which are sequentially laminated, undoped gallium nitride is adopted as the material of the first sublayer, the material of the third sublayer, the material of the fourth sublayer and the material of the quantum barrier of the fourth laminated structure, and silicon-doped gallium nitride is adopted as the material of the second sublayer, the material of the fifth sublayer and the material of the quantum barrier of the third laminated structure; the average doping concentration of silicon in the quantum barrier of the first laminated structure is greater than that of silicon in the quantum barrier of the second laminated structure, and the average doping concentration of silicon in the quantum barrier of the second laminated structure is greater than that of silicon in the quantum barrier of the third laminated structure; the thickness of the first sublayer, the thickness of the second sublayer, the thickness of the third sublayer, the thickness of the fourth sublayer, the thickness of the fifth sublayer, the thickness of the quantum barrier of the third stacked structure and the thickness of the quantum barrier of the fourth stacked structure are equal.
2. The light emitting diode epitaxial wafer of claim 1, wherein the number of quantum barriers of the first stacked structure is greater than the number of quantum barriers of the second stacked structure, the number of quantum barriers of the second stacked structure is greater than the number of quantum barriers of the third stacked structure, and the number of quantum barriers of the third stacked structure is greater than the number of quantum barriers of the fourth stacked structure.
3. The light-emitting diode epitaxial wafer according to claim 2, wherein a difference between the number of quantum barriers of the first stacked structure and the number of quantum barriers of the second stacked structure, a difference between the number of quantum barriers of the second stacked structure and the number of quantum barriers of the third stacked structure, and a difference between the number of quantum barriers of the third stacked structure and the number of quantum barriers of the fourth stacked structure are equal.
4. The light emitting diode epitaxial wafer of claim 3, wherein the difference between the number of quantum barriers of the third stacked structure and the number of quantum barriers of the fourth stacked structure is 1 to 2.
5. The light-emitting diode epitaxial wafer according to claim 4, wherein the number of the quantum barriers of the fourth stacked structure is 1 to 2.
6. The light emitting diode epitaxial wafer as claimed in any one of claims 1 to 4, wherein the ratio of the average doping concentration of silicon in the quantum barrier of the first stacked structure to the average doping concentration of silicon in the quantum barrier of the second stacked structure, and the ratio of the average doping concentration of silicon in the quantum barrier of the second stacked structure to the doping concentration of silicon in the quantum barrier of the third stacked structure are equal.
7. The light-emitting diode epitaxial wafer as claimed in claim 6, wherein the average doping concentration of silicon in the quantum barrier of the first stacked structure is 1.5 times to 3 times that of silicon in the quantum barrier of the second stacked structure, and the average doping concentration of silicon in the quantum barrier of the second stacked structure is 1.5 times to 3 times that of silicon in the quantum barrier of the third stacked structure.
8. The light emitting diode epitaxial wafer of claim 7, wherein the doping concentration of silicon in the quantum barrier of the third stacked structure is 1 x 1017/cm3～5*1017/cm3。
9. A growth method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
the active layer comprises a first laminated structure, a second laminated structure, a third laminated structure and a fourth laminated structure which are sequentially laminated, wherein the first laminated structure, the second laminated structure, the third laminated structure and the fourth laminated structure respectively comprise at least one quantum well and at least one quantum barrier, and the quantum wells and the quantum barriers are alternately laminated; the quantum barrier of the first laminated structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated, the quantum barrier of the second laminated structure comprises a fourth sublayer and a fifth sublayer which are sequentially laminated, undoped gallium nitride is adopted as the material of the first sublayer, the material of the third sublayer, the material of the fourth sublayer and the material of the quantum barrier of the fourth laminated structure, and silicon-doped gallium nitride is adopted as the material of the second sublayer, the material of the fifth sublayer and the material of the quantum barrier of the third laminated structure; the average doping concentration of silicon in the quantum barrier of the first laminated structure is greater than that of silicon in the quantum barrier of the second laminated structure, and the average doping concentration of silicon in the quantum barrier of the second laminated structure is greater than that of silicon in the quantum barrier of the third laminated structure; the thickness of the first sublayer, the thickness of the second sublayer, the thickness of the third sublayer, the thickness of the fourth sublayer, the thickness of the fifth sublayer, the thickness of the quantum barrier of the third stacked structure and the thickness of the quantum barrier of the fourth stacked structure are equal.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990479A (en) * | 2015-02-11 | 2016-10-05 | 晶能光电（常州）有限公司 | GaN-based light emitting diode epitaxial structure and manufacturing method thereof |
| CN106887493A (en) * | 2017-02-15 | 2017-06-23 | 华灿光电（浙江）有限公司 | A kind of epitaxial wafer of light emitting diode and preparation method thereof |
| CN107293619A (en) * | 2017-06-30 | 2017-10-24 | 华灿光电（浙江）有限公司 | A kind of LED epitaxial slice and its manufacture method |
| CN108598226A (en) * | 2018-02-28 | 2018-09-28 | 华灿光电（浙江）有限公司 | A kind of LED epitaxial slice and preparation method thereof |
-
2019
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990479A (en) * | 2015-02-11 | 2016-10-05 | 晶能光电（常州）有限公司 | GaN-based light emitting diode epitaxial structure and manufacturing method thereof |
| CN106887493A (en) * | 2017-02-15 | 2017-06-23 | 华灿光电（浙江）有限公司 | A kind of epitaxial wafer of light emitting diode and preparation method thereof |
| CN107293619A (en) * | 2017-06-30 | 2017-10-24 | 华灿光电（浙江）有限公司 | A kind of LED epitaxial slice and its manufacture method |
| CN108598226A (en) * | 2018-02-28 | 2018-09-28 | 华灿光电（浙江）有限公司 | A kind of LED epitaxial slice and preparation method thereof |
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