CN109755317A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109755317A
CN109755317A CN201810153865.XA CN201810153865A CN109755317A CN 109755317 A CN109755317 A CN 109755317A CN 201810153865 A CN201810153865 A CN 201810153865A CN 109755317 A CN109755317 A CN 109755317A
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China
Prior art keywords
fin
epitaxial structure
dielectric layer
layer
epitaxial
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Pending
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CN201810153865.XA
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English (en)
Inventor
朱峯庆
李威养
杨丰诚
陈燕铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109755317A publication Critical patent/CN109755317A/zh
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    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

本公开实施例提供半导体装置。半导体装置包括基板，其具有第一装置区与第二装置区；第一鳍状物，位于第一装置区中的基板上；第二鳍状物，位于第二装置区中的基板上；第一外延结构，位于第一鳍状物的源极/漏极区中的第一鳍状物上；第二外延结构，位于第二鳍状物的源极/漏极区中的第二鳍状物上；以及介电层，位于第一外延结构与第二外延结构上。第一外延结构掺杂有第一导电型态的第一掺质，第二外延结构掺杂有第二导电型态的第二掺质，且第二导电型态与第一导电型态不同。介电层掺杂有第一掺质。

Description

半导体装置
技术领域
本公开实施例涉及半导体装置与其制作方法，更特别涉及鳍状场效晶体管结构。
背景技术
当半导体产业朝向纳米技术的工艺节点迈进，以达更高的装置密度、更高的效能、与更低的成本时，在三维设计如鳍状场效晶体管(FinFET)面临工艺与设计的问题。一般的鳍状场效晶体管具有自基板延伸的薄的垂直鳍状物，其形成方法可为蚀刻移除基板的部分硅层，或者生长外延层于基板上。鳍状场效晶体管的沟道形成于此垂直鳍状物中。栅极位于鳍状物上，比如围绕鳍状物。
制作鳍状场效晶体管具有其挑战性。举例来说，需减少n型鳍状场效晶体管中的鳍状物与p型鳍状场效晶体管中的鳍状物之间的距离，以增加装置密度。然而当鳍状物之间的距离缩小到一定程度时，如何清楚地切割栅极以分隔p型场效晶体管区与n型场效晶体管区中的鳍状物上的虚置栅极，同时不损伤外延的源极/漏极结构变得相当困难。在一些例子中，在切割栅极时将实质上移除外延的源极/漏极结构，导致装置失效。
如此一来，虽然现有的鳍状场效晶体管装置一般已适用于其发展目的，但仍无法满足每一方面的需求。
发明内容
本公开一实施例提供的半导体装置，包括：基板，具有第一装置区与第二装置区；第一鳍状物，位于第一装置区中的基板上，其中第一鳍状物包括沟道区以及源极/漏极区；第二鳍状物，位于第二装置区中的基板上，其中第二鳍状物包括沟道区以及源极/漏极区；第一外延结构，位于源极/漏极区中的第一鳍状物上，其中第一外延结构掺杂有第一导电型态的第一掺质；第二外延结构，位于源极/漏极区中的第二鳍状物上，其中第二外延结构掺杂有第二导电型态的第二掺质，且第二导电型态与第一导电型态不同；以及介电层，位于第一外延结构与第二外延结构上，其中介电层掺杂有第一掺质。
附图说明
图1是本公开多种实施例中，半导体装置的俯视图。
图2是本公开多种实施例中，半导体装置沿着图1中剖面A-A’定义的剖面的剖视图。
图3A与图3B是本公开一些实施例中，制作半导体装置的方法其流程图。
图4是本公开一些实施例中，制作半导体装置的另一方法其流程图。
图5至图16是本公开多种实施例中，半导体装置于图3A、图3B、与图4所示的方法中多种阶段的剖视图。
附图标记说明：
A-A’ 剖面
P 距离
100 半导体装置
101 第一装置区
102 第二装置区
110 基板
120N、120P 鳍状物
130 浅沟槽隔离区
140 虚置栅极结构
140N、140P 虚置栅极部分
142 栅极堆叠
142N、142P 栅极部分
145 栅极间隔物
150N、150P 外延结构
160 栅极隔离结构
162 沟槽
170N、170P 源极/漏极接点
180 介电层
181 朝上表面
182 朝下表面
185 p型掺质离子
190 层间介电层
200、300 方法
202、204、206、208、210、212、214、216、218、220、222、302、304、306、308、310、312步骤
具体实施方式
应理解下述内容提供的许多不同实施例或实例可实施本公开的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本公开。举例来说，单元尺寸并不限于本公开的范围或数值，而可依工艺条件和/或装置所需的性质而定。此外，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本公开的多种实例可采用重复标号和/或符号使说明简化及明确，但这些重复不代表多种实施例和/或设置中相同标号的元件之间具有相同的对应关系。
此外，空间性的相对用语如“较下方”、“较上方”、“水平”、“垂直”、“上方”、“之上”、“下方”、“之下”、“上”、“下”、“顶”、“底”或类似用语如“水平地”、“下方的”、或“上方的”等等，可用于简化说明某一结构与另一结构在图示中的相对关系。空间性的相对用语可延伸至不同方向且包含结构的装置。
本公开实施例关于半导体装置与其制作方法。特别的是，一些实施例关于但不限于鳍状场效晶体管结构。举例来说，鳍状场效晶体管结构可为互补式金属氧化物半导体装置，其包含p型金属氧化物半导体鳍状场效晶体管装置与n型金属氧化物半导体鳍状场效晶体管装置。下述内容将搭配一或多个鳍状场效晶体管的例子，以说明本公开的多种实施例。然而应理解的是，本公开并不应局限于特定种类的装置，除非明载于权利要求书中。
合适的半导体装置100将搭配图1与图2说明。在这方面，图1是本公开多种实施例的半导体装置100其俯视图，而图2是多种实施例的半导体装置100其剖视图。半导体装置100包含基板110，其上形成有其他结构。在多种例子中，基板110包含半导体元素(单一元素)如结晶结构的硅或锗，半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟，半导体合金如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、和/或磷砷化镓铟，非半导体材料如钠钙玻璃、熔融氧化硅、熔融石英、和/或氟化钙，和/或上述的组合。基板110可具有均匀组成，或包含多种层状物。上述层状物可具有类似或不同的组成。在多种实施例中，一些基板的层状物可具有不均匀的组成以诱发装置应力以调整装置效能。层状基板的例子包含绝缘层上硅的基板110。在这些例子中，基板110的层状物可包含绝缘物如半导体的氧化物、半导体的氮化物、半导体的氮氧化物、半导体的碳化物、和/或其他合适的绝缘材料。
鳍状物(如鳍状物120P和/或鳍状物120N)自基板延伸。鳍状物的形成方法可为蚀刻基板材料、外延生长材料于基板110上、或上述的组合。在一些实施例中，鳍状物120P与120N的形成方法可为外延生长半导体材料如硅、锗、硅锗、或类似物于基板110上。在这些实施例中，将锗或碳导入硅晶格中，可施加应力至硅晶格以改善装置效能。在一些实施例中，外延层的组成为外延生长硅与锗，其形成技术可为采用化学气相沉积或低压化学气相沉积进行的外延沉积。通过在化学气相沉积的外延沉积时，控制气体反应物的输送以及其他工艺参数，可沿着外延层的高度调整硅与锗的浓度。在鳍状物120的组成为外延层的实施例中，先形成外延层于基板上，接着图案化外延层如后续说明。此外，一些实施例中位于基板110上的外延层亦可掺杂p型掺质(如硼、铝、或镓)或n型掺质(如锑、砷、或磷)。在这些实施方式中，鳍状物120P或120N可视情况进行对应掺杂。
在一些实施例中，可进行光刻图案化与蚀刻，以自外延层形成鳍状物120P与120N。举例来说，以光刻技术形成图案化的光致抗蚀剂层于外延层上，接着施加蚀刻工艺如各向异性蚀刻于外延层上，以形成一或多个鳍状物120P与120N。在另一例中，可采用硬掩模。在此例中，硬掩模的形成方法可为沉积硬掩模材料于外延硅锗层上。接着沉积光致抗蚀剂层于硬掩模上。在进行光刻工艺后，硬掩模上的图案化光致抗蚀剂层可作为蚀刻及图案化硬掩模时的蚀刻掩模。之后可采用硬掩模作为蚀刻掩模，并对外延层进行蚀刻工艺如各向异性蚀刻，以形成一或多个鳍状物120P与120N。
为隔离相邻的鳍状物120P与120N，可沉积介电材料(比如热生长的氧化硅与化学气相沉积的氧化硅)以填入相邻的鳍状物120P与120N之间的沟槽。接着以化学机械研磨平坦化介电层，并回蚀刻介电层以露出部分的鳍状物120P与120N。回蚀刻后的介电层仍覆盖其他部分的鳍状物120P与120N。相邻鳍状物之间的介电层可称作浅沟槽隔离区。举例来说，第一装置区101中的鳍状物120P与第二装置区102中的鳍状物120N之间，隔有浅沟槽隔离区130。
半导体装置100包含栅极堆叠(或金属栅极堆叠)142于鳍状物120P与120N的沟道区上。值得注意的是，栅极堆叠142不存在于剖面A-A’上。但为了说明，将以虚线标示栅极堆叠142在剖面A-A’上的投影。在一些实施例中，如图1与图2所示，栅极隔离结构160将栅极堆叠142分隔成栅极部分142P与142N。在一些例子中，金属的栅极堆叠142的形成方法包括沉积含有多晶硅或其他合适材料的虚置栅极层，以及图案化虚置栅极层。栅极硬掩模层可形成于虚置栅极材料层上，其可在形成虚置栅极时作为蚀刻掩模。栅极硬掩模层可包含任何合适材料，比如氧化硅、氮化硅、碳化硅、氮氧化硅、其他合适材料、和/或上述的组合。在一些实施例中，形成虚置栅极的图案化工艺包括以光刻工艺形成图案化光致抗蚀剂层；采用图案化光致抗蚀剂层作为蚀刻掩模，蚀刻硬掩模层；以及采用图案化的硬掩模层作为蚀刻掩模，蚀刻栅极材料层以形成虚置栅极。接着进行栅极置换工艺，以将虚置栅极置换为栅极堆叠142。栅极堆叠142至少包含与鳍状物120P与120N相邻的栅极介电层，以及栅极介电层上的金属层。栅极介电层的组成可为高介电常数的介电物如氧化铪、氧化锆、氧化钽、钛酸钡、氧化钛、氧化铈、氧化镧、氧化镧铝、钛酸铅、钛酸锶、锆酸铅、氧化钨、氧化钇、氧化铋硅、钛酸钡锶、氧化铅锰铌、氧化铅锆钛、氧化铅锌铌、氧化铅钪钽、钛酸铅镧、钽酸锶铋、钛酸铋、或钛酸钡锆。栅极堆叠142可包含一或多个功函数金属层，其组成可为氮化钛、氮化钽、氮碳化钽、氮碳化钛、碳化钛、钼、或钨。半导体装置100亦可包含栅极间隔物145于栅极堆叠142的侧壁上。
半导体装置100亦包含外延结构150P与150N于沟道区中的栅极堆叠142其两侧上的源极/漏极区中的鳍状物120P与120N上。外延结构150P位于第一装置区101中，而外延结构150N位于第二装置区102中。在一些实施例中，源极/漏极结构150P与150N的形成方法为一或多道外延工艺，其生长结晶态的硅结构、硅锗结构、和/或其他合适结构于源极/漏极区中的鳍状物120P与120N上。在其他实施例中，在外延生长之前进行蚀刻工艺，使鳍状物120P与120N的源极/漏极区凹陷。合适的外延工艺包括化学气相沉积技术(如气相外延和/或超高真空化学气相沉积)、分子束外延、和/或其他合适工艺。
在外延生长工艺时，可导入掺杂种类如p型掺质(如硼或BF2)、n型掺质(如磷或砷)、和/或其他合适的掺质(包含上述的组合)，以原位掺杂外延结构150P与150N。若未原位掺杂外延结构150P与150N，则可进行注入工艺(如接面注入工艺)以将对应的掺质导入外延结构150P与150N中。在例示性的实施例中，第一装置区中的外延结构150P包含硼化硅锗，而第二装置区中的外延结构150N包含磷化硅。之后可进行一或多道退火工艺，以活化外延结构150P与150N。合适的退火工艺可包含快速热退火、激光退火工艺、其他合适的退火技术、或上述的组合。
在图1所示的实施例中，半导体装置100包含介电层180形成于外延结构150P与150N上，以保护其免于被后续工艺损伤。在一些实施例中，介电层180亦形成于浅沟槽隔离区130上。介电层180有时称作接点蚀刻停止层，如图1所示。介电层180的材料，以及栅极堆叠142的材料(与之后置换为栅极堆叠142的虚置栅极的材料)可具有不同的蚀刻选择性。在一些实施例中，介电层180的组成可为氮化硅或其他合适材料。在本公开一些实施例中，介电层180掺杂有掺质。在一些实施方式中，形成于外延结构150P与150N上的介电层180可掺杂p型掺质。在此例中，介电层可掺杂硼。综上所述，一实施例中的介电层180含有氮化硅与硼(p型掺质)，其形成于含有硅与磷(n型掺质)的外延结构150N上。
半导体装置100亦包含层间介电层190沉积于基板110上。在沉积层间介电层190之后，可进行化学机械研磨以平坦化层间介电层190。
半导体装置100亦包含栅极隔离结构160，其将栅极堆叠142分隔为第一装置区101中的栅极部分142P及第二装置区102中的栅极部分142N。栅极隔离结构160的组成可为介电材料，其填入电性隔离相邻的栅极堆叠142的沟槽中。栅极切割工艺可形成沟槽以追随隔离结构的形状与轮廓。沟槽的目的在于将其他连续的金属栅极结构分隔成彼此绝缘的部分。栅极隔离结构160中的介电材料可为氮化硅或其他合适材料，其可提供绝缘性且不污染栅极堆叠142。
栅极隔离结构160沿着z方向延伸过栅极堆叠142的高度，使第一装置区101中的栅极部分142P以及第二装置区102中的栅极部分142N绝缘。在一些例子中，栅极隔离结构160并未如图2所示的止于浅沟槽隔离区130的上表面，而是延伸至浅沟槽隔离区130中。当半导体装置100越来越小，外延结构150P与外延结构150N之间的距离P也越来越小。如此一来，清楚的切割栅极而不损伤外延结构150P与150N变得越来越难。图2显示距离P小，且栅极隔离结构160接触介电层180的例子。本公开一些实施例的优点之一为掺杂硼的介电层180，可阻挡栅极切割工艺中的蚀刻，以避免损伤外延结构150N与150P。若不采用掺杂硼的介电层180，栅极切割工艺可能蚀刻移除大量的外延结构150N或150P并留下孔洞。损伤的外延结构150P与150N可能弱化半导体装置100的正常功能，造成其失效并降低良率。由于外延结构中的不同掺质可能影响其对蚀刻剂的敏感度，因此对某一导电型态的外延结构(如外延结构150N)而言，外延结构的损伤更普遍。在一些其他实施例中，接点蚀刻停止层可未掺杂。
图3A与图3B是用以形成半导体装置100的方法200其流程图。方法200中的步骤将搭配图5至图13说明如下，且图5至图13为半导体装置100沿着剖面A-A’的剖视图。在方法200之前、之中、与之后可进行额外步骤，且方法的额外实施例可置换、省略、或调换一些下述步骤。
如图3A的步骤202与图5所示，鳍状物120P形成于第一区101中的基板110上，而鳍状物120N形成于第二区102中的基板110上。在一些例子中，第一装置区101为p型场效晶体管区，而第二装置区102为n型场效晶体管区。鳍状物120P与120N的形成方法可为光刻图案化与蚀刻外延层。举例来说，可采用光刻技术形成图案化光致抗蚀剂层于外延层上。接着对外延层进行蚀刻工艺如各向异性蚀刻，以形成一或多个鳍状物120P与120N。在另一例中，采用硬掩模。在此例中，沉积硬掩模材料于外延层上以形成硬掩模。接着沉积光致抗蚀剂层于硬掩模上。在采用光刻进行图案化后，以硬掩模上的图案化光致抗蚀剂层作为蚀刻与图案化硬掩模时的蚀刻掩模。之后采用硬掩模作为蚀刻掩模，对外延层进行蚀刻工艺如各向异性蚀刻，以形成一或多个鳍状物120P与120N。
每一鳍状物120P与120N包含沟道区，以及沟道区两侧的源极/漏极区。图1为半导体装置100的俯视图，其显示沟道区与源极/漏极区。以第二装置区102中的鳍状物120N为例，栅极堆叠142覆盖鳍状物120N的沟道区，且鳍状物120N的源极/漏极区位于栅极堆叠142的两侧。
如方法200(见图3A)的步骤204与图6所示，隔离结构形成于鳍状物120P与鳍状物120N之间。为了隔离相邻的鳍状物120P与120N，可形成介电层(比如热生长的氧化硅或化学气相沉积的氧化硅)以填入相邻的鳍状物120P与120N之间的沟槽。接着以化学机械研磨平坦化介电层，并回蚀刻介电层以露出鳍状物120P与120N的一部分。回蚀刻后的介电层亦覆盖鳍状物120P与120N的其他部分。上述介电层可称作浅沟槽隔离区。在此例中，浅沟槽隔离区为浅沟槽隔离区130。
如方法200(见图3A)的步骤206与图7所示，虚置栅极结构140形成于鳍状物120P的沟道区与鳍状物120N的沟道区上。值得注意的是，虚置栅极结构140不存在于剖面A-A’上。但为了说明，图7将以虚线标示虚置栅极结构140在剖面A-A’上的投影。在一些例子中，虚置栅极结构140的形成方法包括沉积含多晶硅或其他合适材料的虚置栅极层，并图案化虚置栅极层。栅极硬掩模层可形成于虚置栅极材料层上，并作为形成虚置栅极结构140时的蚀刻掩模。栅极硬掩模层可包含任何合适材料，比如氧化硅、氮化硅、碳化硅、氮氧化硅、其他合适材料、或上述的组合。在一些实施例中，用以形成虚置栅极结构140的图案化工艺包含以光刻工艺形成图案化光致抗蚀剂层；以图案化光致抗蚀剂层作为蚀刻掩模，蚀刻硬掩模层；以及采用图案化硬掩模层作为蚀刻掩模，蚀刻栅极材料层以形成虚置栅极结构140。在一些实施例中，与图1所示的栅极间隔物145类似的栅极间隔物，可形成于虚置栅极结构140的侧壁上。
如方法200(见图3A)的步骤208与图8所示，外延结构(或源极/漏极结构)150P形成于鳍状物120P的源极/漏极区上，而外延结构(或源极/漏极结构)150N形成于鳍状物120N的源极/漏极区上。在一些实施例中，外延结构150P与150N的形成方法为一或多道外延工艺，其可生长结晶态的硅结构、硅锗结构、碳化硅结构、和/或其他合适结构于鳍状物120P与120N上。在其他实施例中，可在外延工艺前先进行蚀刻工艺，使源极/漏极区凹陷。合适的外延工艺包括化学气相沉积工艺技术(如气相外延和/或超高真空化学气相沉积)、分子束外延、和/或其他合适工艺。外延工艺可采用气相和/或液相的前驱物，其可与鳍状物120N与120P的组成作用。在一些实施例中，外延结构150P的组成为外延生长的硅锗，而外延结构150N的组成为外延生长的硅。
在外延生长工艺时，可导入掺杂种类如p型掺质(如硼或BF2)、n型掺质(如磷或砷)、和/或其他合适的掺质(包含上述的组合)，以原位掺杂外延结构150P与150N。若未原位掺杂外延结构150P与150N，则可进行注入工艺(如接面注入工艺)以将对应的掺质导入外延结构150P与150N中。在例示性的实施例中，第一装置区为p型场效晶体管区，且外延结构150P掺杂p型掺质。第二装置区为n型场效晶体管区，且外延结构150N掺杂n型掺质。在例示性的实施例中，第一装置区中的外延结构150P其组成为掺杂硼的硅锗，而第二装置区中的外延结构150N其组成为掺杂磷的硅。之后可进行一或多道退火工艺，以活化外延结构150P与150N。合适的退火工艺可包含快速热退火、激光退火工艺、其他合适的退火技术、或上述的组合。
如方法200(见图3A)的步骤210与图9所示，介电层180形成于外延结构150P与外延结构150N上。在一些实施例中，如图9所示，介电层180亦形成于浅沟槽隔离区130上。介电层180有时可称作接点蚀刻停止层。在一些实施例中，介电层180包括介电材料，其具有合适的蚀刻选择性，以用于之后蚀刻虚置栅极140中的多晶硅或栅极堆叠142中的金属的蚀刻工艺。此外，介电层180的介电材料可顺应性地对应外延结构150P与150N的表面轮廓。在一些实施方式中，介电层180的介电材料包括氮化硅、氮氧化硅、或其他合适材料。在一些例子中，介电层180的沉积方法为搭配合适前驱物的原子层沉积或化学气相沉积。在一些实施例中，介电层180的厚度可介于2nm至10nm之间。在一些实施方式中，如图9所示，介电层180形成于外延结构150P与外延结构150N的整个表面上，而外延结构150N与150P的朝上表面181上的介电层180其厚度，可小于外延结构150N与150P的朝下表面182上的介电层180其厚度。
在一些实施例中，如图9所示，可掺杂介电层180以进一步降低其对蚀刻剂的敏感度。在一些例子中，介电层可掺杂硼或镓，且其掺杂方法可为原位(in-situ)掺杂和/或离子注入。在原位掺杂中，在形成介电层180时可提供含硼气体(如硼氢化物或三氯化硼)至工艺腔室中以掺杂介电层180。当p型掺质的掺杂法为注入时，可先形成未掺杂的介电层180于第一装置区101与第二装置区102中的外延结构150P与150N及浅沟槽隔离区130上。接着将p型掺质离子185注入至未掺杂的介电层180。在一些实施方式中，介电层180中的p型掺质的掺杂剂量介于4E20cm-3至1E21cm-3之间。可在分开的步骤或后续步骤中，退火步骤210中的p型掺质使其活化。举例来说，可在形成层间介电层190之后退火并活化p型掺质。
如方法200(见图3B)的步骤212与图10所示，层间介电层190形成于外延结构150N与150P上。在一些实施例中，在沉积层间介电层190后，可进行化学机械研磨工艺平坦化层间介电层190，以提供后续工艺所用的平坦表面。由于层间介电层190挡住附图中的虚置栅极结构140，因此以虚线标示虚置栅极结构140以达说明目的。
如方法200(见图3B)的步骤214与图11所示，各向异性蚀刻虚置栅极结构140以形成沟槽162，其可分隔第一装置区101中虚置栅极结构140的一部分，以及第二装置区102中虚置栅极结构140的另一部分。步骤214中的各向异性蚀刻，有时可称作“栅极切割”。在一些实施例中，采用含氧气体、含氟气体(如四氟化碳、六氟化硫、二氟化碳、氟仿、和/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化硅、四氯化碳、和/或三氯化硼)、含溴气体(如溴化氢和/或溴仿)、含碘气体、其他合适气体和/或等离子体、和/或上述的组合作为蚀刻剂以进行步骤214。步骤214中的各向异性蚀刻可有效移除虚置栅极结构140中的多晶硅，而掺有p型掺质如硼或镓的介电层180可实质上阻挡蚀刻。由于p型掺杂的介电层180可阻挡蚀刻，即使切割栅极的沟槽162与外延结构150P与150N重叠，外延结构150P与150N仍可保持实质上完整。由于虚置栅极结构140中的多晶硅与p型掺杂的介电层180具有蚀刻选择性，步骤214可称作自对准的栅极切割工艺。步骤214与采用未掺杂的介电层180的栅极切割工艺相较，具有较大的工艺容忍度。
如方法200(见图3B)的步骤216与图12所示，介电材料填入沟槽162中以形成栅极隔离结构160。栅极隔离结构160将虚置栅极结构140分隔成第一装置区101中的虚置栅极部分140P以及第二装置区102中的虚置栅极部分140N。栅极隔离结构160中的介电材料可为氮化硅或其他合适的绝缘材料。由于沟槽162的宽度可窄到几十纳米，因此步骤216采用的沉积方法可具有较佳沟槽填充能力。在一些例子中，填入沟槽162的介电材料其沉积方法可采用原子层沉积或等离子体增强原子层沉积。
如方法200(见图3B)的步骤218与图12所示，将虚置栅极结构140置换为栅极堆叠142。在步骤218中，虚置栅极部分140P与140N置换为栅极部分142P与142N。基本上，步骤218移除虚置栅极部分140P与140N，并形成栅极部分142P与142N以取代虚置栅极部分140P与140N。栅极堆叠142(如栅极部分142P与142N)至少包含与鳍状物120P与120N相邻的栅极介电层，以及栅极介电层上的金属层。栅极介电层的组成可为高介电常数介电物如氧化铪、氧化锆、氧化钽、钛酸钡、氧化钛、氧化铈、氧化镧、氧化镧铝、钛酸铅、钛酸锶、锆酸铅、氧化钨、氧化钇、氧化铋硅、钛酸钡锶、氧化铅锰铌、氧化铅锆钛、氧化铅锌铌、氧化铅钪钽、钛酸铅镧、钽酸锶铋、钛酸铋、或钛酸钡锆。栅极堆叠142可包含一或多个功函数金属层，其组成可为氮化钛、氮化钽、氮碳化钽、氮碳化钛、碳化钛、钼、或钨。
如方法200(见图3B)的步骤220与图13所示，源极/漏极接点170P形成于外延结构150P上，而源极/漏极接点170N形成于外延结构150N上。为形成源极/漏极接点170P与170N，可采用高偏压的各向异性蚀刻工艺以蚀穿层间介电层190与介电层(或接点蚀刻停止层)180，以形成开口露出外延结构150P与150N。在一些例子中，用以形成源极/漏极接点开口的蚀刻剂包括含氧气体、含氟气体(如四氟化碳、六氟化硫、二氟化碳、氟仿、和/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化硅、四氯化碳、和/或三氯化硼)、含溴气体(如溴化氢和/或溴仿)、含碘气体、其他合适气体和/或等离子体、和/或上述的组合。在一些实施例中，可采用惰性气体如氩气或氦气加速蚀刻工艺。在一些实施方式中，为减少接点电阻并加大形成源极/漏极接点的工艺容忍度，可刻意使部分的外延结构150P与150N凹陷以形成开口。如图2所示，源极/漏极接点170P与170N不只穿过层间介电层190与接点蚀刻停止层180，但亦延伸至外延结构150P与150N。值得注意的是，由于层间介电层190的存在，因此以虚线标示栅极堆叠142。接着将导电材料填入开口。在一些例子中，在将导电材料填入开口之前，可先形成硅化物于开口中以降低接点电阻。硅化物的形成方法可为使硅与金属如钛、钽、镍、或钴反应。在一些例子中，硅化物的形成方法可为自对准硅化(salicide)工艺。自对准硅化工艺包含沉积前述的金属之一，进行退火使金属与硅之间产生反应，以及移除未反应的金属材料。为避免杂质扩散至导电材料中，可形成阻挡层于开口的侧壁上。阻挡层的组成可为单层的氮化钛或氮化钽，或多层结构如钛/氮化钛(或钽/氮化钽)。在一些例子中，在形成硅化物与阻挡层之后，才将导电材料填入开口。合适的导电材料包含钨、铜、铝、或钴。
如图3B所示，方法200的步骤222可对半导体装置100继续进行后续工艺，以形成本技术领域已知的多种结构与区域。举例来说，后续工艺可形成多种接点/通孔/线路与多层内连线结构(比如金属层与层间介电层)于基板110上，其设置以连接多种结构以形成可包含一或多个鳍状场效晶体管装置的功能电路。在后续例子中，多层内连线可包含垂直内连线如通孔或接点，以及水平内连线如金属线路。多种内连线结构可采用多种导电材料，其包含铜、钨、和/或硅化物。在一例中，可采用镶嵌和/或双镶嵌工艺以形成铜相关的多层内连线结构。
图4显示制作半导体装置100的方法300。方法300包含步骤302、304、306、308、310、与312。方法300中的步骤将搭配图5至图10及图13至图16详述于下，其为沿着剖面A-A’的剖视图。与图2中对虚置栅极结构140进行栅极切割工艺不同，方法300在置换虚置栅极结构140后才对栅极堆叠142进行栅极切割工艺。如方法300(见图4)的步骤302与第5至10图所示，重复方法200的步骤202、204、206、208、210、与212。在进行步骤302后，形成图10所示的半导体装置100(或其中间结构)。在步骤302后，虚置栅极结构140仍未置换为栅极堆叠142。如方法300(见图4)的步骤304与图14所示，虚置栅极结构140置换为栅极堆叠142。由于层间介电层190挡住附图中的栅极堆叠142，因此以虚线标示栅极堆叠142以达说明目的。
如方法300(见图4)的步骤306与图15所示，各向异性蚀刻栅极堆叠142以形成沟槽162，其将栅极堆叠142分隔成第一装置区101中的栅极部分142P，以及第二装置区102中的栅极部分142N。步骤306中的各向异性蚀刻有时称作“栅极切割”或“金属栅极切割”。在一些实施例中，可采用含氧气体、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、和/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化硅、和/或三氯化硼)、含溴气体(如溴化氢和/或溴仿)、含碘气体、其他合适气体和/或等离子体、和/或上述的组合作为蚀刻剂，以进行步骤306。步骤306中的各向异性蚀刻可有效移除栅极堆叠142中的材料，而掺有p型掺质如硼或镓的介电层180可实质上阻挡蚀刻。由于p型掺杂的介电层180可阻挡蚀刻，即使切割栅极的沟槽162与外延结构150P与150N重叠，外延结构150P与150N仍可保持实质上完整。由于栅极堆叠142中的材料与p型掺杂的介电层180具有蚀刻选择性，步骤306可称作自对准的栅极切割工艺。步骤306与采用未掺杂的介电层180之栅极切割(或金属栅极切割)工艺相较，具有较大的工艺容忍度。
如方法300(见图4)之步骤308及图16所示，将介电材料填入沟槽162。步骤308与方法200的步骤216实质上类似，差别在于方法300中的沟槽162形成于栅极堆叠142中，而非如方法200形成于虚置栅极结构140中。同样地，步骤310与312与方法200中的步骤220与222类似。在步骤310中，源极/漏极接点170P形成于外延结构150P上，而源极/漏极接点170N形成于外延结构150N上。在步骤312中，可对半导体装置100继续进行后续工艺，以形成本技术领域已知的多种结构与区域。
如此一来，本公开提供半导体装置与其制作方法。在本公开一实施例中，半导体装置包括基板，其具有第一装置区与第二装置区；第一鳍状物，位于第一装置区中的基板上；第二鳍状物，位于第二装置区中的基板上；其中第一鳍状物包括沟道区以及源极/漏极区，且第二鳍状物包括沟道区以及源极/漏极区；第一外延结构，位于源极/漏极区中的第一鳍状物上；第二外延结构，位于源极/漏极区中的第二鳍状物上；以及介电层，位于第一外延结构与第二外延结构上。第一外延结构掺杂有第一导电型态的第一掺质，第二外延结构掺杂有第二导电型态的第二掺质，且第二导电型态与第一导电型态不同。介电层掺杂有第一掺质。在一些实施例中，第一装置区为p型场效晶体管区，而第二装置区为n型场效晶体管区。在一些实施例中，第一导电型态为p型导电型态，而第二导电型态为n型导电型态。在一些实施方式中，介电层包括氮化硅。在一些实施方式中，介电层的厚度介于2nm至10nm之间。在一些实施例中，第一掺质为硼。在一些实施例中，第二掺质为磷。在一些例子中，第一外延结构包括硅锗。在一些实施例中，第二外延结构包括硅。
在本公开另一实施例中，半导体装置包括基板，以及n型场效晶体管于基板上。n型场效晶体管包括第一鳍状物于基板上，且第一鳍状物包括沟道区与源极/漏极区；第二鳍状物于基板上，且第二鳍状物包括沟道区与源极/漏极区；第一栅极，位于第一鳍状物的沟道区上以及第二鳍状物的沟道区上；第一外延结构，位于第一鳍状物的源极/漏极区及第二鳍状物的源极/漏极区上，并延伸于第一鳍状物的源极/漏极区及第二鳍状物的源极/漏极区之间；以及掺杂的介电层，直接位于第一外延结构上。第一外延结构掺杂有n型掺质，而掺杂的介电层掺杂有硼。在一些实施例中，掺杂的介电层包括氮化硅。在一些实施例中，第一外延结构包括硅与磷。在一些实施例中，半导体装置还包括p型场效晶体管于基板上。p型场效晶体管包括第三鳍状物于基板上，且第三鳍状物包括沟道区与源极/漏极区；第四鳍状物于基板上，且第四鳍状物包括沟道区与源极/漏极区；第二栅极，位于第三鳍状物的沟道区上以及第四鳍状物的沟道区上；第二外延结构，位于第三鳍状物的源极/漏极区及第四鳍状物的源极/漏极区上，并延伸于第三鳍状物的源极/漏极区及第四鳍状物的源极/漏极区之间；以及掺杂的介电层，直接位于第二外延结构上。第二外延结构掺杂有硼，且掺杂的介电层掺杂有硼。在一些实施例中，第二外延结构包括硅锗。在一些实施例中，n型场效晶体管紧邻p型场效晶体管。
此外，本公开提供半导体装置的制作方法。方法包括提供基板，其具有第一装置区与第二装置区；形成第一鳍状物于第一装置区中，并形成第二鳍状物于第二装置区中，且每一第一鳍状物与第二鳍状物具有沟道区与源极/漏极区；形成虚置栅极结构于第一鳍状物的沟道区及第二鳍状物的沟道区上；形成第一外延结构于第一鳍状物的源极/漏极区上，并形成第二外延结构于第二鳍状物的源极/漏极区上；形成掺杂的介电层于第一外延结构与第二外延结构上；以及各向异性蚀刻虚置栅极结构，以分隔第一装置区中的虚置栅极结构之一部分与第二装置区中的虚置栅极结构之另一部分。第一外延结构包括第一导电型态的第一掺质，且第二外延结构包括第二导电型态的第二掺质，且第一导电型态不同于第二导电型态。掺杂的介电层包括第一掺质。在一些实施例中，第一装置区为p型场效晶体管区，而第二装置区为n型场效晶体管区。在一些实施例中，形成掺杂的介电层于第一与第二外延结构上的步骤，包括在沉积外延层于第一与第二外延结构上时，以第一掺质原位掺杂外延层。在一些实施例中，形成掺杂的介电层于第一与第二外延结构上的步骤，包括沉积外延层于第一与第二鳍状物的外延区上；以及注入第一掺质至外延层。在一些实施例中，第一掺质为硼，且第二掺质为n型掺质。
虽然本公开已采用实例与实施例说明，但应理解本公开并不局限于公开的实施例。相反地，对本领域普通技术人员而言，本公开应涵盖多种调整与类似布置。因此申请专利的范畴应依据最大范围解释，以包含所有的调整与类似布置。

Claims (1)

1.一种半导体装置，包括：
一基板，具有一第一装置区与一第二装置区；
一第一鳍状物，位于该第一装置区中的该基板上，其中该第一鳍状物包括一沟道区以及一源极/漏极区；
一第二鳍状物，位于该第二装置区中的该基板上，其中该第二鳍状物包括一沟道区以及一源极/漏极区；
一第一外延结构，位于该源极/漏极区中的该第一鳍状物上，其中该第一外延结构掺杂有第一导电型态的一第一掺质；
一第二外延结构，位于该源极/漏极区中的该第二鳍状物上，其中该第二外延结构掺杂有第二导电型态的一第二掺质，且第二导电型态与第一导电型态不同；以及
一介电层，位于该第一外延结构与该第二外延结构上，其中该介电层掺杂有该第一掺质。
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