CN109750331A - 铜电镀组合物和在衬底上电镀铜的方法 - Google Patents

铜电镀组合物和在衬底上电镀铜的方法 Download PDF

Info

Publication number
CN109750331A
CN109750331A CN201811229806.2A CN201811229806A CN109750331A CN 109750331 A CN109750331 A CN 109750331A CN 201811229806 A CN201811229806 A CN 201811229806A CN 109750331 A CN109750331 A CN 109750331A
Authority
CN
China
Prior art keywords
copper
substrate
photoresist
feature
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201811229806.2A
Other languages
English (en)
Other versions
CN109750331B (zh
Inventor
R·波克雷尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm and Haas Electronic Materials LLC
Original Assignee
Rohm and Haas Electronic Materials LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm and Haas Electronic Materials LLC filed Critical Rohm and Haas Electronic Materials LLC
Publication of CN109750331A publication Critical patent/CN109750331A/zh
Application granted granted Critical
Publication of CN109750331B publication Critical patent/CN109750331B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Electrochemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

包括二咪唑化合物的铜电镀组合物能够在衬底上实现具有均一形态的铜的电镀。所述组合物和方法能够实现由光刻胶限定的特征的铜电镀。这类特征包括柱、接合焊盘和线空间特征。

Description

铜电镀组合物和在衬底上电镀铜的方法
技术领域
本发明涉及铜电镀组合物和在衬底上电镀铜的方法，其中铜电镀组合物包括二咪唑化合物以提供具有均一形态的铜沉积物。更具体地说，本发明涉及铜电镀组合物和在衬底上电镀铜的方法，其中铜电镀组合物包括二咪唑化合物以提供具有均一形态的铜沉积物，并且其中铜电镀组合物和铜电镀方法可用于电镀由光刻胶限定的特征。
背景技术
由光刻胶限定的特征包括铜柱和再分布层布线，如集成电路芯片和印刷电路板的接合焊盘和线空间特征。所述特征由光刻工艺形成，在光刻工艺中，将光刻胶施加到衬底上，衬底例如半导体晶片芯片，在封装技术中常称为裸片，或环氧树脂/玻璃印刷电路板。一般来说，将光刻胶施加到衬底的表面并将具有图案的掩模施加到光刻胶上。将带有掩模的衬底暴露于如紫外光的辐射。通常，将暴露于辐射的光刻胶部分显影掉或去除，暴露出衬底的表面。取决于掩模的特定图案，可以用留在衬底上的未曝光的光刻胶形成电路线或孔口的轮廓，形成电路线图案或孔口的壁。衬底表面包括使得衬底表面能够导电的金属晶种层或其它导电金属或金属合金材料。接着将含有图案化光刻胶的衬底浸没在金属电镀浴中，通常是铜电镀浴，并将金属电镀在电路线图案或孔口中，形成例如柱、接合焊盘或电路线等特征，即线空间特征。当电镀完成时，用剥离溶液将光刻胶的其余部分从衬底剥离，并进一步处理带有由光刻胶限定的特征的衬底。
柱，如铜柱，通常用焊料盖住以实现镀覆了柱的半导体芯片与衬底之间的粘合以及导电。这类布置可见于先进封装技术中。用焊料盖住的铜柱结构是先进封装应用中快速增长的部分，因为与单独的焊料凸块相比，输入/输出(I/O)密度改进。具有不可回焊铜柱和可回焊焊帽结构的铜柱凸块具有以下优点：(1)铜具有低电阻和高电流密度性能；(2)铜的导热性提供超过三倍的焊料凸块导热性；(3)可改进可能引起可靠性问题的传统球栅阵列热膨胀系数(ball grid array coefficient of thermal expansion，BGA CTE)错配问题；以及(4)铜柱在回焊期间不塌陷，允许极细间距而不损害托起高度。
在所有铜柱凸块制造方法中，电镀是目前为止商业上最可行的方法。在实际工业生产中，考虑到成本和工艺条件，电镀提供大规模生产率，并且在铜柱形成之后没有抛光或腐蚀工艺来改变铜柱表面形态。因此，尤其重要的是通过电镀获得光滑表面形态。用于电镀铜柱的理想的铜电镀化学和方法在用焊料回焊之后产生具有优异均一性、平坦柱形状和无空隙金属间界面的沉积物，并且能够以高沉积速率镀覆以实现高晶片产量。然而，所述镀覆化学和方法的发展是行业的难题，因为一种属性的改进通常是以另一种属性为代价。基于铜柱的结构已被各种制造商用在消费品中，如智能手机和PC。随着晶片级处理(WaferLevel Processing，WLP)继续发展并采用铜柱技术，对于能够制造出可靠铜柱结构的具有先进能力的镀铜浴和镀铜方法的需求将会不断增加。
在金属电镀再分布层布线的情况下还会遇到类似的形态问题。接合焊盘和线空间特征的形态方面的缺陷还损害了先进封装物品的性能。因此，需要能够提供具有均一形态的铜沉积物并且可用于在形成由光刻胶限定的特征时电镀铜的铜电镀组合物和铜电镀方法。
发明内容
本发明包括一种组合物，其包括一个或多个铜离子源；一种或多种电解质；一种或多种加速剂；一种或多种抑制剂；以及一种或多种具有下式的二咪唑化合物：
其中R1、R2、R3和R4独立地选自氢；直链或支链(C1-C4)烷基；以及苯基。
本发明还包括一种方法，其包括：
a)提供衬底；
b)提供铜电镀组合物，其包括一个或多个铜离子源；一种或多种电解质；一种或多种加速剂；一种或多种抑制剂；以及一种或多种具有下式的二咪唑化合物：
其中R1、R2、R3和R4独立地选自氢；直链或支链(C1-C4)烷基；以及苯基；
c)将铜电镀组合物施加到衬底上；以及
d)用铜电镀组合物在衬底上电镀具有均一形态的铜。
本发明的铜电镀组合物能够实现具有均一形态的铜沉积物并且可用于在衬底上电镀铜光刻胶特征。用本发明的铜电镀组合物和方法电镀的光刻胶特征具有基本上均一的形态并且基本上没有结节。如铜柱和接合焊盘等光刻胶特征具有基本上平坦的轮廓。
附图说明
图1是从含有1,5-二氢苯并[1,2-d:4,5-d']二咪唑的本发明铜电镀浴电镀的50μm直径×30μm高度铜柱的放大了50倍的3D图像。
图2是从含有3,3'-(乙烷-1,2-二基)双(1-(2-羟乙基)-1H-咪唑-3-鎓)氯化物的比较性铜电镀浴电镀的50μm直径×30μm高度铜柱的放大了50倍的3D图像。
具体实施方式
除非上下文另作明确指示，否则如本说明书通篇所使用的以下缩写应具有以下含义：A＝安培；A/dm2＝安培/平方分米＝ASD；℃＝摄氏度；UV＝紫外辐射；g＝克；ppm＝百万分率＝mg/L；L＝升；μm＝微米(micron)＝微米(micrometer)；mm＝毫米；cm＝厘米；DI＝去离子；mL＝毫升；mol＝摩尔；mmol＝毫摩尔；Mw＝重均分子量；Mn＝数均分子量；3D＝三维；FIB＝聚焦离子束；WID＝裸片内；WID％＝裸片内的柱的高度均一性的量度标准；TIR＝总指示偏差量＝总指示器读数＝指示器移动全量＝FIM；并且RDL＝再分布层。
如本说明书通篇所使用，术语“镀覆”是指铜电镀。“沉积”和“镀覆”在本说明书通篇中可互换使用。“加速剂”是指增加电镀浴的镀覆速率的有机添加剂。“抑制剂”是指在电镀期间抑制金属的镀覆速率的有机添加剂。术语“阵列”意指有序的布置。术语“部分”意指可以包括整个官能团或官能团的一部分作为子结构的分子或聚合物的一部分。术语“部分”和“基团”在本说明书通篇中可互换使用。术语“孔口”意指开口、孔洞或间隙。术语“形态”意指物品的形式、形状和结构。术语“总指示器偏差量”或“总指示器读数”是零件的平面、圆柱体或波状表面的最大与最小测量值(即，指示器的读数)之间的差值，展示其与其它圆柱体特征或类似情况的平坦度、圆度(圆形度)、圆柱度、同心度的偏差量。术语“轮廓测定法”意指在对物体进行测量和轮廓分析时使用一种技术或使用激光或白光计算机产生的投影对三维物体的表面进行测量。术语“间距”意指衬底上的特征位置彼此间的频率。术语“平均值”意指表示参数的中心值的数字，并且中心值通过将针对特定参数对多个样本所测量或收集的数值相加并且将每个样本的测量值的总和除以样本总数来确定。术语“参数”意指形成定义一个系统或设定其操作条件的集合中的一个的数值或其它可测量的因数。术语“周长”意指柱周围的边界。术语“例如(e.g.)”意指例如(for example)。冠词“一(a/an)”是指单数和复数。
所有数值范围都是包括性的并且可按任何顺序组合，但显然这类数值范围被限制于总计共100％。
本发明包括一种组合物，其包括一个或多个铜离子源；和一个或多个铜离子(阳离子)源的相应阴离子；一种或多种电解质；一种或多种加速剂；一种或多种抑制剂；一种或多种具有下式的咪唑化合物：
其中R1、R2、R3和R4独立地选自氢；直链或支链(C1-C4)烷基；以及苯基；并且溶剂是水。优选地，R1、R2、R3和R4独立地选自氢和直链或支链(C1-C4)烷基；更优选地，R1、R2、R3和R4独立地选自氢和直链(C1-C2)烷基；甚至更优选地，R1、R2、R3和R4独立地选自氢和甲基；最优选地，R1、R2、R3和R4是氢(1,5-二氢苯并[1,2-d:4,5-d']二咪唑)。本发明的二咪唑化合物具有未季铵化的氮。这类化合物可以根据化学文献容易地制得或从商业上获得，如从美国威斯康星州密尔沃基的西格玛-奥德里奇公司(Sigma-Aldrich,Milwaukee,WI,USA)获得。
可以按足够提供具有光滑且均一的表面形态的铜沉积物的量在铜电镀组合物中包括本发明的一种或多种二咪唑化合物。以铜电镀组合物的总重量计，优选地，按以下的量在铜电镀组合物中包括本发明的一种或多种二咪唑化合物：0.25mg/L到1000mg/L(例如，0.5mg/L到800mg/L，或例如1mg/L到700mg/L)；更优选地，10mg/L到500mg/L(例如，15mg/L到450mg/L，或例如25mg/L到250mg/L)；甚至更优选地，30mg/L到500mg/L(例如，35mg/L到400mg/L，或例如40mg/L到350mg/L)；最优选地，40mg/L到200mg/L(例如，45mg/L到150mg/L，或例如50mg/L到100mg/L)。
水性铜电镀组合物包括来自一个或多个来源的铜离子，所述来源例如水溶性铜盐。这种水溶性铜盐包括但不限于：硫酸铜，如五水合硫酸铜；卤化铜，如氯化铜；乙酸铜；硝酸铜；四氟硼酸铜；烷基磺酸铜；芳基磺酸铜；氨基磺酸铜；高氯酸铜以及葡糖酸铜。示范性烷磺酸铜包括(C1-C6)烷磺酸铜，并且更优选是(C1-C3)烷磺酸铜。优选的烷磺酸铜是甲磺酸铜、乙磺酸铜和丙磺酸铜。示范性芳基磺酸铜包括但不限于苯磺酸铜和对甲苯磺酸铜。可使用铜离子源的混合物。这种铜盐是本领域的技术人员众所周知的或可以根据化学文献容易地制得或从商业上获得，如从西格玛-奥德里奇公司获得。除了铜离子(阳离子)之外，铜电镀组合物还包括水溶性铜盐的相应阴离子。除了不可避免的杂质以外，本发明的铜电镀组合物不含其它金属，如合金金属。按能够提供具有光滑且均一的铜形态的铜沉积物的量在本发明的铜电镀组合物中包括一种或多种水溶性铜盐。优选地，一种或多种铜盐的存在量足以提供铜离子浓度为30g/L到70g/L的镀覆溶液；更优选地，浓度为40g/L到60g/L。
本发明的电解质可以是碱性的或酸性的。优选地，电解质是酸性的。优选地，电解质的pH≤2；更优选地，pH≤1。酸性电解质包括但不限于硫酸；乙酸；氟硼酸；烷磺酸，如甲磺酸、乙磺酸、丙磺酸和三氟甲磺酸；芳基磺酸，如苯磺酸、对甲苯磺酸；氨基磺酸；盐酸；氢溴酸；高氯酸；硝酸；铬酸；以及磷酸。在本发明的镀铜组合物中可以使用酸的混合物。优选的酸包括硫酸、甲磺酸、乙磺酸、丙磺酸、盐酸以及其混合物。酸的存在量可在1到400g/L的范围内。电解质一般可购自多种来源并且无需进一步纯化即可使用。
任选地，本发明的电解质可以含有卤离子源。优选使用氯离子和溴离子；更优选地，在铜电镀组合物中包括氯离子。示范性氯离子源包括氯化铜、氯化钠、氯化钾和盐酸(氯化氢)。溴离子源包括溴化钠、溴化钾和溴化氢。本发明中可以使用广泛范围的卤离子浓度。以镀覆组合物计，卤离子浓度优选在0.5mg/L到200mg/L范围内；更优选地，形成10mg/L到150mg/L；最优选地，50mg/L到100mg/L。这类卤离子源一般可在市面上购得并且无需进一步纯化即可使用。
加速剂(也被称为增亮剂)包括但不限于N,N-二甲基-二硫基氨基甲酸-(3-磺丙基)酯；3-巯基-丙基磺酸-(3-磺丙基)酯；3-巯基-丙基磺酸钠盐；碳酸二硫基-O-乙酯-S-酯与3-巯基-1-丙烷磺酸钾盐；双磺丙基二硫化物；双-(钠磺丙基)-二硫化物；3-(苯并噻唑基-S-硫基)丙基磺酸钠盐；吡啶鎓丙基磺基甜菜碱；1-钠-3-巯基丙烷-1-磺酸盐；N,N-二甲基-二硫基氨基甲酸-(3-磺乙基)酯；3-巯基-乙基丙基磺酸-(3-磺乙基)酯；3-巯基-乙基磺酸钠盐；碳酸-二硫基-O-乙酯-S-酯与3-巯基-1-乙烷磺酸钾盐；双磺乙基二硫化物；3-(苯并噻唑基-S-硫基)乙基磺酸钠盐；吡啶鎓乙基磺基甜菜碱；以及1-钠-3-巯基乙烷-1-磺酸盐。这种加速剂可在市面上购得，如从西格玛-奥德里奇公司购得，或可以根据化学文献制得。加速剂可以按各种浓度使用。加速剂优选按0.1mg/L到1000mg/L的量使用；更优选按0.5mg/L到500mg/L的量使用；最优选按1mg/L到50mg/L的量使用。
抑制剂包括但不限于聚丙二醇共聚物和聚乙二醇共聚物，包括环氧乙烷-环氧丙烷(“EO/PO”)共聚物和丁醇-环氧乙烷-环氧丙烷共聚物。抑制剂的重均分子量可在800到15000，优选1000到15,000的范围内。以镀覆组合物的重量计，包括0.5g/L到15g/L、优选0.5g/L到5g/L的量的抑制剂。
铜电镀组合物可以通过按任何顺序组合组分来制备。优选的是，首先向浴液容器中加入无机组分，如铜离子源、水、电解质和任选的卤离子源，接着加入有机组分，如咪唑化合物、加速剂、抑制剂和任何其它有机组分。
任选地，水性铜电镀浴可以包括常规流平剂，条件是这种流平剂基本上不损害铜沉积物的形态。这种流平剂可以包括Step等人的美国专利第6,610,192号、Wang等人的美国专利第7,128,822号、Hayashi等人的美国专利第7,374,652号以及Hagiwara等人的美国专利第6,800,188号中所公开的那些。这种流平剂可以按常规量包括在内；但是，优选将这种流平剂排除在本发明的铜电镀组合物之外。
任选地，本发明的铜电镀组合物可以包括添加剂，如缓冲剂，用以帮助维持所期望的pH；抗微生物剂；表面活性剂，如非离子、阳离子、阴离子和两性离子表面活性剂，表面活性剂优选是非离子表面活性剂；以及消泡剂。这些添加剂是本领域的技术人员众所周知的，并且按其常规量使用，或者可以进行少量实验来确定待包括在本发明的铜电镀组合物中的添加剂的最佳浓度。
铜电镀组合物优选由以下组成：一个或多个铜离子源；和一个或多个铜离子(阳离子)源的相应阴离子；一种或多种电解质；一种或多种加速剂；一种或多种抑制剂；一种或多种具有式(I)的二咪唑化合物；水；以及任选的一个或多个卤离子源；以及一种或多种选自缓冲剂、抗微生物剂、表面活性剂和消泡剂的添加剂。
铜电镀组合物更优选由以下组成：一个或多个铜离子源；和一个或多个铜离子(阳离子)源的相应阴离子；一种或多种电解质；一种或多种加速剂；一种或多种抑制剂；1,5-二氢苯并[1,2-d:4,5-d']二咪唑；水；以及任选的一个或多个卤离子源；以及一种或多种选自缓冲剂、抗微生物剂、表面活性剂和消泡剂的添加剂。
本发明的铜电镀组合物可用于在10℃到65℃的温度下电镀铜。镀覆组合物的温度优选是15℃到50℃，更优选是室温到40℃。
优选在镀覆期间搅拌铜电镀组合物。任何合适的搅拌方法都可以使用。搅拌方法在本领域中是众所周知的。合适的搅拌方法包括但不限于：空气鼓泡、工件搅拌和撞击。
可以通过使衬底与本发明的铜电镀组合物接触而使衬底电镀上铜。衬底可以用作阴极。阳极可以是可溶性阳极，如铜阳极，或不溶性阳极。本领域的技术人员已知各种不溶性阳极。向电极施加电势。电流密度可在0.25ASD到40ASD、优选1ASD到30ASD、更优选10ASD到30ASD的范围内。
本发明的铜电镀组合物和方法可用于在期望光滑且均一形态的铜沉积物的情况下在各种衬底上镀覆具有光滑且均一的形态的铜；但是，所述铜电镀组合物和方法优选用于镀覆由光刻胶限定的特征。
本发明的用于电镀由光刻胶限定的铜特征的方法和组合物能够实现这样的由光刻胶限定的特征的阵列，其所具有的平均TIR使得特征的形态是基本上光滑的，不含结节，并且在柱、接合焊盘和线空间特征方面具有基本上平坦的轮廓。本发明的由光刻胶限定的特征用留在衬底上的光刻胶电镀并且延伸超出衬底平面。这与双重镶嵌和印刷电路板镀覆形成对比，后者不使用光刻胶来限定特征，并且特征延伸超出衬底平面，但嵌入衬底中。由光刻胶限定的特征与镶嵌和印刷电路板特征之间的重要差异在于：在镶嵌和印刷电路板方面，包括侧壁在内的镀覆表面均导电。双重镶嵌和印刷电路板镀覆浴液具有能提供自下而上或超保形填充的浴液配方，其中特征的底部与特征的顶部相比镀覆较快。在由光刻胶限定的特征中，侧壁是不导电的光刻胶，并且镀覆仅发生在具有导电晶种层的特征底部，之后进行保形沉积或以相同镀覆速度各处沉积。
虽然本发明基本上是关于电镀具有圆形形态的铜柱的方法加以描述，但是本发明还适用于其它由光刻胶限定的特征，如接合焊盘和线空间特征。一般来说，除了圆形或圆柱形之外，特征的形状还可以是例如长方形、八边形和矩形。本发明的方法优选用于电镀圆柱形铜柱，其中所述柱具有基本上平坦的顶部。
铜电镀方法提供平均TIR为-3到3、优选-2到2、更优选-2到1、最优选-2到-1的由光刻胶限定的铜特征的阵列，所述特征如铜柱。
衬底上由光刻胶限定的特征的阵列的平均TIR涉及测定单一衬底上来自特征阵列的个别特征的TIR并求其平均值。指定衬底的特征的平均TIR可以通过测定低密度、中密度或高密度间距或其组合的区域的个别特征的TIR，将测量值相加并取这些值的平均值来确定。通过测量若干个别特征的TIR，平均TIR就能代表整个衬底。
个别特征的TIR可以通过下式确定：
TIR＝高度中心-高度边缘，
其中高度中心是沿柱的中轴线测得的柱高，而高度边缘是沿柱边缘在边缘上的最高点测得的柱高。
此外，铜电镀方法和组合物可以提供WID％为0％到16％、优选5％到16％、更优选12％到16％、最优选14％到16％的由光刻胶限定的铜特征的阵列。WID％或裸片内％可以通过下式确定：
WID％＝1/2×[(高度最大-高度最小)/高度平均]×100
其中高度最大是电镀在衬底上的柱阵列的最高柱的高度，如在柱的最高部分所测量。高度最小是电镀在衬底上的柱阵列的最短柱的高度，如在柱的最高部分所测量。高度平均是电镀在衬底上的所有柱的平均高度。最优选地，本发明的铜电镀组合物和方法在衬底上提供这样的由光刻胶限定的特征的阵列，其中在平均TIR与WID％之间达成平衡，使得平均TIR在-3到3的范围内，而WID％在0％到16％的范围内，每个参数的优选范围如上文所公开。
用于确定TIR和WID％的柱参数可以使用光学轮廓测定法测量，如采用KEYENCE 3D激光扫描共聚焦显微镜VK-X系列或类似设备，如白光LEICA DCM 3D。如柱高度和间距的参数可以使用此类装置测量。
由本发明的铜电镀组合物电镀的铜柱可具有3:1到1:1或如2:1到1:1的纵横比。RDL类型的结构可具有大到1:20(高度:宽度)的纵横比。
尽管本发明的方法可用于电镀由光刻胶限定的特征，如柱、接合焊盘和线空间特征，但是所述方法在镀覆作为本发明的优选特征的铜柱的情形下加以描述。本发明的铜柱可以通过以下形成：首先在如半导体芯片或裸片的衬底上沉积导电晶种层。接着用光刻胶材料涂布衬底并成像，使光刻胶层选择性暴露于如紫外辐射的辐射。光刻胶层可通过本领域中已知的常规方法施加到半导体芯片表面。光刻胶层的厚度可视特征的高度而变化。厚度可以在1μm到350μm、优选10μm到230μm、更优选20μm到220μm的范围内。将图案化掩模施加到光刻胶层的表面。光刻胶层可为正性或负性作用光刻胶。当光刻胶是正性作用光刻胶时，暴露于辐射的光刻胶部分用如碱性显影剂的显影剂去除。在表面上形成了具有多个孔口、如通孔的图案，该图案一直向下到达衬底或裸片上的晶种层。柱间距可以在20μm到400μm的范围内；间距优选可以在100μm到350μm的范围内；柱间距更优选可以在100μm到250μm的范围内。通孔的直径可视特征(柱)的直径而变化。通孔的直径可以在2μm到300μm、优选5μm到225μm、更优选15μm到200μm的范围内。接着可以将整个结构放置在本发明的铜电镀组合物中。进行电镀以用具有基本上平坦的顶部的铜柱填充每个通孔的至少一部分。电镀是保形沉积或以相同镀覆速度各处沉积，而不是超保形或超填充的。接着将带有铜柱的整个结构转移到含有焊料的浴液中，焊料如锡焊料或锡合金焊料，如锡/银或锡/铅合金，并在每根铜柱的基本上平坦的表面上电镀上焊料凸块以填充通孔部分。其余光刻胶通过本领域中已知的常规方法去除，在裸片上留下具有焊料凸块的铜柱阵列。未被柱覆盖的其余晶种层通过本领域中众所周知的蚀刻方法去除。将具有焊料凸块的铜柱放置成与衬底的金属触点接触，衬底如印刷电路板，可以由有机层合物、硅或玻璃制成的另一个晶片或裸片或插入件。通过本领域中已知的常规方法加热焊料凸块以回焊焊料并且将铜柱连接到衬底的金属触点上。可使用用于回焊焊料凸块的常规回焊方法。回焊炉的一个实例是来自SikiamaInternational,Inc.的FALCON 8500工具，它包括5个加热区和2个冷却区。回焊循环可在1到5个范围内。铜柱以物理方式和以电气方式接触衬底的金属触点。接着可注入底胶材料来填充裸片、柱与衬底之间的空隙。可使用本领域中众所周知的常规底胶。
图1是使用KEYENCE 3D激光扫描共聚焦显微镜VK-X系列收集的本发明铜柱的3D图像，本发明铜柱具有圆柱形形态，具有基底和平坦的顶表面形态，用于电镀焊料凸块。在回焊期间，将焊料熔融以获得光滑表面。如果柱在回焊期间过于隆起，那么焊料可能熔融并从柱的侧面流走，于是柱顶部就没有足够的焊料用于后续接合步骤，如图2中所示，图2也是像图1一样的3D图像。如果柱过于中凹或具有下沉孔型配置，那么从用于电镀柱的铜浴留下的材料会被滞留在中凹的顶部并污染焊料浴，由此缩短焊料浴的寿命。
为了在柱电镀期间提供铜柱与半导体裸片之间的金属触点和粘合，通常在裸片上沉积由例如钛、钛-钨或铬等材料构成的凸块下金属化层。或者，可以在半导体裸片上沉积金属晶种层，如铜晶种层，以提供铜柱与半导体裸片之间的金属触点。在从裸片去除感光层之后，去除凸块下金属化层或晶种层的所有部分，但柱下面的部分除外。可以使用本领域中已知的常规方法。
虽然铜柱高度会有不同，但是铜柱高度优选在1μm到300μm、更优选5μm到225μm、甚至更优选15μm到200μm的高度范围内。铜柱直径也可以不同。铜柱直径优选是2μm到300μm，更优选地是5μm到225μm，甚至更优选是15μm到200μm。
铜电镀方法和组合物提供具有基本上均一形态且基本上不含结节的由光刻胶限定的铜特征。铜柱和接合焊盘具有基本上平坦的轮廓。铜电镀组合物和方法能够获得可实现所期望的形态的平均TIR并在平均TIR与WID％之间达成平衡。
以下实例意在进一步说明本发明，而非意在限制其范围。
实例1(本发明实例)
铜电镀浴
用如下表1中所公开的组分和量制备本发明的下列铜电镀浴。
表1
将铜电镀浴的组分在室温下搅拌混合在一起。铜电镀浴的pH<1。
实例2(含有季铵化氮的比较实例)
合成3,3'-(乙烷-1,2-二基)双(1-(2-羟乙基)-1H-咪唑-3-鎓)氯化物
将N-(2-羟乙基)咪唑(2.55g，22.7mmol)和1,2-二氯乙烷(1.00g，10.11mmol)称至20mL压力管中。加入乙腈(10mL)，将管密封并加热到90℃保持60小时。冷却到室温，所得沉淀通过过滤分离，用新鲜乙腈洗涤，并在真空中干燥，得到2.91g(59％)呈白色粉末状的化合物。
1H NMR(400MHz,DMSO-d6)δ9.37(s,2H),7.79(s,4H),5.50(t,J＝5.5Hz,2H),4.81(s,4H),4.23(t,J＝4.6Hz,4H),3.70(t,J＝5.2Hz,4H)。13C NMR(101MHz,DMSO-d6)δ136.96,123.06,122.28,59.08,51.84,48.30。
实例3(比较实例)
铜电镀浴
用如下表2中所公开的组分和量制备本发明的下列铜电镀浴。
表2
将铜电镀浴的组分在室温下搅拌混合在一起。铜电镀浴的pH<1。
实例4(本发明实例)
一个300mm硅晶片裸片，它具有两个不同间距区域(密间距＝100μm，并且疏间距＝250μm)，其中每个区域都有50μm厚的图案化光刻胶，并且在每个区域中都有直径为50μm的多个孔口(可购自华盛顿州温哥华市的IMAT公司(IMAT,Inc.,Vancouver,WA))，将它浸没在如实例1的表1中所公开的本发明的铜电镀浴中。阳极为可溶性铜电极。将晶片和阳极连接到整流器，并在孔口底部所暴露的晶种层上电镀上铜柱。镀覆期间的平均电流密度是15ASD，并且铜电镀浴的温度是在25℃下。镀覆浴的pH<1。在电镀后，接着用可购自陶氏化学公司(Dow Chemical Company)的BPR光剥离溶液剥离其余光刻胶，在晶片上的两个不同间距区域留下铜柱阵列。接着分析来自每个区域的八根铜柱的形态。铜柱中心的高度和边缘的高度以及柱的TIR使用KEYENCE 3D激光扫描共聚焦显微镜VK-X系列测量。TIR通过下式确定：
TIR＝高度中心-高度边缘
还测定了八根柱的平均TIR，如表3中所示。
表3
柱阵列的WID％由KEYENCE 3D激光扫描共聚焦显微镜VK-X系列和下式确定：
WID％＝1/2×[(高度最大-高度最小)/高度平均]×100
跨密间距和疏间距的WID％(即跨密间距和疏间距测量8根柱)是15.4％并且平均TIR是-1.6。柱表面均呈现为光滑的并且不含结节。包括反应产物1的铜电镀浴能镀覆出非常好的铜柱。图1是镀覆在晶种层上的间距100μm的柱4的图像，并使用3D图像进行分析，所述图像使用KEYENCE 3D激光扫描共聚焦显微镜VK-X系列收集。顶部表面形态光滑且平坦，适合于容纳焊料。
实例5(比较实例)
一个300mm硅晶片裸片，它具有两个不同间距区域(密间距＝100μm，并且疏间距＝250μm)，其中每个区域都有50μm厚的图案化光刻胶，并且在每个区域中都有直径为50μm的多个孔口(可购自华盛顿州温哥华市的IMAT公司)，将它浸没在如实例3的表2中所公开的含有季铵化氮化合物的比较性铜电镀浴中。阳极为可溶性铜电极。将晶片和阳极连接到整流器，并在孔口底部所暴露的晶种层上电镀上铜柱。镀覆期间的平均电流密度是15ASD，并且铜电镀浴的温度是在25℃下。镀覆浴的pH<1。在电镀后，接着用可购自陶氏化学公司的BPR光剥离溶液剥离其余光刻胶，在晶片上的两个不同区域留下铜柱阵列。接着分析来自每个区域的八根铜柱的形态。铜柱中心的高度和边缘的高度以及柱的TIR使用KEYENCE 3D激光扫描共聚焦显微镜VK-X系列测量。TIR通过下式确定：TIR＝高度中心-高度边缘
还测定了八根柱的平均TIR，如表3中所示。
表3
柱阵列的WID％由KEYENCE 3D激光扫描共聚焦显微镜VK-X系列和下式确定：
WID％＝1/2×[(高度最大-高度最小)/高度平均]×100
跨密间距和疏间距的WID％是17.9％(即跨密间距和疏间距测量8根柱)并且平均TIR是+4.4。柱顶部呈现隆起并且粗糙，因此不适合容纳焊料。图2是镀覆在晶种层上的间距100μm的柱5的图像，并使用3D图像进行分析，所述图像使用KEYENCE 3D激光扫描共聚焦显微镜VK-X系列收集。柱周围的表面形态呈现为光滑的；但是，顶部是圆形的并且粗糙，不适合容纳焊料。

Claims (9)

1.一种组合物，其包含一个或多个铜离子源；一种或多种电解质；一种或多种加速剂；一种或多种抑制剂；以及一种或多种具有下式的咪唑化合物：
其中R1、R2、R3和R4独立地选自氢；直链或支链(C1-C4)烷基；以及苯基。
2.根据权利要求1所述的组合物，其中所述一种或多种咪唑化合物的量是0.25ppm到1000ppm。
3.根据权利要求1所述的组合物，其中R1、R2、R3和R4独立地选自氢和(C1-C2)烷基。
4.根据权利要求3所述的组合物，其中R1、R2、R3和R4独立地选自氢和甲基。
5.一种方法，其包含：
a)提供衬底；
b)提供铜电镀组合物，其包含一个或多个铜离子源；一种或多种电解质；一种或多种加速剂；一种或多种抑制剂；以及一种或多种具有下式的咪唑化合物：
其中R1、R2、R3和R4独立地选自氢；直链或支链(C1-C4)烷基；以及苯基；
c)将所述铜电镀组合物施加到所述衬底上；以及
d)用所述铜电镀组合物在所述衬底上电镀具有均一形态的铜。
6.根据权利要求1所述的方法，其中所述衬底包含由光刻胶限定的特征并且所述由光刻胶限定的特征在电镀期间是用铜电镀的。
7.根据权利要求6所述的方法，其中所述衬底上的所述由光刻胶限定的特征选自柱、接合焊盘和线空间特征中的一个或多个。
8.根据权利要求5所述的方法，其中所述一种或多种咪唑化合物的量是0.25ppm到1000ppm。
9.根据权利要求5所述的方法，其中电镀是在0.25ASD到40ASD的电流密度下进行的。
CN201811229806.2A 2017-11-08 2018-10-22 铜电镀组合物和在衬底上电镀铜的方法 Active CN109750331B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762583120P 2017-11-08 2017-11-08
US62/583120 2017-11-08

Publications (2)

Publication Number Publication Date
CN109750331A true CN109750331A (zh) 2019-05-14
CN109750331B CN109750331B (zh) 2021-07-13

Family

ID=66328336

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811229806.2A Active CN109750331B (zh) 2017-11-08 2018-10-22 铜电镀组合物和在衬底上电镀铜的方法

Country Status (5)

Country Link
US (1) US10612148B2 (zh)
JP (1) JP6754409B2 (zh)
KR (1) KR102241086B1 (zh)
CN (1) CN109750331B (zh)
TW (1) TWI703148B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110424030A (zh) * 2019-08-30 2019-11-08 广州三孚新材料科技股份有限公司 无氰碱性电镀铜液及其制备和在挠性印刷线路板中的应用
CN115557896A (zh) * 2022-09-30 2023-01-03 中纺院（浙江）技术研究院有限公司 一种双官能团咪唑离子液体及其合成方法与应用
TWI835388B (zh) * 2022-01-21 2024-03-11 南韓商東友精細化工有限公司 鍍銅用組合物以及使用該組合物製造含銅導體的方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5149577B2 (zh) * 1971-08-25 1976-12-27
US20030142018A1 (en) * 2002-01-29 2003-07-31 California Amplifier, Inc. High-efficiency transparent microwave antennas
JP2004231709A (ja) * 2003-01-29 2004-08-19 Jfe Chemical Corp 高分子化合物およびその合成法と使用法
CN1809652A (zh) * 2003-02-17 2006-07-26 原子能委员会 涂布表面的方法
CN101421675A (zh) * 2006-04-14 2009-04-29 阿尔特拉公司 双重曝光光刻工艺
CN104053312A (zh) * 2013-03-14 2014-09-17 罗门哈斯电子材料有限公司 填充通孔的方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2023629A1 (de) * 1970-05-14 1971-12-02 Agfa Gevaert AG, 5090 Leverkusen Photographisches Trockenkopierverfahren
US3937154A (en) * 1974-08-28 1976-02-10 Consumat Systems, Inc. Afterburner apparatus for incinerators or the like
US4522745A (en) * 1982-11-17 1985-06-11 Chevron Research Company Fused 5,6,5-membered heterocyclic electroactive polymers
US6176984B1 (en) * 1998-06-29 2001-01-23 Sri International High temperature polybenzazole and polyether electrolytes
US6114498A (en) * 1999-03-09 2000-09-05 The United States Of America As Represented By The Secretary Of The Air Force Benzobisazole polymers containing 2,2'-bipyridine-5,5 '-diyl moieties
DE112004001158T5 (de) * 2003-06-27 2007-01-11 E.I. Du Pont De Nemours And Co., Wilmington Fluorierte Sulfonamidverbindungen und daraus hergestellte Polymer-Elektrolytmembranen zur Verwendung in elektrochemischen Zellen
US8262895B2 (en) * 2010-03-15 2012-09-11 Rohm And Haas Electronic Materials Llc Plating bath and method
JP5407022B2 (ja) * 2011-09-02 2014-02-05 石原ケミカル株式会社 電気銅メッキ浴、当該浴により電着皮膜を形成した電子部品
JP6142165B2 (ja) 2013-03-25 2017-06-07 石原ケミカル株式会社 電気銅メッキ浴、電気銅メッキ方法並びに当該メッキ浴を用いて銅皮膜を形成した電子部品の製造方法
KR101743978B1 (ko) * 2013-11-20 2017-06-07 롬 앤드 하스 일렉트로닉 머트어리얼즈 엘엘씨 평활제로서의 벤즈이미다졸 모이어티를 함유하는 폴리머
US9439294B2 (en) * 2014-04-16 2016-09-06 Rohm And Haas Electronic Materials Llc Reaction products of heterocyclic nitrogen compounds polyepoxides and polyhalogens
US10100421B2 (en) * 2015-08-06 2018-10-16 Dow Global Technologies Llc Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of imidazole and bisepoxide compounds
US10006136B2 (en) * 2015-08-06 2018-06-26 Dow Global Technologies Llc Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of imidazole compounds, bisepoxides and halobenzyl compounds

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5149577B2 (zh) * 1971-08-25 1976-12-27
US20030142018A1 (en) * 2002-01-29 2003-07-31 California Amplifier, Inc. High-efficiency transparent microwave antennas
JP2004231709A (ja) * 2003-01-29 2004-08-19 Jfe Chemical Corp 高分子化合物およびその合成法と使用法
CN1809652A (zh) * 2003-02-17 2006-07-26 原子能委员会 涂布表面的方法
CN101421675A (zh) * 2006-04-14 2009-04-29 阿尔特拉公司 双重曝光光刻工艺
CN104053312A (zh) * 2013-03-14 2014-09-17 罗门哈斯电子材料有限公司 填充通孔的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
A. M. SIMONOV等: "Benzo[1,2-d:3,4-d′]diimidazole derivatives", 《CHEMISTRY OF HETEROCYCLIC COMPOUNDS》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110424030A (zh) * 2019-08-30 2019-11-08 广州三孚新材料科技股份有限公司 无氰碱性电镀铜液及其制备和在挠性印刷线路板中的应用
TWI835388B (zh) * 2022-01-21 2024-03-11 南韓商東友精細化工有限公司 鍍銅用組合物以及使用該組合物製造含銅導體的方法
CN115557896A (zh) * 2022-09-30 2023-01-03 中纺院（浙江）技术研究院有限公司 一种双官能团咪唑离子液体及其合成方法与应用
CN115557896B (zh) * 2022-09-30 2024-06-04 中纺院（浙江）技术研究院有限公司 一种双官能团咪唑离子液体及其合成方法与应用

Also Published As

Publication number Publication date
TW201918486A (zh) 2019-05-16
KR20190052611A (ko) 2019-05-16
CN109750331B (zh) 2021-07-13
JP2019085644A (ja) 2019-06-06
US10612148B2 (en) 2020-04-07
TWI703148B (zh) 2020-09-01
KR102241086B1 (ko) 2021-04-15
US20190136396A1 (en) 2019-05-09
JP6754409B2 (ja) 2020-09-09

Similar Documents

Publication Publication Date Title
TWI600804B (zh) 自含有咪唑化合物、雙環氧化物及鹵基苄基化合物的反應產物的銅電鍍浴電鍍光致抗蝕劑限定的特徵之方法
TWI600803B (zh) 自含有咪唑及雙環氧化物化合物的反應產物的銅電鍍浴電鍍光致抗蝕劑限定的特徵之方法
TWI608132B (zh) 自含有吡啶基烷基胺及雙環氧化物之反應產物的銅電鍍覆浴液電鍍覆光阻劑限定之特徵的方法
TWI618820B (zh) 自含有α胺基酸及雙環氧化物的反應產物的銅電鍍浴電鍍光致抗蝕劑限定的特徵之方法
CN109750331A (zh) 铜电镀组合物和在衬底上电镀铜的方法
US10927468B2 (en) Copper electroplating compositions and methods of electroplating copper on substrates
TWI638067B (zh) 自含有吡唑化合物及雙環氧化物的反應產物的銅電鍍浴液電鍍光致抗蝕劑限定的特徵之方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant