CN109712940A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN109712940A
CN109712940A CN201810015730.7A CN201810015730A CN109712940A CN 109712940 A CN109712940 A CN 109712940A CN 201810015730 A CN201810015730 A CN 201810015730A CN 109712940 A CN109712940 A CN 109712940A
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CN
China
Prior art keywords
layer
chip
hole
top surface
molding
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Pending
Application number
CN201810015730.7A
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English (en)
Inventor
刘子正
郭正铮
郭宏瑞
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109712940A publication Critical patent/CN109712940A/zh
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Abstract

本发明实施例提供半导体封装。所述半导体封装中的一者包括第一芯片、第二芯片、及模塑化合物。所述第一芯片上具有至少一个第一通孔及保护层，且所述至少一个第一通孔形成在所述保护层中。所述第二芯片上具有至少一个第二通孔。所述模塑层包封所述第一芯片及所述第二芯片。所述至少一个第二通孔设置在所述模塑层中且与所述模塑层接触，且所述保护层的顶表面、所述至少一个第一通孔的顶表面及所述至少一个第二通孔的顶表面与所述模塑层的顶表面实质上共面。

Description

半导体封装
技术领域
本发明实施例涉及半导体封装。
背景技术
正在开发用于晶片级封装的三维集成技术来满足高密度集成封装对尺寸减小、高性能内连线、及异质集成(heterogeneous integration)的需求。
发明内容
本发明实施例的一种半导体封装包括第一芯片、第二芯片及模塑化合物。所述第一芯片上具有至少一个第一通孔及保护层，且所述至少一个第一通孔形成在所述保护层中。所述第二芯片上具有至少一个第二通孔。所述模塑层包封所述第一芯片及所述第二芯片。所述至少一个第二通孔设置在所述模塑层中且与所述模塑层接触，且所述保护层的顶表面、所述至少一个第一通孔的顶表面及所述至少一个第二通孔的顶表面与所述模塑层的顶表面实质上共面。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A至图1G是根据一些示例性实施例的半导体封装的制造方法中的各个阶段的示意性剖视图。
图2是示出根据一些示例性实施例的半导体封装的示意性剖视图。
图3A至图3I是根据一些示例性实施例的半导体封装的制造方法中的各个阶段的示意性剖视图。
图4是示出根据一些示例性实施例的半导体封装的示意性剖视图。
图5A至图5F是根据本公开一些示例性实施例的半导体封装的制造方法中的各个阶段的示意性剖视图。
图6是示出根据一些示例性实施例的半导体封装的示意性剖视图。
具体实施方式
以下公开提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
另外，本文中可能使用例如“位于...之下(beneath)”、“位于...下面(below)”、“下部的(lower)”、“位于...上方(above)”、“上部的(upper)”等空间相对性用语以便于阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。装置可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对性用语可同样相应地进行解释。
另外，为易于说明，本文中可使用例如“第一”、“第二”、“第三”、“第四”等用语来阐述与图中所示相似或不同的元件或特征，且可依据存在的次序或说明的上下文而互换地使用。
也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(threedimensional，3D)封装或三维集成电路(three dimensional integrated circuit，3DIC)器件进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫(test pad)，以便能够对三维封装或三维集成电路进行测试、对探针及/或探针卡(probecard)进行使用等。可对中间结构以及最终结构执行验证测试。另外，可将本文中所公开的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用，以提高良率并降低成本。
图1A至图1G是根据一些示例性实施例的半导体封装的制造方法中的各个阶段的示意性剖视图。在示例性实施例中，所述半导体制造方法是封装工艺的一部分。在一些实施例中，示出两个芯片来代表多个芯片，且示出一个或多个封装来代表在半导体制造方法之后获得的多个半导体封装。
参照图1A，提供载体C。在载体C之上依序堆叠剥离层DB及粘合层103。在一些实施例中，在载体C的上表面上形成剥离层DB，且剥离层DB位于载体C与粘合层103之间。载体C例如为玻璃衬底。另一方面，在一些实施例中，剥离层DB是在玻璃衬底上形成的光热转换(light-to heat-conversion，LTHC)释放层。在一些实施例中，粘合层103是管芯贴合膜(die attach film，DAF)。然而，剥离层DB、载体C、及粘合层103的材料仅用于说明，且本公开并非仅限于此。
参照图1B，在载体C之上设置有多个层间穿孔(through interlayer via，TIV)102、第一芯片(管芯)110、及第二芯片(管芯)130。使用粘合层103将第一芯片110及第二芯片130放置到上面形成有层间穿孔102的剥离层DB上。第一芯片110与第二芯片130彼此相邻且被层间穿孔102环绕。在一些实施例中，第一芯片110与第二芯片130可为相同类型的芯片或不同类型的芯片，且可为数字芯片、模拟芯片、或混合信号芯片，例如应用专用集成电路(application-specific integrated circuit，“ASIC”)芯片、高带宽存储器(highbandwidth memory，HBM)芯片、传感器芯片、无线射频芯片(wireless and radiofrequency chip)、存储器芯片、逻辑芯片、或电压调节器芯片。
在一些实施例中，第一芯片110与第二芯片130具有不同的厚度t1、t2。在一些实施例中，第一芯片110包括有源表面112、分布在有源表面112上的多个接垫114、覆盖有源表面112的钝化层116、多个第一通孔118、以及保护层120。接垫114被钝化层116局部地暴露出，第一通孔118设置在接垫114上并电连接到接垫114，且保护层120覆盖第一通孔118及钝化层116。举例来说，第一通孔118从有源表面112到第一通孔118自身的顶表面测量可具有介于约20μm到约25μm范围内的不同高度或相同高度。在示例性实施例中，第一通孔118包括晶种层118a及金属层118b，且晶种层118a仅设置在金属层118b的底部上。晶种层118a及金属层118b的材料可包括例如铜、铜合金、或其他合适的材料选项。在一些实施例中，保护层120可为聚苯并恶唑(polybenzoxazole，PBO)层、聚酰亚胺(PI)层或其他合适的聚合物。在一些替代实施例中，保护层120可由无机材料制成。
在一些实施例中，第二芯片130包括有源表面132、分布在有源表面132上的多个接垫134、覆盖有源表面132的钝化层136、以及多个第二通孔138。接垫134被钝化层136局部地暴露出，且第二通孔138设置在接垫134上并电连接到接垫134。应注意，第二通孔138被暴露出。换句话说，与被第一芯片110的保护层120覆盖的第一通孔118相比，第二芯片130的第二通孔138被暴露出而未被覆盖。在示例性实施例中，第二通孔138包括晶种层138a及金属层138b，且晶种层138a仅设置在金属层138b的底部上。在一些实施例中，举例来说，第二通孔138从有源表面132到第二通孔138自身的顶表面测量可具有介于约20μm到约25μm范围内的不同高度或相同高度。第二通孔138与第一通孔118可具有不同的或相同的高度。在一些实施例中，举例来说，第二通孔138的顶表面高于第一通孔118的顶表面。如图1B所示，第一芯片110的顶表面及第二芯片130的顶表面低于层间穿孔102的顶表面。然而，本公开并非仅限于此。在一些替代实施例中，第一芯片110的顶表面及第二芯片130的顶表面可高于层间穿孔102的顶表面或与层间穿孔102的顶表面实质上共面。
参照图1C，在载体C之上形成模塑化合物140以包封层间穿孔102以及第一芯片110及第二芯片130。在一些实施例中，模塑化合物140是通过模塑工艺形成。层间穿孔102、第一芯片110的保护层120、及第二芯片130的第二通孔138被模塑化合物140包封。换句话说，层间穿孔102、第一芯片110的保护层120、及第二芯片130的第二通孔138未被显露出，且得到模塑化合物140的良好保护。在一些实施例中，模塑化合物140可包含环氧树脂(epoxy)或其他合适的材料。在示例性实施例中，模塑化合物140可包含不含有填料的材料。
参照图1D，对模塑化合物140及第一芯片110的保护层120进行研磨直到暴露出第一通孔118的顶表面及第二通孔138的顶表面为止。在对模塑化合物140进行研磨之后，在粘合层103之上形成模塑层140’。在上述研磨工艺期间，还对保护层120的一些部分进行了研磨以形成保护层120’。在一些实施例中，在模塑化合物140以及保护层120的上述研磨工艺期间，对第一通孔118的一些部分、及第二通孔138的一些部分以及层间穿孔102的一些部分进行研磨直到暴露出第一通孔118的顶表面及第二通孔138的顶表面以及层间穿孔102的顶表面为止。换句话说，模塑层140’暴露出第一芯片110的至少一部分及第二芯片130的至少一部分以及层间穿孔102的至少一部分。在一些实施例中，模塑层140’可通过机械研磨、化学机械抛光(chemical mechanical polishing，CMP)、或另一种合适的机制形成。
模塑层140’包封第一芯片110的侧壁及第二芯片130的侧壁、保护层120’、及第二通孔138，且模塑层140’被层间穿孔102穿透。换句话说，第一芯片110、及第二芯片130、以及层间穿孔102嵌置在模塑层140’中。应注意，尽管第一芯片110、及第二芯片130、以及层间穿孔102嵌置在模塑层140’中，然而模塑层140’会暴露出第一芯片110的顶表面、及第二芯片130的顶表面、以及层间穿孔102的顶表面。换句话说，层间穿孔102的顶表面、保护层120’的顶表面、以及第一通孔118的顶表面及第二通孔138的顶表面与模塑层140’的顶表面实质上共面。另外，第二通孔138设置在模塑层140’中且与模塑层140’接触，而第一通孔118设置在保护层120’中且与保护层120’接触。
参照图1E，在形成模塑层140’及保护层120’之后，与第一芯片110的第一通孔118及第二芯片130的第二通孔138、以及层间穿孔102电连接的重布线层150形成在层间穿孔102的顶表面上、模塑层140’的顶表面上、第一通孔118的顶表面上及第二通孔138的顶表面上、以及保护层120’的顶表面上。如图1E所示，重布线层150包括交替堆叠的多个层间介电层152与多个重布线导电图案154。重布线导电图案154电连接到嵌置在保护层120’中的第一通孔118以及嵌置在模塑层140’中的第二通孔138及层间穿孔102。在一些实施例中，第一通孔118的顶表面及第二通孔138的顶表面、以及层间穿孔102的顶表面与重布线层150的最底部重布线导电图案154接触。第一通孔118的顶表面、及第二通孔138的顶表面以及层间穿孔102的顶表面被最底部层间介电层152局部地覆盖。在示例性实施例中，重布线导电图案154包括晶种层154a及导电层154b，且晶种层154a设置在导电层154b的底部上。另外，最顶部重布线导电图案154包括多个接垫。在一些实施例中，上述接垫包括用于球安装(ballmount)的多个球下金属(under-ball metallurgy，UBM)图案156a及/或用于安装无源组件的至少一个连接接垫156b。球下金属图案156a及连接接垫156b的数目在本公开中并无限制。
参照图1F，在形成重布线层150之后，将多个导电端子160放置在球下金属图案156a上，且将多个无源组件162安装在连接接垫156b上。在一些实施例中，可通过植球(ballplacement)工艺或其他合适的工艺来将导电端子160放置在球下金属图案156a上且可通过焊接工艺、回焊工艺、或其他合适的工艺将无源组件162安装在连接接垫156b上。
参照图1F及图1G，在将导电端子160及无源组件162安装在重布线层150上之后，将图1G所示结构从载体C剥离。也就是说，将载体C、剥离层DB、及粘合层103移除。在一些实施例中，可通过紫外激光来对剥离层DB(例如，光热转换释放层)进行照射。此处，实质上已完成集成扇出型(integrated fan-out，INFO)封装10的形成。在一些实施例中，集成扇出型封装10可与其他电子器件进行连接及/或堆叠。
图2是示出根据一些示例性实施例的半导体封装的示意性剖视图。在图2中，阐述与图1G所示结构相似的半导体封装10，只是省略了层间穿孔。在半导体封装10中，第二芯片130的第二通孔138设置在模塑层140’中且第二通孔138的顶表面与模塑层140’的经抛光的顶表面及第一芯片110的第一通孔118的顶表面实质上共面及齐平。
在一些实施例中，通过执行平面化工艺来消除第一芯片与第二芯片之间的厚度差异以及通孔与层间穿孔之间的高度差异。因此，可将具有不同厚度的芯片(例如，不同类型的芯片或来自不同供应商的芯片)放置在载体上以进行封装。另外，第二通孔是在将第二衬底粘合到载体之后被模塑层包封，而第一通孔是在将第一芯片粘合到载体之前被保护层包封。换句话说，第一芯片的第一通孔设置在保护层中且与保护层接触，且第二芯片的第二通孔设置在模塑层中且与模塑层接触。
图3A至图3I是根据一些示例性实施例的半导体封装的制造方法中的各个阶段的示意性剖视图。在一些实施例中，示出两个芯片来代表多个芯片，且示出一个或多个封装来代表在半导体制造方法之后获得的多个半导体封装。与上述元件相似或实质上相同的元件将使用相同的参考编号，且本文中将不再重复相同元件的某些细节或说明。
参照图3A，提供载体C。在一些实施例中，在载体C之上依序堆叠剥离层DB及介电层DI。在一些实施例中，介电层DI例如为聚合物，例如聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、或类似材料。在一些替代实施例中，介电层DI可包含非有机介电材料，例如氧化硅、氮化硅、碳化硅、氮氧化硅、或类似材料。然而，介电层DI的材料仅用于说明，且本公开并非仅限于此。
接着，在介电层DI之上设置层间穿孔102、具有第一粘合层104的第一芯片110、以及具有第二粘合层106的第二芯片130。在示例性实施例中，第一芯片110与第二芯片130具有不同的厚度t1、t2。然而，通过调整第一粘合层104的厚度t1’及第二粘合层106的厚度t2’，使第一芯片110与第一粘合层104的总厚度实质上等于第二芯片130与第二粘合层106的总厚度，例如，t1+t1’＝t2+t2’。因此，第一芯片110的有源表面112与第二芯片130的有源表面132实质上共面。在一些实施例中，第一芯片110包括有源表面112、分布在有源表面112上的多个接垫114、以及覆盖有源表面112的钝化层116。在一些实施例中，第二芯片130包括有源表面132、分布在有源表面132上的多个接垫134、以及覆盖有源表面132的钝化层136。如图3A所示，举例来说，第一芯片110的顶表面及第二芯片130的顶表面低于层间穿孔102的顶表面。
参照图3B，在载体C之上形成模塑层140a以包封第一芯片110及第二芯片130，且模塑层140a的顶表面不高于第一芯片110的有源表面112及第二芯片130的有源表面132。在一些实施例中，介电层DI上的第一芯片110及第二芯片130以及层间穿孔102的位于载体C之上的部分被包封在模塑层140a中。在一些实施例中，模塑层140a覆盖介电层DI且填充在第一芯片110及第二芯片130与层间穿孔102之间。在示例性实施例中，模塑层140a是通过以下方式形成：使用内表面贴合有释放膜(图中未示出)的模具(mold chase)(图中未示出)来覆盖第一芯片110的有源表面112及第二芯片130的有源表面132以及层间穿孔102的顶部部分，但使第一芯片110的横向侧、及第二芯片130的横向侧以及层间穿孔102的底部部分暴露出。也就是说，模塑层140a的顶表面低于第一芯片110的有源表面112及第二芯片130的有源表面132且低于层间穿孔102的顶表面。在示例性实施例中，模塑层140a的顶表面因来自释放膜的压力而具有碟状凹陷。在示例性实施例中，模塑层140a的材料包括至少一种类型的含填料树脂且所述树脂可为环氧树脂、酚醛树脂、或含硅树脂。在示例性实施例中，所述填料由非熔融无机材料制成，且所述填料包括平均粒径(particle size)介于约3μm到约20μm范围内、约10μm到约20μm范围内、或者介于约15μm到约20μm范围内的金属氧化物粒子、二氧化硅粒子、或硅酸盐粒子。已固化模塑化合物的表面粗糙度或表面平坦度根据在模塑化合物材料中添加了细填料粒子还是粗填料粒子而异。如果对模塑化合物执行平面化工艺，则可能会因移除填料而在模塑化合物中形成一些凹坑，从而造成相对大的表面粗糙度、或甚至不平整度及可能的连接故障。在一些实施例中，模塑层140a是在不执行平面化工艺的条件下形成的。
参照图3C，分别在第一芯片110的有源表面112及第二芯片130的有源表面132之上形成第一通孔118及第二通孔138。如图3C所示，模塑层140a不覆盖层间穿孔102从模塑层140a暴露出的顶部部分。也就是说，第一通孔118及第二通孔138、以及层间穿孔102的顶部部分从模塑层140a的顶表面突出。在示例性实施例中，举例来说，第一通孔118及第二通孔138具有晶种层118a、138a以及金属层118b、138b。第一通孔118及第二通孔138可以如下方式形成。首先，在钝化层116、126之上形成晶种层，且在钝化层116、126之上形成具有开口的掩模，所述开口暴露出晶种层的一部分。晶种层的材料可包括例如铜、铜合金、或其他合适的材料选项。在一些实施例中，晶种层可通过物理气相沉积或其他可适用的方法形成。接着，将金属材料填充到掩模的开口中，从而形成金属层118b、138b。在一些实施例中，所述金属材料可通过镀覆工艺形成。所述镀覆工艺例如为电镀、无电镀覆、浸镀等。金属材料例如为铜、铜合金、或类似材料。晶种层与金属材料可包含相同的材料。然后，移除掩模，且对晶种层进行图案化以形成晶种层118a、138a。在一些实施例中，晶种层118a、138a仅设置在金属层118b、138b的底部上，且在金属层118b、138b的侧壁上未设置有晶种层。在一些替代实施例中，可省略晶种层，第一通孔118及第二通孔138可通过其他合适的方法形成。
参照图3D，在模塑层140a上形成。介电层142与下伏的元件及模塑层140a共形地形成。换句话说，介电层142的顶表面不是平面。介电层142的材料不同于模塑层140a的材料，且介电层142不含填料。如图3D所示，介电层142形成在模塑层140a、第一芯片110的有源表面112及第二芯片130的有源表面132、以及第一通孔118、及第二通孔138以及层间穿孔102的从模塑层140a暴露出的顶部部分之上，使得整体的层间穿孔102、第一芯片110及第二芯片130以及第一通孔118及第二通孔138共同地被模塑层140a及介电层142包封。在一些实施例中，第一通孔118及第二通孔138、以及层间穿孔102的顶部部分被介电层142包封。也就是说，介电层142的顶表面高于层间穿孔102的顶表面且高于第一通孔118的顶表面及第二通孔138的顶表面。在一些实施例中，举例来说，介电层142的厚度(从模塑层140a的顶表面到介电层142的顶表面测量)介于约10μm到约15μm范围内。在示例性实施例中，介电层142的材料包括无填料的聚合材料，且所述聚合材料选自低温可固化聚酰亚胺(PI)材料、高温可固化聚酰亚胺(PI)材料、感光性干膜材料或非感光性干膜材料、环氧树脂、苯并环丁烯、聚苯并恶唑、或任何其他适合的介电材料。在一些实施例中，介电层142是通过涂布工艺、沉积工艺或其他可适用的方法形成。
参照图3E，在一些实施例中，对介电层142执行平面化工艺以形成介电层142’，以使得介电层142的一些部分及层间穿孔102的一些部分被移除，且使得第一芯片110的第一通孔118及第二芯片130的第二通孔138从介电层142’暴露出。作为另外一种选择，在一个实施例中，也可移除第一通孔118的一些部分及第二通孔138的一些部分。在一些实施例中，在平面化之后，介电层142’具有平面顶表面，且第一通孔118及第二通孔138、层间穿孔102、以及介电层142’变得平坦且实质上齐整(即，第一通孔118的顶表面及第二通孔138的顶表面以及层间穿孔102的顶表面与介电层142’的经抛光顶表面实质上共面且齐平)。在一些实施例中，用于将介电层142及层间穿孔102平面化的平面化工艺包括飞切(fly cut)工艺、研磨工艺、或化学机械抛光(“CMP”)工艺。在一些实施例中，举例来说，平面介电层142’的厚度(从模塑层140a的平面顶表面到介电层142’的平面顶表面测量)介于约5μm到约10μm范围内。第一通孔118及第二通孔138、以及层间穿孔102从平面介电层142’的顶表面暴露出以进一步进行连接。平面介电层142’与模塑层140a构成复合模塑化合物。由于介电层142’的材料不含填料且具有更好的流动性(flow ability)，因而介电层142’可在下伏元件及模塑层140a之上提供更好的覆盖与填充能力，从而使模塑层140a与介电层142’的复合结构得到更好的表面平坦度以及结构完整性与强度。
参照图3F，在一些实施例中，形成与第一芯片110的第一通孔118及第二芯片130的第二通孔138、以及层间穿孔102电连接的重布线层150。
参照图3G，在一些实施例中，在形成重布线层150之后，将多个导电端子160放置在球下金属图案156a上，且将多个无源组件162安装在连接接垫156b上。
参照图3H，在将导电端子160及无源组件162安装在重布线层150上之后，将形成在模塑层140a的底表面上的介电层DI从剥离层DB剥离以使得介电层DI与载体C分离。接着，将多个导电端子164放置在接触开口中，且形成多个接触开口O来局部地暴露出层间穿孔102。在一些实施例中，可通过紫外激光来照射剥离层DB(例如，光热转换释放层)，以使得将粘合在模塑层140a的底表面上的介电层DI从载体C剥落。如图3H所示，接着将介电层DI图案化，以使得形成多个接触开口O来局部地暴露出层间穿孔102。接触开口O的数目对应于层间穿孔102的数目。在一些实施例中，介电层DI的接触开口O是通过激光钻孔工艺(laserdrilling process)、机械钻孔工艺(mechanical drilling process)、或其他合适的工艺形成。
参照图3I，在介电层DI中形成接触开口O之后，将多个导电端子164放置在接触开口O中，且将导电端子164电连接到层间穿孔102。此处，实质上已完成集成扇出型(INFO)封装10的形成。在一些实施例中，集成扇出型封装10可与其他电子器件进行堆叠。举例来说，提供另一封装(例如，集成电路(integrated circuit，IC)封装)，且通过导电端子164将所述封装堆叠在集成扇出型封装10之上并电连接到集成扇出型封装10以使得制作出叠层封装(package-on-package，POP)结构。
图4是示出根据一些示例性实施例的半导体封装的示意性剖视图。在图4中，阐述与图3I所示结构相似的半导体封装10，只是省略了层间穿孔。在一些实施例中，第一芯片110及第二芯片130在与有源表面112、132相对的表面上具有接垫122、124，接触开口O被形成为局部地暴露出接垫122、124，且导电端子164被放置在与接垫122、124对应的接触开口O中。
图5A至图5F是根据本公开的一些示例性实施例的半导体封装的制造方法中的各个阶段的示意性剖视图。图3C至图3I的方法与图5A至图5F的方法之间的差异在于第一通孔及第二通孔的形成方法。以下详细示出所述差异，且本文中不再对相似之处进行重复说明。
参照图5A，提供图3B所示结构，且在模塑层140a上形成具有开口144的介电层142，且第一芯片110的接垫114的一些部分及第二芯片130的接垫134的一些部分被开口144暴露出。在一些实施例中，介电层142可通过物理气相沉积或其他可适用的方法形成，且开口144通过光刻工艺及蚀刻工艺形成。介电层142与下伏的元件及模塑层140a实质上共形地形成，且因此介电层142的顶表面不是平面。在一些实施例中，介电层142的顶表面高于层间穿孔102的顶表面，且因此层间穿孔102被包封在介电层142及模塑层140a中。介电层142的形成方法、材料及厚度与图3D所阐述的介电层142的形成方法、材料及厚度相似。
参照图5B，在介电层142上形成导电层148且导电层148填充在开口144中。在一些实施例中，导电层148通过以下方法形成：在介电层142的顶表面上以及开口144的侧壁及底部上形成晶种层148a；以及接着在晶种层148a上形成金属层148b并填充开口144。晶种层148a及金属层148b的形成方法及材料与图3C所阐述的晶种层及金属层的形成方法及材料相似。
参照图5C，对介电层142及导电层148执行平面化工艺以形成介电层142’及在介电层142’中形成第一通孔118及第二通孔138。在一些实施例中，用于将介电层142、层间穿孔102、及导电层148平面化的平面化工艺包括飞切工艺、研磨工艺、或化学机械抛光(“CMP”)工艺。在一些实施例中，第一通孔118包括晶种层118a及金属层118b，且第二通孔138包括晶种层138a及金属层138b。在一些实施例中，在平面化之后，介电层142’具有平面顶表面，且第一通孔118及第二通孔138、层间穿孔102、以及介电层142’变得平坦且实质上齐整(即，第一通孔118的顶表面及第二通孔138的顶表面以及层间穿孔102的顶表面与介电层142’的经抛光顶表面实质上共面且齐平)。
参照图5D，在一些实施例中，形成与第一芯片110的第一通孔118及第二芯片130的第二通孔138、以及层间穿孔102电连接的重布线层150。在形成重布线层150之后，将多个导电端子160放置在球下金属图案156a上，且将多个无源组件162安装在连接接垫156b上。
参照图5E，将形成在模塑层140a的底表面上的介电层DI从剥离层DB剥离以使得介电层DI与载体C分离。接着，将多个导电端子164放置在接触开口中，且形成多个接触开口O来局部地暴露出层间穿孔102。
参照图5F，将多个导电端子164放置在接触开口O中，且将导电端子164电连接到层间穿孔102。此处，实质上已完成集成扇出型(INFO)封装10的形成。
图6是示出根据一些示例性实施例的半导体封装的示意性剖视图。在图6中，阐述与图5F所示结构相似的半导体封装10，只是省略了层间穿孔。在一些实施例中，第一芯片110及第二芯片130在与有源表面112、132相对的表面上具有接垫122、124，接触开口O被形成为局部地暴露出接垫122、124，且导电端子164被放置在接触开口O中。另外，在一些实施例中，介电层142’被用作重布线层150的最底部层间介电层，且因此可无需额外地形成最底部层间介电层，这会减少半导体封装的工艺及成本。
在一些实施例中，各芯片之间的厚度差异通过增加具有不同厚度的粘合层而得到补偿。因此，可将不同类型的芯片放置在载体上以进行封装。在一些实施例中，模塑层被形成为使其顶表面不高于芯片的有源表面，即，模塑层并非是通过包覆模塑(over-molding)技术来形成。因此，不需要对模塑层进行平面化工艺，且防止出现因对包含填料的模塑层执行平面化工艺而引起的凹坑问题。另外，在模塑层之上形成介电层并将所述介电层平面化，以提供更好的平面表面，此有益于稍后在所述介电层上形成金属线或配线、尤其是对于具有精细的线/空间(line/space)的金属线来说。另外，所述介电层为芯片的通孔提供绝缘，且因此，芯片的通孔不需要钝化层。换句话说，形成模塑层及覆盖所述模塑层的介电层会在材料选择方面提供灵活性、为模塑层提供更大的工艺窗口、并且提高具有精细的线/空间的重布线层的可靠性、且使制造方法简单。因此，可降低半导体封装的成本，且可提高半导体封装的性能。
根据一些实施例，一种半导体封装包括第一芯片、第二芯片及模塑化合物。所述第一芯片上具有至少一个第一通孔及保护层，且所述至少一个第一通孔形成在所述保护层中。所述第二芯片上具有至少一个第二通孔。所述模塑层包封所述第一芯片及所述第二芯片。所述至少一个第二通孔设置在所述模塑层中且与所述模塑层接触，且所述保护层的顶表面、所述至少一个第一通孔的顶表面及所述至少一个第二通孔的顶表面与所述模塑层的顶表面实质上共面。
在一些实施例中，还包括重布线层，所述重布线层设置在所述模塑层之上且电连接到所述至少一个第一通孔及所述至少一个第二通孔。
在一些实施例中，所述第一芯片的厚度不同于所述第二芯片的厚度。
在一些实施例中，所述模塑层包含不含有填料的材料。
在一些实施例中，所述模塑层设置在所述至少一个第二通孔之间。
根据一些实施例，一种半导体封装包括第一芯片、模塑层、及介电层。所述第一芯片上具有至少一个第一通孔，所述至少一个第一通孔包括晶种层及导电层，且所述晶种层沿所述导电层的侧壁及底部设置。所述模塑层包封所述第一芯片，且所述模塑层的顶表面不高于所述第一芯片的有源表面。介电层位于所述模塑层之上，且所述至少一个第一通孔设置在所述介电层中。
在一些实施例中，还包括第二芯片，所述第二芯片上具有至少一个第二通孔，其中所述至少一个第二通孔设置在所述介电层中。
在一些实施例中，所述至少一个第二通孔包括导电层及沿所述导电层的侧壁及底部设置的晶种层。
在一些实施例中，所述介电层设置在所述至少一个第一通孔与所述至少一个第二通孔之间。
在一些实施例中，所述第一芯片的厚度不同于所述第二芯片的厚度。
在一些实施例中，所述介电层具有平面表面。
在一些实施例中，所述模塑层的所述顶表面与所述第一芯片的所述有源表面实质上齐平。
在一些实施例中，所述模塑层的所述顶表面具有碟状凹陷。
在一些实施例中，还包括重布线层，所述重布线层位于所述介电层之上且电连接到所述至少一个第一通孔。
根据一些实施例，一种半导体封装的制造方法包括至少以下步骤。在载体上提供具有第一粘合层的第一芯片及具有第二粘合层的第二芯片，且所述第一芯片的有源表面与所述第二芯片的有源表面实质上共面。形成模塑层以包封所述第一芯片及所述第二芯片，且所述模塑层的顶表面不高于所述第一芯片的所述有源表面及所述第二芯片的所述有源表面。在所述模塑层之上的介电层中形成至少一个第一通孔及至少一个第二通孔。所述至少一个第一通孔及所述至少一个第二通孔分别设置在所述第一芯片及所述第二芯片上，且所述介电层的顶表面、所述至少一个第一通孔的顶表面及所述至少一个第二通孔的顶表面实质上共面。
在一些实施例中，所述形成所述至少一个第一通孔、所述至少一个第二通孔及所述介电层的步骤包括：分别在所述第一芯片及所述第二芯片上形成所述至少一个第一通孔及所述至少一个第二通孔；在所述模塑层之上形成所述介电层，以覆盖所述至少一个第一通孔及所述至少一个第二通孔；以及执行平面化工艺，以移除所述介电层的一部分来暴露出所述至少一个第一通孔的顶表面及所述至少一个第二通孔的顶表面。
在一些实施例中，所述形成所述至少一个第一通孔及所述至少一个第二通孔以及所述介电层的步骤包括：在所述模塑层之上形成所述介电层；在所述介电层中形成多个开口；在所述介电层之上形成导电层，所述导电层填充所述开口；以及执行平面化工艺，以移除所述导电层的部分以及所述介电层的部分，从而形成设置在所述介电层中的所述至少一个第一通孔及所述至少一个第二通孔。
在一些实施例中，所述形成所述导电层的步骤包括：在所述介电层之上形成晶种层，其中所述晶种层形成在所述开口中的每一开口的侧壁及底部上；以及从所述晶种层形成金属层。
在一些实施例中，还包括：在所述介电层之上形成重布线层，以分别电连接到所述至少一个第一通孔及所述至少一个第二通孔。
在一些实施例中，所述模塑层包含具有填料的材料。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开内容的各个方面。所属领域中的技术人员应知，其可容易地使用本公开内容作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开内容的精神及范围，而且他们可在不背离本公开内容的精神及范围的条件下对其作出各种改变、代替、及变更。

Claims (1)

1.一种半导体封装，其特征在于，包括：
第一芯片，所述第一芯片上具有至少一个第一通孔及保护层，其中所述至少一个第一通孔设置在所述保护层中；
第二芯片，所述第二芯片上具有至少一个第二通孔；以及
模塑层，包封所述第一芯片及所述第二芯片，其中所述至少一个第二通孔设置在所述模塑层中且与所述模塑层接触，且所述保护层的顶表面、所述至少一个第一通孔的顶表面及所述至少一个第二通孔的顶表面与所述模塑层的顶表面实质上共面。
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US10692838B2 (en) 2020-06-23
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US20190148341A1 (en) 2019-05-16
US10163858B1 (en) 2018-12-25
US11756929B2 (en) 2023-09-12
US11322479B2 (en) 2022-05-03
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US20210288026A1 (en) 2021-09-16

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