CN109560462B - Silicon-based hybrid integrated laser array and preparation method thereof - Google Patents

Abstract

The invention discloses a silicon-based hybrid integrated laser array and a preparation method thereof. The silicon-based hybrid integrated laser array includes: a plurality of parallel-arranged silicon-based hybrid integrated lasers fabricated on an SOI substrate and a III-V semiconductor epitaxial layer; wherein each silicon-based hybrid integrated laser includes: a silicon ridge waveguide; a thermal conductive layer , located in a specific area on both sides of the silicon ridge waveguide, the specific area is the area obtained after removing the top silicon and buried oxide layers from the SOI substrate; the intrinsic layer, which is in the shape of a saddle, includes protrusions and connecting parts at both ends, one of which is The protrusions at both ends are covered above the thermally conductive layer; the intrinsic layer connecting part is sequentially provided with an N-type waveguide layer, an active region, and a P-type capping layer; the III‑V waveguide is formed by patterning a III‑V semiconductor epitaxial layer, and is connected with silicon. Ridge waveguides are connected; P-type ohmic contact layer, P-electrode and N-electrode. The heat dissipation is good, the preparation process is simple and stable, the repeatability is good, and the production cost is low.

Description

Silicon-based hybrid integrated laser array and preparation method thereof

technical field

The present disclosure belongs to the technical field of lasers, and relates to a silicon-based hybrid integrated laser array and a preparation method thereof.

Background technique

With the development of technology, people have higher and higher requirements for data transmission rate, transmission bandwidth and energy consumption. Restricted by the physical characteristics of electronics, traditional electrical interconnections based on electronic integrated chips have energy consumption when transmitting high-speed signals. However, photons have the characteristics of ultra-high transmission speed, ultra-high parallelism, ultra-high bandwidth and ultra-low transmission and interaction power consumption. Since silicon photonics integration combines the ultra-large-scale logic, ultra-high-precision manufacturing, and low-cost advantages of CMOS technology, silicon-based optical interconnects are expected to break through the above bottlenecks in rate, power consumption, bandwidth, and cost.

Silicon photonics integration technology has been greatly developed after preliminary research, but the light source is still a worldwide problem. Since Intel invented the first electrically injected silicon-based hybrid integrated laser in 2006, silicon-based hybrid integrated lasers have been extensively studied. However, modern communication technology usually uses multiplexing technology to improve communication capacity, and research on silicon-based hybrid integrated III-V laser arrays is urgently needed.

At present, there are three common methods for realizing silicon-based hybrid integrated laser arrays. The first method is to bond SOI silicon-based materials and III-V epitaxial materials together by direct wafer bonding or dielectric bonding, and fabricate multiple parallel ridge waveguides on SOI or III-V epitaxial materials. Fabrication of microstructures or curved waveguides on ridge waveguides is used to select wavelengths to realize silicon-based hybrid integrated laser arrays. However, none of the silicon-based hybrid integrated laser arrays mentioned in this solution considers the influence of the poor heat dissipation characteristics of the buried oxide layer (BOX) in the SOI on the laser array. The second method is to directly epitaxially grow III-V semiconductor materials on SOI by MOCVD or MBE, fabricate ridge waveguides on SOI or III-V, and fabricate microstructures on the ridge waveguides for wavelength selection. Although this scheme can realize a self-aligned silicon-based hybrid integrated laser on a SOI material, and does not require precise alignment technology between SOI and III-V, the requirements for epitaxy technology are very high, and the current technology is still immature. It needs to be explored, and the influence of the poor heat dissipation characteristics of the buried oxide layer in the SOI substrate on the device has not been studied. The third method is to couple the prepared III-V laser array with multiple silicon-based waveguide end faces on the SOI in the form of 3D integration or packaging after multiple parallel silicon-based waveguides are fabricated on the SOI. In the form of 3D integration or packaging, it is necessary to precisely align the silicon waveguide on the SOI material with the optical ends of the III-V semiconductor laser array, which requires high packaging technology and high cost. At the same time, it is necessary to consider how to improve End face coupling efficiency.

SUMMARY OF THE INVENTION

(1) Technical problems to be solved

The present disclosure provides a silicon-based hybrid integrated laser array and a preparation method thereof to at least partially solve the above-mentioned technical problems.

(2) Technical solutions

According to one aspect of the present disclosure, a silicon-based hybrid integrated laser array is provided, comprising: a plurality of parallel-arranged silicon-based hybrid integrated lasers fabricated on an SOI substrate and a III-V semiconductor epitaxial layer; wherein each silicon-based hybrid integrated laser array is The base hybrid integrated laser includes: a silicon ridge waveguide; a thermal conductive layer, located in a specific area on both sides of the silicon ridge waveguide, the specific area is the area obtained after removing the top silicon and buried oxide layers of the SOI substrate; an intrinsic layer, the shape of which is a saddle shape , including protrusions and connecting parts at both ends, of which the protrusions at both ends are covered above the thermal conductive layer; the N-type waveguide layer is formed on the connecting part of the intrinsic layer; the active region is formed on the N-type waveguide layer. ; P-type cap layer, formed on the active area; III-V waveguide, formed by patterning III-V semiconductor epitaxial layer, both ends are connected with the front and rear ends of the silicon ridge waveguide, and the structures on both sides are patterned Unetched P-type cap layer and active region below; P-type ohmic contact layer on the III-V waveguide; P-electrode on top of the P-type ohmic contact layer; and N-electrode on the N-type ohmic contact layer above the waveguide layer.

In some embodiments of the present disclosure, the SOI substrate and the III-V semiconductor epitaxial layer are bonded together by bonding, and the bonding includes: metal bonding, dielectric bonding or direct wafer bonding, silicon ridge waveguide and III-V waveguides are fabricated on SOI substrates and III-V semiconductor epitaxial layers, respectively, and then the SOI substrate and III The -V semiconductor epitaxial layers are combined together.

In some embodiments of the present disclosure, each III-V waveguide is in a one-to-one correspondence with each silicon ridge waveguide and is vertically aligned.

In some embodiments of the present disclosure, the SOI substrate sequentially includes, from bottom to top, a substrate silicon, a buried oxide layer, and a top layer silicon. The silicon ridge waveguide is fabricated by patterning the SOI substrate, and is made of the top layer silicon of the SOI substrate. Formed after patterning and etching; the III-V semiconductor epitaxial layer sequentially includes from bottom to top: an intrinsic layer, an N-type waveguide layer, an active region, a P-type cap layer and a P-type ohmic contact layer. The V-waveguide is fabricated by patterning the III-V semiconductor epitaxial layer and then etching the P-type ohmic contact layer, the P-type cap layer, the active region and the N-type waveguide layer.

In some embodiments of the present disclosure, along the direction of the silicon ridge waveguide, the structures at both ends of the silicon ridge waveguide include: a wedge-shaped ridge waveguide and/or a straight ridge waveguide; along the direction of the III-V waveguide, the III-V waveguide The structures at both ends include: wedge-shaped waveguides and/or straight waveguides.

In some embodiments of the present disclosure, the III-V waveguide includes a wedge-shaped waveguide in front and rear sections and a straight waveguide in the middle section. The front and rear ends of the waveguide are connected, and the straight waveguide in the middle section is etched to the lower part of the P-type capping layer; the remaining unetched P-type capping layer is located on both sides of the III-V waveguide, and the active area is located in the P-type cap layer. Under the type cap layer, it is also located on both sides of the III-V waveguide.

In some embodiments of the present disclosure, the material of the thermal conductive layer includes: metal or alloy material, including: SnAu, Sn, Ag, Cu, Au, Al, Fe, or CuAl; semiconductor material, including: polysilicon, single crystal silicon, non- Crystalline silicon or germanium; inorganic non-metallic materials, including: graphene, graphite, carbon fiber, C/C composite materials or carbon black; and thermally conductive polymer materials; and/or P-type ohmic contact regions in III-V semiconductor epitaxial layers, The materials of the P-type cap layer, active region, N-type waveguide layer and intrinsic layer include: any of binary, ternary, and quaternary materials of indium phosphide, gallium arsenide, and gallium antimonide materials two or more.

In some embodiments of the present disclosure, the silicon-based hybrid integrated laser array further includes: a microstructure formed on the structure of the silicon ridge waveguide or the III-V waveguide.

In some embodiments of the present disclosure, the topography of the microstructure includes: one-dimensional, two-micro, and three-dimensional geometric shapes, and the structure includes: grating, photonic crystal or micro-groove; by adjusting the microstructure in each silicon-based hybrid integrated laser The parameters of the structure can realize the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array.

According to another aspect of the present disclosure, a method for fabricating a silicon-based hybrid integrated laser array is provided, comprising: fabricating a plurality of silicon ridge waveguides arranged in parallel on an SOI substrate; fabricating a specific silicon ridge waveguide on the SOI substrate containing the silicon ridge waveguides area, and grow a thermal conductive layer on a specific area; use III-V semiconductor material to epitaxially grow intrinsic layer, N-type waveguide layer, active region, P-type cap layer and P-type ohmic contact layer in turn to form III-V semiconductor epitaxy layer; patterning is performed on the III-V semiconductor epitaxial layer, the saddle-shaped intrinsic layer, the III-V waveguide and the structure on both sides of the III-V waveguide are etched, and the P electrode and the N electrode are grown; will contain silicon ridges The SOI substrate of the waveguide and the thermally conductive layer is bonded with the III-V semiconductor epitaxial layer containing the III-V waveguide, P electrode, and N electrode; and the microstructure is fabricated on the structure of the silicon ridge waveguide or the III-V waveguide to complete the silicon substrate Fabrication of hybrid integrated laser arrays.

(3) Beneficial effects

It can be seen from the above technical solutions that the silicon-based hybrid integrated laser array and the preparation method thereof provided by the present disclosure have the following beneficial effects:

In each silicon-based hybrid integrated laser constituting the array, the top silicon and buried oxide layers are removed in specific areas on both sides of the silicon ridge waveguide to expose the substrate silicon, and then metal or high thermal conductivity materials are filled in this area. The heat generated when the active area emits light is dissipated into the substrate silicon through the N-type waveguide layer, the intrinsic layer and the metal and high thermal conductivity materials in this area, so as to solve the problem of the poor thermal conductivity of the buried oxide layer in the SOI material, which affects the silicon substrate. The problem of poor heat dissipation characteristics of hybrid integrated lasers improves the heat dissipation characteristics and optoelectronic characteristics of silicon-based hybrid integrated laser arrays; in addition, III-V semiconductor epitaxial materials are epitaxially formed by MBE or MOCVD once, and secondary epitaxy and selective growth technology are not required. , the process is simple and stable; the structure on SOI can be compatible with the mature CMOS process, the process is stable, the repeatability is good, and the production cost is low; the structure on the III-V semiconductor material can be compatible with the traditional optoelectronic process technology. High repeatability.

Description of drawings

FIG. 1 is a schematic structural diagram of a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.

2 is a schematic structural diagram of a silicon-based hybrid integrated laser in a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.

3 is a schematic cross-sectional view of the structure of a silicon-based hybrid integrated laser in a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.

4 is a schematic diagram of a cross-sectional thermal distribution of a silicon-based hybrid integrated laser without specific regions and thermal conductive layers on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure.

5 is a schematic diagram of a cross-sectional heat distribution of a silicon-based hybrid integrated laser with specific regions and a thermal conductive layer on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure.

【Symbol Description】

100-silicon-based hybrid integrated laser array; 400-silicon-based hybrid integrated laser;

200-SOI substrate;

201-substrate silicon; 202-buried oxide layer;

203 - top layer silicon; 204 - silicon ridge waveguide;

300-III-V semiconductor epitaxial layer;

301-P type ohmic contact layer; 302-P type capping layer;

303-active region; 304-N-type waveguide layer;

305-intrinsic layer; 306-III-V waveguide;

307-P electrode; 308-N electrode;

500 - microstructure; 700 - thermally conductive layer.

Detailed ways

The present disclosure provides a silicon-based hybrid integrated laser array and a preparation method thereof, which have good heat dissipation properties and optoelectronic properties, and III-V semiconductor epitaxial materials are epitaxially formed by MBE or MOCVD once, and do not require secondary epitaxy and selective growth. Technology, the process is simple and stable; the structure on SOI can be compatible with mature CMOS process, the process is stable, the repeatability is good, and the production cost is low; the structure on III-V semiconductor materials can be compatible with traditional optoelectronic process technology, and there are higher repeatability.

In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the specific embodiments and the accompanying drawings.

In a first exemplary embodiment of the present disclosure, a silicon-based hybrid integrated laser array is provided.

FIG. 1 is a schematic structural diagram of a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure. FIG. 2 is a schematic structural diagram of a silicon-based hybrid integrated laser in a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure. 3 is a schematic cross-sectional view of the structure of a silicon-based hybrid integrated laser in a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.

1-3, the silicon-based hybrid integrated laser array 100 of the present disclosure includes multiple parallel silicon-based hybrid integrated lasers 400 fabricated on the SOI substrate 200 and the III-V semiconductor epitaxial layer 300, Each silicon-based hybrid integrated laser 400 includes: a substrate silicon 201; a buried oxide layer 202; a silicon ridge waveguide 204; , including protrusions and connecting parts at both ends, one of the protrusions at both ends is located on both sides of the silicon ridge waveguide 204 and covers the thermal conductive layer 700; the N-type waveguide layer 304 is located above the silicon ridge waveguide 204 and is formed in the intrinsic layer 305 on the connecting portion; active region 303, formed on the N-type waveguide layer 304; P-type capping layer 302, formed on the active region 303; III-V waveguide 306, formed by III-V semiconductor epitaxy The layer 300 is formed by patterning and is connected to the rear end of the silicon ridge waveguide 204, and the two sides are the P-type capping layer 302 that has not been etched after the patterning and the active region 303 below; the P-type ohmic contact layer 301 is located in III - over V waveguide 306; P electrode 307, formed over P-type ohmic contact layer 301; N electrode 308, formed over N-type waveguide layer 304; and microstructure 500, formed over silicon ridge waveguide 204 or III- On the structure of the V-waveguide 306; wherein, a specific area is located on both sides of the silicon ridge waveguide, and the heat-conducting layer 700 is obtained by removing the top layer of silicon and the buried oxide layer in the area and then growing a heat-conducting material.

Each part of the silicon-based hybrid integrated laser array of this embodiment will be described in detail below with reference to FIG. 2 and FIG. 3 .

In this embodiment, the SOI substrate 200 includes, from bottom to top, a substrate silicon 201 , a buried oxide layer 202 and a top layer silicon 203 .

In this embodiment, the thickness of the buried oxide layer 202 of the SOI substrate 200 is 2 μm; the thickness of the top layer silicon is 220 nm; the width of the plurality of parallel silicon ridge waveguides 204 fabricated on the top layer silicon is 3 μm.

The silicon ridge waveguide 204 is fabricated by patterning the SOI substrate 200 , and is formed by patterning and etching the top layer silicon 203 of the SOI substrate 200 .

In this embodiment, along the direction of the silicon ridge waveguide 204 , the structures at both ends of the silicon ridge waveguide 204 can be wedge-shaped ridge waveguides or straight ridge waveguides, and the width and height can be arbitrary values. Formed by patterning; in the manufacturing process, the structures on both sides of the silicon ridge waveguide 204 are also formed by patterning the top layer silicon 203 of the SOI substrate 200 , as shown in FIG. The pattern formed; the structure on both sides of the silicon ridge waveguide 204 and the pattern of the silicon ridge waveguide 204 can be designed on a photolithography plate, and then the silicon ridge waveguide 204 and the patterns on both sides thereof are formed by one photolithography.

The thermal conductive layer 700, located on both sides of the silicon ridge waveguide 204, is formed by growing a thermal conductive material on the substrate silicon 201 after the top silicon 203 and the buried oxide layer 202 on both sides of the silicon ridge waveguide 204 in the SOI substrate 200 are etched away. In this embodiment, the specific area where the thermally conductive layer is located is located on both sides of the silicon ridge waveguide 204 and is 15 μm away from the silicon ridge waveguide. The size of the specific area is as follows: 100 μm in length and 1 mm in width.

In this embodiment, the materials of the thermal conductive layer 700 include, but are not limited to, metals or alloy materials such as SnAu, Ag, Cu, Au, Al, Fe, and CuAl, semiconductor materials such as polysilicon, single crystal silicon, amorphous silicon, germanium, and graphite. Inorganic non-metallic materials such as ene, graphite, carbon fiber, C/C composite material, carbon black, and thermally conductive polymer materials, etc.; in this embodiment, metal materials with good thermal conductivity or high thermal conductivity materials are preferred.

In this embodiment, the III-V semiconductor epitaxial layer 300 is formed by one-time epitaxial growth of MBE or MOCVD, which does not require secondary epitaxy and selective growth technology, and the process is simple and stable. The III-V semiconductor epitaxial layer 300 structure from top to bottom at least includes: a P-type ohmic contact layer 301, a P-type capping layer 302, an active region 303, an N-type waveguide layer 304 and an intrinsic layer 305. The structure fabricated on the epitaxial layer 300 at least includes: a plurality of III-V waveguides 306 arranged in parallel, P electrodes 307 and N electrodes 308, wherein the P electrodes 307 are fabricated on the P-type ohmic contact layer 301, and the N electrodes 308 are fabricated over the N-type waveguide layer 304 .

In this embodiment, the materials of the P-type ohmic contact region 301 , the P-type capping layer 302 , the active region 303 , the N-type waveguide layer 304 and the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 include but are not limited to the following materials: Any two or more of the binary, ternary, and quaternary materials of steel phosphide, gallium arsenide, and gallium antimonide materials, and the components of any ternary and quaternary materials can be is a different value, and can also be a gradient value.

The III-V waveguide 306 is formed by patterning the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300, the N-type waveguide layer 304, the active region 303, the P-type capping layer 302 and the P-type ohmic contact region 301, including the front , the rear wedge-shaped waveguide and the middle straight waveguide, wherein the front and rear wedge-shaped waveguides are etched to the bottom of the N-type waveguide layer 304, and are connected to the front and rear ends of the silicon ridge waveguide 204, and the middle straight waveguide is etched To the lower part of the P-type capping layer 302, the remaining unetched P-type capping layer 302 is located on both sides of the III-V waveguide 306; the active region is located under the P-type capping layer 302, and is also located in the III-V waveguide Both sides of the V-waveguide 306 .

In the present embodiment, along the direction of the III-V waveguide 306 , the structures at both ends of the III-V waveguide 306 may be wedge-shaped waveguides or straight waveguides, and the width and height may be arbitrary values, determined by the III-V semiconductor epitaxial layer 300 The intrinsic layer 305 , the N-type waveguide layer 304 , the active region 303 , the P-type cap layer 302 , and the P-type ohmic contact region 301 are formed by patterning. In this embodiment, the III-V waveguide 306 includes front and rear sections. The wedge-shaped waveguide and the middle straight waveguide, wherein the front and rear wedge-shaped waveguides are etched to the bottom of the N-type waveguide layer 304 and connected to the front and rear ends of the silicon ridge waveguide 204, and the middle straight waveguide is etched to the P-type In the lower part of the cap layer 302, the remaining part of the P-type cap layer 302 is not etched away. In the manufacturing process, the structures on both sides of the III-V waveguide 306 are also formed by patterning the III-V semiconductor epitaxial layer 300 , see the straight waveguide shape on both sides of the III-V waveguide 306 in FIG. 2 , including the active region 303 and The unetched P-type cap layer 302; the structure on both sides of the III-V waveguide 306 and the pattern of the III-V waveguide 306 can be designed on a lithography plate, and then a single photolithography and etching are used to form silicon Ridge waveguide 204 and the patterns on its sides.

Referring to FIGS. 1 and 2 , the intrinsic layer 305 is saddle-shaped and includes protruding parts and connecting parts at both ends, wherein the protruding parts at one end are located on both sides of the silicon ridge waveguide 204 and cover the thermal conductive material 700 ; The shape of the intrinsic layer 305 is also formed by patterning the III-V semiconductor epitaxial layer 300 .

In the present disclosure, each III-V waveguide 306 has a one-to-one correspondence with each silicon ridge waveguide 204 and is vertically aligned.

In this embodiment, the materials of the III-V semiconductor epitaxial layer 300 include, but are not limited to, one or more of three material systems: indium phosphorus, gallium arsenide, and gallium antimony; the active region is made of indium phosphorus. The quantum well or quantum dot structure composed of the gallium arsenide system and the gallium arsenide system is not limited to these two material systems and the two structures of the quantum well and the quantum dot.

Preferably, the P-type cap layer 302 in the III-V semiconductor epitaxial layer 300 is made of InP material, with a thickness of 1.5 μm; the material of the P-type ohmic contact layer 301 is InGaAs, and the P-type InP cap layer and the P-type InGaAs ohmic contact layer are made of InGaAs. A plurality of P-type III-V ridge waveguides arranged in parallel are fabricated on the ridge, the width of the ridge waveguide is 5 μm, the etching depth is about 1.3 μm, and the end width of the wedge-shaped III-V ridge waveguide at both ends is 400 nm; active The region 303 is made of AlGaInAs material, and its gain peak is around 1.55 μm.

In this embodiment, the SOI substrate 200 and the III-V semiconductor epitaxial layer 300 are bonded together by metal bonding, dielectric bonding or direct wafer bonding. The silicon ridge waveguide 204 and the III-V waveguide 306 are respectively It is fabricated on the SOI substrate 200 and the III-V semiconductor epitaxial layer 300, and then the SOI substrate 200 and the III-V semiconductor epitaxial layer are formed by physically placing the saddle-shaped intrinsic layer 305 on the thermal conductive layer 700. 300 combined.

The thermal conductive layer 700 is in contact with the intrinsic layer 305, so that the heat generated by the active region 303 is transferred into the thermal conductive layer 700 through the N-type waveguide layer 304 and the intrinsic layer 305 by means of heat transfer, and then transferred to the substrate through the thermal conductive layer In the silicon 201, the heat dissipation characteristics of the silicon-based hybrid integrated laser are effectively improved.

In this embodiment, the P electrode 307 is formed on the P-type ohmic contact layer 301; the N-electrode 308 is formed on the N-type waveguide layer 304, and there is a distance between the structures on both sides of the III-V waveguide 306, refer to shown in Figure 3.

In this embodiment, the setting of the microstructure 500 is for adjusting the lasing wavelength of the silicon-based hybrid integrated laser 400 . The microstructure 500 is formed on the structure of the silicon ridge waveguide 204 or the III-V waveguide 306, and its morphology can be one-dimensional, two-micro, or three-dimensional geometric shapes, including but not limited to grating and photonic crystal structures. By adjusting the parameters of the microstructure 500 in each silicon-based hybrid integrated laser array 100 in the silicon-based hybrid integrated laser array 100 , the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array 100 can be realized.

In this embodiment, a one-dimensional microstructure 500 is fabricated on the silicon ridge waveguide 204, and its period is about 230 nm.

In this embodiment, the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 is in contact with the metal thermal conductive layer 700 in a specific area, the N-type waveguide layer 304 is in contact with the silicon ridge waveguide 204, and the light emitted from the active area 303 By means of evanescent wave coupling, the N-type waveguide layer 304 is coupled into the silicon ridge waveguide 204, and the heat emitted by the active region 303 is introduced into the substrate through the N-type waveguide layer 304, the intrinsic layer 305 and the metal thermal conductive layer 700 in a specific area. Silicon 201 is lost.

In a second exemplary embodiment of the present disclosure, a method for fabricating a silicon-based hybrid integrated laser array is provided.

The preparation method of the silicon-based hybrid integrated laser array of the present disclosure includes:

Step S402: fabricating a plurality of silicon ridge waveguides arranged in parallel on the SOI substrate;

In this embodiment, the plurality of parallel-arranged silicon ridge waveguides 204 are formed by CMOS process photolithography, etching technology or optoelectronic process such as ordinary photolithography, electron beam exposure, holographic exposure, etching, focused ion beam FIB and other technologies. Fabricated on top layer silicon 203.

In this embodiment, the thickness of the buried oxide layer 202 of the SOI substrate 200 is 2 μm; the thickness of the top layer silicon is 220 nm; the width of the plurality of parallel silicon ridge waveguides 204 fabricated on the top layer silicon is 3 μm.

Step S404: fabricating a specific area on the SOI substrate containing the silicon ridge waveguide, and growing the thermally conductive layer 700 on the specific area;

In this embodiment, CMOS process photolithography, etching technology or optoelectronic process such as ordinary photolithography, electron beam exposure, holographic exposure, etching, FIB and other technologies are used in a specific area to separate part of the top layer silicon 203 of the SOI substrate 200 and buried oxygen. Layer 202 is formed after removal.

The thermally conductive layer 700 is prepared by growing different thermally conductive materials step by step by means of physical or chemical deposition such as thermal evaporation, magnetron sputtering, etc. The growth order of different thermally conductive materials can be changed; In order to improve the heat dissipation properties of the silicon-based hybrid integrated laser array.

In this embodiment, the specific area where the thermally conductive layer 700 is located is located on both sides of the silicon ridge waveguide 204 and is 15 μm away from the silicon ridge waveguide. The size of the specific area is as follows: 100 μm in length and 1 mm in width.

Step S406: using III-V semiconductor material to epitaxially grow the intrinsic layer, N-type waveguide layer, active region, P-type cap layer and P-type ohmic contact layer in sequence to form a III-V semiconductor epitaxial layer;

In this embodiment, the III-V semiconductor epitaxial layer 300 is prepared by one-time epitaxy by MBE or MOCVD.

The materials of the P-type ohmic contact region 301 , the P-type capping layer 302 , the active region 303 , the N-type waveguide layer 304 and the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 include but are not limited to the following materials: indium phosphide, arsenic Any two or more of the binary, ternary, and quaternary materials of the gallium and gallium antimonide material system, the components of any one of the ternary and quaternary materials can be different values, Can also be a gradient value.

Preferably, the P-type cap layer 302 is made of InP material with a thickness of 1.5 μm; the material of the P-type ohmic contact layer 301 is InGaAs, the active region 303 is made of AlGalnAs material, and its gain peak is around 1.55 μm.

Step S408: performing patterning processing on the III-V semiconductor epitaxial layer, etching the saddle-shaped intrinsic layer, the III-V waveguide and the structures on both sides of the III-V waveguide, and growing the P electrode and the N electrode;

The step S408 includes: using the designed pattern to pattern the III-V semiconductor epitaxial layer, and then partially etching the P-type ohmic contact layer 301, the P-type cap layer 302, the active region 303, and the N-type waveguide layer in sequence 304 to the bottom of the N-type waveguide layer 304 to form the front and rear wedge-shaped waveguides of the III-V waveguide; the other part is sequentially etched to the P-type ohmic contact layer 301 and the P-type cap layer 302 to the bottom of the P-type cap layer 302 to form III- The middle section of the V waveguide is a straight waveguide; the P-type capping layer 302 and the active region 303 are etched away on both sides of the edge to form an N-electrode growth region; the remaining unetched P-type capping layer 302 is located in the III- On both sides of the V waveguide 306, the active region 303 is located under the P-type cap layer 302, and also located on both sides of the III-V waveguide 306, forming a structure on both sides of the III-V waveguide; on the P-type ohmic contact layer A P electrode 307 is formed on top of 301 , and an N electrode 308 is formed on the N-electrode growth region on the N-type waveguide layer 304 .

The P-type III-V ridge waveguide 306 is fabricated by, but not limited to, the following fabrication techniques, such as photolithography, electron beam exposure, holographic exposure, wet etching or dry etching. The preparation methods of the N electrode and the P electrode adopt conventional preparation methods in the art, including thermal evaporation, magnetron sputtering, etc., which will not be repeated here.

In this embodiment, there is a gap between the N electrode 308 and the structures on both sides of the III-V waveguide.

The above designed graphics include: a saddle shape with protruding parts and connecting parts at both ends, and a III-V waveguide shape at the saddle-shaped connecting part. In this embodiment, the III-V waveguide includes the front and rear wedge-shaped waveguides and the middle An example of a segmented straight waveguide.

Step S410: bonding the SOI substrate containing the silicon ridge waveguide and the thermal conductive layer with the III-V semiconductor epitaxial layer containing the III-V waveguide, the P electrode, and the N electrode;

In this embodiment, the surface of the silicon ridge waveguide 204 in the SOI substrate 200 and the surface of the N-type waveguide layer 304 in the III-V semiconductor epitaxial layer 300 are in contact with each other, and are bonded by means of wafer bonding, metal bonding or dielectric bonding. together.

Step S412 : fabricating a microstructure on the structure of the silicon ridge waveguide or the III-V waveguide to complete the preparation of the silicon-based hybrid integrated laser array.

In this embodiment, the microstructure 500 may be fabricated on the III-V waveguide 306 by a CMOS process on the silicon ridge waveguide 204 or an optoelectronic process such as ordinary photolithography, electron beam exposure, holographic exposure, etching, and FIB.

The microstructure 500 can be one-dimensional, two-micro, or three-dimensional geometric shapes, including but not limited to gratings and photonic crystal structures, and the number of periods and geometric parameters can be any value.

In order to verify the beneficial effect of the silicon-based hybrid integrated laser array, simulation experiments with two contrasting structures were carried out. One structure was a silicon-based hybrid integrated laser without specific regions and thermal conductive layers on both sides of the silicon ridge waveguide, and the other structure It is a silicon-based hybrid integrated laser with a specific area and a heat-conducting layer on both sides of the silicon ridge waveguide. The thermal distribution experiments of the two-structure silicon-based hybrid integrated laser are carried out.

4 is a schematic diagram of a cross-sectional thermal distribution of a silicon-based hybrid integrated laser without specific regions and thermal conductive layers on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure. 5 is a schematic diagram of a cross-sectional heat distribution of a silicon-based hybrid integrated laser with specific regions and a thermal conductive layer on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure.

As shown in Figure 4, the maximum temperature of the active region of the silicon-based hybrid integrated laser without a specific area and a heat-conducting layer on both sides of the silicon ridge waveguide is 306°C, while the silicon-based hybrid laser with a specific area and a heat-conducting layer on both sides of the silicon ridge waveguide has a maximum temperature of 306 °C. The maximum temperature of the active region of the integrated laser is 40.3 °C, as shown in Figure 5. It can be seen that the structure containing a specific region and a thermal conductive layer improves the problem of poor thermal conductivity of the laser array caused by the poor thermal conductivity of the buried oxide layer in the SOI material. The heat in the active region is dissipated by introducing the metal into the substrate silicon in a specific region, which can improve the thermal and optoelectronic properties of the entire silicon-based hybrid integrated laser array.

To sum up, the present disclosure provides a silicon-based hybrid integrated laser array and a preparation method thereof, which have good heat dissipation characteristics and optoelectronic characteristics, and III-V semiconductor epitaxial materials are epitaxially formed by MBE or MOCVD once, and do not need two. Sub-epitaxial and selective growth technology, the process is simple and stable; the structure on SOI can be compatible with mature CMOS process, the process is stable, the repeatability is good, and the production cost is low; the structure on III-V semiconductor materials can be compatible with traditional optoelectronic process technology Compatible with high repeatability in production.

Of course, according to actual needs, the silicon-based hybrid integrated laser array and the preparation method thereof of the present disclosure also include other elements, processes and steps, which are not related to the innovation of the present disclosure, and will not be repeated here.

It should also be noted that the directional terms mentioned in the embodiments, such as "up", "down", "front", "rear", "left", "right", etc., only refer to the directions of the drawings, not used to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are denoted by the same or similar reference numbers. Conventional structures or constructions will be omitted when it may lead to obscuring the understanding of the present disclosure. Moreover, the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Furthermore, the word "comprising" or "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Furthermore, unless the steps are specifically described or must occur sequentially, the order of the above steps is not limited to those listed above, and may be varied or rearranged according to the desired design. And the above embodiments can be mixed and matched with each other or with other embodiments based on the consideration of design and reliability, that is, the technical features in different embodiments can be freely combined to form more embodiments.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above-mentioned specific embodiments are only specific embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included within the protection scope of the present disclosure.

Claims (10)

1. A silicon-based hybrid integrated laser array, comprising: a plurality of parallel-arranged silicon-based hybrid integrated lasers fabricated on an SOI substrate and a III-V semiconductor epitaxial layer; Wherein, each silicon-based hybrid integrated laser includes: a silicon ridge waveguide; a heat conduction layer located in a specific area on both sides of the silicon ridge waveguide, the specific area is the area obtained after removing the top silicon and buried oxide layer from the SOI substrate; an intrinsic layer , the shape is saddle-shaped, including protrusions and connecting parts at both ends, of which the protrusions at one end are covered above the thermal conductive layer; the N-type waveguide layer is formed on the connecting part of the intrinsic layer; the active area is formed on the N-type The P-type cap layer is formed on the active area; the III-V waveguide is formed by patterning the III-V semiconductor epitaxial layer, and the two ends are connected to the front and rear ends of the silicon ridge waveguide. The structure on the side is the patterned P-type cap layer that is not etched and the active region below; the P-type ohmic contact layer is located on the III-V waveguide; the P-electrode is located on the P-type ohmic contact layer; and The N electrode is located on the N-type waveguide layer. 2. The silicon-based hybrid integrated laser array according to claim 1, wherein the SOI substrate and the III-V semiconductor epitaxial layer are combined by bonding, and the bonding method comprises: metal bonding, dielectric Bonding or direct wafer bonding, silicon ridge waveguides and III-V waveguides are fabricated on SOI substrates and III-V semiconductor epitaxial layers, respectively, and then by covering the protrusions at one end of the saddle-shaped intrinsic layer On top of the thermally conductive layer, both the SOI substrate and the III-V semiconductor epitaxial layer are bonded together. 3. The silicon-based hybrid integrated laser array of claim 1, wherein each of the III-V waveguides is in a one-to-one correspondence with each of the silicon ridge waveguides and is vertically aligned. 4. The silicon-based hybrid integrated laser array of claim 1, wherein: The SOI substrate sequentially includes from bottom to top: substrate silicon, buried oxide layer and top layer silicon. The silicon ridge waveguide is fabricated by patterning the SOI substrate, and is patterned and etched from the top layer silicon of the SOI substrate. formed after The III-V semiconductor epitaxial layer sequentially includes from bottom to top: an intrinsic layer, an N-type waveguide layer, an active region, a P-type cap layer and a P-type ohmic contact layer, and the III-V waveguide is a III-V semiconductor The epitaxial layer is patterned and then fabricated by etching the P-type ohmic contact layer, the P-type cap layer, the active region and the N-type waveguide layer. 5. The silicon-based hybrid integrated laser array of claim 4, wherein: Along the direction of the silicon ridge waveguide, the structures at both ends of the silicon ridge waveguide include: a wedge-shaped ridge waveguide and/or a straight ridge waveguide; Along the direction of the III-V waveguide, the structures at both ends of the III-V waveguide include: a wedge-shaped ridge waveguide and/or a straight ridge waveguide. 6 . The silicon-based hybrid integrated laser array according to claim 5 , wherein the III-V waveguide comprises: a wedge-shaped waveguide in the front and rear sections and a straight waveguide in the middle section, and the wedge-shaped waveguide in the front and rear sections is patterned and carved. 7 . It is etched to the bottom of the N-type waveguide layer and connected to the front and rear ends of the silicon ridge waveguide. The straight waveguide in the middle section is etched to the bottom of the P-type cap layer; the remaining unetched P-type cap layer is located in the III- On both sides of the V-waveguide, the active regions are located under the P-type capping layer, and are also located on both sides of the III-V waveguide. 7. The silicon-based hybrid integrated laser array of claim 1, wherein: The material of the thermally conductive layer includes: Metal or alloy materials, including: SnAu, Sn, Ag, Cu, Au, Al, Fe or CuAl; Semiconductor materials, including: polysilicon, single crystal silicon, amorphous silicon or germanium; Inorganic non-metallic materials, including: graphene, graphite, carbon fiber, C/C composites, or carbon black; and Thermally conductive polymer materials; and/or The materials of the P-type ohmic contact region, the P-type cap layer, the active region, the N-type waveguide layer and the intrinsic layer in the III-V semiconductor epitaxial layer include: indium phosphide, gallium arsenide, and gallium antimonide materials. Any two or more of binary, ternary, and quaternary materials. 8. The silicon-based hybrid integrated laser array according to any one of claims 1 to 7, further comprising: Microstructure, formed on the structure of silicon ridge waveguide or III-V waveguide. 9. The silicon-based hybrid integrated laser array according to claim 8, wherein the morphology of the microstructure comprises: one-dimensional, two-micro, and three-dimensional geometric shapes, and the structure comprises: grating, photonic crystal or micro groove; By adjusting the parameters of the microstructure in each silicon-based hybrid integrated laser, the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array can be realized. 10. A method for preparing a silicon-based hybrid integrated laser array, comprising: Fabrication of multiple silicon ridge waveguides arranged in parallel on SOI substrate; Making a specific area on the SOI substrate containing the silicon ridge waveguide, the specific area is the area obtained after removing the top silicon and the buried oxide layer of the SOI substrate, and growing a thermal conductive layer on the specific area; Use III-V semiconductor material to epitaxially grow intrinsic layer, N-type waveguide layer, active region, P-type cap layer and P-type ohmic contact layer in turn to form III-V semiconductor epitaxial layer; Patterning is performed on the III-V semiconductor epitaxial layer, and the saddle-shaped intrinsic layer, the III-V waveguide and the structures on both sides of the III-V waveguide are etched, and the P electrode and the N electrode are grown; the intrinsic layer includes Protruding parts and connecting parts at both ends, one of the protruding parts at both ends is covered above the thermal conductive layer; the two ends of the III-V waveguide are connected with the front and rear ends of the silicon ridge waveguide, and the structures on both sides are not patterned. The etched P-type cap layer and the underlying active region; the P-electrode is located on the P-type ohmic contact layer; the N-electrode is located on the N-type waveguide layer; Bond the SOI substrate containing the silicon ridge waveguide and the thermal conductive layer with the III-V semiconductor epitaxial layer containing the III-V waveguide, P electrode and N electrode; the bonding method includes: metal bonding, dielectric bonding or wafer Direct bonding, silicon ridge waveguides and III-V waveguides are fabricated on SOI substrates and III-V semiconductor epitaxial layers, respectively, and then by covering the protrusions at one end of the saddle-shaped intrinsic layer on the thermal conductive layer. above, combining both the SOI substrate and the III-V semiconductor epitaxial layer; and The microstructure is fabricated on the structure of silicon ridge waveguide or III-V waveguide to complete the preparation of silicon-based hybrid integrated laser array.

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