CN109560462B - Silicon-based hybrid integrated laser array and preparation method thereof - Google Patents
Silicon-based hybrid integrated laser array and preparation method thereof Download PDFInfo
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- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
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- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
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Abstract
The invention discloses a silicon-based hybrid integrated laser array and a preparation method thereof. The silicon-based hybrid integrated laser array comprises: manufacturing a plurality of silicon-based hybrid integrated lasers which are arranged in parallel on an SOI substrate and a III-V semiconductor epitaxial layer; wherein each silicon-based hybrid integrated laser comprises: a silicon ridge waveguide; the heat conduction layer is positioned in specific areas on two sides of the silicon ridge waveguide, and the specific areas are areas obtained after top silicon and an oxygen buried layer of the SOI substrate are removed; the intrinsic layer is saddle-shaped and comprises protruding parts and connecting parts at two ends, wherein the protruding parts at two ends cover the upper part of the heat conducting layer; the intrinsic layer connecting part is sequentially provided with an N-type waveguide layer, an active region and a P-type cover layer; the III-V waveguide is formed by patterning a III-V semiconductor epitaxial layer and is connected with the silicon ridge waveguide; a P-type ohmic contact layer, a P electrode and an N electrode. Good heat dissipation, simple and stable preparation process, good repeatability and low manufacturing cost.
Description
Technical Field
The disclosure belongs to the technical field of lasers, and relates to a silicon-based hybrid integrated laser array and a preparation method thereof.
Background
With the development of the technology, people have higher and higher requirements on data transmission rate, transmission bandwidth and energy consumption, and are restricted by the physical characteristics of electrons, and the traditional electric interconnection based on an electric integrated chip has the bottleneck problems of large energy consumption, narrow bandwidth and high cost of an optoelectronic integrated system when high-speed signals are transmitted; and the photons have the characteristics of ultrahigh transmission speed, ultrahigh parallelism, ultrahigh bandwidth, ultralow transmission and interactive power consumption. Since silicon photonic integration combines the advantages of ultra-large scale logic, ultra-high precision manufacturing, and low cost of CMOS processes, silicon-based optical interconnects are expected to break through the above-mentioned bottlenecks of rate, power consumption, bandwidth, and cost.
The silicon photonics synthesis technology has been greatly developed through previous research, but the light source is still a worldwide problem. Since the first electro-injection silicon-based hybrid integrated laser invented by Intel 2006, silicon-based hybrid integrated lasers have been widely studied. However, modern communication technology generally adopts multiplexing technology to improve communication capacity, and the research of silicon-based hybrid integrated III-V laser arrays is urgently needed.
At present, three methods are common in the method for realizing the silicon-based hybrid integrated laser array. The first method is to bond SOI silicon-based material and III-V epitaxial material together by wafer direct bonding or dielectric bonding, to make multiple parallel ridge waveguides on the SOI or III-V epitaxial material, and to make microstructures or curved waveguides on the ridge waveguides for selecting wavelength to realize silicon-based hybrid integrated laser array. However, the silicon-based hybrid integrated laser array mentioned in the scheme does not consider the problem that the laser array is influenced by the poor heat dissipation characteristic of a buried oxide layer (BOX) in the SOI. The second method is to epitaxially grow III-V semiconductor material directly on SOI by MOCVD or MBE, fabricate a ridge waveguide on SOI or III-V, and fabricate a microstructure on the ridge waveguide for selecting a wavelength. Although the scheme can realize the self-aligned silicon-based hybrid integrated laser on an SOI material without the precise alignment technology between SOI and III-V, the requirement on the epitaxial technology is high, the current technology is still not mature, and the research is needed, and the influence of poor heat dissipation property of a buried oxide layer in an SOI substrate on devices is not researched. The third method is that after a plurality of parallel silicon-based waveguides are manufactured on the SOI, the manufactured III-V laser array is coupled with the end faces of the plurality of silicon-based waveguides on the SOI in a 3D integration or packaging mode. In the 3D integration or packaging form, the silicon waveguide on the SOI material needs to be precisely aligned with each optical end of the III-V semiconductor laser array, which requires high packaging technology and high cost, and how to improve the end-face coupling efficiency should be considered.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides a silicon-based hybrid integrated laser array and a method for fabricating the same to at least partially solve the above-mentioned technical problems.
(II) technical scheme
According to an aspect of the present disclosure, there is provided a silicon-based hybrid integrated laser array, comprising: manufacturing a plurality of silicon-based hybrid integrated lasers which are arranged in parallel on an SOI substrate and a III-V semiconductor epitaxial layer; wherein each silicon-based hybrid integrated laser comprises: a silicon ridge waveguide; the heat conduction layer is positioned in specific areas on two sides of the silicon ridge waveguide, and the specific areas are areas obtained after top silicon and an oxygen buried layer of the SOI substrate are removed; the intrinsic layer is saddle-shaped and comprises protruding parts and connecting parts at two ends, wherein the protruding parts at two ends cover the upper part of the heat conducting layer; an N-type waveguide layer formed on the connection portion of the intrinsic layer; an active region formed on the N-type waveguide layer; a P-type cap layer formed on the active region; the III-V waveguide is formed by patterning a III-V semiconductor epitaxial layer, two ends of the III-V waveguide are connected with the front end and the rear end of the silicon ridge waveguide, and the structures on the two sides are a P-type cover layer which is not etched after patterning and an active region below the P-type cover layer; the P-type ohmic contact layer is positioned on the III-V waveguide; the P electrode is positioned on the P-type ohmic contact layer; and the N electrode is positioned on the N-type waveguide layer.
In some embodiments of the present disclosure, the SOI substrate and the III-V semiconductor epitaxial layer are bonded together by means of a bond comprising: the silicon ridge waveguide and the III-V waveguide are respectively manufactured on an SOI substrate and a III-V semiconductor epitaxial layer, and then the SOI substrate and the III-V semiconductor epitaxial layer are combined together by covering protruding parts at two ends of a saddle-shaped intrinsic layer on a heat conduction layer.
In some embodiments of the present disclosure, each III-V waveguide is in one-to-one correspondence with each silicon ridge waveguide, and is aligned in a vertical direction.
In some embodiments of the present disclosure, the SOI substrate comprises, in order from bottom to top: the silicon ridge waveguide is manufactured by patterning an SOI substrate and is formed by patterning and etching the top layer silicon of the SOI substrate; the III-V semiconductor epitaxial layer sequentially comprises from bottom to top: the III-V waveguide is manufactured by patterning a III-V semiconductor epitaxial layer and then etching the P-type ohmic contact layer, the P-type cover layer, the active region and the N-type waveguide layer.
In some embodiments of the present disclosure, along the direction of the silicon ridge waveguide, the structure of the two ends of the silicon ridge waveguide comprises: a tapered ridge waveguide and/or a straight ridge waveguide; along the direction of the III-V waveguide, the structure of the two ends of the III-V waveguide comprises: wedge waveguides and/or straight waveguides.
In some embodiments of the present disclosure, a III-V waveguide comprises: the wedge waveguides of the front section and the rear section are etched to the bottom of the N-type waveguide layer in a patterned manner and are connected with the front end and the rear end of the silicon ridge waveguide, and the straight waveguide of the middle section is etched to the lower part of the P-type cover layer; the remaining un-etched P-type cap layers are located on both sides of the III-V waveguide, and the active region is located below the P-type cap layers and also located on both sides of the III-V waveguide.
In some embodiments of the present disclosure, the material of the thermally conductive layer comprises: a metal or alloy material comprising: SnAu, Sn, Ag, Cu, Au, Al, Fe or CuAl; a semiconductor material comprising: polycrystalline silicon, monocrystalline silicon, amorphous silicon, or germanium; an inorganic non-metallic material comprising: graphene, graphite, carbon fiber, C/C composite or carbon black; and a thermally conductive polymeric material; and/or the materials of the P-type ohmic contact region, the P-type cover layer, the active region, the N-type waveguide layer and the intrinsic layer in the III-V semiconductor epitaxial layer comprise: any two or more of binary system, ternary system and quaternary system materials of indium phosphide, gallium arsenide and gallium antimonide material systems.
In some embodiments of the present disclosure, the silicon-based hybrid integrated laser array further comprises: and the microstructure is formed on the structure of the silicon ridge waveguide or the III-V waveguide.
In some embodiments of the present disclosure, the topography of the microstructures comprises: one-dimensional, two-dimensional and three-dimensional geometric shapes, the structure comprises: gratings, photonic crystals or microgrooves; by adjusting the parameters of the microstructure in each silicon-based hybrid integrated laser, the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array can be realized.
According to another aspect of the present disclosure, there is provided a method for manufacturing a silicon-based hybrid integrated laser array, including: manufacturing a plurality of silicon ridge waveguides which are arranged in parallel on an SOI substrate; manufacturing a specific area on an SOI substrate containing a silicon ridge waveguide, and growing a heat conduction layer on the specific area; epitaxially growing an intrinsic layer, an N-type waveguide layer, an active region, a P-type cover layer and a P-type ohmic contact layer in sequence by using III-V semiconductor materials to form a III-V semiconductor epitaxial layer; patterning the III-V semiconductor epitaxial layer, etching a saddle-shaped intrinsic layer, a III-V waveguide and structures on two sides of the III-V waveguide, and growing a P electrode and an N electrode; bonding an SOI substrate containing a silicon ridge waveguide and a heat conducting layer with a III-V semiconductor epitaxial layer containing a III-V waveguide, a P electrode and an N electrode; and manufacturing a microstructure on the structure of the silicon ridge waveguide or the III-V waveguide to finish the preparation of the silicon-based hybrid integrated laser array.
(III) advantageous effects
According to the technical scheme, the silicon-based hybrid integrated laser array and the preparation method thereof have the following beneficial effects:
in each silicon-based hybrid integrated laser forming the array, the top layer silicon and the oxygen buried layer are removed in specific areas on two sides of the silicon ridge waveguide to expose the substrate silicon, then metal or high-heat-conduction materials are filled in the areas, heat generated during light emitting of the active area enters the substrate silicon through the N-type waveguide layer, the intrinsic layer and the metal and high-heat-conduction materials in the areas to be dissipated, the problem that the poor heat dissipation characteristic of the silicon-based hybrid integrated laser is influenced due to the poor heat conduction characteristic of the oxygen buried layer in the SOI material is solved, and the heat dissipation characteristic and the photoelectric characteristic of the silicon-based hybrid integrated laser array are improved; in addition, the III-V semiconductor epitaxial material is formed by primary epitaxy of MBE or MOCVD, secondary epitaxy and selective area growth technology are not needed, and the process is simple and stable; the structure on the SOI can be compatible with a mature CMOS process, the process is stable, the repeatability is good, and the manufacturing cost is low; the structure on the III-V semiconductor material can be compatible with the traditional photoelectronic process technology, and has higher repeatability in manufacturing.
Drawings
Fig. 1 is a schematic structural diagram of a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of one of the silicon-based hybrid integrated lasers in the silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.
Fig. 3 is a schematic cross-sectional view of a structure of one of the silicon-based hybrid integrated lasers in the silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.
Fig. 4 is a schematic cross-sectional thermal profile of a si-based hybrid integrated laser without a specific region and a thermally conductive layer on both sides of the si-ridge waveguide according to an embodiment of the present disclosure.
Fig. 5 is a schematic cross-sectional thermal profile of a si-based hybrid integrated laser including specific regions and thermally conductive layers on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure.
[ notation ] to show
100-silicon based hybrid integrated laser array; 400-silicon based hybrid integrated laser;
200-SOI substrate;
201-substrate silicon; 202-buried oxide layer;
203-top silicon; 204-a silicon ridge waveguide;
a 300-III-V semiconductor epitaxial layer;
301-P type ohmic contact layer; a 302-P type cap layer;
303-active region; 304-N type waveguide layer;
305 — an intrinsic layer; 306-III-V waveguide;
307-P electrode; 308-N electrode;
500-microstructure; 700-heat conducting layer.
Detailed Description
The invention provides a silicon-based hybrid integrated laser array and a preparation method thereof, which have good heat dissipation characteristic and photoelectric characteristic, and III-V semiconductor epitaxial material is formed by primary epitaxy of MBE or MOCVD, and does not need secondary epitaxy and selective growth technology, and the process is simple and stable; the structure on the SOI can be compatible with a mature CMOS process, the process is stable, the repeatability is good, and the manufacturing cost is low; the structure on the III-V semiconductor material can be compatible with the traditional photoelectronic process technology, and has higher repeatability in manufacturing.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In a first exemplary embodiment of the present disclosure, a silicon-based hybrid integrated laser array is provided.
Fig. 1 is a schematic structural diagram of a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure. Fig. 2 is a schematic structural diagram of one of the silicon-based hybrid integrated lasers in the silicon-based hybrid integrated laser array according to an embodiment of the present disclosure. Fig. 3 is a schematic cross-sectional view of a structure of one of the silicon-based hybrid integrated lasers in the silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.
As shown in fig. 1-3, the silicon-based hybrid integrated laser array 100 of the present disclosure includes multiple silicon-based hybrid integrated lasers 400 fabricated on an SOI substrate 200 and a III-V semiconductor epitaxial layer 300 in parallel, where each silicon-based hybrid integrated laser 400 includes: a substrate silicon 201; a buried oxide layer 202; a silicon ridge waveguide 204; a heat conducting layer 700 located in a specific area on both sides of the silicon ridge waveguide 204; the intrinsic layer 305 is saddle-shaped and comprises protruding parts and connecting parts at two ends, wherein one protruding part at two ends is positioned at two sides of the silicon ridge waveguide 204 and covers the heat conducting layer 700; an N-type waveguide layer 304 formed on the connection portion of the intrinsic layer 305 above the silicon ridge waveguide 204; an active region 303 formed over the N-type waveguide layer 304; a P-type cap layer 302 formed over the active region 303; the III-V waveguide 306 is formed by patterning the III-V semiconductor epitaxial layer 300, is connected with the rear end of the silicon ridge waveguide 204, and is provided with a P-type cover layer 302 which is not etched after patterning and an active region 303 below; a P-type ohmic contact layer 301 on the III-V waveguide 306; a P-electrode 307 formed on the P-type ohmic contact layer 301; an N-electrode 308 formed on the N-type waveguide layer 304; and a microstructure 500 formed on the structure of the silicon ridge waveguide 204 or the III-V waveguide 306; wherein, the specific area is located at two sides of the silicon ridge waveguide, and the heat conduction layer 700 is obtained by growing the heat conduction material after removing the top silicon and the buried oxide layer in the area.
The details of the various parts of the silicon-based hybrid integrated laser array of the present embodiment are described below with reference to fig. 2 and 3.
In this embodiment, the SOI substrate 200 includes, in order from bottom to top: substrate silicon 201, buried oxide layer 202 and top layer silicon 203.
In this embodiment, the buried oxide layer 202 of the SOI substrate 200 has a thickness of 2 μm; the thickness of the top layer silicon is 220 nm; the width of the plurality of parallel silicon ridge waveguides 204 fabricated on top of the top silicon is 3 μm.
The silicon ridge waveguide 204 is formed by patterning the SOI substrate 200, and is formed by patterning and etching the top silicon 203 of the SOI substrate 200.
In this embodiment, along the direction of the silicon ridge waveguide 204, the structure at both ends of the silicon ridge waveguide 204 may be a wedge-shaped ridge waveguide or a straight ridge waveguide, the width and the height of which may be any values, and the top layer silicon 203 of the SOI substrate 200 is patterned; in the manufacturing process, the structures on both sides of the silicon ridge waveguide 204 are also formed by patterning the top silicon 203 of the SOI substrate 200, see the pattern formed on the top silicon 203 of the SOI substrate 200 in a Y-shape in fig. 1; the structure on both sides of the silicon ridge waveguide 204 and the pattern of the silicon ridge waveguide 204 can be designed on a photolithography board, and then the silicon ridge waveguide 204 and the pattern on both sides thereof can be formed by one photolithography.
And the heat conduction layer 700 is positioned at two sides of the silicon ridge waveguide 204 and is formed by growing a heat conduction material on the substrate silicon 201 after the top layer silicon 203 and the buried oxide layer 202 at two sides of the silicon ridge waveguide 204 in the SOI substrate 200 are etched away. In this embodiment, the specific regions where the heat conducting layers are located on two sides of the silicon ridge waveguide 204 and are 15 μm away from the silicon ridge waveguide, and the sizes of the specific regions are as follows: the length was 100 μm and the width was 1 mm.
In this embodiment, the materials of the heat conductive layer 700 include, but are not limited to: metals or alloy materials such as SnAu, Ag, Cu, Au, Al, Fe, CuAl and the like, semiconductor materials such as polycrystalline silicon, monocrystalline silicon, amorphous silicon, germanium and the like, inorganic non-metal materials such as graphene, graphite, carbon fiber, C/C composite material, carbon black and the like, heat-conducting high polymer materials and the like; in this embodiment, a metal material having good thermal conductivity or a highly thermally conductive material is preferable.
In this embodiment, the III-V semiconductor epitaxial layer 300 is formed by primary epitaxial growth of MBE or MOCVD, and does not require secondary epitaxial and selective growth techniques, and the process is simple and stable. The III-V semiconductor epitaxial layer 300 structure at least comprises from top to bottom: the P-type ohmic contact layer 301, the P-type cap layer 302, the active region 303, the N-type waveguide layer 304 and the intrinsic layer 305, the structure fabricated on the III-V semiconductor epitaxial layer 300 at least comprises: the III-V waveguide structure comprises a plurality of III-V waveguides 306, P electrodes 307 and N electrodes 308 which are arranged in parallel, wherein the P electrodes 307 are manufactured on a P-type ohmic contact layer 301, and the N electrodes 308 are manufactured on an N-type waveguide layer 304.
In this embodiment, the materials of the P-type ohmic contact 301, the P-type cap layer 302, the active region 303, the N-type waveguide layer 304 and the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 include, but are not limited to, the following materials: any two or more of binary system, ternary system and quaternary system materials of phosphorized steel, gallium arsenide and gallium antimonide material systems, and the components of any one of the ternary system and quaternary system materials can be different values or gradually changed values.
The III-V waveguide 306 is formed by patterning an intrinsic layer 305, an N-type waveguide layer 304, an active region 303, a P-type cover layer 302 and a P-type ohmic contact region 301 in the III-V semiconductor epitaxial layer 300 and comprises a front-section wedge waveguide, a rear-section wedge waveguide and a middle-section straight waveguide, wherein the front-section wedge waveguide and the rear-section wedge waveguide are etched to the bottom of the N-type waveguide layer 304 and are connected with the front end and the rear end of the silicon ridge waveguide 204, the middle-section straight waveguide is etched to the lower part of the P-type cover layer 302, and the rest un-etched P-type cover layers 302 are positioned on two sides of the III-V waveguide 306; the active region is located under the P-type cap layer 302 and also on both sides of the III-V waveguide 306.
In this embodiment, along the direction of the III-V waveguide 306, the structure at both ends of the III-V waveguide 306 may be a tapered waveguide or a straight waveguide, and the width and height thereof may be any values, and is formed by patterning the intrinsic layer 305, the N-type waveguide layer 304, the active region 303, the P-type cap layer 302, and the P-type ohmic contact region 301 in the III-V semiconductor epitaxial layer 300, in this embodiment, the III-V waveguide 306 includes a front-stage tapered waveguide, a rear-stage tapered waveguide, and a middle-stage straight waveguide, wherein the front-stage tapered waveguide and the rear-stage tapered waveguide are etched to the bottom of the N-type waveguide layer 304 and connected to the front end and the rear end of the silicon ridge waveguide 204, the middle-stage straight waveguide is etched to the lower portion of the P-type cap layer 302, and the remaining portion of. In the manufacturing process, the structures on both sides of the III-V waveguide 306 are also formed by patterning the III-V semiconductor epitaxial layer 300, see the straight waveguide shape on both sides of the III-V waveguide 306 in fig. 2, including the active region 303 and the P-type cap layer 302 which is not etched; the structure on both sides of the III-V waveguide 306 and the pattern of the III-V waveguide 306 can be designed on a single photolithography board and then patterned to different degrees by photolithography and etching once to form the silicon ridge waveguide 204 and its both sides.
Referring to fig. 1 and 2, the intrinsic layer 305, which is shaped like a saddle and includes two protruding portions and a connecting portion, wherein one of the two protruding portions is located on two sides of the silicon ridge waveguide 204 and covers the heat conductive material 700; the intrinsic layer 305 is also shaped by patterning the III-V semiconductor epitaxial layer 300.
In the present disclosure, each III-V waveguide 306 is in one-to-one correspondence with each silicon ridge waveguide 204 and is aligned in the vertical direction.
In this embodiment, the material of the III-V semiconductor epitaxial layer 300 includes, but is not limited to, one or more of indium-phosphorus system, gallium-arsenic system, and gallium-antimony system; the active region adopts a quantum well or quantum dot structure composed of indium-phosphorus system and gallium-arsenic system, and is not limited to the two material systems and the two structures of the quantum well and the quantum dot.
Preferably, the P-type cap layer 302 in the III-V semiconductor epitaxial layer 300 is made of InP material with a thickness of 1.5 μm; the P-type ohmic contact layer 301 is made of InGaAs, a plurality of P-type III-V ridge waveguides which are arranged in parallel are manufactured on the P-type InP cover layer and the P-type InGaAs ohmic contact layer, the width of each ridge waveguide is 5 micrometers, the etching depth is about 1.3 micrometers, and the width of the tail ends of the wedge-shaped III-V ridge waveguides at two ends is 400 nm; the active region 303 is made of AlGaInAs material, and the gain peak is near 1.55 μm.
In this embodiment, the SOI substrate 200 and the III-V semiconductor epitaxial layer 300 are bonded together by metal bonding, dielectric bonding, or wafer direct bonding, etc., and the silicon ridge waveguide 204 and the III-V waveguide 306 are fabricated on the SOI substrate 200 and the III-V semiconductor epitaxial layer 300, respectively, and then the SOI substrate 200 and the III-V semiconductor epitaxial layer 300 are bonded together by physically lapping the saddle-shaped intrinsic layer 305 on the heat conducting layer 700.
The heat conducting layer 700 is in contact with the intrinsic layer 305, so that heat generated by the active region 303 is transferred into the heat conducting layer 700 through the N-type waveguide layer 304 and the intrinsic layer 305 in a heat transfer mode, and then transferred into the substrate silicon 201 through the heat conducting layer, and the heat dissipation characteristic of the silicon-based hybrid integrated laser is effectively improved.
In this embodiment, the P-electrode 307 is formed on the P-type ohmic contact layer 301; an N-electrode 308 is formed over the N-type waveguide layer 304, spaced apart from the structures on either side of the III-V waveguide 306, as shown with reference to FIG. 3.
In this embodiment, the microstructure 500 is arranged to realize the function of adjusting the lasing wavelength of the silicon-based hybrid integrated laser 400. The microstructure 500 is formed on the structure of the silicon ridge waveguide 204 or the III-V waveguide 306, and the shape of the microstructure can be a one-dimensional, two-dimensional or three-dimensional geometric shape, including but not limited to a grating and a photonic crystal. By adjusting the parameters of the microstructure 500 in each silicon-based hybrid integrated laser 400 in the silicon-based hybrid integrated laser array 100, the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array 100 can be achieved.
In this embodiment, a one-dimensional microstructure 500 is fabricated on a silicon ridge waveguide 204, with a period of about 230 nm.
In this embodiment, the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 is in contact with the metal heat conduction layer 700 in the specific region, the N-type waveguide layer 304 is in contact with the silicon ridge waveguide 204, light emitted from the active region 303 is coupled into the silicon ridge waveguide 204 through the N-type waveguide layer 304 by evanescent coupling, and heat emitted from the active region 303 is conducted into the substrate silicon 201 through the N-type waveguide layer 304, the intrinsic layer 305 and the metal heat conduction layer 700 in the specific region and dissipated.
In a second exemplary embodiment of the present disclosure, a method of fabricating a silicon-based hybrid integrated laser array is provided.
The preparation method of the silicon-based hybrid integrated laser array comprises the following steps:
step S402: manufacturing a plurality of silicon ridge waveguides which are arranged in parallel on an SOI substrate;
in this embodiment, the plurality of silicon ridge waveguides 204 arranged in parallel are fabricated on the top layer silicon 203 by photolithography and etching techniques of CMOS process or optoelectronic processes such as general photolithography, electron beam exposure, holographic exposure, etching, focused ion beam FIB, and the like.
In this embodiment, the buried oxide layer 202 of the SOI substrate 200 has a thickness of 2 μm; the thickness of the top layer silicon is 220 nm; the width of the plurality of parallel silicon ridge waveguides 204 fabricated on top of the top silicon is 3 μm.
Step S404: manufacturing a specific region on an SOI substrate containing a silicon ridge waveguide, and growing a heat conduction layer 700 on the specific region;
in this embodiment, the specific region is formed by removing part of the top silicon 203 and the buried oxide layer 202 of the SOI substrate 200 by using a photolithography and etching technique of a CMOS process or an optoelectronic process such as general photolithography, electron beam exposure, holographic exposure, etching, FIB, or the like.
The heat conduction layer 700 is prepared by sequentially growing different heat conduction materials step by step through preparation technologies such as thermal evaporation, magnetron sputtering and the like in a physical or chemical deposition mode, and the growth sequence of the different heat conduction materials can be changed; the provision of a plurality of thermally conductive materials helps to improve the heat dissipation properties of the silicon-based hybrid integrated laser array.
In this embodiment, the specific regions where the heat conducting layer 700 is located are located on two sides of the silicon ridge waveguide 204 and are 15 μm away from the silicon ridge waveguide, and the size of the specific regions is as follows: the length was 100 μm and the width was 1 mm.
Step S406: epitaxially growing an intrinsic layer, an N-type waveguide layer, an active region, a P-type cover layer and a P-type ohmic contact layer in sequence by using III-V semiconductor materials to form a III-V semiconductor epitaxial layer;
in this embodiment, the III-V semiconductor epitaxial layer 300 is prepared by MBE or MOCVD single epitaxy.
The materials of the P-type ohmic contact region 301, the P-type cap layer 302, the active region 303, the N-type waveguide layer 304, and the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 include, but are not limited to, the following materials: any two or more of binary system, ternary system and quaternary system materials of indium phosphide, gallium arsenide and gallium antimonide material systems, and the components of any one of the ternary system and quaternary system materials can be different values or gradually changed values.
Preferably, the P-type cap layer 302 is made of InP material with a thickness of 1.5 μm; the P-type ohmic contact layer 301 is made of InGaAs, the active region 303 is made of AlGalnAs, and the gain peak is about 1.55 μm.
Step S408: patterning the III-V semiconductor epitaxial layer, etching a saddle-shaped intrinsic layer, a III-V waveguide and structures on two sides of the III-V waveguide, and growing a P electrode and an N electrode;
the step S408 includes: patterning the III-V semiconductor epitaxial layer by using a designed pattern, and then sequentially etching a part of the III-V semiconductor epitaxial layer to the bottom of the N-type waveguide layer 304 to form a front section wedge waveguide and a rear section wedge waveguide of the III-V waveguide by using the P-type ohmic contact layer 301, the P-type cover layer 302, the active region 303 and the N-type waveguide layer 304; the other part is etched with the P-type ohmic contact layer 301 and the P-type cover layer 302 in sequence until reaching the lower part of the P-type cover layer 302 to form a middle section straight waveguide of the III-V waveguide; etching off parts on two sides of the edge of the P-type cover layer 302 and the active region 303 to form an N electrode growth region; the remaining un-etched P-type cap layer 302 is located on both sides of the III-V waveguide 306, and the active region 303 is located under the P-type cap layer 302 and also located on both sides of the III-V waveguide 306 to form a structure on both sides of the III-V waveguide; a P electrode 307 is formed on the P-type ohmic contact layer 301, and an N electrode 308 is formed on the N electrode growth region on the N-type waveguide layer 304.
The P-type III-V ridge waveguide 306 is fabricated using, but not limited to, fabrication techniques such as photolithography, electron beam exposure, holographic exposure, wet etching, or dry etching. The preparation methods of the N electrode and the P electrode are conventional in the art, including thermal evaporation, magnetron sputtering, and the like, and are not described herein.
In this embodiment, there is a spacing between the N-electrode 308 and the structures on either side of the III-V waveguide.
The designed pattern includes: a saddle shape with a protrusion and a connection at both ends, and a III-V waveguide shape at the saddle-shaped connection, exemplified in this embodiment by a III-V waveguide comprising front and rear segments of wedge waveguides and an intermediate segment of straight waveguides.
Step S410: bonding an SOI substrate containing a silicon ridge waveguide and a heat conducting layer with a III-V semiconductor epitaxial layer containing a III-V waveguide, a P electrode and an N electrode;
in this embodiment, the surface of the silicon ridge waveguide 204 in the SOI substrate 200 and the surface of the N-type waveguide layer 304 in the III-V semiconductor epitaxial layer 300 are brought into contact with each other and bonded together by means of wafer bonding, metal bonding, or dielectric bonding.
Step S412: and manufacturing a microstructure on the structure of the silicon ridge waveguide or the III-V waveguide to finish the preparation of the silicon-based hybrid integrated laser array.
In this embodiment, the microstructure 500 may be fabricated on the III-V waveguide 306 by a CMOS process on the silicon ridge waveguide 204 or by an optoelectronic process such as general lithography, electron beam exposure, holographic exposure, etching, FIB, and the like.
The microstructure 500 can be a one-dimensional, two-dimensional, or three-dimensional geometry including, but not limited to, a grating, photonic crystal structure, and the number of periods and geometric parameters can be any number.
In order to verify the beneficial effects of the silicon-based hybrid integrated laser array, two simulation experiments of comparison structures are performed, wherein one structure is a silicon-based hybrid integrated laser device with two sides of a silicon ridge waveguide not containing a specific region and a heat conducting layer, the other structure is a silicon-based hybrid integrated laser device with two sides of a silicon ridge waveguide containing a specific region and a heat conducting layer, and the experiments of heat distribution are performed on the silicon-based hybrid integrated laser devices with the two structures.
Fig. 4 is a schematic cross-sectional thermal profile of a si-based hybrid integrated laser without a specific region and a thermally conductive layer on both sides of the si-ridge waveguide according to an embodiment of the present disclosure. Fig. 5 is a schematic cross-sectional thermal profile of a si-based hybrid integrated laser including specific regions and thermally conductive layers on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure.
As shown in fig. 4, the maximum temperature of the active region of the silicon-based hybrid integrated laser without the specific region and the heat conducting layer on both sides of the silicon ridge waveguide is 306 ℃, while the maximum temperature of the active region of the silicon-based hybrid integrated laser with the specific region and the heat conducting layer on both sides of the silicon ridge waveguide is 40.3 ℃, as shown in fig. 5, it can be seen that the structure with the specific region and the heat conducting layer improves the problem of poor heat dissipation property of the laser array caused by poor heat conduction property of the buried oxide layer in the SOI material, and the heat in the active region is conducted into the substrate silicon through the metal of the specific region to be dissipated, so that the thermal property and the photoelectric property of the whole silicon-based hybrid integrated laser.
In summary, the present disclosure provides a silicon-based hybrid integrated laser array and a method for manufacturing the same, which have good heat dissipation and photoelectric properties, and the III-V semiconductor epitaxial material is formed by MBE or MOCVD primary epitaxy, and does not require secondary epitaxy and selective growth technology, and the process is simple and stable; the structure on the SOI can be compatible with a mature CMOS process, the process is stable, the repeatability is good, and the manufacturing cost is low; the structure on the III-V semiconductor material can be compatible with the traditional photoelectronic process technology, and has higher repeatability in manufacturing.
Of course, according to actual needs, the silicon-based hybrid integrated laser array and the method for manufacturing the same according to the present disclosure further include other elements, processes, and steps, which are not described herein again since they are not related to the innovations of the present disclosure.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Furthermore, the word "comprising" or "comprises" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A silicon-based hybrid integrated laser array, comprising: manufacturing a plurality of silicon-based hybrid integrated lasers which are arranged in parallel on an SOI substrate and a III-V semiconductor epitaxial layer;
wherein each silicon-based hybrid integrated laser comprises: a silicon ridge waveguide; the heat conduction layer is positioned in specific areas on two sides of the silicon ridge waveguide, and the specific areas are areas obtained after top silicon and an oxygen buried layer of the SOI substrate are removed; the intrinsic layer is saddle-shaped and comprises protruding parts and connecting parts at two ends, wherein the protruding parts at two ends cover the upper part of the heat conducting layer; an N-type waveguide layer formed on the connection portion of the intrinsic layer; an active region formed on the N-type waveguide layer; a P-type cap layer formed on the active region; the III-V waveguide is formed by patterning a III-V semiconductor epitaxial layer, two ends of the III-V waveguide are connected with the front end and the rear end of the silicon ridge waveguide, and the structures on the two sides are a P-type cover layer which is not etched after patterning and an active region below the P-type cover layer; the P-type ohmic contact layer is positioned on the III-V waveguide; the P electrode is positioned on the P-type ohmic contact layer; and the N electrode is positioned on the N-type waveguide layer.
2. The silicon-based hybrid integrated laser array of claim 1, wherein the SOI substrate and III-V semiconductor epitaxial layers are bonded together by a bonding process comprising: the silicon ridge waveguide and the III-V waveguide are respectively manufactured on an SOI substrate and a III-V semiconductor epitaxial layer, and then the SOI substrate and the III-V semiconductor epitaxial layer are combined together by covering protruding parts at two ends of a saddle-shaped intrinsic layer on a heat conduction layer.
3. The silicon-based hybrid integrated laser array of claim 1, wherein each of the III-V waveguides is in one-to-one correspondence with each of the silicon ridge waveguides and is aligned in a vertical direction.
4. The silicon-based hybrid integrated laser array of claim 1, wherein:
the SOI substrate sequentially comprises from bottom to top: the silicon ridge waveguide is manufactured by patterning an SOI substrate and is formed by patterning and etching the top layer silicon of the SOI substrate;
the III-V semiconductor epitaxial layer sequentially comprises from bottom to top: the III-V waveguide is manufactured by patterning a III-V semiconductor epitaxial layer and then etching the P-type ohmic contact layer, the P-type cover layer, the active region and the N-type waveguide layer.
5. The silicon-based hybrid integrated laser array of claim 4, wherein:
along the direction of the silicon ridge waveguide, the structure at two ends of the silicon ridge waveguide comprises: a tapered ridge waveguide and/or a straight ridge waveguide;
along the direction of the III-V waveguide, the structure of the two ends of the III-V waveguide comprises: a tapered ridge waveguide and/or a straight ridge waveguide.
6. The silicon-based hybrid integrated laser array of claim 5, wherein the III-V waveguide comprises: the wedge waveguides of the front section and the rear section are etched to the bottom of the N-type waveguide layer in a patterned manner and are connected with the front end and the rear end of the silicon ridge waveguide, and the straight waveguide of the middle section is etched to the lower part of the P-type cover layer; the remaining un-etched P-type cap layers are located on both sides of the III-V waveguide, and the active region is located below the P-type cap layers and also located on both sides of the III-V waveguide.
7. The silicon-based hybrid integrated laser array of claim 1, wherein:
the heat conducting layer comprises the following materials:
a metal or alloy material comprising: SnAu, Sn, Ag, Cu, Au, Al, Fe or CuAl;
a semiconductor material comprising: polycrystalline silicon, monocrystalline silicon, amorphous silicon, or germanium;
an inorganic non-metallic material comprising: graphene, graphite, carbon fiber, C/C composite or carbon black; and
a thermally conductive polymeric material; and/or
The materials of the P-type ohmic contact region, the P-type cover layer, the active region, the N-type waveguide layer and the intrinsic layer in the III-V semiconductor epitaxial layer comprise: any two or more of binary system, ternary system and quaternary system materials of indium phosphide, gallium arsenide and gallium antimonide material systems.
8. The silicon-based hybrid integrated laser array of any one of claims 1 to 7, further comprising:
and the microstructure is formed on the structure of the silicon ridge waveguide or the III-V waveguide.
9. The silicon-based hybrid integrated laser array of claim 8, wherein the topography of the microstructures comprises: one-dimensional, two-dimensional and three-dimensional geometric shapes, the structure comprises: gratings, photonic crystals or microgrooves; by adjusting the parameters of the microstructure in each silicon-based hybrid integrated laser, the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array can be realized.
10. A preparation method of a silicon-based hybrid integrated laser array comprises the following steps:
manufacturing a plurality of silicon ridge waveguides which are arranged in parallel on an SOI substrate;
manufacturing a specific region on an SOI substrate containing a silicon ridge waveguide, wherein the specific region is a region obtained after removing top silicon and a buried oxide layer from the SOI substrate, and growing a heat conduction layer on the specific region;
epitaxially growing an intrinsic layer, an N-type waveguide layer, an active region, a P-type cover layer and a P-type ohmic contact layer in sequence by using III-V semiconductor materials to form a III-V semiconductor epitaxial layer;
patterning the III-V semiconductor epitaxial layer, etching a saddle-shaped intrinsic layer, a III-V waveguide and structures on two sides of the III-V waveguide, and growing a P electrode and an N electrode; the intrinsic layer comprises protruding parts and connecting parts at two ends, wherein the protruding parts at two ends cover the heat conducting layer; two ends of the III-V waveguide are connected with the front end and the rear end of the silicon ridge waveguide, and the structures on the two sides are a P-type cover layer which is not etched after patterning and an active region below the P-type cover layer; the P electrode is positioned on the P-type ohmic contact layer; the N electrode is positioned on the N-type waveguide layer;
bonding an SOI substrate containing a silicon ridge waveguide and a heat conducting layer with a III-V semiconductor epitaxial layer containing a III-V waveguide, a P electrode and an N electrode; the bonding mode comprises the following steps: the silicon ridge waveguide and the III-V waveguide are respectively manufactured on an SOI substrate and an III-V semiconductor epitaxial layer, and then the SOI substrate and the III-V semiconductor epitaxial layer are combined together by covering protruding parts at two ends of a saddle-shaped intrinsic layer on a heat conduction layer; and
and manufacturing a microstructure on the structure of the silicon ridge waveguide or the III-V waveguide to finish the preparation of the silicon-based hybrid integrated laser array.
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