CN109560462B - Silicon-based hybrid integrated laser array and preparation method thereof - Google Patents

Silicon-based hybrid integrated laser array and preparation method thereof Download PDF

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CN109560462B
CN109560462B CN201710888586.3A CN201710888586A CN109560462B CN 109560462 B CN109560462 B CN 109560462B CN 201710888586 A CN201710888586 A CN 201710888586A CN 109560462 B CN109560462 B CN 109560462B
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郑婉华
王海玲
王明金
石涛
孟然哲
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
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    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
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Abstract

本发明公开了一种硅基混合集成激光器阵列及其制备方法。硅基混合集成激光器阵列包括:制作在SOI基底和III‑V半导体外延层上的多个平行排布的硅基混合集成激光器;其中,每个硅基混合集成激光器包括:硅脊波导;导热层,位于硅脊波导两侧的特定区域内,该特定区域为SOI基底去除顶层硅和埋氧层之后获得的区域;本征层,形状为马鞍形,包括两端的突出部和连接部,其中一两端的突出部覆盖于导热层上方;本征层连接部上依次有N型波导层、有源区、P型盖层;III‑V波导,由III‑V半导体外延层图案化形成,与硅脊波导相连接;P型欧姆接触层,P电极以及N电极。散热性好,制备工艺简单稳定、重复性好、制作成本低。

Figure 201710888586

The invention discloses a silicon-based hybrid integrated laser array and a preparation method thereof. The silicon-based hybrid integrated laser array includes: a plurality of parallel-arranged silicon-based hybrid integrated lasers fabricated on an SOI substrate and a III-V semiconductor epitaxial layer; wherein each silicon-based hybrid integrated laser includes: a silicon ridge waveguide; a thermal conductive layer , located in a specific area on both sides of the silicon ridge waveguide, the specific area is the area obtained after removing the top silicon and buried oxide layers from the SOI substrate; the intrinsic layer, which is in the shape of a saddle, includes protrusions and connecting parts at both ends, one of which is The protrusions at both ends are covered above the thermally conductive layer; the intrinsic layer connecting part is sequentially provided with an N-type waveguide layer, an active region, and a P-type capping layer; the III‑V waveguide is formed by patterning a III‑V semiconductor epitaxial layer, and is connected with silicon. Ridge waveguides are connected; P-type ohmic contact layer, P-electrode and N-electrode. The heat dissipation is good, the preparation process is simple and stable, the repeatability is good, and the production cost is low.

Figure 201710888586

Description

硅基混合集成激光器阵列及其制备方法Silicon-based hybrid integrated laser array and preparation method thereof

技术领域technical field

本公开属于激光器技术领域,涉及一种硅基混合集成激光器阵列及其制备方法。The present disclosure belongs to the technical field of lasers, and relates to a silicon-based hybrid integrated laser array and a preparation method thereof.

背景技术Background technique

随着技术的发展,人们对数据传输速率、传输带宽和能耗要求越来越高,受电子自身物理特性的制约,传统的基于电集成芯片的电互连在传输高速信号时,存在能耗大、带宽窄及光电子集成系统成本高的瓶颈的问题;而光子具有超高传输速度、超高并行性、超高带宽与超低传输与交互功耗的特点。由于硅光子集成结合了CMOS工艺的超大规模逻辑、超高精度制造、低成本优势,因此,硅基光互连有望突破上述速率、功耗、带宽和成本的瓶颈。With the development of technology, people have higher and higher requirements for data transmission rate, transmission bandwidth and energy consumption. Restricted by the physical characteristics of electronics, traditional electrical interconnections based on electronic integrated chips have energy consumption when transmitting high-speed signals. However, photons have the characteristics of ultra-high transmission speed, ultra-high parallelism, ultra-high bandwidth and ultra-low transmission and interaction power consumption. Since silicon photonics integration combines the ultra-large-scale logic, ultra-high-precision manufacturing, and low-cost advantages of CMOS technology, silicon-based optical interconnects are expected to break through the above bottlenecks in rate, power consumption, bandwidth, and cost.

硅光子集成技术经过前期的研究得到了很大的发展,但是光源仍然是世界性的难题。从2006年Intel发明了第一个电注入硅基混合集成激光器开始,目前硅基混合集成激光器已得到了广泛的研究。但是现代通信技术通常采用多路复用技术提高通信容量,急需硅基混合集成III-V族激光器阵列的研究。Silicon photonics integration technology has been greatly developed after preliminary research, but the light source is still a worldwide problem. Since Intel invented the first electrically injected silicon-based hybrid integrated laser in 2006, silicon-based hybrid integrated lasers have been extensively studied. However, modern communication technology usually uses multiplexing technology to improve communication capacity, and research on silicon-based hybrid integrated III-V laser arrays is urgently needed.

目前实现硅基混合集成激光器阵列的方法常见的由三种方法。第一种方法是通过晶片直接键合或介质键合的方法将SOI硅基材料和III-V外延材料键合在一起,在SOI或III-V外延材料上制作多个平行的脊波导,在脊波导上制作微结构或者弯曲波导用来选择波长实现硅基混合集成激光器阵列。但是该方案中所提到的硅基混合集成激光器阵列都没有考虑SOI 中埋氧层(BOX)的散热特性差对激光器阵列的影响问题。第二种方法是在SOI上通过MOCVD或MBE直接外延生长III-V半导体材料,在SOI 或III-V上制作脊波导,在脊波导上制作微结构用来选择波长。虽然该方案能在一个SOI材料上实现自对准硅基混合集成激光器,不需要SOI和 III-V之间的精确对准技术,但是对外延技术的要求很高,目前技术仍未成熟,还需要探索,也没有研究SOI基底中埋氧层的散热特性差对器件的影响。第三种方法是在SOI制作好多个平行的硅基波导后,将制备好的III-V 激光器阵列通过3D集成或封装的形式与SOI上的多个硅基波导端面耦合。 3D集成或封装的形式,需要将SOI材料上的硅波导与III-V半导体激光器阵列的各处光端精确对准,对封装技术的要求很高,成本也较高,同时还要考虑如何提高端面耦合效率。At present, there are three common methods for realizing silicon-based hybrid integrated laser arrays. The first method is to bond SOI silicon-based materials and III-V epitaxial materials together by direct wafer bonding or dielectric bonding, and fabricate multiple parallel ridge waveguides on SOI or III-V epitaxial materials. Fabrication of microstructures or curved waveguides on ridge waveguides is used to select wavelengths to realize silicon-based hybrid integrated laser arrays. However, none of the silicon-based hybrid integrated laser arrays mentioned in this solution considers the influence of the poor heat dissipation characteristics of the buried oxide layer (BOX) in the SOI on the laser array. The second method is to directly epitaxially grow III-V semiconductor materials on SOI by MOCVD or MBE, fabricate ridge waveguides on SOI or III-V, and fabricate microstructures on the ridge waveguides for wavelength selection. Although this scheme can realize a self-aligned silicon-based hybrid integrated laser on a SOI material, and does not require precise alignment technology between SOI and III-V, the requirements for epitaxy technology are very high, and the current technology is still immature. It needs to be explored, and the influence of the poor heat dissipation characteristics of the buried oxide layer in the SOI substrate on the device has not been studied. The third method is to couple the prepared III-V laser array with multiple silicon-based waveguide end faces on the SOI in the form of 3D integration or packaging after multiple parallel silicon-based waveguides are fabricated on the SOI. In the form of 3D integration or packaging, it is necessary to precisely align the silicon waveguide on the SOI material with the optical ends of the III-V semiconductor laser array, which requires high packaging technology and high cost. At the same time, it is necessary to consider how to improve End face coupling efficiency.

发明内容SUMMARY OF THE INVENTION

(一)要解决的技术问题(1) Technical problems to be solved

本公开提供了一种硅基混合集成激光器阵列及其制备方法,以至少部分解决以上所提出的技术问题。The present disclosure provides a silicon-based hybrid integrated laser array and a preparation method thereof to at least partially solve the above-mentioned technical problems.

(二)技术方案(2) Technical solutions

根据本公开的一个方面,提供了一种硅基混合集成激光器阵列,包括:制作在SOI基底和III-V半导体外延层上的多个平行排布的硅基混合集成激光器;其中,每个硅基混合集成激光器包括:硅脊波导;导热层,位于硅脊波导两侧的特定区域内,该特定区域为SOI基底去除顶层硅和埋氧层之后获得的区域;本征层,形状为马鞍形,包括两端的突出部和连接部,其中一两端的突出部覆盖于导热层上方;N型波导层,形成于本征层的连接部之上;有源区,形成于N型波导层之上;P型盖层,形成于有源区之上;III-V波导,由III-V半导体外延层图案化形成,两端与硅脊波导的前、后端相连接,两侧的结构为图案化后未被刻蚀的P型盖层以及下方的有源区;P型欧姆接触层,位于III-V波导之上;P电极,位于P型欧姆接触层之上;以及N电极,位于N型波导层之上。According to one aspect of the present disclosure, a silicon-based hybrid integrated laser array is provided, comprising: a plurality of parallel-arranged silicon-based hybrid integrated lasers fabricated on an SOI substrate and a III-V semiconductor epitaxial layer; wherein each silicon-based hybrid integrated laser array is The base hybrid integrated laser includes: a silicon ridge waveguide; a thermal conductive layer, located in a specific area on both sides of the silicon ridge waveguide, the specific area is the area obtained after removing the top silicon and buried oxide layers of the SOI substrate; an intrinsic layer, the shape of which is a saddle shape , including protrusions and connecting parts at both ends, of which the protrusions at both ends are covered above the thermal conductive layer; the N-type waveguide layer is formed on the connecting part of the intrinsic layer; the active region is formed on the N-type waveguide layer. ; P-type cap layer, formed on the active area; III-V waveguide, formed by patterning III-V semiconductor epitaxial layer, both ends are connected with the front and rear ends of the silicon ridge waveguide, and the structures on both sides are patterned Unetched P-type cap layer and active region below; P-type ohmic contact layer on the III-V waveguide; P-electrode on top of the P-type ohmic contact layer; and N-electrode on the N-type ohmic contact layer above the waveguide layer.

在本公开的一些实施例中,SOI基底与III-V半导体外延层通过键合的方式结合在一起,该键合的方式包括:金属键合、介质键合或者晶片直接键合,硅脊波导和III-V波导是分别通过在SOI基底和III-V半导体外延层上制作而成,然后通过将马鞍形的本征层的一两端的突出部覆盖于导热层之上,将SOI基底与III-V半导体外延层二者结合在一起。In some embodiments of the present disclosure, the SOI substrate and the III-V semiconductor epitaxial layer are bonded together by bonding, and the bonding includes: metal bonding, dielectric bonding or direct wafer bonding, silicon ridge waveguide and III-V waveguides are fabricated on SOI substrates and III-V semiconductor epitaxial layers, respectively, and then the SOI substrate and III The -V semiconductor epitaxial layers are combined together.

在本公开的一些实施例中,每个III-V波导与每个硅脊波导是一一对应的,且在垂直方向是对齐的。In some embodiments of the present disclosure, each III-V waveguide is in a one-to-one correspondence with each silicon ridge waveguide and is vertically aligned.

在本公开的一些实施例中,SOI基底自下而上依次包括:衬底硅,埋氧层以及顶层硅,该硅脊波导是SOI基底经过图案化制作出来的,是由 SOI基底的顶层硅经图案化、刻蚀后形成的;III-V半导体外延层自下而上依次包括:本征层,N型波导层,有源区,P型盖层以及P型欧姆接触层,该III-V波导是III-V半导体外延层经过图案化,然后刻蚀P型欧姆接触层、 P型盖层、有源区和N型波导层制作出来的。In some embodiments of the present disclosure, the SOI substrate sequentially includes, from bottom to top, a substrate silicon, a buried oxide layer, and a top layer silicon. The silicon ridge waveguide is fabricated by patterning the SOI substrate, and is made of the top layer silicon of the SOI substrate. Formed after patterning and etching; the III-V semiconductor epitaxial layer sequentially includes from bottom to top: an intrinsic layer, an N-type waveguide layer, an active region, a P-type cap layer and a P-type ohmic contact layer. The V-waveguide is fabricated by patterning the III-V semiconductor epitaxial layer and then etching the P-type ohmic contact layer, the P-type cap layer, the active region and the N-type waveguide layer.

在本公开的一些实施例中,沿着硅脊波导的方向,该硅脊波导两端的结构包括:楔形脊波导和/或直脊波导;沿着III-V波导的方向,该III-V 波导两端的结构包括:楔形波导和/或直波导。In some embodiments of the present disclosure, along the direction of the silicon ridge waveguide, the structures at both ends of the silicon ridge waveguide include: a wedge-shaped ridge waveguide and/or a straight ridge waveguide; along the direction of the III-V waveguide, the III-V waveguide The structures at both ends include: wedge-shaped waveguides and/or straight waveguides.

在本公开的一些实施例中,III-V波导包括:前、后段的楔形波导和中间段的直波导,前、后段楔形波导经图案化刻蚀至N型波导层底部,与硅脊波导的前、后端相连接,中间段直波导经刻蚀至P型盖层下部;剩下的未被刻蚀的P型盖层位于该III-V波导的两侧,有源区位于P型盖层之下,同样也位于该III-V波导的两侧。In some embodiments of the present disclosure, the III-V waveguide includes a wedge-shaped waveguide in front and rear sections and a straight waveguide in the middle section. The front and rear ends of the waveguide are connected, and the straight waveguide in the middle section is etched to the lower part of the P-type capping layer; the remaining unetched P-type capping layer is located on both sides of the III-V waveguide, and the active area is located in the P-type cap layer. Under the type cap layer, it is also located on both sides of the III-V waveguide.

在本公开的一些实施例中,导热层的材料包括:金属或合金材料,包括:SnAu、Sn、Ag、Cu、Au、Al、Fe或CuAl;半导体材料,包括:多晶硅、单晶硅、非晶硅或锗;无机非金属材料,包括:石墨烯、石墨、碳纤维、C/C复合材料或炭黑;以及导热高分子材料;和/或III-V半导体外延层中P型欧姆接触区、P型盖层、有源区、N型波导层以及本征层的材料包括:磷化铟、砷化镓、锑化镓材料系的二元系、三元系、四元系材料中的任意两种或多种。In some embodiments of the present disclosure, the material of the thermal conductive layer includes: metal or alloy material, including: SnAu, Sn, Ag, Cu, Au, Al, Fe, or CuAl; semiconductor material, including: polysilicon, single crystal silicon, non- Crystalline silicon or germanium; inorganic non-metallic materials, including: graphene, graphite, carbon fiber, C/C composite materials or carbon black; and thermally conductive polymer materials; and/or P-type ohmic contact regions in III-V semiconductor epitaxial layers, The materials of the P-type cap layer, active region, N-type waveguide layer and intrinsic layer include: any of binary, ternary, and quaternary materials of indium phosphide, gallium arsenide, and gallium antimonide materials two or more.

在本公开的一些实施例中,硅基混合集成激光器阵列,还包括:微结构,形成于硅脊波导或III-V波导的结构上。In some embodiments of the present disclosure, the silicon-based hybrid integrated laser array further includes: a microstructure formed on the structure of the silicon ridge waveguide or the III-V waveguide.

在本公开的一些实施例中,微结构的形貌包括:一维、二微、三维的几何形状,结构包括:光栅、光子晶体或微槽;通过调节每个硅基混合集成激光器中的微结构的参数,能够实现该硅基混合集成激光器阵列的激射波长范围的控制和调节。In some embodiments of the present disclosure, the topography of the microstructure includes: one-dimensional, two-micro, and three-dimensional geometric shapes, and the structure includes: grating, photonic crystal or micro-groove; by adjusting the microstructure in each silicon-based hybrid integrated laser The parameters of the structure can realize the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array.

根据本公开的另一个方面,提供了一种硅基混合集成激光器阵列的制备方法,包括:在SOI基底上制作多个平行排布的硅脊波导;在含有硅脊波导的SOI基底上制作特定区域,并在特定区域上生长导热层;利用III-V 半导体材料依次外延生长本征层、N型波导层、有源区、P型盖层以及P 型欧姆接触层,形成III-V半导体外延层;在III-V半导体外延层上进行图案化处理,刻蚀出马鞍形的本征层、III-V波导以及III-V波导两侧的结构,生长P电极、N电极;将含有硅脊波导和导热层的SOI基底与含有III-V 波导、P电极、N电极的III-V半导体外延层键合起来;以及在硅脊波导或 III-V波导的结构上制作微结构,完成硅基混合集成激光器阵列的制备。According to another aspect of the present disclosure, a method for fabricating a silicon-based hybrid integrated laser array is provided, comprising: fabricating a plurality of silicon ridge waveguides arranged in parallel on an SOI substrate; fabricating a specific silicon ridge waveguide on the SOI substrate containing the silicon ridge waveguides area, and grow a thermal conductive layer on a specific area; use III-V semiconductor material to epitaxially grow intrinsic layer, N-type waveguide layer, active region, P-type cap layer and P-type ohmic contact layer in turn to form III-V semiconductor epitaxy layer; patterning is performed on the III-V semiconductor epitaxial layer, the saddle-shaped intrinsic layer, the III-V waveguide and the structure on both sides of the III-V waveguide are etched, and the P electrode and the N electrode are grown; will contain silicon ridges The SOI substrate of the waveguide and the thermally conductive layer is bonded with the III-V semiconductor epitaxial layer containing the III-V waveguide, P electrode, and N electrode; and the microstructure is fabricated on the structure of the silicon ridge waveguide or the III-V waveguide to complete the silicon substrate Fabrication of hybrid integrated laser arrays.

(三)有益效果(3) Beneficial effects

从上述技术方案可以看出,本公开提供的硅基混合集成激光器阵列及其制备方法,具有以下有益效果:It can be seen from the above technical solutions that the silicon-based hybrid integrated laser array and the preparation method thereof provided by the present disclosure have the following beneficial effects:

在构成阵列的每路硅基混合集成激光器中,在硅脊波导两侧的特定区域去除掉顶层硅和埋氧层,露出衬底硅,然后在该区域中填入了金属或高导热材料,将有源区发光时产生的热量通过N型波导层、本征层和该区域内的金属和高导热材料进入衬底硅散掉,解决SOI材料中由于埋氧层导热特性差从而影响硅基混合集成激光器散热特性差的问题,提高了硅基混合集成激光器阵列的散热特性及光电特性;另外,III-V半导体外延材料由 MBE或MOCVD一次外延而成,不需要二次外延及选区生长技术,工艺简单稳定;SOI上的结构可以与成熟的CMOS工艺兼容,工艺稳定、重复性好、制作成本低;在III-V半导体材料上的结构可以与传统的光电子工艺技术兼容,制作上有较高的重复性。In each silicon-based hybrid integrated laser constituting the array, the top silicon and buried oxide layers are removed in specific areas on both sides of the silicon ridge waveguide to expose the substrate silicon, and then metal or high thermal conductivity materials are filled in this area. The heat generated when the active area emits light is dissipated into the substrate silicon through the N-type waveguide layer, the intrinsic layer and the metal and high thermal conductivity materials in this area, so as to solve the problem of the poor thermal conductivity of the buried oxide layer in the SOI material, which affects the silicon substrate. The problem of poor heat dissipation characteristics of hybrid integrated lasers improves the heat dissipation characteristics and optoelectronic characteristics of silicon-based hybrid integrated laser arrays; in addition, III-V semiconductor epitaxial materials are epitaxially formed by MBE or MOCVD once, and secondary epitaxy and selective growth technology are not required. , the process is simple and stable; the structure on SOI can be compatible with the mature CMOS process, the process is stable, the repeatability is good, and the production cost is low; the structure on the III-V semiconductor material can be compatible with the traditional optoelectronic process technology. High repeatability.

附图说明Description of drawings

图1为根据本公开实施例硅基混合集成激光器阵列的结构示意图。FIG. 1 is a schematic structural diagram of a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.

图2为根据本公开实施例硅基混合集成激光器阵列中的一个硅基混合集成激光器的结构示意图。2 is a schematic structural diagram of a silicon-based hybrid integrated laser in a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.

图3为根据本公开实施例硅基混合集成激光器阵列中的一个硅基混合集成激光器的结构剖面示意图。3 is a schematic cross-sectional view of the structure of a silicon-based hybrid integrated laser in a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.

图4为根据本公开实施例硅脊波导两侧不含有特定区域及导热层的硅基混合集成激光器的剖面热分布示意图。4 is a schematic diagram of a cross-sectional thermal distribution of a silicon-based hybrid integrated laser without specific regions and thermal conductive layers on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure.

图5为根据本公开实施例硅脊波导两侧含有特定区域及导热层的硅基混合集成激光器的剖面热分布示意图。5 is a schematic diagram of a cross-sectional heat distribution of a silicon-based hybrid integrated laser with specific regions and a thermal conductive layer on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure.

【符号说明】【Symbol Description】

100-硅基混合集成激光器阵列; 400-硅基混合集成激光器;100-silicon-based hybrid integrated laser array; 400-silicon-based hybrid integrated laser;

200-SOI基底;200-SOI substrate;

201-衬底硅; 202-埋氧层;201-substrate silicon; 202-buried oxide layer;

203-顶层硅; 204-硅脊波导;203 - top layer silicon; 204 - silicon ridge waveguide;

300-III-V半导体外延层;300-III-V semiconductor epitaxial layer;

301-P型欧姆接触层; 302-P型盖层;301-P type ohmic contact layer; 302-P type capping layer;

303-有源区; 304-N型波导层;303-active region; 304-N-type waveguide layer;

305-本征层; 306-III-V波导;305-intrinsic layer; 306-III-V waveguide;

307-P电极; 308-N电极;307-P electrode; 308-N electrode;

500-微结构; 700-导热层。500 - microstructure; 700 - thermally conductive layer.

具体实施方式Detailed ways

本公开提供了一种硅基混合集成激光器阵列及其制备方法,具有良好的散热特性和光电特性,且III-V半导体外延材料由MBE或MOCVD一次外延而成,不需要二次外延及选区生长技术,工艺简单稳定;SOI上的结构可以与成熟的CMOS工艺兼容,工艺稳定、重复性好、制作成本低;在III-V半导体材料上的结构可以与传统的光电子工艺技术兼容,制作上有较高的重复性。The present disclosure provides a silicon-based hybrid integrated laser array and a preparation method thereof, which have good heat dissipation properties and optoelectronic properties, and III-V semiconductor epitaxial materials are epitaxially formed by MBE or MOCVD once, and do not require secondary epitaxy and selective growth. Technology, the process is simple and stable; the structure on SOI can be compatible with mature CMOS process, the process is stable, the repeatability is good, and the production cost is low; the structure on III-V semiconductor materials can be compatible with traditional optoelectronic process technology, and there are higher repeatability.

为使本公开的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本公开进一步详细说明。In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the specific embodiments and the accompanying drawings.

在本公开的第一个示例性实施例中,提供了一种硅基混合集成激光器阵列。In a first exemplary embodiment of the present disclosure, a silicon-based hybrid integrated laser array is provided.

图1为根据本公开实施例硅基混合集成激光器阵列的结构示意图。图 2为根据本公开实施例硅基混合集成激光器阵列中的一个硅基混合集成激光器的结构示意图。图3为根据本公开实施例硅基混合集成激光器阵列中的一个硅基混合集成激光器的结构剖面示意图。FIG. 1 is a schematic structural diagram of a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure. FIG. 2 is a schematic structural diagram of a silicon-based hybrid integrated laser in a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure. 3 is a schematic cross-sectional view of the structure of a silicon-based hybrid integrated laser in a silicon-based hybrid integrated laser array according to an embodiment of the present disclosure.

结合图1-图3所示,该本公开的硅基混合集成激光器阵列100,包括制作在SOI基底200和III-V半导体外延层300上的多路平行排布的硅基混合集成激光器400,每个硅基混合集成激光器400包括:衬底硅201;埋氧层202;硅脊波导204;导热层700,位于硅脊波导204两侧的特定区域内;本征层305,形状为马鞍形,包括两端的突出部和连接部,其中一两端的突出部位于硅脊波导204的两侧、覆盖于导热层700上方;N型波导层304,位于硅脊波导204的上方,形成于本征层305的连接部之上;有源区303,形成于N型波导层304之上;P型盖层302,形成于有源区 303之上;III-V波导306,由III-V半导体外延层300图案化形成,与硅脊波导204的后端相连接,两侧为图案化后未被刻蚀的P型盖层302以及下方的有源区303;P型欧姆接触层301,位于III-V波导306之上;P电极307,形成于P型欧姆接触层301之上;N电极308,形成于N型波导层304之上;以及微结构500,形成于硅脊波导204或III-V波导306的结构上;其中,特定区域位于硅脊波导两侧,导热层700是通过将区域内的顶层硅和埋氧层去除后生长导热材料得到的。1-3, the silicon-based hybrid integrated laser array 100 of the present disclosure includes multiple parallel silicon-based hybrid integrated lasers 400 fabricated on the SOI substrate 200 and the III-V semiconductor epitaxial layer 300, Each silicon-based hybrid integrated laser 400 includes: a substrate silicon 201; a buried oxide layer 202; a silicon ridge waveguide 204; , including protrusions and connecting parts at both ends, one of the protrusions at both ends is located on both sides of the silicon ridge waveguide 204 and covers the thermal conductive layer 700; the N-type waveguide layer 304 is located above the silicon ridge waveguide 204 and is formed in the intrinsic layer 305 on the connecting portion; active region 303, formed on the N-type waveguide layer 304; P-type capping layer 302, formed on the active region 303; III-V waveguide 306, formed by III-V semiconductor epitaxy The layer 300 is formed by patterning and is connected to the rear end of the silicon ridge waveguide 204, and the two sides are the P-type capping layer 302 that has not been etched after the patterning and the active region 303 below; the P-type ohmic contact layer 301 is located in III - over V waveguide 306; P electrode 307, formed over P-type ohmic contact layer 301; N electrode 308, formed over N-type waveguide layer 304; and microstructure 500, formed over silicon ridge waveguide 204 or III- On the structure of the V-waveguide 306; wherein, a specific area is located on both sides of the silicon ridge waveguide, and the heat-conducting layer 700 is obtained by removing the top layer of silicon and the buried oxide layer in the area and then growing a heat-conducting material.

下面结合图2和图3,对本实施例的硅基混合集成激光器阵列的各个部分进行详细介绍。Each part of the silicon-based hybrid integrated laser array of this embodiment will be described in detail below with reference to FIG. 2 and FIG. 3 .

本实施例中,SOI基底200自下而上依次包括:衬底硅201,埋氧层 202以及顶层硅203。In this embodiment, the SOI substrate 200 includes, from bottom to top, a substrate silicon 201 , a buried oxide layer 202 and a top layer silicon 203 .

本实施例中,SOI基底200的埋氧层202的厚度为2μm;顶层硅的厚度为220nm;在顶层硅上面制作的多个平行的硅脊波导204的宽度为3 μm。In this embodiment, the thickness of the buried oxide layer 202 of the SOI substrate 200 is 2 μm; the thickness of the top layer silicon is 220 nm; the width of the plurality of parallel silicon ridge waveguides 204 fabricated on the top layer silicon is 3 μm.

硅脊波导204是SOI基底200经过图案化制作出来的,是由SOI基底 200的顶层硅203经图案化、刻蚀后形成的。The silicon ridge waveguide 204 is fabricated by patterning the SOI substrate 200 , and is formed by patterning and etching the top layer silicon 203 of the SOI substrate 200 .

本实施例中,沿着硅脊波导204的方向,该硅脊波导204两端的结构可以是楔形脊波导或直脊波导,其宽度和高度可以是任意的数值,由SOI 基底200的顶层硅203经图案化形成;在制作过程中,硅脊波导204两侧的结构也是由SOI基底200的顶层硅203经图案化形成,参见图1中呈Y 字形形状的在SOI基底200的顶层硅203上形成的图案;硅脊波导204两侧的结构与硅脊波导204的图案可以设计在一个光刻板上,然后采用一次光刻形成硅脊波导204和其两侧的图案。In this embodiment, along the direction of the silicon ridge waveguide 204 , the structures at both ends of the silicon ridge waveguide 204 can be wedge-shaped ridge waveguides or straight ridge waveguides, and the width and height can be arbitrary values. Formed by patterning; in the manufacturing process, the structures on both sides of the silicon ridge waveguide 204 are also formed by patterning the top layer silicon 203 of the SOI substrate 200 , as shown in FIG. The pattern formed; the structure on both sides of the silicon ridge waveguide 204 and the pattern of the silicon ridge waveguide 204 can be designed on a photolithography plate, and then the silicon ridge waveguide 204 and the patterns on both sides thereof are formed by one photolithography.

导热层700,位于硅脊波导204的两侧,由SOI基底200中硅脊波导 204两侧的顶层硅203和埋氧层202被刻蚀掉后在衬底硅201上方生长导热材料形成。本实施例中,导热层所在的特定区域位于硅脊波导204两侧,距离硅脊波导15μm处,该特定区域的尺寸如下:长度为100μm、宽度为1mm。The thermal conductive layer 700, located on both sides of the silicon ridge waveguide 204, is formed by growing a thermal conductive material on the substrate silicon 201 after the top silicon 203 and the buried oxide layer 202 on both sides of the silicon ridge waveguide 204 in the SOI substrate 200 are etched away. In this embodiment, the specific area where the thermally conductive layer is located is located on both sides of the silicon ridge waveguide 204 and is 15 μm away from the silicon ridge waveguide. The size of the specific area is as follows: 100 μm in length and 1 mm in width.

本实施例中,导热层700的材料包括但不限于:SnAu、Ag、Cu、Au、 Al、Fe、CuAl等金属或合金材料,多晶硅、单晶硅、非晶硅、锗等半导体材料,石墨烯、石墨、碳纤维、C/C复合材料、炭黑等无机非金属材料以及导热高分子材料等;本实施例中优选导热性好的金属材料或高导热材料。In this embodiment, the materials of the thermal conductive layer 700 include, but are not limited to, metals or alloy materials such as SnAu, Ag, Cu, Au, Al, Fe, and CuAl, semiconductor materials such as polysilicon, single crystal silicon, amorphous silicon, germanium, and graphite. Inorganic non-metallic materials such as ene, graphite, carbon fiber, C/C composite material, carbon black, and thermally conductive polymer materials, etc.; in this embodiment, metal materials with good thermal conductivity or high thermal conductivity materials are preferred.

本实施例中,III-V半导体外延层300是由MBE或MOCVD一次外延生长而成,不需要二次外延及选区生长技术,工艺简单稳定。该III-V半导体外延层300结构从上到下至少包括:P型欧姆接触层301、P型盖层 302、有源区303、N型波导层304以及本征层305,在III-V半导体外延层300上制作的结构至少包括:多个平行排布的III-V波导306、P电极 307以及N电极308,其中,P电极307制作在P型欧姆接触层301之上, N电极308制作在N型波导层304之上。In this embodiment, the III-V semiconductor epitaxial layer 300 is formed by one-time epitaxial growth of MBE or MOCVD, which does not require secondary epitaxy and selective growth technology, and the process is simple and stable. The III-V semiconductor epitaxial layer 300 structure from top to bottom at least includes: a P-type ohmic contact layer 301, a P-type capping layer 302, an active region 303, an N-type waveguide layer 304 and an intrinsic layer 305. The structure fabricated on the epitaxial layer 300 at least includes: a plurality of III-V waveguides 306 arranged in parallel, P electrodes 307 and N electrodes 308, wherein the P electrodes 307 are fabricated on the P-type ohmic contact layer 301, and the N electrodes 308 are fabricated over the N-type waveguide layer 304 .

本实施例中,III-V半导体外延层300中P型欧姆接触区301、P型盖层302、有源区303、N型波导层304以及本征层305的材料包括但不限于如下材料:磷化钢、砷化镓、锑化镓材料系的二元系、三元系、四元系材料中的任意两种或多种,任意一种三元系、四元系材料的组份可以是不同的数值,也可以是渐变的数值。In this embodiment, the materials of the P-type ohmic contact region 301 , the P-type capping layer 302 , the active region 303 , the N-type waveguide layer 304 and the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 include but are not limited to the following materials: Any two or more of the binary, ternary, and quaternary materials of steel phosphide, gallium arsenide, and gallium antimonide materials, and the components of any ternary and quaternary materials can be is a different value, and can also be a gradient value.

III-V波导306,由III-V半导体外延层300中的本征层305,N型波导层304,有源区303,P型盖层302以及P型欧姆接触区301图案化形成,包括前、后段楔形波导与中间段直波导,其中,前、后段楔形波导经刻蚀至N型波导层304底部,与硅脊波导204的前、后端相连接,中间段直波导经刻蚀至P型盖层302下部,剩下的未被刻蚀的P型盖层302位于该III-V 波导306的两侧;有源区位于P型盖层302之下,同样也位于该III-V波导306的两侧。The III-V waveguide 306 is formed by patterning the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300, the N-type waveguide layer 304, the active region 303, the P-type capping layer 302 and the P-type ohmic contact region 301, including the front , the rear wedge-shaped waveguide and the middle straight waveguide, wherein the front and rear wedge-shaped waveguides are etched to the bottom of the N-type waveguide layer 304, and are connected to the front and rear ends of the silicon ridge waveguide 204, and the middle straight waveguide is etched To the lower part of the P-type capping layer 302, the remaining unetched P-type capping layer 302 is located on both sides of the III-V waveguide 306; the active region is located under the P-type capping layer 302, and is also located in the III-V waveguide Both sides of the V-waveguide 306 .

本实施例中,沿着III-V波导306的方向,该III-V波导306两端的结构可以是楔形波导或直波导,其宽度和高度可以是任意的数值,由III-V 半导体外延层300中的本征层305,N型波导层304,有源区303,P型盖层302,以及P型欧姆接触区301图案化形成,本实施例中该III-V波导 306包括前、后段楔形波导与中间段直波导,其中,前、后段楔形波导经刻蚀至N型波导层304底部,与硅脊波导204的前、后端相连接,中间段直波导经刻蚀至P型盖层302下部,还剩余部分P型盖层302未被刻蚀掉。在制作过程中,III-V波导306两侧的结构也是由III-V半导体外延层300 经图案化形成,参见图2中III-V波导306两侧的直波导形状,包括有源区303和未被刻蚀的P型盖层302;III-V波导306两侧的结构与III-V波导306的图案可以设计在一个光刻板上,然后采用一次光刻、刻蚀不同的程度从而形成硅脊波导204和其两侧的图案。In the present embodiment, along the direction of the III-V waveguide 306 , the structures at both ends of the III-V waveguide 306 may be wedge-shaped waveguides or straight waveguides, and the width and height may be arbitrary values, determined by the III-V semiconductor epitaxial layer 300 The intrinsic layer 305 , the N-type waveguide layer 304 , the active region 303 , the P-type cap layer 302 , and the P-type ohmic contact region 301 are formed by patterning. In this embodiment, the III-V waveguide 306 includes front and rear sections. The wedge-shaped waveguide and the middle straight waveguide, wherein the front and rear wedge-shaped waveguides are etched to the bottom of the N-type waveguide layer 304 and connected to the front and rear ends of the silicon ridge waveguide 204, and the middle straight waveguide is etched to the P-type In the lower part of the cap layer 302, the remaining part of the P-type cap layer 302 is not etched away. In the manufacturing process, the structures on both sides of the III-V waveguide 306 are also formed by patterning the III-V semiconductor epitaxial layer 300 , see the straight waveguide shape on both sides of the III-V waveguide 306 in FIG. 2 , including the active region 303 and The unetched P-type cap layer 302; the structure on both sides of the III-V waveguide 306 and the pattern of the III-V waveguide 306 can be designed on a lithography plate, and then a single photolithography and etching are used to form silicon Ridge waveguide 204 and the patterns on its sides.

参照图1和图2所示,本征层305,形状为马鞍形,包括两端的突出部和连接部,其中一两端的突出部位于硅脊波导204的两侧,覆盖于导热材料700的上方;该本征层305的形状也是通过图案化III-V半导体外延层300形成的。Referring to FIGS. 1 and 2 , the intrinsic layer 305 is saddle-shaped and includes protruding parts and connecting parts at both ends, wherein the protruding parts at one end are located on both sides of the silicon ridge waveguide 204 and cover the thermal conductive material 700 ; The shape of the intrinsic layer 305 is also formed by patterning the III-V semiconductor epitaxial layer 300 .

在本公开中,每个III-V波导306与每个硅脊波导204是一一对应的,且在垂直方向是对齐的。In the present disclosure, each III-V waveguide 306 has a one-to-one correspondence with each silicon ridge waveguide 204 and is vertically aligned.

本实施例中,III-V半导体外延层300的材料包括但不限于铟磷系、镓砷系和镓锑系这三种材料系的一种或几种;有源区采用的是由铟磷系、镓砷系构成的量子阱或量子点结构,且不局限于这两种材料系及量子阱、量子点这两种结构。In this embodiment, the materials of the III-V semiconductor epitaxial layer 300 include, but are not limited to, one or more of three material systems: indium phosphorus, gallium arsenide, and gallium antimony; the active region is made of indium phosphorus. The quantum well or quantum dot structure composed of the gallium arsenide system and the gallium arsenide system is not limited to these two material systems and the two structures of the quantum well and the quantum dot.

优选地,III-V半导体外延层300中的P型盖层302选用InP材料,厚度为1.5μm;P型欧姆接触层301的材料为InGaAs,在P型InP盖层和P 型InGaAs欧姆接触层上制作有多个平行排布的P型III-V脊波导,该脊波导的宽度为5μm,刻蚀深度约在1.3μm附近,两端的楔形III-V脊波导的末端宽度为400nm;有源区303采用AlGaInAs材料,其增益峰在1.55μm 附近。Preferably, the P-type cap layer 302 in the III-V semiconductor epitaxial layer 300 is made of InP material, with a thickness of 1.5 μm; the material of the P-type ohmic contact layer 301 is InGaAs, and the P-type InP cap layer and the P-type InGaAs ohmic contact layer are made of InGaAs. A plurality of P-type III-V ridge waveguides arranged in parallel are fabricated on the ridge, the width of the ridge waveguide is 5 μm, the etching depth is about 1.3 μm, and the end width of the wedge-shaped III-V ridge waveguide at both ends is 400 nm; active The region 303 is made of AlGaInAs material, and its gain peak is around 1.55 μm.

本实施例中,SOI基底200与III-V半导体外延层300通过金属键合、介质键合或者晶片直接键合等键合的方式结合在一起,硅脊波导204和 III-V波导306是分别通过在SOI基底200和III-V半导体外延层300上制作而成,然后通过将马鞍形的本征层305以物理的方式搭在导热层700之上将SOI基底200与III-V半导体外延层300二者结合在一起。In this embodiment, the SOI substrate 200 and the III-V semiconductor epitaxial layer 300 are bonded together by metal bonding, dielectric bonding or direct wafer bonding. The silicon ridge waveguide 204 and the III-V waveguide 306 are respectively It is fabricated on the SOI substrate 200 and the III-V semiconductor epitaxial layer 300, and then the SOI substrate 200 and the III-V semiconductor epitaxial layer are formed by physically placing the saddle-shaped intrinsic layer 305 on the thermal conductive layer 700. 300 combined.

导热层700与本征层305相接触,使得有源区303产生的热量通过热传递的方式经由N型波导层304、本征层305传入导热层700中,然后由导热层传入衬底硅201中,有效提高了硅基混合集成激光器的散热特性。The thermal conductive layer 700 is in contact with the intrinsic layer 305, so that the heat generated by the active region 303 is transferred into the thermal conductive layer 700 through the N-type waveguide layer 304 and the intrinsic layer 305 by means of heat transfer, and then transferred to the substrate through the thermal conductive layer In the silicon 201, the heat dissipation characteristics of the silicon-based hybrid integrated laser are effectively improved.

本实施例中,P电极307,形成于P型欧姆接触层301之上;N电极 308,形成于N型波导层304之上,与III-V波导306两侧的结构之间存在间距,参照图3所示。In this embodiment, the P electrode 307 is formed on the P-type ohmic contact layer 301; the N-electrode 308 is formed on the N-type waveguide layer 304, and there is a distance between the structures on both sides of the III-V waveguide 306, refer to shown in Figure 3.

本实施例中,微结构500的设置是为了实现调节该硅基混合集成激光器400的激射波长的作用。该微结构500形成于硅脊波导204或III-V波导306的结构上,其形貌可以是一维、二微、三维的几何形状,包括但不限于光栅、光子晶体这两种结构。通过调节硅基混合集成激光器阵列100 中的每个硅基混合集成激光器400中的微结构500的参数,可以实现该硅基混合集成激光器阵列100的激射波长范围的控制和调节。In this embodiment, the setting of the microstructure 500 is for adjusting the lasing wavelength of the silicon-based hybrid integrated laser 400 . The microstructure 500 is formed on the structure of the silicon ridge waveguide 204 or the III-V waveguide 306, and its morphology can be one-dimensional, two-micro, or three-dimensional geometric shapes, including but not limited to grating and photonic crystal structures. By adjusting the parameters of the microstructure 500 in each silicon-based hybrid integrated laser array 100 in the silicon-based hybrid integrated laser array 100 , the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array 100 can be realized.

本实施例中,在硅脊波导204上制作有一维微结构500,其周期在230 nm左右。In this embodiment, a one-dimensional microstructure 500 is fabricated on the silicon ridge waveguide 204, and its period is about 230 nm.

本实施例中,III-V半导体外延层300中的本征层305与特定区域内的金属导热层700相接触,N型波导层304与硅脊波导204相接触,有源区 303发出的光通过倏逝波耦合的方式经过N型波导层304耦合进入硅脊波导204中,有源区303发出的热量通过N型波导层304、本征层305和特定区域的金属导热层700导入衬底硅201散失掉。In this embodiment, the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 is in contact with the metal thermal conductive layer 700 in a specific area, the N-type waveguide layer 304 is in contact with the silicon ridge waveguide 204, and the light emitted from the active area 303 By means of evanescent wave coupling, the N-type waveguide layer 304 is coupled into the silicon ridge waveguide 204, and the heat emitted by the active region 303 is introduced into the substrate through the N-type waveguide layer 304, the intrinsic layer 305 and the metal thermal conductive layer 700 in a specific area. Silicon 201 is lost.

在本公开的第二个示例性实施例中,提供了一种硅基混合集成激光器阵列的制备方法。In a second exemplary embodiment of the present disclosure, a method for fabricating a silicon-based hybrid integrated laser array is provided.

本公开的硅基混合集成激光器阵列的制备方法,包括:The preparation method of the silicon-based hybrid integrated laser array of the present disclosure includes:

步骤S402:在SOI基底上制作多个平行排布的硅脊波导;Step S402: fabricating a plurality of silicon ridge waveguides arranged in parallel on the SOI substrate;

本实施例中,多个平行排布的硅脊波导204由CMOS工艺的光刻、刻蚀技术或光电子工艺如普通光刻、电子束曝光、全息曝光、刻蚀、聚焦离子束FIB等技术在顶层硅203上制作。In this embodiment, the plurality of parallel-arranged silicon ridge waveguides 204 are formed by CMOS process photolithography, etching technology or optoelectronic process such as ordinary photolithography, electron beam exposure, holographic exposure, etching, focused ion beam FIB and other technologies. Fabricated on top layer silicon 203.

本实施例中,SOI基底200的埋氧层202的厚度为2μm;顶层硅的厚度为220nm;在顶层硅上面制作的多个平行的硅脊波导204的宽度为3 μm。In this embodiment, the thickness of the buried oxide layer 202 of the SOI substrate 200 is 2 μm; the thickness of the top layer silicon is 220 nm; the width of the plurality of parallel silicon ridge waveguides 204 fabricated on the top layer silicon is 3 μm.

步骤S404:在含有硅脊波导的SOI基底上制作特定区域,并在特定区域上生长导热层700;Step S404: fabricating a specific area on the SOI substrate containing the silicon ridge waveguide, and growing the thermally conductive layer 700 on the specific area;

本实施例中,特定区域采用CMOS工艺的光刻、刻蚀技术或光电子工艺如普通光刻、电子束曝光、全息曝光、刻蚀、FIB等技术将SOI基底200 的部分顶层硅203和埋氧层202去除后形成。In this embodiment, CMOS process photolithography, etching technology or optoelectronic process such as ordinary photolithography, electron beam exposure, holographic exposure, etching, FIB and other technologies are used in a specific area to separate part of the top layer silicon 203 of the SOI substrate 200 and buried oxygen. Layer 202 is formed after removal.

导热层700是通过物理或化学沉积的方式诸如热蒸发、磁控溅射等制备技术依次分步生长不同的导热材料制备而成,不同导热材料的生长顺序可以变化;设置多种导热材料有助于提高该该硅基混合集成激光器阵列的散热性质。The thermally conductive layer 700 is prepared by growing different thermally conductive materials step by step by means of physical or chemical deposition such as thermal evaporation, magnetron sputtering, etc. The growth order of different thermally conductive materials can be changed; In order to improve the heat dissipation properties of the silicon-based hybrid integrated laser array.

本实施例中,导热层700所在的特定区域位于硅脊波导204两侧,距离硅脊波导15μm处,该特定区域的尺寸如下:长度为100μm、宽度为1 mm。In this embodiment, the specific area where the thermally conductive layer 700 is located is located on both sides of the silicon ridge waveguide 204 and is 15 μm away from the silicon ridge waveguide. The size of the specific area is as follows: 100 μm in length and 1 mm in width.

步骤S406:利用III-V半导体材料依次外延生长本征层、N型波导层、有源区、P型盖层以及P型欧姆接触层,形成III-V半导体外延层;Step S406: using III-V semiconductor material to epitaxially grow the intrinsic layer, N-type waveguide layer, active region, P-type cap layer and P-type ohmic contact layer in sequence to form a III-V semiconductor epitaxial layer;

本实施例中,III-V半导体外延层300是由MBE或MOCVD一次外延而制备。In this embodiment, the III-V semiconductor epitaxial layer 300 is prepared by one-time epitaxy by MBE or MOCVD.

III-V半导体外延层300中P型欧姆接触区301、P型盖层302、有源区303、N型波导层304以及本征层305的材料包括但不限于如下材料:磷化铟、砷化镓、锑化镓材料系的二元系、三元系、四元系材料中的任意两种或多种,任意一种三元系、四元系材料的组份可以是不同的数值,也可以是渐变的数值。The materials of the P-type ohmic contact region 301 , the P-type capping layer 302 , the active region 303 , the N-type waveguide layer 304 and the intrinsic layer 305 in the III-V semiconductor epitaxial layer 300 include but are not limited to the following materials: indium phosphide, arsenic Any two or more of the binary, ternary, and quaternary materials of the gallium and gallium antimonide material system, the components of any one of the ternary and quaternary materials can be different values, Can also be a gradient value.

优选地,P型盖层302选用InP材料,厚度为1.5μm;P型欧姆接触层301的材料为InGaAs,有源区303采用AlGalnAs材料,其增益峰在1.55 μm附近。Preferably, the P-type cap layer 302 is made of InP material with a thickness of 1.5 μm; the material of the P-type ohmic contact layer 301 is InGaAs, the active region 303 is made of AlGalnAs material, and its gain peak is around 1.55 μm.

步骤S408:在III-V半导体外延层上进行图案化处理,刻蚀出马鞍形的本征层、III-V波导以及III-V波导两侧的结构,生长P电极、N电极;Step S408: performing patterning processing on the III-V semiconductor epitaxial layer, etching the saddle-shaped intrinsic layer, the III-V waveguide and the structures on both sides of the III-V waveguide, and growing the P electrode and the N electrode;

该步骤S408包括:利用设计好的图形对III-V半导体外延层上进行图案化处理,然后一部分依次刻蚀P型欧姆接触层301、P型盖层302、有源区303、N型波导层304直至N型波导层304底部,形成III-V波导的前、后段楔形波导;另一部分依次刻蚀P型欧姆接触层301、P型盖层302 直至P型盖层302下部,形成III-V波导的中间段直波导;P型盖层302 和有源区303刻蚀掉边缘两侧的部分,形成N电极生长区;剩下的未被刻蚀的P型盖层302位于该III-V波导306的两侧,有源区303位于P型盖层302之下,同样也位于该III-V波导306的两侧,形成III-V波导两侧的结构;在在P型欧姆接触层301之上制作P电极307,在N型波导层304 之上的N电极生长区制作N电极308。The step S408 includes: using the designed pattern to pattern the III-V semiconductor epitaxial layer, and then partially etching the P-type ohmic contact layer 301, the P-type cap layer 302, the active region 303, and the N-type waveguide layer in sequence 304 to the bottom of the N-type waveguide layer 304 to form the front and rear wedge-shaped waveguides of the III-V waveguide; the other part is sequentially etched to the P-type ohmic contact layer 301 and the P-type cap layer 302 to the bottom of the P-type cap layer 302 to form III- The middle section of the V waveguide is a straight waveguide; the P-type capping layer 302 and the active region 303 are etched away on both sides of the edge to form an N-electrode growth region; the remaining unetched P-type capping layer 302 is located in the III- On both sides of the V waveguide 306, the active region 303 is located under the P-type cap layer 302, and also located on both sides of the III-V waveguide 306, forming a structure on both sides of the III-V waveguide; on the P-type ohmic contact layer A P electrode 307 is formed on top of 301 , and an N electrode 308 is formed on the N-electrode growth region on the N-type waveguide layer 304 .

P型III-V脊波导306采用但不限于如下制备技术,诸如光刻、电子束曝光、全息曝光、湿法腐蚀或干法刻蚀等制备而成。N电极与P电极的制备方式采用本领域常规制备方式,包括热蒸发、磁控溅射等,这里不作赘述。The P-type III-V ridge waveguide 306 is fabricated by, but not limited to, the following fabrication techniques, such as photolithography, electron beam exposure, holographic exposure, wet etching or dry etching. The preparation methods of the N electrode and the P electrode adopt conventional preparation methods in the art, including thermal evaporation, magnetron sputtering, etc., which will not be repeated here.

本实施例中,N电极308与III-V波导两侧的结构之间存在间距。In this embodiment, there is a gap between the N electrode 308 and the structures on both sides of the III-V waveguide.

上述设计好的图形包括:具有两端的突出部和连接部的马鞍形,以及处于马鞍形连接部的III-V波导形状,本实施例中以III-V波导包括前、后段楔形波导和中间段直波导举例说明。The above designed graphics include: a saddle shape with protruding parts and connecting parts at both ends, and a III-V waveguide shape at the saddle-shaped connecting part. In this embodiment, the III-V waveguide includes the front and rear wedge-shaped waveguides and the middle An example of a segmented straight waveguide.

步骤S410:将含有硅脊波导和导热层的SOI基底与含有III-V波导、 P电极、N电极的III-V半导体外延层键合起来;Step S410: bonding the SOI substrate containing the silicon ridge waveguide and the thermal conductive layer with the III-V semiconductor epitaxial layer containing the III-V waveguide, the P electrode, and the N electrode;

本实施例中,将SOI基底200中硅脊波导204的表面和III-V半导体外延层300中N型波导层304的表面相互接触,通过晶片键合、金属键合或介质键合的方式结合在一起。In this embodiment, the surface of the silicon ridge waveguide 204 in the SOI substrate 200 and the surface of the N-type waveguide layer 304 in the III-V semiconductor epitaxial layer 300 are in contact with each other, and are bonded by means of wafer bonding, metal bonding or dielectric bonding. together.

步骤S412:在硅脊波导或III-V波导的结构上制作微结构,完成硅基混合集成激光器阵列的制备。Step S412 : fabricating a microstructure on the structure of the silicon ridge waveguide or the III-V waveguide to complete the preparation of the silicon-based hybrid integrated laser array.

本实施例中,微结构500可以是由CMOS工艺在硅脊波导204或光电子工艺如普通光刻、电子束曝光、全息曝光、刻蚀、FIB等技术在III-V 波导306上制备而成。In this embodiment, the microstructure 500 may be fabricated on the III-V waveguide 306 by a CMOS process on the silicon ridge waveguide 204 or an optoelectronic process such as ordinary photolithography, electron beam exposure, holographic exposure, etching, and FIB.

该微结构500可以是一维、二微、三维的几何形状,包括但不限于光栅、光子晶体结构,且周期数目和几何参数可以是任意数值。The microstructure 500 can be one-dimensional, two-micro, or three-dimensional geometric shapes, including but not limited to gratings and photonic crystal structures, and the number of periods and geometric parameters can be any value.

为了验证该硅基混合集成激光器阵列的有益效果,做了两个对比结构的仿真实验,一种结构是硅脊波导两侧不含有特定区域及导热层的硅基混合集成激光器,另一种结构是硅脊波导两侧含有特定区域及导热层的硅基混合集成激光器,对这两种结构的硅基混合集成激光器进行了热分布的实验。In order to verify the beneficial effect of the silicon-based hybrid integrated laser array, simulation experiments with two contrasting structures were carried out. One structure was a silicon-based hybrid integrated laser without specific regions and thermal conductive layers on both sides of the silicon ridge waveguide, and the other structure It is a silicon-based hybrid integrated laser with a specific area and a heat-conducting layer on both sides of the silicon ridge waveguide. The thermal distribution experiments of the two-structure silicon-based hybrid integrated laser are carried out.

图4为根据本公开实施例硅脊波导两侧不含有特定区域及导热层的硅基混合集成激光器的剖面热分布示意图。图5为根据本公开实施例硅脊波导两侧含有特定区域及导热层的硅基混合集成激光器的剖面热分布示意图。4 is a schematic diagram of a cross-sectional thermal distribution of a silicon-based hybrid integrated laser without specific regions and thermal conductive layers on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure. 5 is a schematic diagram of a cross-sectional heat distribution of a silicon-based hybrid integrated laser with specific regions and a thermal conductive layer on both sides of a silicon ridge waveguide according to an embodiment of the present disclosure.

如图4所示,硅脊波导两侧不含有特定区域及导热层的硅基混合集成激光器的有源区的最高温度306℃,而硅脊波导两侧含有特定区域及导热层的硅基混合集成激光器的有源区的最高温度为40.3℃,如图5所示,可见,含有特定区域及导热层的结构改善了SOI材料中埋氧层导热特性差引起的激光器阵列散热特性差的问题,将有源区中的热量通过特定区域的金属导入衬底硅散掉,可以改善整个硅基混合集成激光器阵列的热特性和光电特性。As shown in Figure 4, the maximum temperature of the active region of the silicon-based hybrid integrated laser without a specific area and a heat-conducting layer on both sides of the silicon ridge waveguide is 306°C, while the silicon-based hybrid laser with a specific area and a heat-conducting layer on both sides of the silicon ridge waveguide has a maximum temperature of 306 °C. The maximum temperature of the active region of the integrated laser is 40.3 °C, as shown in Figure 5. It can be seen that the structure containing a specific region and a thermal conductive layer improves the problem of poor thermal conductivity of the laser array caused by the poor thermal conductivity of the buried oxide layer in the SOI material. The heat in the active region is dissipated by introducing the metal into the substrate silicon in a specific region, which can improve the thermal and optoelectronic properties of the entire silicon-based hybrid integrated laser array.

综上所述,本公开提供了一种硅基混合集成激光器阵列及其制备方法,具有良好的散热特性和光电特性,且III-V半导体外延材料由MBE或 MOCVD一次外延而成,不需要二次外延及选区生长技术,工艺简单稳定; SOI上的结构可以与成熟的CMOS工艺兼容,工艺稳定、重复性好、制作成本低;在III-V半导体材料上的结构可以与传统的光电子工艺技术兼容,制作上有较高的重复性。To sum up, the present disclosure provides a silicon-based hybrid integrated laser array and a preparation method thereof, which have good heat dissipation characteristics and optoelectronic characteristics, and III-V semiconductor epitaxial materials are epitaxially formed by MBE or MOCVD once, and do not need two. Sub-epitaxial and selective growth technology, the process is simple and stable; the structure on SOI can be compatible with mature CMOS process, the process is stable, the repeatability is good, and the production cost is low; the structure on III-V semiconductor materials can be compatible with traditional optoelectronic process technology Compatible with high repeatability in production.

当然,根据实际需要,本公开的硅基混合集成激光器阵列及其制备方法还包含其他的元件、工艺和步骤,由于同本公开的创新之处无关,此处不再赘述。Of course, according to actual needs, the silicon-based hybrid integrated laser array and the preparation method thereof of the present disclosure also include other elements, processes and steps, which are not related to the innovation of the present disclosure, and will not be repeated here.

还需要说明的是,实施例中提到的方向用语,例如“上”、“下”、“前”、“后”、“左”、“右”等,仅是参考附图的方向,并非用来限制本公开的保护范围。贯穿附图,相同的元素由相同或相近的附图标记来表示。在可能导致对本公开的理解造成混淆时,将省略常规结构或构造。并且图中各部件的形状和尺寸不反映真实大小和比例,而仅示意本公开实施例的内容。另外,在权利要求中,不应将位于括号之间的任何参考符号构造成对权利要求的限制。It should also be noted that the directional terms mentioned in the embodiments, such as "up", "down", "front", "rear", "left", "right", etc., only refer to the directions of the drawings, not used to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are denoted by the same or similar reference numbers. Conventional structures or constructions will be omitted when it may lead to obscuring the understanding of the present disclosure. Moreover, the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

再者,单词“包含”或“包括”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。Furthermore, the word "comprising" or "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

此外,除非特别描述或必须依序发生的步骤,上述步骤的顺序并无限制于以上所列,且可根据所需设计而变化或重新安排。并且上述实施例可基于设计及可靠度的考虑,彼此混合搭配使用或与其他实施例混合搭配使用,即不同实施例中的技术特征可以自由组合形成更多的实施例。Furthermore, unless the steps are specifically described or must occur sequentially, the order of the above steps is not limited to those listed above, and may be varied or rearranged according to the desired design. And the above embodiments can be mixed and matched with each other or with other embodiments based on the consideration of design and reliability, that is, the technical features in different embodiments can be freely combined to form more embodiments.

以上所述的具体实施例,对本公开的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本公开的具体实施例而已,并不用于限制本公开,凡在本公开的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本公开的保护范围之内。The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above-mentioned specific embodiments are only specific embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included within the protection scope of the present disclosure.

Claims (10)

1.一种硅基混合集成激光器阵列,包括:制作在SOI基底和III-V半导体外延层上的多个平行排布的硅基混合集成激光器;1. A silicon-based hybrid integrated laser array, comprising: a plurality of parallel-arranged silicon-based hybrid integrated lasers fabricated on an SOI substrate and a III-V semiconductor epitaxial layer; 其中,每个硅基混合集成激光器包括:硅脊波导;导热层,位于硅脊波导两侧的特定区域内,该特定区域为SOI基底去除顶层硅和埋氧层之后获得的区域;本征层,形状为马鞍形,包括两端的突出部和连接部,其中一两端的突出部覆盖于导热层上方;N型波导层,形成于本征层的连接部之上;有源区,形成于N型波导层之上;P型盖层,形成于有源区之上;III-V波导,由III-V半导体外延层图案化形成,两端与硅脊波导的前、后端相连接,两侧的结构为图案化后未被刻蚀的P型盖层以及下方的有源区;P型欧姆接触层,位于III-V波导之上;P电极,位于P型欧姆接触层之上;以及N电极,位于N型波导层之上。Wherein, each silicon-based hybrid integrated laser includes: a silicon ridge waveguide; a heat conduction layer located in a specific area on both sides of the silicon ridge waveguide, the specific area is the area obtained after removing the top silicon and buried oxide layer from the SOI substrate; an intrinsic layer , the shape is saddle-shaped, including protrusions and connecting parts at both ends, of which the protrusions at one end are covered above the thermal conductive layer; the N-type waveguide layer is formed on the connecting part of the intrinsic layer; the active area is formed on the N-type The P-type cap layer is formed on the active area; the III-V waveguide is formed by patterning the III-V semiconductor epitaxial layer, and the two ends are connected to the front and rear ends of the silicon ridge waveguide. The structure on the side is the patterned P-type cap layer that is not etched and the active region below; the P-type ohmic contact layer is located on the III-V waveguide; the P-electrode is located on the P-type ohmic contact layer; and The N electrode is located on the N-type waveguide layer. 2.根据权利要求1所述的硅基混合集成激光器阵列,其中,所述SOI基底与III-V半导体外延层通过键合的方式结合在一起,该键合的方式包括:金属键合、介质键合或者晶片直接键合,硅脊波导和III-V波导是分别通过在SOI基底和III-V半导体外延层上制作而成,然后通过将马鞍形的本征层的一两端的突出部覆盖于导热层之上,将SOI基底与III-V半导体外延层二者结合在一起。2. The silicon-based hybrid integrated laser array according to claim 1, wherein the SOI substrate and the III-V semiconductor epitaxial layer are combined by bonding, and the bonding method comprises: metal bonding, dielectric Bonding or direct wafer bonding, silicon ridge waveguides and III-V waveguides are fabricated on SOI substrates and III-V semiconductor epitaxial layers, respectively, and then by covering the protrusions at one end of the saddle-shaped intrinsic layer On top of the thermally conductive layer, both the SOI substrate and the III-V semiconductor epitaxial layer are bonded together. 3.根据权利要求1所述的硅基混合集成激光器阵列,其中,每个所述III-V波导与每个所述硅脊波导是一一对应的,且在垂直方向是对齐的。3. The silicon-based hybrid integrated laser array of claim 1, wherein each of the III-V waveguides is in a one-to-one correspondence with each of the silicon ridge waveguides and is vertically aligned. 4.根据权利要求1所述的硅基混合集成激光器阵列,其中:4. The silicon-based hybrid integrated laser array of claim 1, wherein: 所述SOI基底自下而上依次包括:衬底硅,埋氧层以及顶层硅,所述硅脊波导是SOI基底经过图案化制作出来的,是由SOI基底的顶层硅经图案化、刻蚀后形成的;The SOI substrate sequentially includes from bottom to top: substrate silicon, buried oxide layer and top layer silicon. The silicon ridge waveguide is fabricated by patterning the SOI substrate, and is patterned and etched from the top layer silicon of the SOI substrate. formed after 所述III-V半导体外延层自下而上依次包括:本征层,N型波导层,有源区,P型盖层以及P型欧姆接触层,所述III-V波导是III-V半导体外延层经过图案化,然后刻蚀P型欧姆接触层、P型盖层、有源区和N型波导层制作出来的。The III-V semiconductor epitaxial layer sequentially includes from bottom to top: an intrinsic layer, an N-type waveguide layer, an active region, a P-type cap layer and a P-type ohmic contact layer, and the III-V waveguide is a III-V semiconductor The epitaxial layer is patterned and then fabricated by etching the P-type ohmic contact layer, the P-type cap layer, the active region and the N-type waveguide layer. 5.根据权利要求4所述的硅基混合集成激光器阵列,其中:5. The silicon-based hybrid integrated laser array of claim 4, wherein: 沿着所述硅脊波导的方向,该硅脊波导两端的结构包括:楔形脊波导和/或直脊波导;Along the direction of the silicon ridge waveguide, the structures at both ends of the silicon ridge waveguide include: a wedge-shaped ridge waveguide and/or a straight ridge waveguide; 沿着所述III-V波导的方向,该III-V波导两端的结构包括:楔形脊波导和/或直脊波导。Along the direction of the III-V waveguide, the structures at both ends of the III-V waveguide include: a wedge-shaped ridge waveguide and/or a straight ridge waveguide. 6.根据权利要求5所述的硅基混合集成激光器阵列,其中,所述III-V波导包括:前、后段的楔形波导和中间段的直波导,前、后段楔形波导经图案化刻蚀至N型波导层底部,与硅脊波导的前、后端相连接,中间段直波导经刻蚀至P型盖层下部;剩下的未被刻蚀的P型盖层位于该III-V波导的两侧,有源区位于P型盖层之下,同样也位于该III-V波导的两侧。6 . The silicon-based hybrid integrated laser array according to claim 5 , wherein the III-V waveguide comprises: a wedge-shaped waveguide in the front and rear sections and a straight waveguide in the middle section, and the wedge-shaped waveguide in the front and rear sections is patterned and carved. 7 . It is etched to the bottom of the N-type waveguide layer and connected to the front and rear ends of the silicon ridge waveguide. The straight waveguide in the middle section is etched to the bottom of the P-type cap layer; the remaining unetched P-type cap layer is located in the III- On both sides of the V-waveguide, the active regions are located under the P-type capping layer, and are also located on both sides of the III-V waveguide. 7.根据权利要求1所述的硅基混合集成激光器阵列,其中:7. The silicon-based hybrid integrated laser array of claim 1, wherein: 所述导热层的材料包括:The material of the thermally conductive layer includes: 金属或合金材料,包括:SnAu、Sn、Ag、Cu、Au、Al、Fe或CuAl;Metal or alloy materials, including: SnAu, Sn, Ag, Cu, Au, Al, Fe or CuAl; 半导体材料,包括:多晶硅、单晶硅、非晶硅或锗;Semiconductor materials, including: polysilicon, single crystal silicon, amorphous silicon or germanium; 无机非金属材料,包括:石墨烯、石墨、碳纤维、C/C复合材料或炭黑;以及Inorganic non-metallic materials, including: graphene, graphite, carbon fiber, C/C composites, or carbon black; and 导热高分子材料;和/或Thermally conductive polymer materials; and/or 所述III-V半导体外延层中P型欧姆接触区、P型盖层、有源区、N型波导层以及本征层的材料包括:磷化铟、砷化镓、锑化镓材料系的二元系、三元系、四元系材料中的任意两种或多种。The materials of the P-type ohmic contact region, the P-type cap layer, the active region, the N-type waveguide layer and the intrinsic layer in the III-V semiconductor epitaxial layer include: indium phosphide, gallium arsenide, and gallium antimonide materials. Any two or more of binary, ternary, and quaternary materials. 8.根据权利要求1至7任一项所述的硅基混合集成激光器阵列,还包括:8. The silicon-based hybrid integrated laser array according to any one of claims 1 to 7, further comprising: 微结构,形成于硅脊波导或III-V波导的结构上。Microstructure, formed on the structure of silicon ridge waveguide or III-V waveguide. 9.根据权利要求8所述的硅基混合集成激光器阵列,其中,所述微结构的形貌包括:一维、二微、三维的几何形状,结构包括:光栅、光子晶体或微槽;通过调节每个硅基混合集成激光器中的微结构的参数,能够实现该硅基混合集成激光器阵列的激射波长范围的控制和调节。9. The silicon-based hybrid integrated laser array according to claim 8, wherein the morphology of the microstructure comprises: one-dimensional, two-micro, and three-dimensional geometric shapes, and the structure comprises: grating, photonic crystal or micro groove; By adjusting the parameters of the microstructure in each silicon-based hybrid integrated laser, the control and adjustment of the lasing wavelength range of the silicon-based hybrid integrated laser array can be realized. 10.一种硅基混合集成激光器阵列的制备方法,包括:10. A method for preparing a silicon-based hybrid integrated laser array, comprising: 在SOI基底上制作多个平行排布的硅脊波导;Fabrication of multiple silicon ridge waveguides arranged in parallel on SOI substrate; 在含有硅脊波导的SOI基底上制作特定区域,该特定区域为SOI基底去除顶层硅和埋氧层之后获得的区域,并在特定区域上生长导热层;Making a specific area on the SOI substrate containing the silicon ridge waveguide, the specific area is the area obtained after removing the top silicon and the buried oxide layer of the SOI substrate, and growing a thermal conductive layer on the specific area; 利用III-V半导体材料依次外延生长本征层、N型波导层、有源区、P型盖层以及P型欧姆接触层,形成III-V半导体外延层;Use III-V semiconductor material to epitaxially grow intrinsic layer, N-type waveguide layer, active region, P-type cap layer and P-type ohmic contact layer in turn to form III-V semiconductor epitaxial layer; 在III-V半导体外延层上进行图案化处理,刻蚀出马鞍形的本征层、III-V波导以及III-V波导两侧的结构,生长P电极、N电极;所述本征层包括两端的突出部和连接部,其中一两端的突出部覆盖于导热层上方;所述III-V波导的两端与硅脊波导的前、后端相连接,两侧的结构为图案化后未被刻蚀的P型盖层以及下方的有源区;所述P电极位于P型欧姆接触层之上;所述N电极位于N型波导层之上;Patterning is performed on the III-V semiconductor epitaxial layer, and the saddle-shaped intrinsic layer, the III-V waveguide and the structures on both sides of the III-V waveguide are etched, and the P electrode and the N electrode are grown; the intrinsic layer includes Protruding parts and connecting parts at both ends, one of the protruding parts at both ends is covered above the thermal conductive layer; the two ends of the III-V waveguide are connected with the front and rear ends of the silicon ridge waveguide, and the structures on both sides are not patterned. The etched P-type cap layer and the underlying active region; the P-electrode is located on the P-type ohmic contact layer; the N-electrode is located on the N-type waveguide layer; 将含有硅脊波导和导热层的SOI基底与含有III-V波导、P电极、N电极的III-V半导体外延层键合起来;该键合的方式包括:金属键合、介质键合或者晶片直接键合,硅脊波导和III-V波导是分别通过在SOI基底和III-V半导体外延层上制作而成,然后通过将马鞍形的本征层的一两端的突出部覆盖于导热层之上,将SOI基底与III-V半导体外延层二者结合在一起;以及Bond the SOI substrate containing the silicon ridge waveguide and the thermal conductive layer with the III-V semiconductor epitaxial layer containing the III-V waveguide, P electrode and N electrode; the bonding method includes: metal bonding, dielectric bonding or wafer Direct bonding, silicon ridge waveguides and III-V waveguides are fabricated on SOI substrates and III-V semiconductor epitaxial layers, respectively, and then by covering the protrusions at one end of the saddle-shaped intrinsic layer on the thermal conductive layer. above, combining both the SOI substrate and the III-V semiconductor epitaxial layer; and 在硅脊波导或III-V波导的结构上制作微结构,完成硅基混合集成激光器阵列的制备。The microstructure is fabricated on the structure of silicon ridge waveguide or III-V waveguide to complete the preparation of silicon-based hybrid integrated laser array.
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